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authorGravatar qwerty19106 <qwerty19106@gmail.com> 2018-10-01 11:37:25 +0400
committerGravatar qwerty19106 <qwerty19106@gmail.com> 2018-10-01 11:37:25 +0400
commitd9ad9d48bbfc494f18b0f51c0249af2178fe91df (patch)
treec5e90617bfed602a098dccb6a8dd720f736bd4e1 /src
parent454bb4ee49be3f877a5df4a85b295c840b735f9d (diff)
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Fix function names and remove exclusive access
Diffstat (limited to 'src')
-rw-r--r--src/peripheral/scb.rs6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index cb00454..8e2e7af 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -646,7 +646,7 @@ impl SCB {
/// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
#[inline]
- pub fn set_systick(&mut self) {
+ pub fn set_pendst() {
unsafe {
(*Self::ptr()).icsr.write(SCB_ICSR_PENDSTSET);
}
@@ -654,7 +654,7 @@ impl SCB {
/// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending
#[inline]
- pub fn is_systick_pending() -> bool {
+ pub fn is_pendst_pending() -> bool {
unsafe {
(*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET
}
@@ -663,7 +663,7 @@ impl SCB {
/// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
#[inline]
- pub fn clear_systick_pending(&mut self) {
+ pub fn clear_pendst() {
unsafe {
(*Self::ptr()).icsr.write(SCB_ICSR_PENDSTCLR);
}