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authorGravatar Adam Greig <adam@adamgreig.com> 2017-06-15 00:06:36 +0100
committerGravatar Adam Greig <adam@adamgreig.com> 2017-06-15 00:11:44 +0100
commitda097d8ac51a773d3f33c6263f1c263025390657 (patch)
treee40a39aec41b6e5b2692c1b3502718379efa7aad /src
parentaa3e5d04305db00101967bca330956b13162faa6 (diff)
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Mask set and way parameters before shifting to prevent overflow
Diffstat (limited to 'src')
-rw-r--r--src/peripheral/mod.rs12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index d04a320..15e4a47 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -1019,8 +1019,8 @@ impl Cbp {
// Cortex-M7 have a DCACHE or ICACHE at all, it seems safe to do the same thing as the
// CMSIS-Core implementation and use fixed values.
unsafe { self.dcisw.write(
- (((way as u32) << CBP_SW_WAY_POS) & CBP_SW_WAY_MASK) |
- (((set as u32) << CBP_SW_SET_POS) & CBP_SW_SET_MASK));
+ (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS) |
+ (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS));
}
}
@@ -1043,8 +1043,8 @@ impl Cbp {
pub fn dccsw(&self, set: u16, way: u16) {
// See comment for dcisw() about the format here
unsafe { self.dccsw.write(
- (((way as u32) << CBP_SW_WAY_POS) & CBP_SW_WAY_MASK) |
- (((set as u32) << CBP_SW_SET_POS) & CBP_SW_SET_MASK));
+ (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS) |
+ (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS));
}
}
@@ -1061,8 +1061,8 @@ impl Cbp {
pub fn dccisw(&self, set: u16, way: u16) {
// See comment for dcisw() about the format here
unsafe { self.dccisw.write(
- (((way as u32) << CBP_SW_WAY_POS) & CBP_SW_WAY_MASK) |
- (((set as u32) << CBP_SW_SET_POS) & CBP_SW_SET_MASK));
+ (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS) |
+ (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS));
}
}