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authorGravatar Jorge Aparicio <japaricious@gmail.com> 2017-04-11 22:01:09 -0500
committerGravatar Jorge Aparicio <japaricious@gmail.com> 2017-04-11 22:01:09 -0500
commite5fd02bd1c13bec4cc2e170f382000737857fcfc (patch)
treeaa109928c6d157d150de579474142bed7fc9f411 /src
parent6ee9676db2456081481f1da3e10466d108fa7af6 (diff)
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make NVIC.set_priority and basepri::write unsafe
Diffstat (limited to 'src')
-rw-r--r--src/peripheral/mod.rs2
-rw-r--r--src/register/basepri.rs2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index 1f9e147..d14d782 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -380,7 +380,7 @@ impl Nvic {
///
/// NOTE See `get_priority` method for an explanation of how NVIC priorities
/// work.
- pub fn set_priority<I>(&self, interrupt: I, prio: u8)
+ pub unsafe fn set_priority<I>(&self, interrupt: I, prio: u8)
where
I: Nr,
{
diff --git a/src/register/basepri.rs b/src/register/basepri.rs
index e9164c1..d5ec002 100644
--- a/src/register/basepri.rs
+++ b/src/register/basepri.rs
@@ -16,7 +16,7 @@ pub fn read() -> u8 {
/// Writes to the CPU register
#[inline(always)]
-pub fn write(basepri: u8) {
+pub unsafe fn write(basepri: u8) {
unsafe {
asm!("msr BASEPRI, $0"
: