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| author |  Adam Greig <adam@adamgreig.com>
| 2017-06-14 23:38:11 +0100 |
|---|---|---|
| committer | Adam Greig <adam@adamgreig.com>
| 2017-06-14 23:38:11 +0100 |
| commit | ea7ce5c3b0e38c5c8c9fe4e71860b830e30f22ba (patch) | |
| tree | 34e2143cea6d38e6d4c7a07d471f78c05b55a4fd /src | |
| parent | bd0a100ebf0a012a95e12d3070fa01e7a5b3658c (diff) | |
| download | cortex-m-ea7ce5c3b0e38c5c8c9fe4e71860b830e30f22ba.tar.gz cortex-m-ea7ce5c3b0e38c5c8c9fe4e71860b830e30f22ba.tar.zst cortex-m-ea7ce5c3b0e38c5c8c9fe4e71860b830e30f22ba.zip | |
Remove config flags on CPUID fields.
This prevents these changes being breaking changes as these fields used to be
exposed. To be re-added in a future breaking release.
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/mod.rs | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index b85f699..1c71e11 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -104,16 +104,12 @@ pub struct Cpuid { pub isar: [RO<u32>; 5], reserved1: u32, /// Cache Level ID - #[cfg(armv7m)] pub clidr: RO<u32>, /// Cache Type - #[cfg(armv7m)] pub ctr: RO<u32>, /// Cache Size ID - #[cfg(armv7m)] pub ccsidr: RO<u32>, /// Cache Size Selection - #[cfg(armv7m)] pub csselr: RW<u32>, } |