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authorGravatar Jorge Aparicio <japaricious@gmail.com> 2017-02-28 21:07:03 -0500
committerGravatar Jorge Aparicio <japaricious@gmail.com> 2017-02-28 21:08:13 -0500
commitfede2074f7fa74e0ab0211bab7af4240954f4e0a (patch)
tree5bd1a6f6dcf0430f435ceb71eb345a4f209fff4e /src
parentafa752b249d0d33ca9a46a6b4e390e13206990c3 (diff)
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fix get/set_priority
these methods must write to the highest bits of the IPR registers
Diffstat (limited to 'src')
-rw-r--r--src/peripheral/nvic.rs11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs
index 91e158c..054a74e 100644
--- a/src/peripheral/nvic.rs
+++ b/src/peripheral/nvic.rs
@@ -3,6 +3,12 @@
use interrupt::Nr;
use volatile_register::{RO, RW};
+#[cfg(thumbv6m)]
+const PRIORITY_BITS: u8 = 2;
+
+#[cfg(not(thumbv6m))]
+const PRIORITY_BITS: u8 = 4;
+
/// Registers
#[repr(C)]
pub struct Registers {
@@ -59,7 +65,7 @@ impl Registers {
{
let nr = interrupt.nr();
- self.ipr[usize::from(nr)].read()
+ self.ipr[usize::from(nr)].read() >> (8 - PRIORITY_BITS)
}
/// Is `interrupt` active or pre-empted and stacked
@@ -107,6 +113,7 @@ impl Registers {
{
let nr = interrupt.nr();
- self.ipr[usize::from(nr)].write(prio);
+ self.ipr[usize::from(nr)].write((prio & ((1 << PRIORITY_BITS) - 1)) <<
+ (8 - PRIORITY_BITS));
}
}