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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2023-02-26 23:12:38 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2023-02-26 23:12:38 +0000 |
| commit | 067af8406f306bf8fba53ce738e441a8ba7fefe1 (patch) | |
| tree | 40144c41f30e4c267837283e588db9b2ff65cfad /xtask/tests/ci.rs | |
| parent | 88c6f8637f4eccbb44f57be5bc10bcfc88fbb3c8 (diff) | |
| parent | d6086d3f075be0060ffc3fd0559bcf662dc09a98 (diff) | |
| download | cortex-m-067af8406f306bf8fba53ce738e441a8ba7fefe1.tar.gz cortex-m-067af8406f306bf8fba53ce738e441a8ba7fefe1.tar.zst cortex-m-067af8406f306bf8fba53ce738e441a8ba7fefe1.zip | |
Merge #472
472: nvic: do not require `&mut self` for `request`. r=adamgreig a=Dirbaio
It's not needed, the register write is stateless/atomic.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Diffstat (limited to 'xtask/tests/ci.rs')
0 files changed, 0 insertions, 0 deletions