diff options
| -rw-r--r-- | .travis.yml | 5 | ||||
| -rw-r--r-- | Cargo.toml | 5 | ||||
| -rw-r--r-- | ci/script.sh | 4 | ||||
| -rw-r--r-- | src/register/basepri.rs | 15 | ||||
| -rw-r--r-- | src/register/basepri_max.rs | 15 |
5 files changed, 38 insertions, 6 deletions
diff --git a/.travis.yml b/.travis.yml index d780549..5c47bd4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -23,7 +23,10 @@ script: after_script: set +e -cache: cargo +cache: + cargo: true + directories: + - $HOME/.xargo before_cache: - chmod -R a+r $HOME/.cargo; @@ -12,4 +12,7 @@ version = "0.3.1" [dependencies] aligned = "0.1.1" bare-metal = "0.1.0" -volatile-register = "0.2.0"
\ No newline at end of file +volatile-register = "0.2.0" + +[features] +cm7-r0p1 = []
\ No newline at end of file diff --git a/ci/script.sh b/ci/script.sh index 9b60f0c..d5d1c69 100644 --- a/ci/script.sh +++ b/ci/script.sh @@ -2,6 +2,10 @@ set -euxo pipefail main() { case $TARGET in + thumbv7em-none-eabi*) + xargo check --target $TARGET --features cm7-r0p1 + xargo check --target $TARGET + ;; thumbv*-none-eabi*) xargo check --target $TARGET ;; diff --git a/src/register/basepri.rs b/src/register/basepri.rs index a024d74..c9be9d3 100644 --- a/src/register/basepri.rs +++ b/src/register/basepri.rs @@ -18,11 +18,22 @@ pub fn read() -> u8 { } /// Writes to the CPU register +/// +/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the +/// `cm7-r0p1` Cargo feature or this function WILL misbehave. +#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))] #[inline] -pub unsafe fn write(_basepri: u8) { +pub unsafe fn write(basepri: u8) { match () { #[cfg(target_arch = "arm")] - () => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"), + () => match () { + #[cfg(not(feature = "cm7-r0p1"))] + () => asm!("msr BASEPRI, $0" :: "r"(basepri) : "memory" : "volatile"), + #[cfg(feature = "cm7-r0p1")] + () => asm!("cpsid i + msr BASEPRI, $0 + cpsie i" :: "r"(basepri) : "memory" : "volatile"), + }, #[cfg(not(target_arch = "arm"))] () => unimplemented!(), } diff --git a/src/register/basepri_max.rs b/src/register/basepri_max.rs index 0833aa7..c386e86 100644 --- a/src/register/basepri_max.rs +++ b/src/register/basepri_max.rs @@ -4,12 +4,23 @@ /// /// - `basepri != 0` AND `basepri::read() == 0`, OR /// - `basepri != 0` AND `basepri < basepri::read()` +/// +/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the +/// `cm7-r0p1` Cargo feature or this function WILL misbehave. +#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))] #[inline] -pub fn write(_basepri: u8) { +pub fn write(basepri: u8) { match () { #[cfg(target_arch = "arm")] () => unsafe { - asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"); + match () { + #[cfg(not(feature = "cm7-r0p1"))] + () => asm!("msr BASEPRI_MAX, $0" :: "r"(basepri) : "memory" : "volatile"), + #[cfg(feature = "cm7-r0p1")] + () => asm!("cpsid i + msr BASEPRI_MAX, $0 + cpsie i" :: "r"(basepri) : "memory" : "volatile"), + } }, #[cfg(not(target_arch = "arm"))] () => unimplemented!(), |