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-rw-r--r--cortex-m-rt/asm.s23
1 files changed, 23 insertions, 0 deletions
diff --git a/cortex-m-rt/asm.s b/cortex-m-rt/asm.s
index 50a3fa5..1be4a02 100644
--- a/cortex-m-rt/asm.s
+++ b/cortex-m-rt/asm.s
@@ -17,3 +17,26 @@ HardFaultTrampoline:
0:
mrs r0, PSP
b HardFault
+
+ .section .text.FpuTrampoline, "ax"
+ .global FpuTrampoline
+ # .type and .thumb_func are both required; otherwise its Thumb bit does not
+ # get set and an invalid vector table is generated
+ .type FpuTrampoline,%function
+ .thumb_func
+ # This enables the FPU and jumps to the main function.
+FpuTrampoline:
+ # Address of SCB.CPACR.
+ ldr r0, =0xE000ED88
+ # Enable access to CP10 and CP11 from both privileged and unprivileged mode.
+ ldr r1, =(0b1111 << 20)
+ # RMW.
+ ldr r2, [r0]
+ orr r2, r2, r1
+ str r2, [r0]
+ # Barrier is required on some processors.
+ dsb
+ isb
+ # Hand execution over to `main`.
+ bl main
+ # Note: `main` must not return. `bl` is used only because it has a wider range than `b`.