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| author |  Jonas Schievink <jonasschievink@gmail.com>
| 2020-08-30 00:29:59 +0200 |
|---|---|---|
| committer | Jonas Schievink <jonasschievink@gmail.com>
| 2020-08-30 00:44:29 +0200 |
| commit | e9eae4ded99c6f1f3a62bf379664e1503798c11f (patch) | |
| tree | c7e4826e89a1f82a01b7ffc965c15c485838e8dd /cortex-m-rt/asm.s | |
| parent | b9afdecc8fff3d2fe2d1a8c2695cc92cfebb3bb9 (diff) | |
| download | cortex-m-e9eae4ded99c6f1f3a62bf379664e1503798c11f.tar.gz cortex-m-e9eae4ded99c6f1f3a62bf379664e1503798c11f.tar.zst cortex-m-e9eae4ded99c6f1f3a62bf379664e1503798c11f.zip | |
Avoid depending on `cortex-m`
Diffstat (limited to 'cortex-m-rt/asm.s')
| -rw-r--r-- | cortex-m-rt/asm.s | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/cortex-m-rt/asm.s b/cortex-m-rt/asm.s index 50a3fa5..1be4a02 100644 --- a/cortex-m-rt/asm.s +++ b/cortex-m-rt/asm.s @@ -17,3 +17,26 @@ HardFaultTrampoline: 0: mrs r0, PSP b HardFault + + .section .text.FpuTrampoline, "ax" + .global FpuTrampoline + # .type and .thumb_func are both required; otherwise its Thumb bit does not + # get set and an invalid vector table is generated + .type FpuTrampoline,%function + .thumb_func + # This enables the FPU and jumps to the main function. +FpuTrampoline: + # Address of SCB.CPACR. + ldr r0, =0xE000ED88 + # Enable access to CP10 and CP11 from both privileged and unprivileged mode. + ldr r1, =(0b1111 << 20) + # RMW. + ldr r2, [r0] + orr r2, r2, r1 + str r2, [r0] + # Barrier is required on some processors. + dsb + isb + # Hand execution over to `main`. + bl main + # Note: `main` must not return. `bl` is used only because it has a wider range than `b`. |