3 files changed, 0 insertions, 6 deletions
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs
index 32d0baf..ad2b6e6 100644
--- a/src/peripheral/cpuid.rs
+++ b/src/peripheral/cpuid.rs
@@ -66,7 +66,6 @@ pub struct RegisterBlock {
 
 /// Type of cache to select on CSSELR writes.
 #[cfg(not(armv6m))]
-#[allow(clippy::missing_inline_in_public_items)]
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
 pub enum CsselrCacheType {
     /// Select DCache or unified cache
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index 1b25b5f..b619328 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -97,7 +97,6 @@ pub struct RegisterBlock {
 
 /// FPU access mode
 #[cfg(has_fpu)]
-#[allow(clippy::missing_inline_in_public_items)]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 pub enum FpuAccessMode {
     /// FPU is not accessible
@@ -194,7 +193,6 @@ impl SCB {
 }
 
 /// Processor core exceptions (internal interrupts)
-#[allow(clippy::missing_inline_in_public_items)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 pub enum Exception {
     /// Non maskable interrupt
@@ -260,7 +258,6 @@ impl Exception {
 }
 
 /// Active exception number
-#[allow(clippy::missing_inline_in_public_items)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 pub enum VectActive {
     /// Thread mode
@@ -913,7 +910,6 @@ impl SCB {
 }
 
 /// System handlers, exceptions with configurable priority
-#[allow(clippy::missing_inline_in_public_items)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 #[repr(u8)]
 pub enum SystemHandler {
diff --git a/src/peripheral/syst.rs b/src/peripheral/syst.rs
index 69bc488..abcd00b 100644
--- a/src/peripheral/syst.rs
+++ b/src/peripheral/syst.rs
@@ -18,7 +18,6 @@ pub struct RegisterBlock {
 }
 
 /// SysTick clock source
-#[allow(clippy::missing_inline_in_public_items)]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 pub enum SystClkSource {
     /// Core-provided clock