aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/peripheral/dcb.rs1
-rw-r--r--src/peripheral/test.rs1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/peripheral/dcb.rs b/src/peripheral/dcb.rs
index 3d89c61..1d5680e 100644
--- a/src/peripheral/dcb.rs
+++ b/src/peripheral/dcb.rs
@@ -33,6 +33,7 @@ impl DCB {
pub fn disable_trace(&mut self) {
// unset bit 24 / TRCENA
unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); }
+ }
/// Is there a debugger attached? (see notes)
///
diff --git a/src/peripheral/test.rs b/src/peripheral/test.rs
index 1120dbb..49fd7cf 100644
--- a/src/peripheral/test.rs
+++ b/src/peripheral/test.rs
@@ -109,6 +109,7 @@ fn nvic() {
assert_eq!(address(&nvic.icpr), 0xE000E280);
assert_eq!(address(&nvic.iabr), 0xE000E300);
assert_eq!(address(&nvic.ipr), 0xE000E400);
+ #[cfg(not(armv6m))]
assert_eq!(address(&nvic.stir), 0xE000EF00);
}