diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/delay.rs | 22 | ||||
-rw-r--r-- | src/lib.rs | 2 | ||||
-rw-r--r-- | src/peripheral/icb.rs | 6 | ||||
-rw-r--r-- | src/peripheral/mod.rs | 8 | ||||
-rw-r--r-- | src/peripheral/scb.rs | 14 |
5 files changed, 30 insertions, 22 deletions
diff --git a/src/delay.rs b/src/delay.rs index 8ed1fea..66a63bf 100644 --- a/src/delay.rs +++ b/src/delay.rs @@ -6,7 +6,7 @@ use embedded_hal::blocking::delay::{DelayMs, DelayUs}; /// System timer (SysTick) as a delay provider. pub struct Delay { syst: SYST, - ahb_frequency: u32, + frequency: u32, } impl Delay { @@ -14,13 +14,19 @@ impl Delay { /// /// `ahb_frequency` is a frequency of the AHB bus in Hz. #[inline] - pub fn new(mut syst: SYST, ahb_frequency: u32) -> Self { - syst.set_clock_source(SystClkSource::Core); + pub fn new(syst: SYST, ahb_frequency: u32) -> Self { + Self::with_source(syst, ahb_frequency, SystClkSource::Core) + } - Delay { - syst, - ahb_frequency, - } + /// Configures the system timer (SysTick) as a delay provider + /// with a clock source. + /// + /// `frequency` is the frequency of your `clock_source` in Hz. + #[inline] + pub fn with_source(mut syst: SYST, frequency: u32, clock_source: SystClkSource) -> Self { + syst.set_clock_source(clock_source); + + Delay { syst, frequency } } /// Releases the system timer (SysTick) resource. @@ -32,7 +38,7 @@ impl Delay { /// Delay using the Cortex-M systick for a certain duration, in µs. #[allow(clippy::missing_inline_in_public_items)] pub fn delay_us(&mut self, us: u32) { - let ticks = (u64::from(us)) * (u64::from(self.ahb_frequency)) / 1_000_000; + let ticks = (u64::from(us)) * (u64::from(self.frequency)) / 1_000_000; let full_cycles = ticks >> 24; if full_cycles > 0 { @@ -76,6 +76,8 @@ // - A generated #[derive(Debug)] function (in which case the attribute needs // to be applied to the struct). #![deny(clippy::missing_inline_in_public_items)] +// Don't warn about feature(asm) being stable on Rust >= 1.59.0 +#![allow(stable_features)] extern crate bare_metal; extern crate volatile_register; diff --git a/src/peripheral/icb.rs b/src/peripheral/icb.rs index 9b29655..e1de33b 100644 --- a/src/peripheral/icb.rs +++ b/src/peripheral/icb.rs @@ -1,6 +1,6 @@ //! Implementation Control Block -#[cfg(any(armv7m, armv8m, target_arch = "x86_64"))] +#[cfg(any(armv7m, armv8m, native))] use volatile_register::RO; use volatile_register::RW; @@ -12,12 +12,12 @@ pub struct RegisterBlock { /// The bottom four bits of this register give the number of implemented /// interrupt lines, divided by 32. So a value of `0b0010` indicates 64 /// interrupts. - #[cfg(any(armv7m, armv8m, target_arch = "x86_64"))] + #[cfg(any(armv7m, armv8m, native))] pub ictr: RO<u32>, /// The ICTR is not defined in the ARMv6-M Architecture Reference manual, so /// we replace it with this. - #[cfg(not(any(armv7m, armv8m, target_arch = "x86_64")))] + #[cfg(not(any(armv7m, armv8m, native)))] _reserved: u32, /// Auxiliary Control Register diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index 5c5e7ce..3756553 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -71,8 +71,8 @@ pub mod dcb; pub mod dwt; #[cfg(not(armv6m))] pub mod fpb; -// NOTE(target_arch) is for documentation purposes -#[cfg(any(has_fpu, target_arch = "x86_64"))] +// NOTE(native) is for documentation purposes +#[cfg(any(has_fpu, native))] pub mod fpu; pub mod icb; #[cfg(all(not(armv6m), not(armv8m_base)))] @@ -405,7 +405,7 @@ pub struct FPU { unsafe impl Send for FPU {} -#[cfg(any(has_fpu, target_arch = "x86_64"))] +#[cfg(any(has_fpu, native))] impl FPU { /// Pointer to the register block pub const PTR: *const fpu::RegisterBlock = 0xE000_EF30 as *const _; @@ -417,7 +417,7 @@ impl FPU { } } -#[cfg(any(has_fpu, target_arch = "x86_64"))] +#[cfg(any(has_fpu, native))] impl ops::Deref for FPU { type Target = self::fpu::RegisterBlock; diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 28cfca8..eeea0c5 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -182,7 +182,7 @@ impl SCB { 5 => VectActive::Exception(Exception::BusFault), #[cfg(not(armv6m))] 6 => VectActive::Exception(Exception::UsageFault), - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] 7 => VectActive::Exception(Exception::SecureFault), 11 => VectActive::Exception(Exception::SVCall), #[cfg(not(armv6m))] @@ -197,7 +197,7 @@ impl SCB { /// Processor core exceptions (internal interrupts) #[derive(Clone, Copy, Debug, Eq, PartialEq)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] -#[cfg_attr(feature = "std-map", derive(PartialOrd, Hash))] +#[cfg_attr(feature = "std", derive(PartialOrd, Hash))] pub enum Exception { /// Non maskable interrupt NonMaskableInt, @@ -218,7 +218,7 @@ pub enum Exception { UsageFault, /// Secure fault interrupt (only on ARMv8-M) - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] SecureFault, /// SV call interrupt @@ -250,7 +250,7 @@ impl Exception { Exception::BusFault => -11, #[cfg(not(armv6m))] Exception::UsageFault => -10, - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] Exception::SecureFault => -9, Exception::SVCall => -5, #[cfg(not(armv6m))] @@ -264,7 +264,7 @@ impl Exception { /// Active exception number #[derive(Clone, Copy, Debug, Eq, PartialEq)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] -#[cfg_attr(feature = "std-map", derive(PartialOrd, Hash))] +#[cfg_attr(feature = "std", derive(PartialOrd, Hash))] pub enum VectActive { /// Thread mode ThreadMode, @@ -293,7 +293,7 @@ impl VectActive { 5 => VectActive::Exception(Exception::BusFault), #[cfg(not(armv6m))] 6 => VectActive::Exception(Exception::UsageFault), - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] 7 => VectActive::Exception(Exception::SecureFault), 11 => VectActive::Exception(Exception::SVCall), #[cfg(not(armv6m))] @@ -934,7 +934,7 @@ pub enum SystemHandler { UsageFault = 6, /// Secure fault interrupt (only on ARMv8-M) - #[cfg(any(armv8m, target_arch = "x86_64"))] + #[cfg(any(armv8m, native))] SecureFault = 7, /// SV call interrupt |