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2020-07-21Add new InterruptNumber traitGravatar Adam Greig 2-34/+53
2020-07-18Correct typo in RASR register aliasesGravatar R. Kyle Murphy 2-9/+9
Fixes the typo in the a1, a2, and a3 aliases of the RASR MPU register.
2020-07-12Allow the taken flag to be optimized outGravatar Jonas Schievink 1-3/+6
2020-07-09Expand iff and reword last sentenceGravatar Daniel Egger 1-2/+2
Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-09Change spelling of initialisation to AEGravatar Daniel Egger 1-1/+1
Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-09Update src/asm.rsGravatar Daniel Egger 1-1/+1
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-07-09Better delay descriptionGravatar Daniel Egger 1-4/+7
CC #236 Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-05Merge pull request #205 from hug-dev/enable-exceptionsGravatar Daniel Egger 1-0/+75
Add SCB methods to enable/disable exceptions
2020-07-05Use assembly sequences to enable caches.Gravatar Cliff L. Biffle 1-8/+16
See #232, which this partially fixes -- there's still the question of taking an interrupt in the midst of these sequences.
2020-06-24Add a function to get SHCSR enable bit positionsGravatar Hugues de Valon 1-47/+28
This removes the duplication of the look-up table and enforces some safety checks with the match statement. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-06-19Correct the documentation for the `SCB::set_pendst` functionGravatar Peter Taylor 1-1/+1
2020-06-11Merge #220Gravatar bors[bot] 2-0/+350
220: Implement accessing FPSCR r=adamgreig a=bugadani On the nRF52, sometimes it is necessary to manipulate the FPSCR register, otherwise the device wakes up immediately from sleep. (At least on this device) the FPSCR is only available through `vmrs` instructions. I've implemented reading the register, parsing its bits and writing a raw value to the register, but let me know if I should also implement manipulation of the named bits. I would also like to request some assistance to get this to actually build, it's not clear to me how `.s` files are compiled in this library. I'm also not certain where the actual place for this would be - in the registers, or in the `fpu` module. Co-authored-by: Dániel Buga <bugadani@gmail.com> Co-authored-by: Dániel Buga <daniel@revolutionrobotics.org>
2020-06-10Merge #225 #226Gravatar bors[bot] 3-2/+113
225: Initial ARMv8-M MPU support. r=adamgreig a=cbiffle The v8-M MPU is entirely different from, and incompatible with, the earlier PMSA MPU. And so this commit does two things: 1. Makes the old RegisterBlock depend on armv6m (for M0+) and armv7m. 2. Defines a new RegisterBlock containing the right layout for v8m. The hack for documenting fields by opting in x86-64 means the v8m version won't appear in the docs. 226: Expose the orphaned ICTR/ACTLR registers. r=adamgreig a=cbiffle In ARMv7-M these were floating alone in system control space, without a unifying name. As a result, they weren't exposed in earlier versions of this crate. In ARMv8-M they have been given a name, the Implementation Control Block, and more registers have been added. I've used that name for all architecture revisions. Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
2020-06-10Merge #227Gravatar bors[bot] 1-1/+12
227: ITM: don't test reserved bits in is_fifo_ready r=adamgreig a=bcantrill This is a follow up to the discussion in #219, capturing the conclusion by @cbiffle and @adamgreig there: to indicate that the ITM FIFO is ready on FIFOREADY (only) on ARMv7-M (only) and to indicate the FIFI is ready on *either* FIFOREADY *or* DISABLED on ARMv8-M. ITM has been tested and verified on an ARMv7-M CPU (an STM32F407, a Cortex-M4) and an ARMv8-M CPU (an LPC55S69, a Cortex-M33). Without this fix, any use of ITM will hang on ARMv8-M -- which may in fact be the root cause of #74... Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
2020-06-09ITM: don't test reserved bits in is_fifo_readyGravatar Cliff L. Biffle 1-1/+12
On ARMv7-M, bits 31:1 of the value read from STIMx are reserved, so comparing them against zero is a bad idea. On ARMv8-M, bit 1 has been repurposed to indicate DISABLED. This means that the is_fifo_ready impl hangs forever when ITM is disabled on a Cortex-M33 (for example). Changed to test only the FIFOREADY bit on ARMv7-M, and to test either FIFOREADY or DISABLED on ARMv8-M.
2020-06-09Expose the orphaned ICTR/ACTLR registers.Gravatar Cliff L. Biffle 2-1/+77
In ARMv7-M these were floating alone in system control space, without a unifying name. As a result, they weren't exposed in earlier versions of this crate. In ARMv8-M they have been given a name, the Implementation Control Block, and more registers have been added. I've used that name for all architecture revisions.
2020-06-09Initial ARMv8-M MPU support.Gravatar Cliff L. Biffle 1-1/+36
The v8-M MPU is entirely different from, and incompatible with, the earlier PMSA MPU. And so this commit does two things: 1. Makes the old RegisterBlock depend on armv6m (for M0+) and armv7m. 2. Defines a new RegisterBlock containing the right layout for v8m. The hack for documenting fields by opting in x86-64 means the v8m version won't appear in the docs.
2020-06-06Add #[allow(clippy::missing_inline_in_public_items)] for consistencyGravatar Dániel Buga 1-0/+1
2020-06-06Make RMode methods actually accessibleGravatar Dániel Buga 1-4/+4
2020-06-06Add missing #[inline]sGravatar Dániel Buga 1-0/+14
2020-06-06Oops. Fix pattern matchingGravatar Dániel Buga 1-4/+4
2020-06-06Add methods to RModeGravatar Dániel Buga 1-13/+39
2020-06-06Implement bit manipulation methodsGravatar Dániel Buga 1-0/+128
2020-06-06Fix clippy warningGravatar Dániel Buga 1-0/+1
2020-05-28Stylistic updates, add from_bitsGravatar Dániel Buga 1-11/+17
2020-05-28Fix remaining compiler sadnessGravatar Dániel Buga 1-5/+9
2020-05-28Where did those ifs come from...Gravatar Dániel Buga 1-9/+9
2020-05-28Fix doc commentsGravatar Dániel Buga 1-15/+15
2020-05-28Fix store instructionsGravatar Dániel Buga 1-1/+1
2020-05-27Add doc commentsGravatar Dániel Buga 1-0/+12
2020-05-27Implement accessing FPSCRGravatar Dániel Buga 2-0/+159
2020-05-24ITM: don't test reserved bits in is_fifo_readyGravatar Cliff L. Biffle 1-1/+1
On ARMv7-M, bits 31:1 of the value read from STIMx are reserved, so comparing them against zero is a bad idea. On ARMv8-M, bit 1 has been repurposed to indicate DISABLED. This means that the is_fifo_ready impl hangs forever when ITM is disabled on a Cortex-M33 (for example). Changed to test only the FIFOREADY bit.
2020-05-05Use #!cfg_attr for inline_asmGravatar Stian Eklund 1-2/+1
This fixes the previous commit where the #![feature()] flag was used by mistake.
2020-04-28Use llmv_asm! macro for inline assemblyGravatar Stian Eklund 15-39/+40
\ fixes #204 the `asm!` macro will soon be deprecated. This changes all of the `asm!` calls to `llvm_asm!` To my knowledge doing a direct replacement should be fine.
2020-04-15Add SCB methods to enable/disable exceptionsGravatar Hugues de Valon 1-0/+94
Some exceptions might be disabled by default which means that the HardFault handler will be called instead of the exception handler. This commit adds methods on the SCB peripheral that use the SHCSR register to enable/disable exceptions. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-04-15Merge #181Gravatar bors[bot] 7-15/+19
181: Add cfg to Peripheral fields r=thejpster a=hug-dev The cfg conditional compilation attribute was only set on impl blocks of peripherals. This commit also sets it on the fields themselves to be more consistent. Also adds Armv8-M Baseline to the blacklist of the ITM peripheral (cf rule `FMQF` of the Armv8-M ARM). Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-04-15Merge #180Gravatar bors[bot] 2-1/+277
180: Add Security Attribution Unit support r=thejpster a=hug-dev The SAU is a Armv8-M core peripheral that, alongside the Implementation Defined Attribution Unit, manages the security attribution of the memory zones. This driver provides abstraction to help setting the SAU up. This pull-request adds a new dependency, `bitfield` which provides a really nice way to describe bit fields in registers with methods to access them. It makes it really easier to use/write rather than having to manually declare the shift number and mask constants. Although `bitfield` does not have any dependency, I am well aware of the increased cost of memory its addition could cause to embedded targets. I am really open to criticism about its use, if you would prefer me not to use it, or if you would like to see benchmarks of memory usage for some reference targets of embedded Rust 😃 Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-04-10Update cfg gates with Armv8-MGravatar Hugues de Valon 7-15/+19
Update cfg attributes and code documentation to take into consideration the new Armv8-M architecture profiles. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-18Add TODO with link to rust-lang/rust/issues/13926Gravatar Роман Кривенков 1-0/+4
2020-03-17Update unsafe commentsGravatar Роман Кривенков 1-8/+4
2020-03-17Prevent unnecessary bounds check in SCB::{get_priority, set_priority}Gravatar Роман Кривенков 1-4/+22
2020-03-17Use u8 repr for enum instead of custom methodGravatar Daniel Egger 1-34/+19
This is an alternative proposal to #202 as suggested in https://github.com/rust-embedded/cortex-m/pull/202#issuecomment-600017553 Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-03-15Merge #201Gravatar bors[bot] 1-0/+29
201: Add UDF instruction. Closes #199. r=jonas-schievink a=adamgreig Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-03-15Swap infinite loops for unreachable_unchecked()Gravatar Adam Greig 1-2/+2
2020-03-15Mark asm::udf as divergentGravatar Adam Greig 1-3/+8
2020-03-15Add UDF instruction. Closes #199.Gravatar Adam Greig 1-0/+24
2020-03-15Add CPSR to asm::delay's clobber flags. Fixes #195Gravatar Adam Greig 1-1/+1
2020-03-14Allow clippy::match_single_bindingGravatar Hugues de Valon 2-0/+4
Clippy complains that the match expressions used for cfg gating could be rewritten as a let statement, this is a false positive. Also adds inline on two functions. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-02Initial Rust CMSE supportGravatar Hugues de Valon 3-0/+383
Armv8-M and Armv8.1-M architecture profiles have an optional Security Extension which provides a set of Security features. This patch adds initial support of the Cortex-M Security Extensions but providing support for the TT intrinsics and helper functions on top of it in the newly added cmse module of this crate. The code is a Rust idiomatic implementation of the C requirements described in this document: https://developer.arm.com/docs/ecm0359818/latest Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-01Merge #193Gravatar bors[bot] 1-35/+27
193: Make `Peripherals` non-exhaustive and improve its docs r=therealprof a=jonas-schievink This means that it's no longer a breaking change to add fields to it, which is important since Arm is likely to add more in upcoming architectures. They could also add extensions that add peripherals. Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
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