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2020-04-15Merge #181Gravatar bors[bot] 7-15/+19
181: Add cfg to Peripheral fields r=thejpster a=hug-dev The cfg conditional compilation attribute was only set on impl blocks of peripherals. This commit also sets it on the fields themselves to be more consistent. Also adds Armv8-M Baseline to the blacklist of the ITM peripheral (cf rule `FMQF` of the Armv8-M ARM). Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-04-15Merge #180Gravatar bors[bot] 2-1/+277
180: Add Security Attribution Unit support r=thejpster a=hug-dev The SAU is a Armv8-M core peripheral that, alongside the Implementation Defined Attribution Unit, manages the security attribution of the memory zones. This driver provides abstraction to help setting the SAU up. This pull-request adds a new dependency, `bitfield` which provides a really nice way to describe bit fields in registers with methods to access them. It makes it really easier to use/write rather than having to manually declare the shift number and mask constants. Although `bitfield` does not have any dependency, I am well aware of the increased cost of memory its addition could cause to embedded targets. I am really open to criticism about its use, if you would prefer me not to use it, or if you would like to see benchmarks of memory usage for some reference targets of embedded Rust 😃 Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-04-10Update cfg gates with Armv8-MGravatar Hugues de Valon 7-15/+19
Update cfg attributes and code documentation to take into consideration the new Armv8-M architecture profiles. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-18Add TODO with link to rust-lang/rust/issues/13926Gravatar Роман Кривенков 1-0/+4
2020-03-17Update unsafe commentsGravatar Роман Кривенков 1-8/+4
2020-03-17Prevent unnecessary bounds check in SCB::{get_priority, set_priority}Gravatar Роман Кривенков 1-4/+22
2020-03-17Use u8 repr for enum instead of custom methodGravatar Daniel Egger 1-34/+19
This is an alternative proposal to #202 as suggested in https://github.com/rust-embedded/cortex-m/pull/202#issuecomment-600017553 Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-03-15Merge #201Gravatar bors[bot] 1-0/+29
201: Add UDF instruction. Closes #199. r=jonas-schievink a=adamgreig Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-03-15Swap infinite loops for unreachable_unchecked()Gravatar Adam Greig 1-2/+2
2020-03-15Mark asm::udf as divergentGravatar Adam Greig 1-3/+8
2020-03-15Add UDF instruction. Closes #199.Gravatar Adam Greig 1-0/+24
2020-03-15Add CPSR to asm::delay's clobber flags. Fixes #195Gravatar Adam Greig 1-1/+1
2020-03-14Allow clippy::match_single_bindingGravatar Hugues de Valon 2-0/+4
Clippy complains that the match expressions used for cfg gating could be rewritten as a let statement, this is a false positive. Also adds inline on two functions. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-02Initial Rust CMSE supportGravatar Hugues de Valon 3-0/+383
Armv8-M and Armv8.1-M architecture profiles have an optional Security Extension which provides a set of Security features. This patch adds initial support of the Cortex-M Security Extensions but providing support for the TT intrinsics and helper functions on top of it in the newly added cmse module of this crate. The code is a Rust idiomatic implementation of the C requirements described in this document: https://developer.arm.com/docs/ecm0359818/latest Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-03-01Merge #193Gravatar bors[bot] 1-35/+27
193: Make `Peripherals` non-exhaustive and improve its docs r=therealprof a=jonas-schievink This means that it's no longer a breaking change to add fields to it, which is important since Arm is likely to add more in upcoming architectures. They could also add extensions that add peripherals. Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-03-01Remove unnecessary parenthesisGravatar Hugues de Valon 1-2/+2
Otherwise Cargo complains! Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-02-05Merge #192Gravatar bors[bot] 3-94/+298
192: Update and improve cache operations. r=jonas-schievink a=adamgreig Closes #47, #188. I've implemented the proposed methods from #47 and marked all d-cache invalidation functions as unsafe. It's not unsafe to invalidate i-cache or branch predictor as they are read-only caches. The clean and clean+invalidate operations do not alter memory from the executing core's point of view so are also safe. It wasn't possible to remove the requirement to pass in `&mut CPUID` as you require synchronized access to `CPUID` to read the number of sets and ways in the cache, which is required to fully clean or invalidate them, which is required to enable or disable them. So it goes. Breaking change due to changing safety of d-cache invalidation functions. Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-02-04Add missing inline(always) and change more initialised->initializedGravatar Adam Greig 2-8/+9
2020-02-04Apply suggestions from code reviewGravatar Adam Greig 1-28/+28
Co-Authored-By: Jonas Schievink <jonasschievink@gmail.com>
2020-02-04Update documentation for cache functions; use dynamic cache line sizeGravatar Adam Greig 2-49/+124
2020-01-16Use a private field instead of `#[non_exhaustive]`Gravatar Jonas Schievink 1-1/+5
2020-01-16Make `Peripherals` `#[non_exhaustive]`Gravatar Jonas Schievink 1-0/+1
2020-01-16Clean up the doc examples in `peripheral`Gravatar Jonas Schievink 1-35/+22
The Clippy lint was unnecessarily `#[allow]`ed.
2020-01-15Update and improve cache operations.Gravatar Adam Greig 2-72/+200
Closes #47, #188. Breaking change due to changing safety of d-cache invalidation functions.
2020-01-15Merge #191Gravatar bors[bot] 3-87/+4
191: Remove deprecated APIs and the `const-fn` feature r=adamgreig a=jonas-schievink Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-01-15Remove deprecated APIs and the `const-fn` featureGravatar Jonas Schievink 3-87/+4
2020-01-15Fix typoGravatar Jonas Schievink 1-1/+1
2020-01-15Remove `aligned`, improve ITM codeGravatar Jonas Schievink 2-49/+64
2019-12-18Add Security Attribution Unit supportGravatar Hugues de Valon 2-1/+277
The SAU is a Armv8-M core peripheral that, alongside the Implementation Defined Attribution Unit, manages the security attribution of the memory zones. This driver provides abstraction to help setting the SAU up. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2019-11-26Add explanation about clippy::missing_inline_in_public_items lint.Gravatar Mara Bos 1-0/+14
2019-10-29Enable the missing_inline_in_public_items clippy lint.Gravatar Mara Bos 9-0/+17
2019-10-29Merge #171Gravatar bors[bot] 13-0/+103
171: Add `#[inline]` to lots of trivial functions. r=korken89 a=m-ou-se Now the only public non-inline functions left are: - `write_all` - `write_aligned` - All (derived) `Debug` implementations (Checked using Clippy's [`missing_inline_in_public_items`][1] lint.) [1]: https://rust-lang.github.io/rust-clippy/master/#missing_inline_in_public_items Co-authored-by: Mara Bos <m-ou.se@m-ou.se>
2019-10-29Merge #174Gravatar bors[bot] 6-9/+7
174: Enable clippy in CI r=thejpster a=m-ou-se Co-authored-by: Mara Bos <m-ou.se@m-ou.se>
2019-10-29Make clippy happy, again.Gravatar Mara Bos 6-9/+7
2019-10-29Merge #167Gravatar bors[bot] 1-3/+24
167: Deprecate basepri/basepri_max on thumbv8m.base r=korken89 a=JJJollyjim First step in resolving #155 Co-authored-by: Jamie McClymont <jamie@kwiius.com>
2019-10-29Add another missing #[inline].Gravatar Mara Bos 1-0/+1
2019-10-29Add `#[inline]` to some more functions.Gravatar Mara Bos 5-0/+27
Now the only public non-inline functions left are: - write_all - write_aligned - All (derived) Debug implementations (Checked using Clippy's missing_inline_in_public_items lint.)
2019-10-29Add `#[inline]` to lots of trivial functions.Gravatar Mara Bos 8-0/+75
2019-10-28Merge #172Gravatar bors[bot] 11-49/+53
172: Make Clippy happy. r=therealprof a=m-ou-se Co-authored-by: Mara Bos <m-ou.se@m-ou.se>
2019-10-15add a safe method to software unlock the DWTGravatar Jorge Aparicio 1-0/+9
today the alternative is an unsafe write to the LAR register
2019-10-09Make Clippy happy.Gravatar Mara Bos 11-49/+53
2019-09-21Deprecate nonexistent registers on thumbv8m.baseGravatar Jamie McClymont 1-3/+24
First step in resolving #155
2019-09-10Make some trivial functions eligible for inliningGravatar Jonas Schievink 1-0/+14
2019-09-08Remove unnecessary unsafe blockGravatar Jonas Schievink 1-1/+1
2019-09-08Fix errors and warningsGravatar Jonas Schievink 1-16/+14
2019-09-06Allow writing to the CONTROL registerGravatar Jonas Schievink 1-2/+63
2019-08-11Add {M,P}SPLIM access routines found on ARMv8-MGravatar Aurabindo Jayamohanan 3-0/+100
Signed-off-by: Aurabindo Jayamohanan <mail@aurabindo.in>
2019-07-29Fix missing `crate::`Gravatar Adam Greig 2-2/+2
2019-07-29Update for 2018 editionGravatar Adam Greig 13-70/+59
2019-07-24Define MSRV to be 1.31.0 and unconditionally use const-fnGravatar Adam Greig 1-4/+3
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