1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
|
//! Low level access to Cortex-M processors
//!
//! This crate provides access to:
//!
//! - Core peripherals like NVIC, SCB and SysTick.
//! - Core registers like CONTROL, MSP and PSR.
//! - Interrupt manipulation mechanisms
//! - Data structures like the vector table
//! - Miscellaneous assembly instructions like `bkpt`
#![cfg_attr(feature = "semihosting", feature(macro_reexport))]
#![cfg_attr(target_arch = "arm", feature(core_intrinsics))]
#![deny(missing_docs)]
#![deny(warnings)]
#![feature(asm)]
#![feature(const_fn)]
#![feature(naked_functions)]
#![no_std]
#[cfg(feature = "semihosting")]
pub extern crate cortex_m_semihosting as semihosting;
extern crate volatile_register;
#[macro_use]
mod macros;
#[macro_use]
pub mod asm;
pub mod exception;
pub mod interrupt;
pub mod peripheral;
pub mod register;
/// Stack frame
#[repr(C)]
pub struct StackFrame {
/// (General purpose) Register 0
pub r0: u32,
/// (General purpose) Register 1
pub r1: u32,
/// (General purpose) Register 2
pub r2: u32,
/// (General purpose) Register 3
pub r3: u32,
/// (General purpose) Register 12
pub r12: u32,
/// Linker Register
pub lr: u32,
/// Program Counter
pub pc: u32,
/// Program Status Register
pub xpsr: u32,
}
/// Vector Table
///
/// # References
///
/// - ARMv7-M Architecture Reference Manual (issue E.b) - Section B1.5 - ARMv7-M exception model
#[repr(C)]
pub struct VectorTable {
/// Reset value of the Main Stack Pointer (MSP)
pub sp_main: &'static (),
/// Reset
pub reset: extern "C" fn() -> !,
/// Non Maskable Interrupt
pub nmi: Option<Handler>,
/// Hard Fault
pub hard_fault: Option<Handler>,
/// Memory Management
pub mem_manage: Option<Handler>,
/// Bus Fault
pub bus_fault: Option<Handler>,
/// Usage Fault
pub usage_fault: Option<Handler>,
reserved0: [u32; 4],
/// Supervisor Call
pub svcall: Option<Handler>,
/// Debug Monitor
pub debug_monitor: Option<Handler>,
reserved1: u32,
/// PendSV
pub pendsv: Option<Handler>,
/// SysTick
pub sys_tick: Option<Handler>,
/// Interrupts. An IMPLEMENTATION DEFINED number of them.
pub interrupts: [Option<Handler>; 0],
}
/// A reserved spot in the vector table
#[derive(Clone, Copy)]
#[repr(u32)]
pub enum Reserved {
/// Reserved
Vector = 0,
}
/// Exception/Interrupt Handler
pub type Handler = unsafe extern "C" fn();
/// Returns the vector table
pub fn vector_table() -> &'static VectorTable {
unsafe { deref(peripheral::scb().vtor.read() as usize) }
}
#[cfg(test)]
fn address<T>(r: &T) -> usize {
r as *const T as usize
}
unsafe fn deref<T>(a: usize) -> &'static T {
&*(a as *const T)
}
unsafe fn deref_mut<T>(a: usize) -> &'static mut T {
&mut *(a as *mut T)
}
|
