blob: 46ab629b22336e42a990d021103a2be59fcd8fe6 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
#![no_main]
#![no_std]
extern crate cortex_m_rt;
#[cfg(target_env = "")] // appease clippy
#[panic_handler]
fn panic(info: &core::panic::PanicInfo) -> ! {
cortex_m::interrupt::disable();
minitest::log!("{}", info);
minitest::fail()
}
#[minitest::tests]
mod tests {
use minitest::log;
#[init]
fn init() -> cortex_m::Peripherals {
log!("Hello world!");
cortex_m::Peripherals::take().unwrap()
}
#[test]
fn double_take() {
assert!(cortex_m::Peripherals::take().is_none());
}
#[test]
#[cfg(not(feature = "semihosting"))] // QEMU does not model the cycle counter
fn cycle_count(p: &mut cortex_m::Peripherals) {
#[cfg(not(armv6m))]
{
use cortex_m::peripheral::DWT;
assert!(p.DWT.has_cycle_counter());
p.DCB.enable_trace();
p.DWT.disable_cycle_counter();
const TEST_COUNT: u32 = 0x5555_AAAA;
p.DWT.set_cycle_count(TEST_COUNT);
assert_eq!(DWT::cycle_count(), TEST_COUNT);
p.DWT.enable_cycle_counter();
assert!(DWT::cycle_count() > TEST_COUNT);
}
#[cfg(armv6m)]
{
assert!(!p.DWT.has_cycle_counter());
}
}
}
|