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authorGravatar bors[bot] <26634292+bors[bot]@users.noreply.github.com> 2022-07-27 19:15:09 +0000
committerGravatar GitHub <noreply@github.com> 2022-07-27 19:15:09 +0000
commitb87fca3d21d92018ac4d50b200cf8e77cb577028 (patch)
tree48f6da77b0c2ba1bb54e6ad8f30f5dad0e3765d7 /build.rs
parentd4816e054b556e326c5e3d4c40f7120372aafc50 (diff)
parent368ab1d4fb780386f3162c7a84502e301af7f3b0 (diff)
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Merge #652
652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check. Context: [cortex-m:src/register/mod.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/src/register/mod.rs#L33): ``` #[cfg(all(not(armv6m), not(armv8m_base)))] pub mod basepri; ``` [cortex-m:build.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/build.rs#L21): ``` } else if target.starts_with("thumbv8m.base") { println!("cargo:rustc-cfg=cortex_m"); println!("cargo:rustc-cfg=armv8m"); println!("cargo:rustc-cfg=armv8m_base"); ``` Co-authored-by: David Watson <david@neonquill.com>
Diffstat (limited to 'build.rs')
-rw-r--r--build.rs18
1 files changed, 12 insertions, 6 deletions
diff --git a/build.rs b/build.rs
index 7c518c90..ff9ebe35 100644
--- a/build.rs
+++ b/build.rs
@@ -7,15 +7,21 @@ fn main() {
println!("cargo:rustc-cfg=rustc_is_nightly");
}
- if target.starts_with("thumbv6m") {
- println!("cargo:rustc-cfg=armv6m");
- }
-
+ // These targets all have know support for the BASEPRI register.
if target.starts_with("thumbv7m")
| target.starts_with("thumbv7em")
- | target.starts_with("thumbv8m")
+ | target.starts_with("thumbv8m.main")
+ {
+ println!("cargo:rustc-cfg=have_basepri");
+
+ // These targets are all known to _not_ have the BASEPRI register.
+ } else if target.starts_with("thumb")
+ && !(target.starts_with("thumbv6m") | target.starts_with("thumbv8m.base"))
{
- println!("cargo:rustc-cfg=armv7m");
+ panic!(
+ "Unknown target '{}'. Need to update BASEPRI logic in build.rs.",
+ target
+ );
}
println!("cargo:rerun-if-changed=build.rs");