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authorGravatar Emil Fresk <emil.fresk@gmail.com> 2020-10-07 15:17:00 +0200
committerGravatar Emil Fresk <emil.fresk@gmail.com> 2020-10-07 15:17:00 +0200
commit6d003e20a83edc064b532d67853f27ec13f4fa4f (patch)
tree077b18048986d8d225ea4f80bfe7a9cd2996ae89 /examples/t-schedule-core-stable.rs
parent36781cdd890752d6876623d8802b860e950b24eb (diff)
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Now core contains the same `Peripherals` type based on monotonic
Diffstat (limited to 'examples/t-schedule-core-stable.rs')
-rw-r--r--examples/t-schedule-core-stable.rs28
1 files changed, 28 insertions, 0 deletions
diff --git a/examples/t-schedule-core-stable.rs b/examples/t-schedule-core-stable.rs
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+++ b/examples/t-schedule-core-stable.rs
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+//! [compile-pass] Check `schedule` code generation
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use panic_halt as _;
+
+#[rtic::app(device = lm3s6965, monotonic = rtic::cyccnt::CYCCNT)]
+mod app {
+ #[init]
+ fn init(c: init::Context) -> init::LateResources {
+ let _c: rtic::Peripherals = c.core;
+
+ init::LateResources {}
+ }
+
+ #[task]
+ fn some_task(_: some_task::Context) {}
+
+ // RTIC requires that unused interrupts are declared in an extern block when
+ // using software tasks; these free interrupts will be used to dispatch the
+ // software tasks.
+ extern "C" {
+ fn SSI0();
+ }
+}