diff options
author | 2019-06-13 23:56:59 +0200 | |
---|---|---|
committer | 2019-06-13 23:56:59 +0200 | |
commit | 81275bfa4f41e2066770087f3a33cad4227eab41 (patch) | |
tree | c779a68e7cecf4c2613c7593376f980cea5dbc05 /src/export.rs | |
parent | fafeeb27270ef24fc3852711c6032f65aa7dbcc0 (diff) | |
download | rtic-81275bfa4f41e2066770087f3a33cad4227eab41.tar.gz rtic-81275bfa4f41e2066770087f3a33cad4227eab41.tar.zst rtic-81275bfa4f41e2066770087f3a33cad4227eab41.zip |
rtfm-syntax refactor + heterogeneous multi-core support
Diffstat (limited to 'src/export.rs')
-rw-r--r-- | src/export.rs | 56 |
1 files changed, 41 insertions, 15 deletions
diff --git a/src/export.rs b/src/export.rs index afed9091..7646e3c5 100644 --- a/src/export.rs +++ b/src/export.rs @@ -1,21 +1,27 @@ -//! IMPLEMENTATION DETAILS. DO NOT USE ANYTHING IN THIS MODULE - -use core::{cell::Cell, u8}; +use core::{ + cell::Cell, + sync::atomic::{AtomicBool, Ordering}, +}; +pub use crate::tq::{NotReady, TimerQueue}; #[cfg(armv7m)] -use cortex_m::register::basepri; +pub use cortex_m::register::basepri; pub use cortex_m::{ - asm::wfi, interrupt, peripheral::scb::SystemHandler, peripheral::syst::SystClkSource, - peripheral::Peripherals, + asm::wfi, + interrupt, + peripheral::{scb::SystemHandler, syst::SystClkSource, DWT}, + Peripherals, }; -use heapless::spsc::SingleCore; -pub use heapless::{consts, i, spsc::Queue}; - -#[cfg(feature = "timer-queue")] -pub use crate::tq::{NotReady, TimerQueue}; +use heapless::spsc::{MultiCore, SingleCore}; +pub use heapless::{consts, i::Queue as iQueue, spsc::Queue}; +pub use heapless::{i::BinaryHeap as iBinaryHeap, BinaryHeap}; +#[cfg(feature = "heterogeneous")] +pub use microamp::shared; -pub type FreeQueue<N> = Queue<u8, N, u8, SingleCore>; -pub type ReadyQueue<T, N> = Queue<(T, u8), N, u8, SingleCore>; +pub type MCFQ<N> = Queue<u8, N, u8, MultiCore>; +pub type MCRQ<T, N> = Queue<(T, u8), N, u8, MultiCore>; +pub type SCFQ<N> = Queue<u8, N, u8, SingleCore>; +pub type SCRQ<T, N> = Queue<(T, u8), N, u8, SingleCore>; #[cfg(armv7m)] #[inline(always)] @@ -43,6 +49,26 @@ where f(); } +pub struct Barrier { + inner: AtomicBool, +} + +impl Barrier { + pub const fn new() -> Self { + Barrier { + inner: AtomicBool::new(false), + } + } + + pub fn release(&self) { + self.inner.store(true, Ordering::Release) + } + + pub fn wait(&self) { + while !self.inner.load(Ordering::Acquire) {} + } +} + // Newtype over `Cell` that forbids mutation through a shared reference pub struct Priority { inner: Cell<u8>, @@ -95,7 +121,7 @@ pub unsafe fn lock<T, R>( if current < ceiling { if ceiling == (1 << nvic_prio_bits) { - priority.set(u8::MAX); + priority.set(u8::max_value()); let r = interrupt::free(|_| f(&mut *ptr)); priority.set(current); r @@ -124,7 +150,7 @@ pub unsafe fn lock<T, R>( let current = priority.get(); if current < ceiling { - priority.set(u8::MAX); + priority.set(u8::max_value()); let r = interrupt::free(|_| f(&mut *ptr)); priority.set(current); r |