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author | 2017-07-20 16:13:02 -0500 | |
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committer | 2017-07-20 16:13:02 -0500 | |
commit | 6577f4a91aef8ea2626448d6b7985126f648b5db (patch) | |
tree | 0533a6bca74b1aeb5102ba3b23fc63d87c164e78 /src | |
parent | 877a32448fa9933d6f60ae1f25551751d4d651a8 (diff) | |
download | rtic-6577f4a91aef8ea2626448d6b7985126f648b5db.tar.gz rtic-6577f4a91aef8ea2626448d6b7985126f648b5db.tar.zst rtic-6577f4a91aef8ea2626448d6b7985126f648b5db.zip |
bump cortex-m version to v0.3.1
barrier! is no longer needed
Diffstat (limited to 'src')
-rw-r--r-- | src/lib.rs | 9 |
1 files changed, 0 insertions, 9 deletions
@@ -19,13 +19,6 @@ use cortex_m::interrupt::Nr; #[cfg(not(armv6m))] use cortex_m::register::{basepri_max, basepri}; -#[cfg(not(armv6m))] -macro_rules! barrier { - () => { - asm!("" ::: "memory" : "volatile"); - } -} - #[inline(always)] unsafe fn claim<T, U, R, F, G>( data: T, @@ -54,9 +47,7 @@ where let old = basepri::read(); let hw = (max_priority - ceiling) << (8 - nvic_prio_bits); basepri_max::write(hw); - barrier!(); let ret = f(g(data), &mut Threshold(ceiling)); - barrier!(); basepri::write(old); ret } |