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-rw-r--r--rtic-sync/CHANGELOG.md4
-rw-r--r--rtic-sync/src/arbiter.rs20
2 files changed, 22 insertions, 2 deletions
diff --git a/rtic-sync/CHANGELOG.md b/rtic-sync/CHANGELOG.md
index 1ffe6f02..8f0261a8 100644
--- a/rtic-sync/CHANGELOG.md
+++ b/rtic-sync/CHANGELOG.md
@@ -9,8 +9,8 @@ For each category, _Added_, _Changed_, _Fixed_ add new entries at the top!
### Added
-- `arbiter::spi::ArbiterDevice` for sharing SPI buses using `embedded-hal-async`
-- `arbiter::i2c::ArbiterDevice` for sharing I2C buses using `embedded-hal-async`
+- `arbiter::spi::ArbiterDevice` for sharing SPI buses using `embedded-hal-async` traits.
+- `arbiter::i2c::ArbiterDevice` for sharing I2C buses using `embedded-hal-async` traits.
### Changed
diff --git a/rtic-sync/src/arbiter.rs b/rtic-sync/src/arbiter.rs
index 615a7ed7..99d41748 100644
--- a/rtic-sync/src/arbiter.rs
+++ b/rtic-sync/src/arbiter.rs
@@ -352,6 +352,26 @@ pub mod i2c {
BUS: I2c<A>,
A: AddressMode,
{
+ async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> {
+ let mut bus = self.bus.access().await;
+ bus.read(address, read).await
+ }
+
+ async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> {
+ let mut bus = self.bus.access().await;
+ bus.write(address, write).await
+ }
+
+ async fn write_read(
+ &mut self,
+ address: A,
+ write: &[u8],
+ read: &mut [u8],
+ ) -> Result<(), Self::Error> {
+ let mut bus = self.bus.access().await;
+ bus.write_read(address, write, read).await
+ }
+
async fn transaction(
&mut self,
address: A,