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2023-03-01Add rtic-timer (timerqueue + monotonic) and rtic-monotonics (systick-monotonic)Gravatar Emil Fresk 3-555/+0
2023-03-01executor update for less unsafe and more clearGravatar Per Lindgren 1-19/+26
2023-03-01More work on new spawn/executorGravatar Emil Fresk 2-27/+9
2023-03-01New executor designGravatar Emil Fresk 2-67/+101
2023-03-01Start CI, disable docs buildingGravatar Emil Fresk 1-1/+1
2023-03-01Clippy fixesGravatar Emil Fresk 1-2/+2
2023-03-01Fix locks, basepri writeback errorGravatar Emil Fresk 1-1/+1
2023-03-01export Cell removed, expmples updatedGravatar Per Lindgren 1-4/+1
2023-03-01Removed Priority, simplified lifetime handlingGravatar Emil Fresk 1-78/+25
2023-03-01More removalGravatar Emil Fresk 4-758/+0
2023-03-01Even more cleanupGravatar Emil Fresk 1-70/+0
2023-03-01Old xtask test passGravatar Emil Fresk 4-76/+883
2023-03-01RTIC v2: Initial commitGravatar Emil Fresk 1-118/+9
rtic-syntax is now part of RTIC repository
2022-07-27Remove use of basepri register on thumbv8m.baseGravatar David Watson 1-41/+104
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-06-07fix ci: use SYST::PTRGravatar Jorge Aparicio 1-2/+2
SYST::ptr has been deprecated in cortex-m v0.7.5 SYST::PTR is available since cortex-m v0.7.0
2022-05-24Fix clash with defmtGravatar Emil Fresk 1-1/+3
2022-04-20Added check for resource usage and to generate an compile error for thumbv6 ↵Gravatar Emil Fresk 1-0/+10
exceptions
2022-04-20Masks take 3Gravatar Emil Fresk 1-0/+24
2022-03-02Added support for SRP based scheduling for armv6mGravatar Per Lindgren 1-13/+135
2022-02-22Clippy with pedantic suggestionsGravatar Henrik Tjäder 3-16/+16
2022-02-20Provide Mutex relative to prelude to fix doc linking issues coming from ↵Gravatar Henrik Tjäder 1-0/+1
rtic-core
2022-02-18rtic::mutex::prelude::* fixes glob import lintGravatar Henrik Tjäder 1-0/+5
rtic-core Mutex, Exclusive and multi-lock retained in old location to not be backwards breaking
2022-02-09Fix/mute clippy errorsGravatar Henrik Tjäder 1-0/+1
2021-12-25Docfix: MSRV and Semantic VersioningGravatar Per Lindgren 1-3/+3
2021-12-25Docfix: remove pre-release noteGravatar Per Lindgren 1-4/+1
2021-12-25Merge #565 #566Gravatar bors[bot] 1-0/+1
565: Edition: Bump to 2021 r=korken89 a=AfoHT 566: v1.0.0 r=korken89 a=AfoHT This should fail building until all deps are released and accessible on crates.io (There are some required PRs for edition2021 for each repo, alternatively just bringing in the v1.0 PR should have commits included, we can drop the extra PRs later on) https://github.com/rtic-rs/rtic-monotonic/pull/6 https://github.com/rtic-rs/rtic-core/pull/22 https://github.com/rtic-rs/rtic-syntax/pull/68 Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2021-12-25Clippy lintsGravatar Henrik Tjäder 2-1/+9
2021-12-25Edition: Bump to 2021Gravatar Henrik Tjäder 1-0/+1
2021-12-14Idle: Switch to NOP instead of WFIGravatar Henrik Tjäder 1-0/+1
Add example how to get old WFI behaviour
2021-11-25Remove #[deny(warnings)], but deny warnings for CIGravatar Henrik Tjäder 1-1/+1
2021-11-25Docs: add RTIC logoGravatar Henrik Tjäder 1-0/+4
2021-11-09New monotonic trait workingGravatar Emil Fresk 2-22/+7
2021-11-02added doc for RacyCellGravatar Per Lindgren 1-0/+21
2021-11-02Fixed aliasing issue due to RacyCell implementationGravatar Emil Fresk 1-6/+6
2021-09-28Fix export of SYSTGravatar Emil Fresk 1-1/+1
2021-09-27Fix a bug in the timer queue due to comparison bug in embedded-timeGravatar Emil Fresk 1-2/+5
2021-09-14Cleanup export and actually use rtic::export, made fn init inlineGravatar Emil Fresk 1-3/+4
2021-08-16Remove linked list impl - use heapless, linked list init now const fnGravatar Emil Fresk 4-605/+5
2021-07-09const genericsGravatar Andrey Zgarbul 3-46/+28
2021-06-06assert emptyGravatar James Hillyerd 1-0/+1
2021-06-06Allow zero sized LinkedListGravatar James Hillyerd 1-0/+12
2021-04-08Goodbye static mutGravatar Emil Fresk 1-0/+28
2021-04-08Fixed UB in `spawn_at`Gravatar Emil Fresk 1-2/+4
2021-03-22Updated schedule example with all combinationsGravatar Emil Fresk 1-1/+1
2021-03-20Cancel and reschedule workingGravatar Emil Fresk 3-16/+646
Support cfgs in the imports Account for extern tasks
2021-03-13Added interface for cancel/rescheduleGravatar Emil Fresk 2-232/+12
Use wrapping add for marker No need to store handle to queue Remove unnecessary `SpawnHandle::new` Fix test Updated interface to follow proposal
2021-02-25Review fixesGravatar Emil Fresk 1-1/+1
2021-02-22Updated to new interfaceGravatar Emil Fresk 1-3/+2
2021-02-22Added enable/disable timer callsGravatar Emil Fresk 1-1/+4
2021-02-22Of by 1Gravatar Emil Fresk 1-2/+2
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