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| author |  Gerd Zellweger <mail@gerdzellweger.com>
| 2018-05-03 16:07:44 -0700 |
|---|---|---|
| committer | Gerd Zellweger <mail@gerdzellweger.com>
| 2018-05-03 16:07:44 -0700 |
| commit | 24f14b623184b4220f2201a6be2aa1a177edc454 (patch) | |
| tree | 9cb237f91e6ce89953cebf97050a28c35dc94792 | |
| parent | b7b09f9396a842d22e305a11d2ee3e57ee76d75c (diff) | |
| download | rust-x86-24f14b623184b4220f2201a6be2aa1a177edc454.tar.gz rust-x86-24f14b623184b4220f2201a6be2aa1a177edc454.tar.zst rust-x86-24f14b623184b4220f2201a6be2aa1a177edc454.zip | |
Fix build by disabling compilation of pml4_index for 32-bit.
Signed-off-by: Gerd Zellweger <mail@gerdzellweger.com>
| -rw-r--r-- | src/bits64/paging.rs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/bits64/paging.rs b/src/bits64/paging.rs index 5a8068e..3d7a37a 100644 --- a/src/bits64/paging.rs +++ b/src/bits64/paging.rs @@ -1,6 +1,5 @@ //! Description of the data-structures for IA-32e paging mode. -/// Represents a physical memory address pub type PAddr = u64; pub type VAddr = usize; @@ -16,7 +15,6 @@ pub const MAXPHYADDR: u64 = 52; const ADDRESS_MASK: u64 = ((1 << MAXPHYADDR) - 1) & !0xfff; /// A PML4 table. -/// In practice this has only 4 entries but it still needs to be the size of a 4K page. pub type PML4 = [PML4Entry; 512]; /// A page directory pointer table. @@ -29,6 +27,7 @@ pub type PD = [PDEntry; 512]; pub type PT = [PTEntry; 512]; /// Given virtual address calculate corresponding entry in PML4. +#[cfg(target_arch="x86_64")] #[inline] pub fn pml4_index(addr: VAddr) -> usize { (addr >> 39) & 0b111111111 |