Formatting with new cargo fmt command.

Signed-off-by: Gerd Zellweger <mail@gerdzellweger.com>

15 files changed, 236 insertions, 106 deletions

diff --git a/src/controlregs.rs b/src/controlregs.rs
index b6cd334..c243caf 100644
--- a/src/controlregs.rs
+++ b/src/controlregs.rs
@@ -1,15 +1,13 @@
 //! Functions to read and write control registers.
 
-pub unsafe fn cr0() -> u64
-{
+pub unsafe fn cr0() -> u64 {
     let ret: u64;
     asm!("mov %cr0, $0" : "=r" (ret));
     ret
 }
 
 /// Write cr0.
-pub unsafe fn cr0_write(val: u64)
-{
+pub unsafe fn cr0_write(val: u64) {
     asm!("mov $0, %cr0" :: "r" (val) : "memory");
 }
 
diff --git a/src/dtables.rs b/src/dtables.rs
index 1aff96b..d2e3413 100644
--- a/src/dtables.rs
+++ b/src/dtables.rs
@@ -5,10 +5,10 @@
 #[derive(Debug)]
 #[repr(C, packed)]
 pub struct DescriptorTablePointer {
-   /// Size of the DT.
-   pub limit: u16,
-   /// Pointer to the memory region containing the DT.
-   pub base: u64
+    /// Size of the DT.
+    pub limit: u16,
+    /// Pointer to the memory region containing the DT.
+    pub base: u64,
 }
 
 /// Load GDT table.
@@ -24,4 +24,4 @@ pub unsafe fn lldt(ldt: &DescriptorTablePointer) {
 /// Load IDT table.
 pub unsafe fn lidt(idt: &DescriptorTablePointer) {
     asm!("lidt ($0)" :: "r" (idt) : "memory");
-}
\ No newline at end of file
+}
diff --git a/src/io.rs b/src/io.rs
index eded102..bb7cfb0 100644
--- a/src/io.rs
+++ b/src/io.rs
@@ -2,36 +2,36 @@
 
 /// Write 8 bits to port
 pub unsafe fn outb(port: u16, val: u8) {
-	asm!("outb %al, %dx" :: "{dx}"(port), "{al}"(val));
+    asm!("outb %al, %dx" :: "{dx}"(port), "{al}"(val));
 }
 
 /// Read 8 bits from port
 pub unsafe fn inb(port: u16) -> u8 {
-	let ret : u8;
-	asm!("inb %dx, %al" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
-	return ret;
+    let ret: u8;
+    asm!("inb %dx, %al" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
+    return ret;
 }
 
 /// Write 16 bits to port
 pub unsafe fn outw(port: u16, val: u16) {
-	asm!("outw %ax, %dx" :: "{dx}"(port), "{al}"(val));
+    asm!("outw %ax, %dx" :: "{dx}"(port), "{al}"(val));
 }
 
 /// Read 16 bits from port
 pub unsafe fn inw(port: u16) -> u16 {
-	let ret : u16;
-	asm!("inw %dx, %ax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
-	return ret;
+    let ret: u16;
+    asm!("inw %dx, %ax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
+    return ret;
 }
 
 /// Write 32 bits to port
 pub unsafe fn outl(port: u16, val: u32) {
-	asm!("outl %eax, %dx" :: "{dx}"(port), "{al}"(val));
+    asm!("outl %eax, %dx" :: "{dx}"(port), "{al}"(val));
 }
 
 /// Read 32 bits from port
 pub unsafe fn inl(port: u16) -> u32 {
-	let ret : u32;
-	asm!("inl %dx, %eax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
-	return ret;
+    let ret: u32;
+    asm!("inl %dx, %eax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
+    return ret;
 }
diff --git a/src/irq.rs b/src/irq.rs
index 6aa9beb..c7a90fa 100644
--- a/src/irq.rs
+++ b/src/irq.rs
@@ -9,43 +9,145 @@ pub struct InterruptDescription {
     pub mnemonic: &'static str,
     pub description: &'static str,
     pub irqtype: &'static str,
-    pub source: &'static str
+    pub source: &'static str,
 }
 
 impl fmt::Display for InterruptDescription {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "{} ({}, vec={}) {}", self.mnemonic, self.irqtype, self.vector, self.description)
+        write!(f,
+               "{} ({}, vec={}) {}",
+               self.mnemonic,
+               self.irqtype,
+               self.vector,
+               self.description)
     }
 }
 
 
 /// x86 External Interrupts (1-16).
-pub static EXCEPTIONS: [InterruptDescription; 15] = [
-    InterruptDescription{ vector: 0,  mnemonic: "#DE", description: "Divide Error", irqtype: "Fault", source: "DIV and IDIV instructions." },
-    InterruptDescription{ vector: 1,  mnemonic: "#DB", description: "RESERVED", irqtype: "Fault/ Trap", source: "For Intel use only." },
-    InterruptDescription{ vector: 2,  mnemonic: "NMI", description: "Interrupt", irqtype: "Interrupt", source: "Nonmaskable external interrupt." },
-    InterruptDescription{ vector: 3,  mnemonic: "#BP", description: "Breakpoint", irqtype: "Trap", source: "INT 3 instruction." },
-    InterruptDescription{ vector: 4,  mnemonic: "#OF", description: "Overflow", irqtype: "Trap", source: "INTO instruction." },
-    InterruptDescription{ vector: 5,  mnemonic: "#BR", description: "BOUND Range Exceeded", irqtype: "Fault", source: "BOUND instruction." },
-    InterruptDescription{ vector: 6,  mnemonic: "#UD", description: "Invalid Opcode (Undefined Opcode)", irqtype: "Fault", source: "UD2 instruction or reserved opcode." },
-    InterruptDescription{ vector: 7,  mnemonic: "#NM", description: "Device Not Available (No Math Coprocessor)", irqtype: "Fault", source: "Floating-point or WAIT/FWAIT instruction." },
-    InterruptDescription{ vector: 8,  mnemonic: "#DF", description: "Double Fault", irqtype: "Abort", source: "Any instruction that can generate an exception, an NMI, or an INTR." },
-    InterruptDescription{ vector: 9,  mnemonic: ""   , description: "Coprocessor Segment Overrun", irqtype: "Fault", source: "Floating-point instruction." },
-    InterruptDescription{ vector: 10, mnemonic: "#TS", description: "Invalid TSS", irqtype: "Fault", source: "Task switch or TSS access." },
-    InterruptDescription{ vector: 11, mnemonic: "#NP", description: "Segment Not Present", irqtype: "Fault", source: "Loading segment registers or accessing system segments." },
-    InterruptDescription{ vector: 12, mnemonic: "#SS", description: "Stack-Segment Fault", irqtype: "Fault", source: "Stack operations and SS register loads." },
-    InterruptDescription{ vector: 13, mnemonic: "#GP", description: "General Protection", irqtype: "Fault", source: "Any memory reference and other protection checks." },
-    InterruptDescription{ vector: 14, mnemonic: "#PF", description: "Page Fault", irqtype: "Fault", source: "Any memory reference." }
-];
+pub static EXCEPTIONS: [InterruptDescription; 15] = [InterruptDescription {
+                                                         vector: 0,
+                                                         mnemonic: "#DE",
+                                                         description: "Divide Error",
+                                                         irqtype: "Fault",
+                                                         source: "DIV and IDIV instructions.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 1,
+                                                         mnemonic: "#DB",
+                                                         description: "RESERVED",
+                                                         irqtype: "Fault/ Trap",
+                                                         source: "For Intel use only.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 2,
+                                                         mnemonic: "NMI",
+                                                         description: "Interrupt",
+                                                         irqtype: "Interrupt",
+                                                         source: "Nonmaskable external interrupt.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 3,
+                                                         mnemonic: "#BP",
+                                                         description: "Breakpoint",
+                                                         irqtype: "Trap",
+                                                         source: "INT 3 instruction.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 4,
+                                                         mnemonic: "#OF",
+                                                         description: "Overflow",
+                                                         irqtype: "Trap",
+                                                         source: "INTO instruction.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 5,
+                                                         mnemonic: "#BR",
+                                                         description: "BOUND Range Exceeded",
+                                                         irqtype: "Fault",
+                                                         source: "BOUND instruction.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 6,
+                                                         mnemonic: "#UD",
+                                                         description: "Invalid Opcode (Undefined \
+                                                                       Opcode)",
+                                                         irqtype: "Fault",
+                                                         source: "UD2 instruction or reserved \
+                                                                  opcode.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 7,
+                                                         mnemonic: "#NM",
+                                                         description: "Device Not Available (No \
+                                                                       Math Coprocessor)",
+                                                         irqtype: "Fault",
+                                                         source: "Floating-point or WAIT/FWAIT \
+                                                                  instruction.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 8,
+                                                         mnemonic: "#DF",
+                                                         description: "Double Fault",
+                                                         irqtype: "Abort",
+                                                         source: "Any instruction that can \
+                                                                  generate an exception, an NMI, \
+                                                                  or an INTR.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 9,
+                                                         mnemonic: "",
+                                                         description: "Coprocessor Segment Overrun",
+                                                         irqtype: "Fault",
+                                                         source: "Floating-point instruction.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 10,
+                                                         mnemonic: "#TS",
+                                                         description: "Invalid TSS",
+                                                         irqtype: "Fault",
+                                                         source: "Task switch or TSS access.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 11,
+                                                         mnemonic: "#NP",
+                                                         description: "Segment Not Present",
+                                                         irqtype: "Fault",
+                                                         source: "Loading segment registers or \
+                                                                  accessing system segments.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 12,
+                                                         mnemonic: "#SS",
+                                                         description: "Stack-Segment Fault",
+                                                         irqtype: "Fault",
+                                                         source: "Stack operations and SS register \
+                                                                  loads.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 13,
+                                                         mnemonic: "#GP",
+                                                         description: "General Protection",
+                                                         irqtype: "Fault",
+                                                         source: "Any memory reference and other \
+                                                                  protection checks.",
+                                                     },
+                                                     InterruptDescription {
+                                                         vector: 14,
+                                                         mnemonic: "#PF",
+                                                         description: "Page Fault",
+                                                         irqtype: "Fault",
+                                                         source: "Any memory reference.",
+                                                     }];
 
 
 /// Enable Interrupts.
-pub unsafe fn enable()  {
+pub unsafe fn enable() {
     asm!("sti");
 }
 
 /// Disable Interrupts.
-pub unsafe fn disable()  {
+pub unsafe fn disable() {
     asm!("cli");
 }
 
@@ -77,11 +179,10 @@ pub struct IdtEntry {
     /// The upper 48 bits of ISR (the last 16 bits must be zero).
     pub base_hi: u64,
     /// Must be zero.
-    pub res1: u16
+    pub res1: u16,
 }
 
 impl IdtEntry {
-
     /// Create a "missing" IdtEntry.  This is a `const` function, so we can
     /// call it at compile time to initialize static variables.
     ///
@@ -156,23 +257,29 @@ impl fmt::Debug for PageFaultError {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         let p = match self.contains(PFAULT_ERROR_P) {
             false => "The fault was caused by a non-present page.",
-            true => "The fault was caused by a page-level protection violation."
+            true => "The fault was caused by a page-level protection violation.",
         };
         let wr = match self.contains(PFAULT_ERROR_WR) {
             false => "The access causing the fault was a read.",
-            true => "The access causing the fault was a write."
+            true => "The access causing the fault was a write.",
         };
         let us = match self.contains(PFAULT_ERROR_US) {
-            false => "The access causing the fault originated when the processor was executing in supervisor mode.",
-            true => "The access causing the fault originated when the processor was executing in user mode."
+            false => {
+                "The access causing the fault originated when the processor was executing in \
+                 supervisor mode."
+            }
+            true => {
+                "The access causing the fault originated when the processor was executing in user \
+                 mode."
+            }
         };
         let rsvd = match self.contains(PFAULT_ERROR_RSVD) {
             false => "The fault was not caused by reserved bit violation.",
-            true => "The fault was caused by reserved bits set to 1 in a page directory."
+            true => "The fault was caused by reserved bits set to 1 in a page directory.",
         };
         let id = match self.contains(PFAULT_ERROR_ID) {
             false => "The fault was not caused by an instruction fetch.",
-            true => "The fault was caused by an instruction fetch."
+            true => "The fault was caused by an instruction fetch.",
         };
 
         write!(f, "{}\n{}\n{}\n{}\n{}", p, wr, us, rsvd, id)
@@ -187,4 +294,4 @@ fn bit_macro() {
     assert!(PFAULT_ERROR_US.bits() == 0b100);
     assert!(PFAULT_ERROR_WR.bits() == 0b10);
     assert!(PFAULT_ERROR_P.bits() == 0b1);
-}
\ No newline at end of file
+}
diff --git a/src/msr.rs b/src/msr.rs
index 445e6cc..6b4613a 100644
--- a/src/msr.rs
+++ b/src/msr.rs
@@ -1,4 +1,4 @@
-//!  MSR value list and function to read and write them.
+//! MSR value list and function to read and write them.
 
 /// Write 64 bits to msr register.
 pub unsafe fn wrmsr(msr: u32, value: u64) {
diff --git a/src/paging.rs b/src/paging.rs
index d6ae1a0..aa218d9 100644
--- a/src/paging.rs
+++ b/src/paging.rs
@@ -1,4 +1,4 @@
-//!  Description of the data-structures for IA-32e paging mode.
+//! Description of the data-structures for IA-32e paging mode.
 use core::fmt;
 
 /// Represents a physical memory address
@@ -92,8 +92,8 @@ impl fmt::UpperHex for VAddr {
 }
 
 pub const BASE_PAGE_SIZE: u64 = 4096; // 4 KiB
-pub const LARGE_PAGE_SIZE: u64 = 1024*1024*2; // 2 MiB
-pub const HUGE_PAGE_SIZE: u64 = 1024*1024*1024; // 1 GiB
+pub const LARGE_PAGE_SIZE: u64 = 1024 * 1024 * 2; // 2 MiB
+pub const HUGE_PAGE_SIZE: u64 = 1024 * 1024 * 1024; // 1 GiB
 pub const CACHE_LINE_SIZE: usize = 64; // 64 Bytes
 
 /// MAXPHYADDR, which is at most 52; (use CPUID for finding system value).
@@ -104,16 +104,16 @@ const ADDRESS_MASK: u64 = ((1 << MAXPHYADDR) - 1) & !0xfff;
 
 /// A PML4 table.
 /// In practice this has only 4 entries but it still needs to be the size of a 4K page.
-pub type PML4  = [PML4Entry; 512];
+pub type PML4 = [PML4Entry; 512];
 
 /// A page directory pointer table.
-pub type PDPT  = [PDPTEntry; 512];
+pub type PDPT = [PDPTEntry; 512];
 
 /// A page directory.
-pub type PD    = [PDEntry; 512];
+pub type PD = [PDEntry; 512];
 
 /// A page table.
-pub type PT    = [PTEntry; 512];
+pub type PT = [PTEntry; 512];
 
 /// Given virtual address calculate corresponding entry in PML4.
 pub fn pml4_index(addr: VAddr) -> usize {
@@ -166,7 +166,6 @@ bitflags! {
 
 
 impl PML4Entry {
-
     /// Creates a new PML4Entry.
     ///
     /// # Arguments
@@ -225,7 +224,6 @@ bitflags! {
 }
 
 impl PDPTEntry {
-
     /// Creates a new PDPTEntry.
     ///
     /// # Arguments
@@ -284,7 +282,6 @@ bitflags! {
 }
 
 impl PDEntry {
-
     /// Creates a new PDEntry.
     ///
     /// # Arguments
@@ -336,7 +333,6 @@ bitflags! {
 
 
 impl PTEntry {
-
     /// Creates a new PTEntry.
     ///
     /// # Arguments
@@ -346,7 +342,7 @@ impl PTEntry {
     pub fn new(page: PAddr, flags: PTEntry) -> PTEntry {
         let page_val = page.as_u64();
         assert!(page_val % BASE_PAGE_SIZE == 0);
-        PTEntry{ bits: page_val | flags.bits }
+        PTEntry { bits: page_val | flags.bits }
     }
 
     /// Retrieves the physical address in this entry.
diff --git a/src/perfcnt/intel/counters.rs b/src/perfcnt/intel/counters.rs
index 47495e6..e2987cc 100644
--- a/src/perfcnt/intel/counters.rs
+++ b/src/perfcnt/intel/counters.rs
@@ -9,4 +9,4 @@ use super::description::PebsType;
 use super::description::Tuple;
 use super::description::MSRIndex;
 
-include!(concat!(env!("OUT_DIR"), "/counters.rs"));
\ No newline at end of file
+include!(concat!(env!("OUT_DIR"), "/counters.rs"));
diff --git a/src/perfcnt/intel/description.rs b/src/perfcnt/intel/description.rs
index 6a2ae9a..f64426d 100644
--- a/src/perfcnt/intel/description.rs
+++ b/src/perfcnt/intel/description.rs
@@ -3,7 +3,7 @@ use std::fmt;
 pub enum PebsType {
     Regular,
     PebsOrRegular,
-    PebsOnly
+    PebsOnly,
 }
 
 impl fmt::Debug for PebsType {
@@ -19,7 +19,7 @@ impl fmt::Debug for PebsType {
 
 pub enum Tuple {
     One(u8),
-    Two(u8,u8)
+    Two(u8, u8),
 }
 
 impl fmt::Debug for Tuple {
@@ -34,7 +34,7 @@ impl fmt::Debug for Tuple {
 pub enum MSRIndex {
     None,
     One(u8),
-    Two(u8, u8)
+    Two(u8, u8),
 }
 
 impl fmt::Debug for MSRIndex {
@@ -68,7 +68,6 @@ impl fmt::Debug for Counter {
 
 #[derive(Debug)]
 pub struct IntelPerformanceCounterDescription {
-
     /// This field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs.
     ///
     /// The set of values for this field is defined architecturally.
@@ -180,7 +179,7 @@ pub struct IntelPerformanceCounterDescription {
     /// This field lists the known bugs that apply to the events.
     ///
     /// For the latest, up to date errata refer to the following links:
-    ////
+    /// /
     /// * Haswell:
     ///   http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf
     ///
@@ -199,20 +198,37 @@ pub struct IntelPerformanceCounterDescription {
 
     pub filter: Option<&'static str>,
 
-    pub extsel: bool
+    pub extsel: bool,
 }
 
 impl IntelPerformanceCounterDescription {
-
     #[allow(dead_code)]
-    fn new(event_code: Tuple, umask: Tuple, event_name: &'static str,
-           brief_description: &'static str, public_description: Option<&'static str>,
-           counter: Counter, counter_ht_off: Counter, pebs_counters: Option<Counter>,
-           sample_after_value: u64, msr_index: MSRIndex, msr_value: u64, taken_alone: bool,
-           counter_mask: u8, invert: bool, any_thread: bool, edge_detect: bool, pebs:
-           PebsType, precise_store: bool, data_la: bool, l1_hit_indication: bool,
-           errata: Option<&'static str>, offcore: bool, unit: Option<&'static str>,
-           filter: Option<&'static str>, extsel: bool) -> IntelPerformanceCounterDescription {
+    fn new(event_code: Tuple,
+           umask: Tuple,
+           event_name: &'static str,
+           brief_description: &'static str,
+           public_description: Option<&'static str>,
+           counter: Counter,
+           counter_ht_off: Counter,
+           pebs_counters: Option<Counter>,
+           sample_after_value: u64,
+           msr_index: MSRIndex,
+           msr_value: u64,
+           taken_alone: bool,
+           counter_mask: u8,
+           invert: bool,
+           any_thread: bool,
+           edge_detect: bool,
+           pebs: PebsType,
+           precise_store: bool,
+           data_la: bool,
+           l1_hit_indication: bool,
+           errata: Option<&'static str>,
+           offcore: bool,
+           unit: Option<&'static str>,
+           filter: Option<&'static str>,
+           extsel: bool)
+           -> IntelPerformanceCounterDescription {
 
         IntelPerformanceCounterDescription {
             event_code: event_code,
@@ -239,7 +255,7 @@ impl IntelPerformanceCounterDescription {
             offcore: offcore,
             unit: unit,
             filter: filter,
-            extsel: extsel
+            extsel: extsel,
         }
     }
 }
diff --git a/src/perfcnt/intel/mod.rs b/src/perfcnt/intel/mod.rs
index 99793be..960e0c6 100644
--- a/src/perfcnt/intel/mod.rs
+++ b/src/perfcnt/intel/mod.rs
@@ -1,4 +1,4 @@
 //! Information about Intel's performance counters.
 
 pub mod counters;
-pub mod description;
\ No newline at end of file
+pub mod description;
diff --git a/src/perfcnt/mod.rs b/src/perfcnt/mod.rs
index 431f00e..74b80a2 100644
--- a/src/perfcnt/mod.rs
+++ b/src/perfcnt/mod.rs
@@ -13,7 +13,7 @@ const MODEL_LEN: usize = 30;
 #[derive(Default)]
 struct ModelWriter {
     buffer: [u8; MODEL_LEN],
-    index: usize
+    index: usize,
 }
 
 impl ModelWriter {
@@ -27,7 +27,7 @@ impl Write for ModelWriter {
         // TODO: There exists probably a more efficient way of doing this:
         for c in s.chars() {
             if self.index >= self.buffer.len() {
-                return Err(Error)
+                return Err(Error);
             }
             self.buffer[self.index] = c as u8;
             self.index += 1;
@@ -75,4 +75,4 @@ fn counter_test() {
             assert!(p.event_name == "INST_RETIRED.ANY");
         });
     });
-}
\ No newline at end of file
+}
diff --git a/src/rflags.rs b/src/rflags.rs
index 2fadd51..6af25b1 100644
--- a/src/rflags.rs
+++ b/src/rflags.rs
@@ -53,4 +53,4 @@ impl RFlags {
     pub fn new() -> RFlags {
         RFLAGS_A1
     }
-}
\ No newline at end of file
+}
diff --git a/src/segmentation.rs b/src/segmentation.rs
index d2354d4..0a7ee15 100644
--- a/src/segmentation.rs
+++ b/src/segmentation.rs
@@ -27,11 +27,11 @@ impl SegmentSelector {
     ///  * `index` index in GDT or LDT array.
     ///
     pub fn new(index: u16) -> SegmentSelector {
-        SegmentSelector{bits: index << 3}
+        SegmentSelector { bits: index << 3 }
     }
 
-    pub fn from_raw(bits: u16) -> SegmentSelector{
-        SegmentSelector{bits: bits}
+    pub fn from_raw(bits: u16) -> SegmentSelector {
+        SegmentSelector { bits: bits }
     }
 }
 
@@ -39,27 +39,34 @@ impl fmt::Debug for SegmentSelector {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         let r0 = match self.contains(RPL_0) {
             false => "",
-            true => "Ring 0 segment selector."
+            true => "Ring 0 segment selector.",
         };
         let r1 = match self.contains(RPL_1) {
             false => "",
-            true => "Ring 1 segment selector."
+            true => "Ring 1 segment selector.",
         };
         let r2 = match self.contains(RPL_2) {
             false => "",
-            true => "Ring 2 segment selector."
+            true => "Ring 2 segment selector.",
         };
         let r3 = match self.contains(RPL_3) {
             false => "",
-            true => "Ring 3 segment selector."
+            true => "Ring 3 segment selector.",
         };
         let tbl = match self.contains(TI_LDT) {
             false => "GDT Table",
-            true => "LDT Table"
+            true => "LDT Table",
         };
 
-        write!(f, "Index {} in {}, {}{}{}{}", self.bits >> 3, tbl, r0, r1, r2, r3)
-        //write!(f, "Index")
+        write!(f,
+               "Index {} in {}, {}{}{}{}",
+               self.bits >> 3,
+               tbl,
+               r0,
+               r1,
+               r2,
+               r3)
+        // write!(f, "Index")
     }
 }
 
@@ -149,8 +156,8 @@ impl SegmentDescriptor {
         let limit_low: u64 = limit as u64 & 0xffff;
         let limit_high: u64 = (limit as u64 & (0b1111 << 16)) >> 16;
 
-        SegmentDescriptor{
-            bits: limit_low | base_low << 16 | limit_high << (32+16) | base_high << (32+24)
+        SegmentDescriptor {
+            bits: limit_low | base_low << 16 | limit_high << (32 + 16) | base_high << (32 + 24),
         }
     }
 }
diff --git a/src/syscall.rs b/src/syscall.rs
index 01d87fd..c554177 100644
--- a/src/syscall.rs
+++ b/src/syscall.rs
@@ -12,7 +12,6 @@
 /// * Only values of class INTEGER or class MEMORY are passed to the kernel.
 ///
 /// This code is inspired by the syscall.rs (https://github.com/kmcallister/syscall.rs/) project.
-
 #[macro_export]
 macro_rules! syscall {
     ($arg0:expr)
@@ -98,7 +97,14 @@ pub unsafe fn syscall5(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64, ar
 
 #[inline(always)]
 #[allow(unused_mut)]
-pub unsafe fn syscall6(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64, arg5: u64, arg6: u64) -> u64 {
+pub unsafe fn syscall6(arg0: u64,
+                       arg1: u64,
+                       arg2: u64,
+                       arg3: u64,
+                       arg4: u64,
+                       arg5: u64,
+                       arg6: u64)
+                       -> u64 {
     let mut ret: u64;
     asm!("syscall" : "={rax}" (ret)
                    : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3),
@@ -106,4 +112,4 @@ pub unsafe fn syscall6(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64, ar
                    : "rcx", "r11", "memory"
                    : "volatile");
     ret
-}
\ No newline at end of file
+}
diff --git a/src/task.rs b/src/task.rs
index c4e37bf..f37bd8d 100644
--- a/src/task.rs
+++ b/src/task.rs
@@ -26,11 +26,11 @@ pub struct TaskStateSegment {
 
 impl TaskStateSegment {
     pub fn new() -> TaskStateSegment {
-        TaskStateSegment{
+        TaskStateSegment {
             reserved: 0,
-            rsp: [0,0,0],
+            rsp: [0, 0, 0],
             reserved2: 0,
-            ist: [0,0,0,0,0,0,0],
+            ist: [0, 0, 0, 0, 0, 0, 0],
             reserved3: 0,
             reserved4: 0,
             iomap_base: 0,
@@ -41,4 +41,4 @@ impl TaskStateSegment {
 /// Load the task state register.
 pub unsafe fn load_ltr(sel: segmentation::SegmentSelector) {
     asm!("ltr $0" :: "r" (sel));
-}
\ No newline at end of file
+}
diff --git a/src/time.rs b/src/time.rs
index 7d402f4..eff567d 100644
--- a/src/time.rs
+++ b/src/time.rs
@@ -42,4 +42,4 @@ pub unsafe fn rdtscp() -> u64 {
 
     asm!("rdtscp" : "={eax}" (low), "={edx}" (high) ::: "volatile");
     ((high as u64) << 32) | (low as u64)
-}
\ No newline at end of file
+}