llvm_asm! instead of asm! to compile on nightly.

20 files changed, 84 insertions, 84 deletions

diff --git a/Cargo.toml b/Cargo.toml
index c72fd61..1c19cf6 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "x86"
-version = "0.31.0"
+version = "0.32.0"
 authors = [
   "Gerd Zellweger <mail@gerdzellweger.com>",
   "Eric Kidd <git@randomhacks.net>",
diff --git a/src/bits32/eflags.rs b/src/bits32/eflags.rs
index aa4d23e..94fe91d 100644
--- a/src/bits32/eflags.rs
+++ b/src/bits32/eflags.rs
@@ -70,14 +70,14 @@ impl EFlags {
 #[inline(always)]
 pub unsafe fn read() -> EFlags {
     let r: u32;
-    asm!("pushfl; popl $0" : "=r"(r) :: "memory");
+    llvm_asm!("pushfl; popl $0" : "=r"(r) :: "memory");
     EFlags::from_bits_truncate(r)
 }
 
 #[cfg(target_arch = "x86")]
 #[inline(always)]
 pub unsafe fn set(val: EFlags) {
-    asm!("pushl $0; popfl" :: "r"(val.bits()) : "memory" "flags");
+    llvm_asm!("pushl $0; popfl" :: "r"(val.bits()) : "memory" "flags");
 }
 
 /// Clears the AC flag bit in EFLAGS register.
@@ -92,7 +92,7 @@ pub unsafe fn set(val: EFlags) {
 /// that the CPU supports the instruction (check CPUID).
 #[inline(always)]
 pub unsafe fn clac() {
-    asm!("clac" ::: "memory" "flags" : "volatile");
+    llvm_asm!("clac" ::: "memory" "flags" : "volatile");
 }
 
 /// Sets the AC flag bit in EFLAGS register.
@@ -107,5 +107,5 @@ pub unsafe fn clac() {
 /// that the CPU supports the instruction (check CPUID).
 #[inline(always)]
 pub unsafe fn stac() {
-    asm!("stac" ::: "memory" "flags" : "volatile");
+    llvm_asm!("stac" ::: "memory" "flags" : "volatile");
 }
diff --git a/src/bits32/mod.rs b/src/bits32/mod.rs
index a90ef82..c7c1b75 100644
--- a/src/bits32/mod.rs
+++ b/src/bits32/mod.rs
@@ -6,6 +6,6 @@ pub mod task;
 
 #[inline(always)]
 pub unsafe fn stack_jmp(stack: *mut (), ip: *const ()) -> ! {
-    asm!("mov esp, $0; jmp $1" :: "rg"(stack), "r"(ip) :: "volatile", "intel");
+    llvm_asm!("mov esp, $0; jmp $1" :: "rg"(stack), "r"(ip) :: "volatile", "intel");
     loop {}
 }
diff --git a/src/bits32/segmentation.rs b/src/bits32/segmentation.rs
index b046035..ff9cc9d 100644
--- a/src/bits32/segmentation.rs
+++ b/src/bits32/segmentation.rs
@@ -8,7 +8,7 @@ use crate::segmentation::SegmentSelector;
 /// to reload cs and continue at 1:.
 #[cfg(target_arch = "x86")]
 pub unsafe fn load_cs(sel: SegmentSelector) {
-    asm!("pushl $0; \
+    llvm_asm!("pushl $0; \
           pushl $$1f; \
           lretl; \
           1:" :: "ri" (sel.bits() as u32) : "memory");
diff --git a/src/bits64/registers.rs b/src/bits64/registers.rs
index 73cba05..2700794 100644
--- a/src/bits64/registers.rs
+++ b/src/bits64/registers.rs
@@ -3,7 +3,7 @@
 pub fn rip() -> u64 {
     let rip: u64;
     unsafe {
-        asm!("leaq 0(%rip), $0" : "=r" (rip) ::);
+        llvm_asm!("leaq 0(%rip), $0" : "=r" (rip) ::);
     }
     rip
 }
@@ -13,7 +13,7 @@ pub fn rip() -> u64 {
 pub fn rsp() -> u64 {
     let rsp: u64;
     unsafe {
-        asm!("mov %rsp, $0" : "=r" (rsp) ::);
+        llvm_asm!("mov %rsp, $0" : "=r" (rsp) ::);
     }
     return rsp;
 }
@@ -23,7 +23,7 @@ pub fn rsp() -> u64 {
 pub fn rbp() -> u64 {
     let rbp: u64;
     unsafe {
-        asm!("mov %rbp, $0" : "=r" (rbp) ::);
+        llvm_asm!("mov %rbp, $0" : "=r" (rbp) ::);
     }
     return rbp;
 }
diff --git a/src/bits64/rflags.rs b/src/bits64/rflags.rs
index 970e19a..8f7bc6b 100644
--- a/src/bits64/rflags.rs
+++ b/src/bits64/rflags.rs
@@ -79,14 +79,14 @@ impl RFlags {
 #[inline(always)]
 pub unsafe fn read() -> RFlags {
     let r: u64;
-    asm!("pushfq; popq $0" : "=r"(r) :: "memory");
+    llvm_asm!("pushfq; popq $0" : "=r"(r) :: "memory");
     RFlags::from_bits_truncate(r)
 }
 
 #[cfg(target_arch = "x86_64")]
 #[inline(always)]
 pub unsafe fn set(val: RFlags) {
-    asm!("pushq $0; popfq" :: "r"(val.bits()) : "memory" "flags");
+    llvm_asm!("pushq $0; popfq" :: "r"(val.bits()) : "memory" "flags");
 }
 
 // clac and stac are also usable in 64-bit mode
diff --git a/src/bits64/segmentation.rs b/src/bits64/segmentation.rs
index cf6ccbd..1d67bf5 100644
--- a/src/bits64/segmentation.rs
+++ b/src/bits64/segmentation.rs
@@ -137,7 +137,7 @@ impl BuildDescriptor<Descriptor64> for DescriptorBuilder {
 /// to reload cs and continue at 1:.
 #[cfg(target_arch = "x86_64")]
 pub unsafe fn load_cs(sel: SegmentSelector) {
-    asm!("pushq $0; \
+    llvm_asm!("pushq $0; \
           leaq  1f(%rip), %rax; \
           pushq %rax; \
           lretq; \
@@ -148,14 +148,14 @@ pub unsafe fn load_cs(sel: SegmentSelector) {
 /// Needs FSGSBASE-Enable Bit (bit 16 of CR4) set.
 #[cfg(target_arch = "x86_64")]
 pub unsafe fn wrgsbase(base: u64) {
-    asm!("wrgsbase $0" :: "r" (base) : "memory");
+    llvm_asm!("wrgsbase $0" :: "r" (base) : "memory");
 }
 
 /// Write FS Segment Base
 /// Needs FSGSBASE-Enable Bit (bit 16 of CR4) set.
 #[cfg(target_arch = "x86_64")]
 pub unsafe fn wrfsbase(base: u64) {
-    asm!("wrfsbase $0" :: "r" (base) : "memory");
+    llvm_asm!("wrfsbase $0" :: "r" (base) : "memory");
 }
 
 /// Read GS Segment Base
@@ -163,7 +163,7 @@ pub unsafe fn wrfsbase(base: u64) {
 #[cfg(target_arch = "x86_64")]
 pub unsafe fn rdgsbase() -> u64 {
     let gs_base: u64;
-    asm!("rdgsbase $0" : "=r" (gs_base) );
+    llvm_asm!("rdgsbase $0" : "=r" (gs_base) );
     gs_base
 }
 
@@ -172,21 +172,21 @@ pub unsafe fn rdgsbase() -> u64 {
 #[cfg(target_arch = "x86_64")]
 pub unsafe fn rdfsbase() -> u64 {
     let fs_base: u64;
-    asm!("rdfsbase $0" : "=r" (fs_base) );
+    llvm_asm!("rdfsbase $0" : "=r" (fs_base) );
     fs_base
 }
 
 /// "Dereferences" the fs register at offset 0.
 pub unsafe fn fs_deref() -> u64 {
     let fs: u64;
-    asm!("movq %fs:0x0, $0" : "=r" (fs) );
+    llvm_asm!("movq %fs:0x0, $0" : "=r" (fs) );
     fs
 }
 
 /// "Dereferences" the gs register at offset 0.
 pub unsafe fn gs_deref() -> u64 {
     let gs: u64;
-    asm!("movq %gs:0x0, $0" : "=r" (gs) );
+    llvm_asm!("movq %gs:0x0, $0" : "=r" (gs) );
     gs
 }
 
@@ -201,5 +201,5 @@ pub unsafe fn gs_deref() -> u64 {
 /// The SWAPGS instruction is a privileged instruction intended for use by system software.
 #[cfg(target_arch = "x86_64")]
 pub unsafe fn swapgs() {
-    asm!("swapgs" ::: "gs");
+    llvm_asm!("swapgs" ::: "gs");
 }
diff --git a/src/bits64/sgx.rs b/src/bits64/sgx.rs
index eeb2640..09e8352 100644
--- a/src/bits64/sgx.rs
+++ b/src/bits64/sgx.rs
@@ -22,7 +22,7 @@ macro_rules! encls {
 unsafe fn encls2(rax: u64, rbx: u64) -> (u32, u64) {
     let eax: u32;
     let out_rbx: u64;
-    asm!("encls" : "={eax}" (eax), "={rbx}" (out_rbx)
+    llvm_asm!("encls" : "={eax}" (eax), "={rbx}" (out_rbx)
                  : "{rax}" (rax), "{rbx}" (rbx));
     (eax, out_rbx)
 }
@@ -31,7 +31,7 @@ unsafe fn encls2(rax: u64, rbx: u64) -> (u32, u64) {
 unsafe fn encls3(rax: u64, rbx: u64, rcx: u64) -> (u32, u64) {
     let eax: u32;
     let out_rbx: u64;
-    asm!("encls" : "={eax}" (eax), "={rbx}" (out_rbx)
+    llvm_asm!("encls" : "={eax}" (eax), "={rbx}" (out_rbx)
                  : "{rax}" (rax), "{rbx}" (rbx), "{rcx}" (rcx));
     (eax, out_rbx)
 }
@@ -40,7 +40,7 @@ unsafe fn encls3(rax: u64, rbx: u64, rcx: u64) -> (u32, u64) {
 unsafe fn encls4(rax: u64, rbx: u64, rcx: u64, rdx: u64) -> (u32, u64) {
     let eax: u32;
     let out_rbx: u64;
-    asm!("encls" : "={eax}" (eax), "={rbx}" (out_rbx)
+    llvm_asm!("encls" : "={eax}" (eax), "={rbx}" (out_rbx)
                  : "{rax}" (rax), "{rbx}" (rbx), "{rcx}" (rcx), "{rdx}" (rdx));
     (eax, out_rbx)
 }
@@ -252,7 +252,7 @@ macro_rules! enclu {
 unsafe fn enclu3(rax: u64, rbx: u64, rcx: u64) -> (u32, u64) {
     let eax: u32;
     let out_rcx: u64;
-    asm!("enclu" : "={eax}" (eax), "={rcx}" (out_rcx)
+    llvm_asm!("enclu" : "={eax}" (eax), "={rcx}" (out_rcx)
                  : "{rax}" (rax), "{rbx}" (rbx), "{rcx}" (rcx));
     (eax, out_rcx)
 }
@@ -261,7 +261,7 @@ unsafe fn enclu3(rax: u64, rbx: u64, rcx: u64) -> (u32, u64) {
 unsafe fn enclu4(rax: u64, rbx: u64, rcx: u64, rdx: u64) -> (u32, u64) {
     let eax: u32;
     let out_rcx: u64;
-    asm!("enclu" : "={eax}" (eax), "={rcx}" (out_rcx)
+    llvm_asm!("enclu" : "={eax}" (eax), "={rcx}" (out_rcx)
                  : "{rax}" (rax), "{rbx}" (rbx), "{rcx}" (rcx), "{rdx}" (rdx));
     (eax, out_rcx)
 }
diff --git a/src/bits64/syscall.rs b/src/bits64/syscall.rs
index be525f7..a4ad0f5 100644
--- a/src/bits64/syscall.rs
+++ b/src/bits64/syscall.rs
@@ -93,7 +93,7 @@ macro_rules! syscall {
 #[allow(unused_mut)]
 pub unsafe fn syscall0(arg0: u64) -> u64 {
     let mut ret: u64;
-    asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0) : "rcx", "r11", "memory" : "volatile");
+    llvm_asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0) : "rcx", "r11", "memory" : "volatile");
     ret
 }
 
@@ -101,7 +101,7 @@ pub unsafe fn syscall0(arg0: u64) -> u64 {
 #[allow(unused_mut)]
 pub unsafe fn syscall1(arg0: u64, arg1: u64) -> u64 {
     let mut ret: u64;
-    asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1)
+    llvm_asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1)
                    : "rcx", "r11", "memory" : "volatile");
     ret
 }
@@ -110,7 +110,7 @@ pub unsafe fn syscall1(arg0: u64, arg1: u64) -> u64 {
 #[allow(unused_mut)]
 pub unsafe fn syscall2(arg0: u64, arg1: u64, arg2: u64) -> u64 {
     let mut ret: u64;
-    asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2)
+    llvm_asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2)
                    : "rcx", "r11", "memory" : "volatile");
     ret
 }
@@ -119,7 +119,7 @@ pub unsafe fn syscall2(arg0: u64, arg1: u64, arg2: u64) -> u64 {
 #[allow(unused_mut)]
 pub unsafe fn syscall3(arg0: u64, arg1: u64, arg2: u64, arg3: u64) -> u64 {
     let mut ret: u64;
-    asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3)
+    llvm_asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3)
                    : "rcx", "r11", "memory" : "volatile");
     ret
 }
@@ -128,7 +128,7 @@ pub unsafe fn syscall3(arg0: u64, arg1: u64, arg2: u64, arg3: u64) -> u64 {
 #[allow(unused_mut)]
 pub unsafe fn syscall4(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64) -> u64 {
     let mut ret: u64;
-    asm!("syscall" : "={rax}" (ret)
+    llvm_asm!("syscall" : "={rax}" (ret)
                    : "{rax}"  (arg0), "{rdi}"  (arg1), "{rsi}"  (arg2), "{rdx}"  (arg3), "{r10}"  (arg4)
                    : "rcx", "r11", "memory" : "volatile");
     ret
@@ -138,7 +138,7 @@ pub unsafe fn syscall4(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64) ->
 #[allow(unused_mut)]
 pub unsafe fn syscall5(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64, arg5: u64) -> u64 {
     let mut ret: u64;
-    asm!("syscall" : "={rax}" (ret)
+    llvm_asm!("syscall" : "={rax}" (ret)
                    : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3), "{r10}" (arg4), "{r8}" (arg5)
                    : "rcx", "r11", "memory"
                    : "volatile");
@@ -157,7 +157,7 @@ pub unsafe fn syscall6(
     arg6: u64,
 ) -> u64 {
     let mut ret: u64;
-    asm!("syscall" : "={rax}" (ret)
+    llvm_asm!("syscall" : "={rax}" (ret)
                    : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3),
                      "{r10}" (arg4), "{r8}" (arg5), "{r9}" (arg6)
                    : "rcx", "r11", "memory"
diff --git a/src/bits64/vmx.rs b/src/bits64/vmx.rs
index 5330951..f64ece7 100644
--- a/src/bits64/vmx.rs
+++ b/src/bits64/vmx.rs
@@ -27,13 +27,13 @@ fn vmx_capture_status() -> Result<()> {
 /// `addr` specifies a 4KB-aligned physical address of VMXON region initialized
 /// in accordance with Intel SDM, Volume 3C, Section 24.11.5.
 pub unsafe fn vmxon(addr: u64) -> Result<()> {
-    asm!("vmxon $0" : /* no outputs */ : "m"(addr));
+    llvm_asm!("vmxon $0" : /* no outputs */ : "m"(addr));
     vmx_capture_status()
 }
 
 /// Disable VMX operation.
 pub unsafe fn vmxoff() -> Result<()> {
-    asm!("vmxoff");
+    llvm_asm!("vmxoff");
     vmx_capture_status()
 }
 
@@ -42,7 +42,7 @@ pub unsafe fn vmxoff() -> Result<()> {
 /// Ensures that VMCS data maintained on the processor is copied to the VMCS region
 /// located at 4KB-aligned physical address `addr` and initializes some parts of it.
 pub unsafe fn vmclear(addr: u64) -> Result<()> {
-    asm!("vmclear $0" : /* no outputs */ : "m"(addr));
+    llvm_asm!("vmclear $0" : /* no outputs */ : "m"(addr));
     vmx_capture_status()
 }
 
@@ -50,14 +50,14 @@ pub unsafe fn vmclear(addr: u64) -> Result<()> {
 ///
 /// Marks the current-VMCS pointer valid and loads it with the physical address `addr`.
 pub unsafe fn vmptrld(addr: u64) -> Result<()> {
-    asm!("vmptrld $0" : /* no outputs */ : "m"(addr));
+    llvm_asm!("vmptrld $0" : /* no outputs */ : "m"(addr));
     vmx_capture_status()
 }
 
 /// Return current VMCS pointer.
 pub unsafe fn vmptrst() -> Result<u64> {
     let value: u64 = 0;
-    asm!("vmptrst ($0)" : /* no outputs */ : "r"(&value) : "memory");
+    llvm_asm!("vmptrst ($0)" : /* no outputs */ : "r"(&value) : "memory");
     vmx_capture_status().and(Ok(value))
 }
 
@@ -65,27 +65,27 @@ pub unsafe fn vmptrst() -> Result<u64> {
 pub unsafe fn vmread(field: u32) -> Result<u64> {
     let field: u64 = field.into();
     let value: u64;
-    asm!("vmread $1, $0" : "=r"(value) : "r"(field));
+    llvm_asm!("vmread $1, $0" : "=r"(value) : "r"(field));
     vmx_capture_status().and(Ok(value))
 }
 
 /// Write to a specified field in a VMCS.
 pub unsafe fn vmwrite(field: u32, value: u64) -> Result<()> {
     let field: u64 = field.into();
-    asm!("vmwrite $1, $0" : /* no outputs */ : "r"(field), "r"(value));
+    llvm_asm!("vmwrite $1, $0" : /* no outputs */ : "r"(field), "r"(value));
     vmx_capture_status()
 }
 
 /// Launch virtual machine.
 #[inline(always)]
 pub unsafe fn vmlaunch() -> Result<()> {
-    asm!("vmlaunch");
+    llvm_asm!("vmlaunch");
     vmx_capture_status()
 }
 
 /// Resume virtual machine.
 #[inline(always)]
 pub unsafe fn vmresume() -> Result<()> {
-    asm!("vmresume");
+    llvm_asm!("vmresume");
     vmx_capture_status()
 }
diff --git a/src/controlregs.rs b/src/controlregs.rs
index 4138a37..00117ea 100644
--- a/src/controlregs.rs
+++ b/src/controlregs.rs
@@ -90,43 +90,43 @@ bitflags! {
 /// Read cr0
 pub unsafe fn cr0() -> Cr0 {
     let ret: usize;
-    asm!("mov %cr0, $0" : "=r" (ret));
+    llvm_asm!("mov %cr0, $0" : "=r" (ret));
     Cr0::from_bits_truncate(ret)
 }
 
 /// Write cr0.
 pub unsafe fn cr0_write(val: Cr0) {
-    asm!("mov $0, %cr0" :: "r" (val.bits) : "memory");
+    llvm_asm!("mov $0, %cr0" :: "r" (val.bits) : "memory");
 }
 
 /// Contains page-fault linear address.
 pub unsafe fn cr2() -> usize {
     let ret: usize;
-    asm!("mov %cr2, $0" : "=r" (ret));
+    llvm_asm!("mov %cr2, $0" : "=r" (ret));
     ret
 }
 
 /// Write cr2, for instance to reset cr2
 pub unsafe fn cr2_write(val: u64) {
-    asm!("mov $0, %cr2" :: "r" (val) : "memory");
+    llvm_asm!("mov $0, %cr2" :: "r" (val) : "memory");
 }
 
 /// Contains page-table root pointer.
 pub unsafe fn cr3() -> u64 {
     let ret: u64;
-    asm!("mov %cr3, $0" : "=r" (ret));
+    llvm_asm!("mov %cr3, $0" : "=r" (ret));
     ret
 }
 
 /// Switch page-table PML4 pointer.
 pub unsafe fn cr3_write(val: u64) {
-    asm!("mov $0, %cr3" :: "r" (val) : "memory");
+    llvm_asm!("mov $0, %cr3" :: "r" (val) : "memory");
 }
 
 /// Contains various flags to control operations in protected mode.
 pub unsafe fn cr4() -> Cr4 {
     let ret: usize;
-    asm!("mov %cr4, $0" : "=r" (ret));
+    llvm_asm!("mov %cr4, $0" : "=r" (ret));
     Cr4::from_bits_truncate(ret)
 }
 
@@ -142,7 +142,7 @@ pub unsafe fn cr4() -> Cr4 {
 /// }
 /// ```
 pub unsafe fn cr4_write(val: Cr4) {
-    asm!("mov $0, %cr4" :: "r" (val.bits) : "memory");
+    llvm_asm!("mov $0, %cr4" :: "r" (val.bits) : "memory");
 }
 
 /// Read Extended Control Register XCR0.
diff --git a/src/dtables.rs b/src/dtables.rs
index 2bbca40..780d6d4 100644
--- a/src/dtables.rs
+++ b/src/dtables.rs
@@ -56,12 +56,12 @@ impl<T> fmt::Debug for DescriptorTablePointer<T> {
 
 /// Load the GDTR register with the specified base and limit.
 pub unsafe fn lgdt<T>(gdt: &DescriptorTablePointer<T>) {
-    asm!("lgdt ($0)" :: "r" (gdt) : "memory");
+    llvm_asm!("lgdt ($0)" :: "r" (gdt) : "memory");
 }
 
 /// Retrieve base and limit from the GDTR register.
 pub unsafe fn sgdt<T>(idt: &mut DescriptorTablePointer<T>) {
-    asm!("sgdt ($0)" : "=r" (idt as *mut DescriptorTablePointer<T>) :: "memory");
+    llvm_asm!("sgdt ($0)" : "=r" (idt as *mut DescriptorTablePointer<T>) :: "memory");
 }
 
 /// Loads the segment selector into the selector field of the local
@@ -72,7 +72,7 @@ pub unsafe fn sgdt<T>(idt: &mut DescriptorTablePointer<T>) {
 /// the segment descriptor for the LDT in the global
 /// descriptor table (GDT).
 pub unsafe fn load_ldtr(selector: SegmentSelector) {
-    asm!("lldt $0" :: "r" (selector.bits()) : "memory");
+    llvm_asm!("lldt $0" :: "r" (selector.bits()) : "memory");
 }
 
 /// Returns the segment selector from the local descriptor table register (LDTR).
@@ -81,16 +81,16 @@ pub unsafe fn load_ldtr(selector: SegmentSelector) {
 /// (located in the GDT) for the current LDT.
 pub unsafe fn ldtr() -> SegmentSelector {
     let selector: u16;
-    asm!("sldt $0" : "=r"(selector));
+    llvm_asm!("sldt $0" : "=r"(selector));
     SegmentSelector::from_raw(selector)
 }
 
 /// Load the IDTR register with the specified base and limit.
 pub unsafe fn lidt<T>(idt: &DescriptorTablePointer<T>) {
-    asm!("lidt ($0)" :: "r" (idt) : "memory");
+    llvm_asm!("lidt ($0)" :: "r" (idt) : "memory");
 }
 
 /// Retrieve base and limit from the IDTR register.
 pub unsafe fn sidt<T>(idt: &mut DescriptorTablePointer<T>) {
-    asm!("sidt ($0)" : "=r" (idt as *mut DescriptorTablePointer<T>) :: "memory");
+    llvm_asm!("sidt ($0)" : "=r" (idt as *mut DescriptorTablePointer<T>) :: "memory");
 }
diff --git a/src/io.rs b/src/io.rs
index 27f9d49..6b1139b 100644
--- a/src/io.rs
+++ b/src/io.rs
@@ -3,42 +3,42 @@
 /// Write 8 bits to port
 #[inline]
 pub unsafe fn outb(port: u16, val: u8) {
-    asm!("outb %al, %dx" :: "{dx}"(port), "{al}"(val));
+    llvm_asm!("outb %al, %dx" :: "{dx}"(port), "{al}"(val));
 }
 
 /// Read 8 bits from port
 #[inline]
 pub unsafe fn inb(port: u16) -> u8 {
     let ret: u8;
-    asm!("inb %dx, %al" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
+    llvm_asm!("inb %dx, %al" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
     ret
 }
 
 /// Write 16 bits to port
 #[inline]
 pub unsafe fn outw(port: u16, val: u16) {
-    asm!("outw %ax, %dx" :: "{dx}"(port), "{al}"(val));
+    llvm_asm!("outw %ax, %dx" :: "{dx}"(port), "{al}"(val));
 }
 
 /// Read 16 bits from port
 #[inline]
 pub unsafe fn inw(port: u16) -> u16 {
     let ret: u16;
-    asm!("inw %dx, %ax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
+    llvm_asm!("inw %dx, %ax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
     ret
 }
 
 /// Write 32 bits to port
 #[inline]
 pub unsafe fn outl(port: u16, val: u32) {
-    asm!("outl %eax, %dx" :: "{dx}"(port), "{al}"(val));
+    llvm_asm!("outl %eax, %dx" :: "{dx}"(port), "{al}"(val));
 }
 
 /// Read 32 bits from port
 #[inline]
 pub unsafe fn inl(port: u16) -> u32 {
     let ret: u32;
-    asm!("inl %dx, %eax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
+    llvm_asm!("inl %dx, %eax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
     ret
 }
 
diff --git a/src/irq.rs b/src/irq.rs
index 5a29663..47b8e1e 100644
--- a/src/irq.rs
+++ b/src/irq.rs
@@ -352,7 +352,7 @@ impl fmt::Display for PageFaultError {
 /// # Safety
 /// Only allowed if we have IO privileges for the current operating level in RFlags.
 pub unsafe fn enable() {
-    asm!("sti");
+    llvm_asm!("sti");
 }
 
 /// Disable Interrupts.
@@ -360,7 +360,7 @@ pub unsafe fn enable() {
 /// # Safety
 /// Only allowed if we have IO privileges for the current operating level in RFlags.
 pub unsafe fn disable() {
-    asm!("cli");
+    llvm_asm!("cli");
 }
 
 /// Generate a software interrupt.
@@ -368,7 +368,7 @@ pub unsafe fn disable() {
 #[macro_export]
 macro_rules! int {
     ($x:expr) => {{
-        asm!("int $0" :: "N" ($x));
+        llvm_asm!("int $0" :: "N" ($x));
     }};
 }
 
diff --git a/src/lib.rs b/src/lib.rs
index 6892a7b..e361508 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,6 +1,6 @@
 #![cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 #![allow(stable_features)]
-#![feature(asm, core_intrinsics)]
+#![feature(llvm_asm, core_intrinsics)]
 #![no_std]
 #![cfg_attr(test, allow(unused_features))]
 #![cfg_attr(all(test, feature = "vmtest"), feature(custom_test_frameworks))]
@@ -88,7 +88,7 @@ pub enum Ring {
 /// Will cause a general protection fault if used outside of ring 0.
 #[inline(always)]
 pub unsafe fn halt() {
-    asm!("hlt" :::: "volatile");
+    llvm_asm!("hlt" :::: "volatile");
 }
 
 #[cfg(all(test, feature = "vmtest"))]
@@ -115,7 +115,7 @@ mod x86testing {
 #[inline(always)]
 pub unsafe fn rdpid() -> u64 {
     let mut pid: u64;
-    asm!("rdpid $0" : "=r"(pid));
+    llvm_asm!("rdpid $0" : "=r"(pid));
     return pid;
 }
 
diff --git a/src/msr.rs b/src/msr.rs
index 8abd46f..e8cbbb5 100644
--- a/src/msr.rs
+++ b/src/msr.rs
@@ -4,14 +4,14 @@
 pub unsafe fn wrmsr(msr: u32, value: u64) {
     let low = value as u32;
     let high = (value >> 32) as u32;
-    asm!("wrmsr" :: "{ecx}" (msr), "{eax}" (low), "{edx}" (high) : "memory" : "volatile" );
+    llvm_asm!("wrmsr" :: "{ecx}" (msr), "{eax}" (low), "{edx}" (high) : "memory" : "volatile" );
 }
 
 /// Read 64 bits msr register.
 #[allow(unused_mut)]
 pub unsafe fn rdmsr(msr: u32) -> u64 {
     let (high, low): (u32, u32);
-    asm!("rdmsr" : "={eax}" (low), "={edx}" (high) : "{ecx}" (msr) : "memory" : "volatile");
+    llvm_asm!("rdmsr" : "={eax}" (low), "={edx}" (high) : "{ecx}" (msr) : "memory" : "volatile");
     ((high as u64) << 32) | (low as u64)
 }
 
diff --git a/src/segmentation.rs b/src/segmentation.rs
index c58403e..878b643 100644
--- a/src/segmentation.rs
+++ b/src/segmentation.rs
@@ -554,27 +554,27 @@ impl Descriptor {
 
 /// Reload stack segment register.
 pub unsafe fn load_ss(sel: SegmentSelector) {
-    asm!("movw $0, %ss " :: "r" (sel.bits()) : "memory");
+    llvm_asm!("movw $0, %ss " :: "r" (sel.bits()) : "memory");
 }
 
 /// Reload data segment register.
 pub unsafe fn load_ds(sel: SegmentSelector) {
-    asm!("movw $0, %ds " :: "r" (sel.bits()) : "memory");
+    llvm_asm!("movw $0, %ds " :: "r" (sel.bits()) : "memory");
 }
 
 /// Reload es segment register.
 pub unsafe fn load_es(sel: SegmentSelector) {
-    asm!("movw $0, %es " :: "r" (sel.bits()) : "memory");
+    llvm_asm!("movw $0, %es " :: "r" (sel.bits()) : "memory");
 }
 
 /// Reload fs segment register.
 pub unsafe fn load_fs(sel: SegmentSelector) {
-    asm!("movw $0, %fs " :: "r" (sel.bits()) : "memory");
+    llvm_asm!("movw $0, %fs " :: "r" (sel.bits()) : "memory");
 }
 
 /// Reload gs segment register.
 pub unsafe fn load_gs(sel: SegmentSelector) {
-    asm!("movw $0, %gs " :: "r" (sel.bits()) : "memory");
+    llvm_asm!("movw $0, %gs " :: "r" (sel.bits()) : "memory");
 }
 
 pub use crate::current::segmentation::load_cs;
@@ -582,42 +582,42 @@ pub use crate::current::segmentation::load_cs;
 /// Returns the current value of the code segment register.
 pub fn cs() -> SegmentSelector {
     let segment: u16;
-    unsafe { asm!("mov %cs, $0" : "=r" (segment) ) };
+    unsafe { llvm_asm!("mov %cs, $0" : "=r" (segment) ) };
     SegmentSelector::from_raw(segment)
 }
 
 /// Returns the current value of the extra segment register.
 pub fn es() -> SegmentSelector {
     let segment: u16;
-    unsafe { asm!("mov %es, $0" : "=r" (segment) ) };
+    unsafe { llvm_asm!("mov %es, $0" : "=r" (segment) ) };
     SegmentSelector::from_raw(segment)
 }
 
 /// Returns the current value of the stack segment register.
 pub fn ss() -> SegmentSelector {
     let segment: u16;
-    unsafe { asm!("mov %ss, $0" : "=r" (segment) ) };
+    unsafe { llvm_asm!("mov %ss, $0" : "=r" (segment) ) };
     SegmentSelector::from_raw(segment)
 }
 
 /// Returns the current value of the data segment register.
 pub fn ds() -> SegmentSelector {
     let segment: u16;
-    unsafe { asm!("mov %ds, $0" : "=r" (segment) ) };
+    unsafe { llvm_asm!("mov %ds, $0" : "=r" (segment) ) };
     SegmentSelector::from_raw(segment)
 }
 
 /// Returns the current value of the FS segment register.
 pub fn fs() -> SegmentSelector {
     let segment: u16;
-    unsafe { asm!("mov %fs, $0" : "=r" (segment) ) };
+    unsafe { llvm_asm!("mov %fs, $0" : "=r" (segment) ) };
     SegmentSelector::from_raw(segment)
 }
 
 /// Returns the current value of the GS segment register.
 pub fn gs() -> SegmentSelector {
     let segment: u16;
-    unsafe { asm!("mov %gs, $0" : "=r" (segment) ) };
+    unsafe { llvm_asm!("mov %gs, $0" : "=r" (segment) ) };
     SegmentSelector::from_raw(segment)
 }
 
diff --git a/src/task.rs b/src/task.rs
index e71ea8f..40fdc2c 100644
--- a/src/task.rs
+++ b/src/task.rs
@@ -6,11 +6,11 @@ pub use crate::segmentation;
 /// Returns the current value of the task register.
 pub fn tr() -> segmentation::SegmentSelector {
     let segment: u16;
-    unsafe { asm!("str $0" : "=r" (segment) ) };
+    unsafe { llvm_asm!("str $0" : "=r" (segment) ) };
     segmentation::SegmentSelector::from_raw(segment)
 }
 
 /// Loads the task register.
 pub unsafe fn load_tr(sel: segmentation::SegmentSelector) {
-    asm!("ltr $0" :: "r" (sel.bits()));
+    llvm_asm!("ltr $0" :: "r" (sel.bits()));
 }
diff --git a/src/tlb.rs b/src/tlb.rs
index 37014e9..e89a3ed 100644
--- a/src/tlb.rs
+++ b/src/tlb.rs
@@ -6,7 +6,7 @@
 /// This function is unsafe as it causes a general protection fault (GP) if the current privilege
 /// level is not 0.
 pub unsafe fn flush(addr: usize) {
-    asm!("invlpg ($0)" :: "r" (addr) : "memory");
+    llvm_asm!("invlpg ($0)" :: "r" (addr) : "memory");
 }
 
 /// Invalidate the TLB completely by reloading the CR3 register.
diff --git a/x86test/README.md b/x86test/README.md
index 7e0f443..cb97e08 100644
--- a/x86test/README.md
+++ b/x86test/README.md
@@ -30,7 +30,7 @@ For example say we have a function like this:
 #[inline]
 pub unsafe fn inw(port: u16) -> u16 {
     let ret: u16;
-    asm!("inw %dx, %ax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
+    llvm_asm!("inw %dx, %ax" : "={ax}"(ret) : "{dx}"(port) :: "volatile");
     ret
 }
 ```