Added performance counter data.

112 files changed, 210397 insertions, 12 deletions

diff --git a/Cargo.toml b/Cargo.toml
index ba6a4cc..9f1972e 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 
 name = "x86"
-version = "0.3.1"
+version = "0.4.0"
 authors = ["Gerd Zellweger <mail@gerdzellweger.com>"]
 
 description = "Library to program x86 (amd64) hardware. Contains x86 specific data structure descriptions, data-tables, as well as convenience function to call assembly instructions typically not exposed in higher level languages."
@@ -9,11 +9,25 @@ description = "Library to program x86 (amd64) hardware. Contains x86 specific da
 homepage = "https://github.com/gz/rust-x86"
 repository = "https://github.com/gz/rust-x86"
 documentation = "http://gz.github.io/rust-x86/x86/"
-
 readme = "README.md"
 keywords = ["ia32", "os", "amd64", "x86", "x86-64"]
 license = "MIT"
 
+build = "build.rs"
+
+[build-dependencies.phf_codegen]
+phf_codegen = "0.7.5"
+
+[build-dependencies.serde_json]
+serde_json = "0.6.0"
+
+[build-dependencies.csv]
+csv = "0.14.3"
+
 [dependencies]
 bitflags = "0.1.0"
-raw-cpuid = "1.*"
\ No newline at end of file
+raw-cpuid = "1.*"
+
+[dependencies.phf]
+git = "https://github.com/sfackler/rust-phf.git"
+features = ["core"]
diff --git a/build.rs b/build.rs
new file mode 100644
index 0000000..a459ad1
--- /dev/null
+++ b/build.rs
@@ -0,0 +1,376 @@
+#![feature(convert)]
+
+extern crate phf_codegen;
+extern crate serde_json;
+extern crate csv;
+
+use std::ascii::AsciiExt;
+use std::env;
+use std::fs::File;
+use std::io::{BufWriter, BufReader, Write};
+use std::path::Path;
+use std::collections::HashMap;
+use std::mem;
+
+use serde_json::Value;
+
+include!(concat!(env!("CARGO_MANIFEST_DIR"), "/src/perfcnt/intel/description.rs"));
+
+/// We need to convert parsed strings to static because we're reusing
+/// the struct definition which declare strings (rightfully) as
+/// static in the generated code.
+fn string_to_static_str<'a>(s: &'a str) -> &'static str {
+    unsafe {
+        let ret = mem::transmute(&s as &str);
+        mem::forget(s);
+        ret
+    }
+}
+
+fn parse_bool(input: &str) -> bool {
+    match input.trim() {
+        "0" => false,
+        "1" => true,
+        _ => panic!("Unknown boolean value {}", input),
+    }
+}
+
+fn parse_performance_counters(input: &str, variable: &str, file: &mut BufWriter<File>) {
+    let mut builder = phf_codegen::Map::new();
+    let f = File::open(input).unwrap();
+    let reader = BufReader::new(f);
+    let data: Value = serde_json::from_reader(reader).unwrap();
+    let mut all_events = HashMap::new();
+
+    if data.is_array() {
+        let entries = data.as_array().unwrap();
+        for entry in entries.iter() {
+
+            if !entry.is_object() {
+                panic!("Expected JSON object.");
+            }
+
+            let mut event_code = Tuple::One(0);
+            let mut umask = Tuple::One(0);
+            let mut event_name = "";
+            let mut brief_description = "";
+            let mut public_description = None;
+            let mut counter = Counter::Fixed(0);
+            let mut counter_ht_off = Counter::Fixed(0);
+            let mut pebs_counters = None;
+            let mut sample_after_value = 0;
+            let mut msr_index = MSRIndex::None;
+            let mut msr_value = 0;
+            let mut taken_alone = false;
+            let mut counter_mask = 0;
+            let mut invert = false;
+            let mut any_thread = false;
+            let mut edge_detect = false;
+            let mut pebs = PebsType::Regular;
+            let mut precise_store = false;
+            let mut data_la = false;
+            let mut l1_hit_indication = false;
+            let mut errata = None;
+            let mut offcore = false;
+
+            let mut do_insert: bool = false;
+
+            let pcn = entry.as_object().unwrap();
+            for (key, value) in pcn.iter() {
+                if !value.is_string() {
+                    panic!("Not a string");
+                }
+                let value_string = value.as_string().unwrap();
+                let value_str = string_to_static_str(value_string).trim();
+                let split_str_parts: Vec<&str> = value_string.split(",").map(|x| x.trim()).collect();
+
+                match key.as_str() {
+                    "EventName" => {
+                        if !all_events.contains_key(value_str.clone()) {
+                            all_events.insert(value_str, 0);
+                            assert!(all_events.contains_key(value_str));
+                            do_insert = true;
+                        }
+                        else {
+                            do_insert = false;
+                            println!("WARN: Key {} already exists.", value_str);
+                        }
+                        event_name = value_str;
+                    }
+
+                    "EventCode" => {
+                        let split_parts: Vec<u64> = split_str_parts.iter()
+                            .map(|x| { assert!(x.starts_with("0x")); u64::from_str_radix(&x[2..], 16).unwrap() })
+                            .collect();
+
+                        match split_parts.len() {
+                            1 => event_code = Tuple::One(split_parts[0] as u8),
+                            2 => event_code = Tuple::Two(split_parts[0] as u8, split_parts[1] as u8),
+                            _ => panic!("More than two event codes?")
+                        }
+                    },
+
+                    "UMask" => {
+                        let split_parts: Vec<u64> = split_str_parts.iter()
+                            .map(|x| { assert!(x.starts_with("0x")); u64::from_str_radix(&x[2..], 16).unwrap() })
+                            .collect();
+
+                        match split_parts.len() {
+                            1 => umask = Tuple::One(split_parts[0] as u8),
+                            2 => umask = Tuple::Two(split_parts[0] as u8, split_parts[1] as u8),
+                            _ => panic!("More than two event codes?")
+                        }
+                    },
+
+                    "BriefDescription" => brief_description = value_str,
+
+                    "PublicDescription" => {
+                        if brief_description != value_str && value_str != "tbd" {
+                            public_description = Some(value_str);
+                        }
+                        else {
+                            public_description = None;
+                        }
+                    },
+
+                    "Counter" => {
+                        if value_str.starts_with("Fixed counter") {
+                            let mask: u64 = value_str["Fixed counter".len()..]
+                                .split(",")
+                                .map(|x| x.trim())
+                                .map(|x| u64::from_str_radix(&x, 10).unwrap())
+                                .fold(0, |acc, c| { assert!(c < 8); acc | 1 << c });
+                            counter = Counter::Fixed(mask as u8);
+                        }
+                        else {
+                            let mask: u64 = value_str
+                                .split(",")
+                                .map(|x| x.trim())
+                                .map(|x| u64::from_str_radix(&x, 10).unwrap())
+                                .fold(0, |acc, c| { assert!(c < 8); acc | 1 << c });
+                            counter = Counter::Programmable(mask as u8);
+                        }
+                    },
+
+                    "CounterHTOff" => {
+                        if value_str.starts_with("Fixed counter") {
+                            let mask: u64 = value_str["Fixed counter".len()..]
+                                .split(",")
+                                .map(|x| x.trim())
+                                .map(|x| u64::from_str_radix(&x, 10).unwrap())
+                                .fold(0, |acc, c| { assert!(c < 8); acc | 1 << c });
+                            counter_ht_off = Counter::Fixed(mask as u8);
+                        }
+                        else {
+                            let mask: u64 = value_str
+                                .split(",")
+                                .map(|x| x.trim())
+                                .map(|x| u64::from_str_radix(&x, 10).unwrap())
+                                .fold(0, |acc, c| { assert!(c < 8); acc | 1 << c });
+                            counter_ht_off = Counter::Programmable(mask as u8);
+                        }
+                    },
+
+                    "PEBScounters" => {
+                        if value_str.starts_with("Fixed counter") {
+                            let mask: u64 = value_str["Fixed counter".len()..]
+                                .split(",")
+                                .map(|x| x.trim())
+                                .map(|x| u64::from_str_radix(&x, 10).unwrap())
+                                .fold(0, |acc, c| { assert!(c < 8); acc | 1 << c });
+                            pebs_counters = Some(Counter::Fixed(mask as u8));
+                        }
+                        else {
+                            let mask: u64 = value_str
+                                .split(",")
+                                .map(|x| x.trim())
+                                .map(|x| u64::from_str_radix(&x, 10).unwrap())
+                                .fold(0, |acc, c| { assert!(c < 8); acc | 1 << c });
+                            pebs_counters = Some(Counter::Programmable(mask as u8));
+                        }
+                    },
+
+                    "SampleAfterValue" => sample_after_value = u64::from_str_radix(&value_str, 10).unwrap(),
+
+                    "MSRIndex" => {
+                        let split_parts: Vec<u64> = value_str
+                            .split(",")
+                            .map(|x| x.trim())
+                            .map(|x| {
+                                if x.len() > 2 && x[..2].starts_with("0x") {
+                                    u64::from_str_radix(&x[2..], 16).unwrap()
+                                }
+                                else {
+                                    u64::from_str_radix(&x, 10).unwrap()
+                                }
+                            })
+                            .collect();
+
+                            msr_index = match split_parts.len() {
+                                1 => {
+                                    if split_parts[0] != 0 {
+                                        MSRIndex::One(split_parts[0] as u8)
+                                    }
+                                    else {
+                                        MSRIndex::None
+                                    }
+                                },
+                                2 => MSRIndex::Two(split_parts[0] as u8, split_parts[1] as u8),
+                                _ => panic!("More than two MSR indexes?")
+                            }
+                    },
+                    "MSRValue" => {
+                        msr_value = if value_str.len() > 2 && value_str[..2].starts_with("0x") {
+                            u64::from_str_radix(&value_str[2..], 16).unwrap()
+                        }
+                        else {
+                            u64::from_str_radix(&value_str, 10).unwrap()
+                        }
+                    },
+                    "TakenAlone" => {
+                        taken_alone = parse_bool(value_str);
+                    },
+                    "CounterMask" => {
+                        counter_mask = if value_str.len() > 2 && value_str[..2].starts_with("0x") {
+                            u8::from_str_radix(&value_str[2..], 16).unwrap()
+                        }
+                        else {
+                            u8::from_str_radix(&value_str, 10).unwrap()
+                        }
+                    },
+                    "Invert" => {
+                        invert = parse_bool(value_str);
+                    }
+                    "AnyThread" => any_thread = parse_bool(value_str),
+                    "EdgeDetect" => edge_detect = parse_bool(value_str),
+                    "PEBS" => {
+                        pebs = match value_str.trim() {
+                            "0" => PebsType::Regular,
+                            "1" => PebsType::PebsOrRegular,
+                            "2" => PebsType::PebsOnly,
+                            _ => panic!("Unknown PEBS type: {}", value_str),
+                        }
+                    },
+                    "PRECISE_STORE" => precise_store = parse_bool(value_str),
+                    "Data_LA" => data_la = parse_bool(value_str),
+                    "L1_Hit_Indication" => l1_hit_indication = parse_bool(value_str),
+                    "Errata" => {
+                        errata = if value_str != "null" {
+                            Some(value_str)
+                        }
+                        else {
+                            None
+                        };
+                    },
+                    "Offcore" => offcore = parse_bool(value_str),
+                    "ELLC" => {
+                        // Ignored due to missing documentation.
+                    },
+                    _ => panic!("Unknown member: {} in file {}", key, input),
+                };
+            }
+
+            let ipcd = IntelPerformanceCounterDescription::new(
+                event_code,
+                umask,
+                event_name,
+                brief_description,
+                public_description,
+                counter,
+                counter_ht_off,
+                pebs_counters,
+                sample_after_value,
+                msr_index,
+                msr_value,
+                taken_alone,
+                counter_mask,
+                invert,
+                any_thread,
+                edge_detect,
+                pebs,
+                precise_store,
+                data_la,
+                l1_hit_indication,
+                errata,
+                offcore
+            );
+
+            //println!("{:?}", ipcd.event_name);
+            if do_insert == true {
+                builder.entry(ipcd.event_name, format!("{:?}", ipcd).as_str());
+            }
+        }
+    }
+    else {
+        panic!("JSON data is not an array.");
+    }
+
+
+    write!(file, "pub static {}: phf::Map<&'static str, IntelPerformanceCounterDescription> = ", variable).unwrap();
+    builder.build(file).unwrap();
+    write!(file, ";\n").unwrap();
+}
+
+fn make_file_name<'a>(path: &'a Path) -> (String, String) {
+    let stem = path.file_stem().unwrap().to_str().unwrap();
+
+    // File name without _core*.json
+    println!("{:?}", stem);
+    let core_start = stem.find("_core").unwrap();
+    let (output_file, _) = stem.split_at(core_start);
+
+    // File name without _V*.json at the end:
+    let version_start = stem.find("_V").unwrap();
+    let (variable, _) = stem.split_at(version_start);
+    let uppercase = variable.to_ascii_uppercase();
+    let variable_clean = uppercase.replace("-", "_");
+    let variable_upper = variable_clean.as_str();
+
+    (output_file.to_string(), variable_upper.to_string())
+}
+
+fn main() {
+    let mut rdr = csv::Reader::from_file("./x86data/perfmon_data/mapfile.csv").unwrap();
+    let mut data_files = HashMap::new();
+
+    // Parse CSV
+    for record in rdr.decode() {
+        let (family_model, version, file_name, event_type): (String, String, String, String) = record.unwrap();
+        // TODO: Parse offcore counter descriptions.
+        if file_name.contains("_core_") && !data_files.contains_key(&file_name) {
+            data_files.insert(file_name.clone(), (family_model, version, event_type));
+        }
+    }
+
+    // build hash-table to select performance counter per CPU architecture
+    let path = Path::new(&env::var("OUT_DIR").unwrap()).join("counters.rs");
+    let mut filewriter = BufWriter::new(File::create(&path).unwrap());
+
+    let mut builder = phf_codegen::Map::new();
+    for (file, data) in &data_files {
+        let (ref family_model, _, _): (String, String, String) = *data;
+        let path = Path::new(file.as_str());
+        let (_, ref variable_upper) = make_file_name(&path);
+
+        builder.entry(family_model.as_str(), format!("&{}", variable_upper.as_str()).as_str());
+    }
+
+    write!(&mut filewriter, "pub static {}: phf::Map<&'static str, &'static phf::Map<&'static str, IntelPerformanceCounterDescription>> = ", "COUNTER_MAP").unwrap();
+    builder.build(&mut filewriter).unwrap();
+    write!(&mut filewriter, ";\n").unwrap();
+
+    // Parse all json files and write hash-tables from it
+    // TODO: Parse offcore counter descriptions.
+    for (file, data) in &data_files {
+        if file.contains("_core_") {
+            let (ref family_model, ref version, ref event_type): (String, String, String) = *data;
+            println!("Processing {:?} {} {} {}", file, family_model, version, event_type);
+
+            let path = Path::new(file.as_str());
+            let (_, ref variable_upper) = make_file_name(&path);
+            parse_performance_counters(format!("x86data/perfmon_data{}", file).as_str(),
+                                       variable_upper, &mut filewriter);
+        }
+    }
+
+}
diff --git a/src/lib.rs b/src/lib.rs
index 0c06be5..79a60c3 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -5,17 +5,22 @@
 #![crate_name = "x86"]
 #![crate_type = "lib"]
 
+#[cfg(test)]
+#[macro_use]
+extern crate std;
+
 #[macro_use]
 extern crate bitflags;
 
 #[macro_use]
 extern crate raw_cpuid;
 
-#[cfg(test)]
-extern crate std;
+#[macro_use]
+extern crate phf;
 
 #[cfg(not(test))]
 mod std {
+    pub use core::fmt;
     pub use core::ops;
     pub use core::option;
 }
@@ -31,6 +36,7 @@ pub mod segmentation;
 pub mod task;
 pub mod dtables;
 pub mod syscall;
+pub mod perfcnt;
 pub mod cpuid {
     pub use raw_cpuid::*;
 }
\ No newline at end of file
diff --git a/src/perfcnt/intel/counters.rs b/src/perfcnt/intel/counters.rs
new file mode 100644
index 0000000..d05fd5c
--- /dev/null
+++ b/src/perfcnt/intel/counters.rs
@@ -0,0 +1,8 @@
+use phf;
+use super::description::IntelPerformanceCounterDescription;
+use super::description::Counter;
+use super::description::PebsType;
+use super::description::Tuple;
+use super::description::MSRIndex;
+
+include!(concat!(env!("OUT_DIR"), "/counters.rs"));
\ No newline at end of file
diff --git a/src/perfcnt/intel/description.rs b/src/perfcnt/intel/description.rs
new file mode 100644
index 0000000..3093c60
--- /dev/null
+++ b/src/perfcnt/intel/description.rs
@@ -0,0 +1,235 @@
+use std::fmt;
+
+pub enum PebsType {
+    Regular,
+    PebsOrRegular,
+    PebsOnly
+}
+
+impl fmt::Debug for PebsType {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        let name = match *self {
+            PebsType::Regular => "Regular",
+            PebsType::PebsOrRegular => "PebsOrRegular",
+            PebsType::PebsOnly => "PebsOnly",
+        };
+        write!(f, "PebsType::{}", name)
+    }
+}
+
+pub enum Tuple {
+    One(u8),
+    Two(u8,u8)
+}
+
+impl fmt::Debug for Tuple {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match *self {
+            Tuple::One(a) => write!(f, "Tuple::One({})", a),
+            Tuple::Two(a, b) => write!(f, "Tuple::Two({}, {})", a, b),
+        }
+    }
+}
+
+pub enum MSRIndex {
+    None,
+    One(u8),
+    Two(u8, u8)
+}
+
+impl fmt::Debug for MSRIndex {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match *self {
+            MSRIndex::None => write!(f, "MSRIndex::None"),
+            MSRIndex::One(a) => write!(f, "MSRIndex::One({})", a),
+            MSRIndex::Two(a, b) => write!(f, "MSRIndex::Two({}, {})", a, b),
+        }
+    }
+}
+
+pub enum Counter {
+    /// Bit-mask containing the fixed counters
+    /// usable with the corresponding performance event.
+    Fixed(u8),
+
+    /// Bit-mask containing the programmable counters
+    /// usable with the corresponding performance event.
+    Programmable(u8),
+}
+
+impl fmt::Debug for Counter {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match *self {
+            Counter::Fixed(a) => write!(f, "Counter::Fixed({})", a),
+            Counter::Programmable(a) => write!(f, "Counter::Programmable({})", a),
+        }
+    }
+}
+
+#[derive(Debug)]
+pub struct IntelPerformanceCounterDescription {
+
+    /// This field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs.
+    ///
+    /// The set of values for this field is defined architecturally.
+    /// Each value corresponds to an event logic unit and should be used with a unit
+    /// mask value to obtain an architectural performance event.
+    pub event_code: Tuple,
+
+    /// This field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs.
+    ///
+    /// It further qualifies the event logic unit selected in the event select
+    /// field to detect a specific micro-architectural condition.
+    pub umask: Tuple,
+
+    /// It is a string of characters to identify the programming of an event.
+    pub event_name: &'static str,
+
+    /// This field contains a description of what is being counted by a particular event.
+    pub brief_description: &'static str,
+
+    /// In some cases, this field will contain a more detailed description of what is counted by an event.
+    pub public_description: Option<&'static str>,
+
+    /// This field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX)
+    /// counters that can be used to count the event.
+    pub counter: Counter,
+
+    /// This field lists the counters where this event can be sampled
+    /// when Intel® Hyper-Threading Technology (Intel® HT Technology) is
+    /// disabled.
+    ///
+    /// When Intel® HT Technology is disabled, some processor cores gain access to
+    /// the programmable counters of the second thread, making a total of eight
+    /// programmable counters available. The additional counters will be
+    /// numbered 4,5,6,7. Fixed counter behavior remains unaffected.
+    pub counter_ht_off: Counter,
+
+    /// This field is only relevant to PEBS events.
+    ///
+    /// It lists the counters where the event can be sampled when it is programmed as a PEBS event.
+    pub pebs_counters: Option<Counter>,
+
+    /// Sample After Value (SAV) is the value that can be preloaded
+    /// into the counter registers to set the point at which they will overflow.
+    ///
+    /// To make the counter overflow after N occurrences of the event,
+    /// it should be loaded with (0xFF..FF – N) or –(N-1). On overflow a
+    /// hardware interrupt is generated through the Local APIC and additional
+    /// architectural state can be collected in the interrupt handler.
+    /// This is useful in event-based sampling. This field gives a recommended
+    /// default overflow value, which may be adjusted based on workload or tool preference.
+    pub sample_after_value: u64,
+
+    /// Additional MSRs may be required for programming certain events.
+    /// This field gives the address of such MSRS.
+    pub msr_index: MSRIndex,
+
+    /// When an MSRIndex is used (indicated by the MSRIndex column), this field will
+    /// contain the value that needs to be loaded into the
+    /// register whose address is given in MSRIndex column.
+    ///
+    /// For example, in the case of the load latency events, MSRValue defines the
+    /// latency threshold value to write into the MSR defined in MSRIndex (0x3F6).
+    pub msr_value: u64,
+
+    /// This field is set for an event which can only be sampled or counted by itself,
+    /// meaning that when this event is being collected,
+    /// the remaining programmable counters are not available to count any other events.
+    pub taken_alone: bool,
+
+    /// This field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR.
+    pub counter_mask: u8,
+
+    /// This field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR.
+    pub invert: bool,
+
+    /// This field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR.
+    pub any_thread: bool,
+
+    /// This field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR.
+    pub edge_detect: bool,
+
+    /// A '0' in this field means that the event cannot be programmed as a PEBS event.
+    /// A '1' in this field means that the event is a  precise event and can be programmed
+    /// in one of two ways – as a regular event or as a PEBS event.
+    /// And a '2' in this field means that the event can only be programmed as a PEBS event.
+    pub pebs: PebsType,
+
+    /// A '1' in this field means the event uses the Precise Store feature and Bit 3 and
+    /// bit 63 in IA32_PEBS_ENABLE MSR must be set to enable IA32_PMC3 as a PEBS counter
+    /// and enable the precise store facility respectively.
+    ///
+    /// Processors based on SandyBridge and IvyBridge micro-architecture offer a
+    /// precise store capability that provides a means to profile store memory
+    /// references in the system.
+    pub precise_store: bool,
+
+    /// A '1' in this field means that when the event is configured as a PEBS event,
+    /// the Data Linear Address facility is supported.
+    ///
+    /// The Data Linear Address facility is a new feature added to Haswell as a
+    /// replacement or extension of the precise store facility in SNB.
+    pub data_la: bool,
+
+    /// A '1' in this field means that when the event is configured as a PEBS event,
+    /// the DCU hit field of the PEBS record is set to 1 when the store hits in the
+    /// L1 cache and 0 when it misses.
+    pub l1_hit_indication: bool,
+
+    /// This field lists the known bugs that apply to the events.
+    ///
+    /// For the latest, up to date errata refer to the following links:
+    ////
+    /// * Haswell:
+    ///   http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf
+    ///
+    /// * IvyBridge:
+    ///   https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf
+    ///
+    /// * SandyBridge:
+    ///   https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-family-mobile-specification-update.pdf
+    pub errata: Option<&'static str>,
+
+    /// There is only 1 file for core and offcore events in this format.
+    /// This field is set to 1 for offcore events and 0 for core events.
+    pub offcore: bool,
+}
+
+impl IntelPerformanceCounterDescription {
+
+    #[allow(dead_code)]
+    fn new(event_code: Tuple, umask: Tuple, event_name: &'static str,
+           brief_description: &'static str, public_description: Option<&'static str>,
+           counter: Counter, counter_ht_off: Counter, pebs_counters: Option<Counter>,
+           sample_after_value: u64, msr_index: MSRIndex, msr_value: u64, taken_alone: bool,
+           counter_mask: u8, invert: bool, any_thread: bool, edge_detect: bool, pebs:
+           PebsType, precise_store: bool, data_la: bool, l1_hit_indication: bool,
+           errata: Option<&'static str>, offcore: bool) -> IntelPerformanceCounterDescription {
+
+        IntelPerformanceCounterDescription {
+            event_code: event_code,
+            umask: umask,
+            event_name: event_name,
+            brief_description: brief_description,
+            public_description: public_description,
+            counter: counter,
+            counter_ht_off: counter_ht_off,
+            pebs_counters: pebs_counters,
+            sample_after_value: sample_after_value,
+            msr_index: msr_index,
+            msr_value: msr_value,
+            taken_alone: taken_alone,
+            counter_mask: counter_mask,
+            invert: invert,
+            any_thread: any_thread,
+            edge_detect: edge_detect,
+            pebs: pebs,
+            precise_store: precise_store,
+            data_la: data_la,
+            l1_hit_indication: l1_hit_indication,
+            errata: errata,
+            offcore: offcore
+        }
+    }
+}
diff --git a/src/perfcnt/intel/mod.rs b/src/perfcnt/intel/mod.rs
new file mode 100644
index 0000000..25b22dc
--- /dev/null
+++ b/src/perfcnt/intel/mod.rs
@@ -0,0 +1,2 @@
+pub mod counters;
+pub mod description;
\ No newline at end of file
diff --git a/src/perfcnt/mod.rs b/src/perfcnt/mod.rs
new file mode 100644
index 0000000..95edf9d
--- /dev/null
+++ b/src/perfcnt/mod.rs
@@ -0,0 +1,68 @@
+use super::cpuid;
+use phf;
+
+pub mod intel;
+
+use core::fmt::{Write, Result};
+use core::str;
+
+/*
+pub trait Write {
+
+    fn write_char(&mut self, c: char) -> Result { ... }
+    fn write_fmt(&mut self, args: Arguments) -> Result { ... }
+}*/
+
+#[derive(Default)]
+struct ModelWriter {
+    buffer: [u8; 20],
+    index: usize
+}
+
+impl ModelWriter {
+    fn as_str(&self) -> &str {
+        str::from_utf8(&self.buffer).unwrap()
+    }
+}
+
+impl Write for ModelWriter {
+    fn write_str(&mut self, s: &str) -> Result {
+        for c in s.chars() {
+            self.buffer[self.index] = c as u8;
+            self.index += 1;
+        }
+        Ok(())
+    }
+}
+
+/// Return performance counter description for the running micro-architecture.
+pub fn available_counters() -> Option<&'static phf::Map<&'static str, intel::description::IntelPerformanceCounterDescription>> {
+
+    let cpuid = cpuid::CpuId::new();
+
+    cpuid.get_vendor_info().map(|vf| {
+        cpuid.get_feature_info().map(|fi| {
+            let vendor = vf.as_string();
+            let (family, extended_model, model) = (fi.family_id(), fi.extended_model_id(), fi.model_id());
+
+            let mut writer: ModelWriter = Default::default();
+            let res = write!(writer, "{}-{}-{:X}{:X}", vendor, family, extended_model, model);
+            let key = writer.as_str();
+
+            match intel::counters::COUNTER_MAP.contains_key(key) {
+                true => return Some(intel::counters::COUNTER_MAP[key]),
+                false => return None
+            };
+        });
+    });
+
+    None
+}
+
+#[cfg(test)]
+#[test]
+fn list_mine() {
+    for counter in available_counters() {
+        println!("{:?}", counter);
+    }
+}
\ No newline at end of file
diff --git a/src/syscall.rs b/src/syscall.rs
index a1fa036..61e9ee7 100644
--- a/src/syscall.rs
+++ b/src/syscall.rs
@@ -42,14 +42,14 @@ macro_rules! syscall {
 
 #[inline(always)]
 pub unsafe fn syscall0(arg0: u64) -> u64 {
-    let mut ret: u64;
+    let ret: u64;
     asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0) : "rcx", "r11", "memory" : "volatile");
     ret
 }
 
 #[inline(always)]
 pub unsafe fn syscall1(arg0: u64, arg1: u64) -> u64 {
-    let mut ret: u64;
+    let ret: u64;
     asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1)
                    : "rcx", "r11", "memory" : "volatile");
     ret
@@ -57,7 +57,7 @@ pub unsafe fn syscall1(arg0: u64, arg1: u64) -> u64 {
 
 #[inline(always)]
 pub unsafe fn syscall2(arg0: u64, arg1: u64, arg2: u64) -> u64 {
-    let mut ret: u64;
+    let ret: u64;
     asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2)
                    : "rcx", "r11", "memory" : "volatile");
     ret
@@ -65,7 +65,7 @@ pub unsafe fn syscall2(arg0: u64, arg1: u64, arg2: u64) -> u64 {
 
 #[inline(always)]
 pub unsafe fn syscall3(arg0: u64, arg1: u64, arg2: u64, arg3: u64) -> u64 {
-    let mut ret: u64;
+    let ret: u64;
     asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3)
                    : "rcx", "r11", "memory" : "volatile");
     ret
@@ -73,7 +73,7 @@ pub unsafe fn syscall3(arg0: u64, arg1: u64, arg2: u64, arg3: u64) -> u64 {
 
 #[inline(always)]
 pub unsafe fn syscall4(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64) -> u64 {
-    let mut ret: u64;
+    let ret: u64;
     asm!("syscall" : "={rax}" (ret)
                    : "{rax}"  (arg0), "{rdi}"  (arg1), "{rsi}"  (arg2), "{rdx}"  (arg3), "{r10}"  (arg4)
                    : "rcx", "r11", "memory" : "volatile");
@@ -82,7 +82,7 @@ pub unsafe fn syscall4(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64) ->
 
 #[inline(always)]
 pub unsafe fn syscall5(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64, arg5: u64) -> u64 {
-    let mut ret: u64;
+    let ret: u64;
     asm!("syscall" : "={rax}" (ret)
                    : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3), "{r10}" (arg4), "{r8}" (arg5)
                    : "rcx", "r11", "memory"
@@ -92,7 +92,7 @@ pub unsafe fn syscall5(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64, ar
 
 #[inline(always)]
 pub unsafe fn syscall6(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64, arg5: u64, arg6: u64) -> u64 {
-    let mut ret: u64;
+    let ret: u64;
     asm!("syscall" : "={rax}" (ret)
                    : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3),
                      "{r10}" (arg4), "{r8}" (arg5), "{r9}" (arg6)
diff --git a/x86data/perfmon_data/BDW-DE/BroadwellDE_core_V1.json b/x86data/perfmon_data/BDW-DE/BroadwellDE_core_V1.json
new file mode 100644
index 0000000..e59c4ec
--- /dev/null
+++ b/x86data/perfmon_data/BDW-DE/BroadwellDE_core_V1.json
@@ -0,0 +1,7316 @@
+[
+  {
+    "EventCode": "0x00",
+    "UMask": "0x01",
+    "EventName": "INST_RETIRED.ANY",
+    "BriefDescription": "Instructions retired from execution.",
+    "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions...",
+    "Counter": "Fixed counter 1",
+    "CounterHTOff": "Fixed counter 1",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x00",
+    "UMask": "0x02",
+    "EventName": "CPU_CLK_UNHALTED.THREAD",
+    "BriefDescription": "Core cycles when the thread is not in halt state",
+    "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events...",
+    "Counter": "Fixed counter 2",
+    "CounterHTOff": "Fixed counter 2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x00",
+    "UMask": "0x03",
+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",
+    "BriefDescription": "Reference cycles when the core is not in halt state.",
+    "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case....",
+    "Counter": "Fixed counter 3",
+    "CounterHTOff": "Fixed counter 3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x03",
+    "UMask": "0x02",
+    "EventName": "LD_BLOCKS.STORE_FORWARD",
+    "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
+    "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x03",
+    "UMask": "0x08",
+    "EventName": "LD_BLOCKS.NO_SR",
+    "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
+    "PublicDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x05",
+    "UMask": "0x01",
+    "EventName": "MISALIGN_MEM_REF.LOADS",
+    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
+    "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x05",
+    "UMask": "0x02",
+    "EventName": "MISALIGN_MEM_REF.STORES",
+    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
+    "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x07",
+    "UMask": "0x01",
+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
+    "BriefDescription": "False dependencies in MOB due to partial compare",
+    "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x08",
+    "UMask": "0x01",
+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
+    "BriefDescription": "Load misses in all DTLB levels that cause page walks",
+    "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x08",
+    "UMask": "0x02",
+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
+    "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x08",
+    "UMask": "0x10",
+    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
+    "BriefDescription": "Cycles when PMH is busy with page walks",
+    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x08",
+    "UMask": "0x20",
+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
+    "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
+    "PublicDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x0D",
+    "UMask": "0x08",
+    "EventName": "INT_MISC.RAT_STALL_CYCLES",
+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
+    "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x0D",
+    "UMask": "0x03",
+    "EventName": "INT_MISC.RECOVERY_CYCLES",
+    "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",
+    "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x0E",
+    "UMask": "0x01",
+    "EventName": "UOPS_ISSUED.ANY",
+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
+    "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x0E",
+    "UMask": "0x10",
+    "EventName": "UOPS_ISSUED.FLAGS_MERGE",
+    "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
+    "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x0E",
+    "UMask": "0x20",
+    "EventName": "UOPS_ISSUED.SLOW_LEA",
+    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
+    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x0E",
+    "UMask": "0x40",
+    "EventName": "UOPS_ISSUED.SINGLE_MUL",
+    "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
+    "PublicDescription": "Number of Multiply packed/scalar single precision uops allocated",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x0E",
+    "UMask": "0x01",
+    "EventName": "UOPS_ISSUED.STALL_CYCLES",
+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
+    "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "1",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x14",
+    "UMask": "0x01",
+    "EventName": "ARITH.FPU_DIV_ACTIVE",
+    "BriefDescription": "Cycles when divider is busy executing divide operations",
+    "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x21",
+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
+    "BriefDescription": "Demand Data Read miss L2, no rejects",
+    "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x41",
+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
+    "BriefDescription": "Demand Data Read requests that hit L2 cache",
+    "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x30",
+    "EventName": "L2_RQSTS.L2_PF_MISS",
+    "BriefDescription": "L2 prefetch requests that miss L2 cache",
+    "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x50",
+    "EventName": "L2_RQSTS.L2_PF_HIT",
+    "BriefDescription": "L2 prefetch requests that hit L2 cache",
+    "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0xE1",
+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
+    "BriefDescription": "Demand Data Read requests",
+    "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0xE2",
+    "EventName": "L2_RQSTS.ALL_RFO",
+    "BriefDescription": "RFO requests to L2 cache",
+    "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0xE4",
+    "EventName": "L2_RQSTS.ALL_CODE_RD",
+    "BriefDescription": "L2 code requests",
+    "PublicDescription": "This event counts the total number of L2 code requests.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0xF8",
+    "EventName": "L2_RQSTS.ALL_PF",
+    "BriefDescription": "Requests from L2 hardware prefetchers",
+    "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x27",
+    "UMask": "0x50",
+    "EventName": "L2_DEMAND_RQSTS.WB_HIT",
+    "BriefDescription": "Not rejected writebacks that hit L2 cache",
+    "PublicDescription": "This event counts the number of WB requests that hit L2 cache. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2e",
+    "UMask": "0x41",
+    "EventName": "LONGEST_LAT_CACHE.MISS",
+    "BriefDescription": "Core-originated cacheable demand requests missed L3",
+    "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2e",
+    "UMask": "0x4F",
+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+    "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
+    "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3c",
+    "UMask": "0x01",
+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
+    "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3c",
+    "UMask": "0x02",
+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x48",
+    "UMask": "0x01",
+    "EventName": "L1D_PEND_MISS.PENDING",
+    "BriefDescription": "L1D miss oustandings duration in cycles",
+    "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
+    "Counter": "2",
+    "CounterHTOff": "2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x48",
+    "UMask": "0x01",
+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
+    "BriefDescription": "Cycles with L1D load Misses outstanding.",
+    "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.",
+    "Counter": "2",
+    "CounterHTOff": "2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x49",
+    "UMask": "0x01",
+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",
+    "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x49",
+    "UMask": "0x02",
+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
+    "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
+    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x49",
+    "UMask": "0x10",
+    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
+    "BriefDescription": "Cycles when PMH is busy with page walks",
+    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x49",
+    "UMask": "0x20",
+    "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
+    "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",
+    "PublicDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x4c",
+    "UMask": "0x02",
+    "EventName": "LOAD_HIT_PRE.HW_PF",
+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
+    "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x4f",
+    "UMask": "0x10",
+    "EventName": "EPT.WALK_CYCLES",
+    "BriefDescription": "Cycle count for an Extended Page table walk.",
+    "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x51",
+    "UMask": "0x01",
+    "EventName": "L1D.REPLACEMENT",
+    "BriefDescription": "L1D data line replacements",
+    "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x54",
+    "UMask": "0x01",
+    "EventName": "TX_MEM.ABORT_CONFLICT",
+    "BriefDescription": "Number of times a TSX line had a cache conflict",
+    "PublicDescription": "Number of times a TSX line had a cache conflict",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x54",
+    "UMask": "0x02",
+    "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
+    "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
+    "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x54",
+    "UMask": "0x04",
+    "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
+    "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
+    "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x54",
+    "UMask": "0x08",
+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
+    "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
+    "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x54",
+    "UMask": "0x10",
+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
+    "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
+    "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x54",
+    "UMask": "0x20",
+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
+    "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
+    "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x54",
+    "UMask": "0x40",
+    "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
+    "BriefDescription": "Number of times we could not allocate Lock Buffer",
+    "PublicDescription": "Number of times we could not allocate Lock Buffer",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x58",
+    "UMask": "0x01",
+    "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
+    "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
+    "PublicDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "1000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x58",
+    "UMask": "0x02",
+    "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "1000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x58",
+    "UMask": "0x04",
+    "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
+    "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
+    "PublicDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "1000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x58",
+    "UMask": "0x08",
+    "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "1000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5C",
+    "UMask": "0x01",
+    "EventName": "CPL_CYCLES.RING0",
+    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
+    "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5C",
+    "UMask": "0x02",
+    "EventName": "CPL_CYCLES.RING123",
+    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
+    "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5C",
+    "UMask": "0x01",
+    "EventName": "CPL_CYCLES.RING0_TRANS",
+    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
+    "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "1",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5d",
+    "UMask": "0x01",
+    "EventName": "TX_EXEC.MISC1",
+    "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
+    "PublicDescription": "Unfriendly TSX abort triggered by  a flowmarker",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5d",
+    "UMask": "0x02",
+    "EventName": "TX_EXEC.MISC2",
+    "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
+    "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5d",
+    "UMask": "0x04",
+    "EventName": "TX_EXEC.MISC3",
+    "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
+    "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5d",
+    "UMask": "0x08",
+    "EventName": "TX_EXEC.MISC4",
+    "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
+    "PublicDescription": "RTM region detected inside HLE",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5d",
+    "UMask": "0x10",
+    "EventName": "TX_EXEC.MISC5",
+    "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
+    "PublicDescription": "# HLE inside HLE+",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5E",
+    "UMask": "0x01",
+    "EventName": "RS_EVENTS.EMPTY_CYCLES",
+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
+    "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0x01",
+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
+    "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0x02",
+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
+    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
+    "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0x04",
+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
+    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
+    "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0x08",
+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
+    "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0x01",
+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
+    "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0x08",
+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
+    "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x63",
+    "UMask": "0x01",
+    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
+    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
+    "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x63",
+    "UMask": "0x02",
+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
+    "BriefDescription": "Cycles when L1D is locked",
+    "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x02",
+    "EventName": "IDQ.EMPTY",
+    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
+    "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x04",
+    "EventName": "IDQ.MITE_UOPS",
+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
+    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x08",
+    "EventName": "IDQ.DSB_UOPS",
+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
+    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x10",
+    "EventName": "IDQ.MS_DSB_UOPS",
+    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
+    "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x20",
+    "EventName": "IDQ.MS_MITE_UOPS",
+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
+    "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x30",
+    "EventName": "IDQ.MS_UOPS",
+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
+    "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x30",
+    "EventName": "IDQ.MS_CYCLES",
+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
+    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x04",
+    "EventName": "IDQ.MITE_CYCLES",
+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
+    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x08",
+    "EventName": "IDQ.DSB_CYCLES",
+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
+    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x10",
+    "EventName": "IDQ.MS_DSB_CYCLES",
+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
+    "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x10",
+    "EventName": "IDQ.MS_DSB_OCCUR",
+    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
+    "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "1",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x18",
+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
+    "PublicDescription": "This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "4",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x18",
+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
+    "PublicDescription": "This event counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x24",
+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
+    "BriefDescription": "Cycles MITE is delivering 4 Uops",
+    "PublicDescription": "This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "4",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x24",
+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
+    "BriefDescription": "Cycles MITE is delivering any Uop",
+    "PublicDescription": "This event counts the number of cycles  uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x3c",
+    "EventName": "IDQ.MITE_ALL_UOPS",
+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
+    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "ICACHE.HIT",
+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
+    "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x80",
+    "UMask": "0x02",
+    "EventName": "ICACHE.MISSES",
+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
+    "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x80",
+    "UMask": "0x04",
+    "EventName": "ICACHE.IFDATA_STALL",
+    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
+    "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x85",
+    "UMask": "0x01",
+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
+    "BriefDescription": "Misses at all ITLB levels that cause page walks",
+    "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x85",
+    "UMask": "0x02",
+    "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
+    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
+    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x85",
+    "UMask": "0x10",
+    "EventName": "ITLB_MISSES.WALK_DURATION",
+    "BriefDescription": "Cycles when PMH is busy with page walks",
+    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x85",
+    "UMask": "0x20",
+    "EventName": "ITLB_MISSES.STLB_HIT_4K",
+    "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",
+    "PublicDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x87",
+    "UMask": "0x01",
+    "EventName": "ILD_STALL.LCP",
+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
+    "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x41",
+    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
+    "BriefDescription": "Not taken macro-conditional branches",
+    "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x81",
+    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
+    "BriefDescription": "Taken speculative and retired macro-conditional branches",
+    "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x82",
+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
+    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
+    "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x84",
+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
+    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
+    "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x88",
+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
+    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
+    "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x90",
+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
+    "BriefDescription": "Taken speculative and retired direct near calls",
+    "PublicDescription": "This event counts taken speculative and retired direct near calls.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0xA0",
+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
+    "BriefDescription": "Taken speculative and retired indirect calls",
+    "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0xC1",
+    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
+    "BriefDescription": "Speculative and retired macro-conditional branches",
+    "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0xC2",
+    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
+    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
+    "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0xC4",
+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
+    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
+    "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0xC8",
+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
+    "BriefDescription": "Speculative and retired indirect return branches.",
+    "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0xD0",
+    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
+    "BriefDescription": "Speculative and retired direct near calls",
+    "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0xFF",
+    "EventName": "BR_INST_EXEC.ALL_BRANCHES",
+    "BriefDescription": "Speculative and retired  branches",
+    "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0x41",
+    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
+    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
+    "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0x81",
+    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
+    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
+    "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0x84",
+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
+    "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0xC1",
+    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
+    "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0xC4",
+    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
+    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
+    "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0xFF",
+    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
+    "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x9c",
+    "UMask": "0x01",
+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
+    "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x9C",
+    "UMask": "0x01",
+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "4",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x9C",
+    "UMask": "0x01",
+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is  delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "3",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x9C",
+    "UMask": "0x01",
+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "2",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x9C",
+    "UMask": "0x01",
+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x9C",
+    "UMask": "0x01",
+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "1",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x01",
+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
+    "BriefDescription": "Cycles per thread when uops are executed in port 0",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x02",
+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
+    "BriefDescription": "Cycles per thread when uops are executed in port 1",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x04",
+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
+    "BriefDescription": "Cycles per thread when uops are executed in port 2",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x08",
+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
+    "BriefDescription": "Cycles per thread when uops are executed in port 3",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x10",
+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
+    "BriefDescription": "Cycles per thread when uops are executed in port 4",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x20",
+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
+    "BriefDescription": "Cycles per thread when uops are executed in port 5",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x40",
+    "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
+    "BriefDescription": "Cycles per thread when uops are executed in port 6",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x80",
+    "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
+    "BriefDescription": "Cycles per thread when uops are executed in port 7",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA2",
+    "UMask": "0x01",
+    "EventName": "RESOURCE_STALLS.ANY",
+    "BriefDescription": "Resource-related stall cycles",
+    "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA2",
+    "UMask": "0x04",
+    "EventName": "RESOURCE_STALLS.RS",
+    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
+    "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA2",
+    "UMask": "0x08",
+    "EventName": "RESOURCE_STALLS.SB",
+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
+    "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA2",
+    "UMask": "0x10",
+    "EventName": "RESOURCE_STALLS.ROB",
+    "BriefDescription": "Cycles stalled due to re-order buffer full.",
+    "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x01",
+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
+    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
+    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand* load request missing the L2 cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x08",
+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
+    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
+    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand load request missing the L1 data cache.",
+    "Counter": "2",
+    "CounterHTOff": "2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "8",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x02",
+    "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
+    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
+    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand load request (that is cycles with non-completed load waiting for its data from memory subsystem)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "2",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x04",
+    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
+    "BriefDescription": "Total execution stalls",
+    "PublicDescription": "Counts number of cycles nothing is executed on any execution port.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "4",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x05",
+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
+    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
+    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.\r\n\r\n(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "5",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x06",
+    "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
+    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
+    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "6",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x0C",
+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
+    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
+    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.",
+    "Counter": "2",
+    "CounterHTOff": "2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "12",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xa8",
+    "UMask": "0x01",
+    "EventName": "LSD.UOPS",
+    "BriefDescription": "Number of Uops delivered by the LSD. Read more on LSD under LSD_REPLAY.REPLAY",
+    "PublicDescription": "Number of Uops delivered by the LSD. Read more on LSD under LSD_REPLAY.REPLAY",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xAB",
+    "UMask": "0x02",
+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
+    "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xae",
+    "UMask": "0x01",
+    "EventName": "ITLB.ITLB_FLUSH",
+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
+    "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb0",
+    "UMask": "0x01",
+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
+    "BriefDescription": "Demand Data Read requests sent to uncore",
+    "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb0",
+    "UMask": "0x02",
+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
+    "BriefDescription": "Cacheable and noncachaeble code read requests",
+    "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb0",
+    "UMask": "0x04",
+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
+    "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb0",
+    "UMask": "0x08",
+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
+    "BriefDescription": "Demand and prefetch data reads",
+    "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable \"Demands\" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb1",
+    "UMask": "0x01",
+    "EventName": "UOPS_EXECUTED.THREAD",
+    "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
+    "PublicDescription": "Number of uops to be executed per-thread each cycle.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb1",
+    "UMask": "0x02",
+    "EventName": "UOPS_EXECUTED.CORE",
+    "BriefDescription": "Number of uops executed on the core.",
+    "PublicDescription": "Number of uops executed from any thread",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB1",
+    "UMask": "0x01",
+    "EventName": "UOPS_EXECUTED.STALL_CYCLES",
+    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
+    "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "1",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb2",
+    "UMask": "0x01",
+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
+    "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
+    "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xBC",
+    "UMask": "0x11",
+    "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
+    "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
+    "PublicDescription": "Number of DTLB page walker hits in the L1+FB",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xBC",
+    "UMask": "0x21",
+    "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
+    "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
+    "PublicDescription": "Number of ITLB page walker hits in the L1+FB",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xBC",
+    "UMask": "0x12",
+    "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
+    "BriefDescription": "Number of DTLB page walker hits in the L2",
+    "PublicDescription": "Number of DTLB page walker hits in the L2",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xBC",
+    "UMask": "0x22",
+    "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
+    "BriefDescription": "Number of ITLB page walker hits in the L2",
+    "PublicDescription": "Number of ITLB page walker hits in the L2",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xBC",
+    "UMask": "0x14",
+    "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
+    "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
+    "PublicDescription": "Number of DTLB page walker hits in the L3 + XSNP",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xBC",
+    "UMask": "0x24",
+    "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
+    "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
+    "PublicDescription": "Number of ITLB page walker hits in the L3 + XSNP",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xBC",
+    "UMask": "0x18",
+    "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
+    "BriefDescription": "Number of DTLB page walker hits in Memory",
+    "PublicDescription": "Number of DTLB page walker hits in Memory",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC0",
+    "UMask": "0x00",
+    "EventName": "INST_RETIRED.ANY_P",
+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
+    "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC0",
+    "UMask": "0x02",
+    "EventName": "INST_RETIRED.X87",
+    "BriefDescription": "FP operations  retired. X87 FP operations that have no exceptions:",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC0",
+    "UMask": "0x01",
+    "EventName": "INST_RETIRED.PREC_DIST",
+    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
+    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.",
+    "Counter": "1",
+    "CounterHTOff": "1",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC1",
+    "UMask": "0x08",
+    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
+    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC1",
+    "UMask": "0x10",
+    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
+    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC1",
+    "UMask": "0x40",
+    "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
+    "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
+    "PublicDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC2",
+    "UMask": "0x01",
+    "EventName": "UOPS_RETIRED.ALL",
+    "BriefDescription": "Actually retired uops.",
+    "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC2",
+    "UMask": "0x02",
+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
+    "BriefDescription": "Retirement slots used.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC2",
+    "UMask": "0x01",
+    "EventName": "UOPS_RETIRED.STALL_CYCLES",
+    "BriefDescription": "Cycles without actually retired uops.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "1",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC2",
+    "UMask": "0x01",
+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
+    "BriefDescription": "Cycles with less than 10 actually retired uops.",
+    "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.  ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "10",
+    "Invert": "1",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC3",
+    "UMask": "0x01",
+    "EventName": "MACHINE_CLEARS.CYCLES",
+    "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
+    "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC3",
+    "UMask": "0x02",
+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
+    "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC3",
+    "UMask": "0x04",
+    "EventName": "MACHINE_CLEARS.SMC",
+    "BriefDescription": "Self-modifying code (SMC) detected.",
+    "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC3",
+    "UMask": "0x20",
+    "EventName": "MACHINE_CLEARS.MASKMOV",
+    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
+    "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x01",
+    "EventName": "BR_INST_RETIRED.CONDITIONAL",
+    "BriefDescription": "Conditional branch instructions retired.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x02",
+    "EventName": "BR_INST_RETIRED.NEAR_CALL",
+    "BriefDescription": "Direct and indirect near call instructions retired.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x00",
+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
+    "BriefDescription": "All (macro) branch instructions retired.",
+    "PublicDescription": "This event counts all (macro) branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x08",
+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",
+    "BriefDescription": "Return instructions retired.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x10",
+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",
+    "BriefDescription": "Not taken branch instructions retired.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x20",
+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
+    "BriefDescription": "Taken branch instructions retired.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x40",
+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",
+    "BriefDescription": "Far branch instructions retired.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x04",
+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
+    "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
+    "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC5",
+    "UMask": "0x01",
+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",
+    "BriefDescription": "Mispredicted conditional branch instructions retired.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC5",
+    "UMask": "0x00",
+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
+    "BriefDescription": "All mispredicted macro branch instructions retired.",
+    "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC5",
+    "UMask": "0x08",
+    "EventName": "BR_MISP_RETIRED.RET",
+    "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC5",
+    "UMask": "0x04",
+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
+    "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
+    "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x01",
+    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+    "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
+    "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x02",
+    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+    "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+    "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x04",
+    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
+    "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ",
+    "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x08",
+    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
+    "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
+    "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x10",
+    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
+    "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
+    "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc8",
+    "UMask": "0x01",
+    "EventName": "HLE_RETIRED.START",
+    "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
+    "PublicDescription": "Number of times we entered an HLE region; does not count nested transactions",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc8",
+    "UMask": "0x02",
+    "EventName": "HLE_RETIRED.COMMIT",
+    "BriefDescription": "Number of times HLE commit succeeded",
+    "PublicDescription": "Number of times HLE commit succeeded",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc8",
+    "UMask": "0x04",
+    "EventName": "HLE_RETIRED.ABORTED",
+    "BriefDescription": "Number of times HLE abort was triggered",
+    "PublicDescription": "Number of times HLE abort was triggered",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc8",
+    "UMask": "0x08",
+    "EventName": "HLE_RETIRED.ABORTED_MISC1",
+    "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
+    "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc8",
+    "UMask": "0x10",
+    "EventName": "HLE_RETIRED.ABORTED_MISC2",
+    "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
+    "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc8",
+    "UMask": "0x20",
+    "EventName": "HLE_RETIRED.ABORTED_MISC3",
+    "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
+    "PublicDescription": "Number of times a disallowed operation caused an HLE abort",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc8",
+    "UMask": "0x40",
+    "EventName": "HLE_RETIRED.ABORTED_MISC4",
+    "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
+    "PublicDescription": "Number of times HLE caused a fault",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc8",
+    "UMask": "0x80",
+    "EventName": "HLE_RETIRED.ABORTED_MISC5",
+    "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
+    "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc9",
+    "UMask": "0x01",
+    "EventName": "RTM_RETIRED.START",
+    "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
+    "PublicDescription": "Number of times we entered an RTM region; does not count nested transactions",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc9",
+    "UMask": "0x02",
+    "EventName": "RTM_RETIRED.COMMIT",
+    "BriefDescription": "Number of times RTM commit succeeded",
+    "PublicDescription": "Number of times RTM commit succeeded",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc9",
+    "UMask": "0x04",
+    "EventName": "RTM_RETIRED.ABORTED",
+    "BriefDescription": "Number of times RTM abort was triggered",
+    "PublicDescription": "Number of times RTM abort was triggered ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc9",
+    "UMask": "0x08",
+    "EventName": "RTM_RETIRED.ABORTED_MISC1",
+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
+    "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc9",
+    "UMask": "0x10",
+    "EventName": "RTM_RETIRED.ABORTED_MISC2",
+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
+    "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc9",
+    "UMask": "0x20",
+    "EventName": "RTM_RETIRED.ABORTED_MISC3",
+    "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
+    "PublicDescription": "Number of times a disallowed operation caused an RTM abort",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc9",
+    "UMask": "0x40",
+    "EventName": "RTM_RETIRED.ABORTED_MISC4",
+    "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
+    "PublicDescription": "Number of times a RTM caused a fault",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc9",
+    "UMask": "0x80",
+    "EventName": "RTM_RETIRED.ABORTED_MISC5",
+    "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
+    "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCA",
+    "UMask": "0x02",
+    "EventName": "FP_ASSIST.X87_OUTPUT",
+    "BriefDescription": "Number of X87 assists due to output value.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCA",
+    "UMask": "0x04",
+    "EventName": "FP_ASSIST.X87_INPUT",
+    "BriefDescription": "Number of X87 assists due to input value.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCA",
+    "UMask": "0x08",
+    "EventName": "FP_ASSIST.SIMD_OUTPUT",
+    "BriefDescription": "Number of SIMD FP assists due to Output values",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCA",
+    "UMask": "0x10",
+    "EventName": "FP_ASSIST.SIMD_INPUT",
+    "BriefDescription": "Number of SIMD FP assists due to input values",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCA",
+    "UMask": "0x1E",
+    "EventName": "FP_ASSIST.ANY",
+    "BriefDescription": "Cycles with any input/output SSE or FP assist",
+    "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCC",
+    "UMask": "0x20",
+    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
+    "BriefDescription": "Count cases of saving new LBR",
+    "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x01",
+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
+    "BriefDescription": "Loads with latency value being above 4",
+    "PublicDescription": "This event counts loads with latency value being above four.",
+    "Counter": "3",
+    "CounterHTOff": "3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0x3F6",
+    "MSRValue": "0x4",
+    "TakenAlone": "1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x01",
+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
+    "BriefDescription": "Loads with latency value being above 8",
+    "PublicDescription": "This event counts loads with latency value being above eight.",
+    "Counter": "3",
+    "CounterHTOff": "3",
+    "SampleAfterValue": "50021",
+    "MSRIndex": "0x3F6",
+    "MSRValue": "0x8",
+    "TakenAlone": "1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x01",
+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
+    "BriefDescription": "Loads with latency value being above 16",
+    "PublicDescription": "This event counts loads with latency value being above 16.",
+    "Counter": "3",
+    "CounterHTOff": "3",
+    "SampleAfterValue": "20011",
+    "MSRIndex": "0x3F6",
+    "MSRValue": "0x10",
+    "TakenAlone": "1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x01",
+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
+    "BriefDescription": "Loads with latency value being above 32",
+    "PublicDescription": "This event counts loads with latency value being above 32.",
+    "Counter": "3",
+    "CounterHTOff": "3",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0x3F6",
+    "MSRValue": "0x20",
+    "TakenAlone": "1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x01",
+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
+    "BriefDescription": "Loads with latency value being above 64",
+    "PublicDescription": "This event counts loads with latency value being above 64.",
+    "Counter": "3",
+    "CounterHTOff": "3",
+    "SampleAfterValue": "2003",
+    "MSRIndex": "0x3F6",
+    "MSRValue": "0x40",
+    "TakenAlone": "1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x01",
+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
+    "BriefDescription": "Loads with latency value being above 128",
+    "PublicDescription": "This event counts loads with latency value being above 128.",
+    "Counter": "3",
+    "CounterHTOff": "3",
+    "SampleAfterValue": "1009",
+    "MSRIndex": "0x3F6",
+    "MSRValue": "0x80",
+    "TakenAlone": "1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x01",
+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
+    "BriefDescription": "Loads with latency value being above 256",
+    "PublicDescription": "This event counts loads with latency value being above 256.",
+    "Counter": "3",
+    "CounterHTOff": "3",
+    "SampleAfterValue": "503",
+    "MSRIndex": "0x3F6",
+    "MSRValue": "0x100",
+    "TakenAlone": "1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x01",
+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
+    "BriefDescription": "Loads with latency value being above 512",
+    "PublicDescription": "This event counts loads with latency value being above 512.",
+    "Counter": "3",
+    "CounterHTOff": "3",
+    "SampleAfterValue": "101",
+    "MSRIndex": "0x3F6",
+    "MSRValue": "0x200",
+    "TakenAlone": "1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD0",
+    "UMask": "0x11",
+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
+    "BriefDescription": "Retired load uops that miss the STLB.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD0",
+    "UMask": "0x12",
+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
+    "BriefDescription": "Retired store uops that miss the STLB.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "1",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD0",
+    "UMask": "0x21",
+    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
+    "BriefDescription": "Retired load uops with locked access.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with locked access retired to the architected path.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD0",
+    "UMask": "0x41",
+    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
+    "BriefDescription": "Retired load uops that split across a cacheline boundary.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD0",
+    "UMask": "0x42",
+    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
+    "BriefDescription": "Retired store uops that split across a cacheline boundary.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "1",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD0",
+    "UMask": "0x81",
+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
+    "BriefDescription": "All retired load uops.",
+    "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD0",
+    "UMask": "0x82",
+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
+    "BriefDescription": "All retired store uops.",
+    "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "1",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD1",
+    "UMask": "0x01",
+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
+    "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD1",
+    "UMask": "0x02",
+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
+    "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD1",
+    "UMask": "0x04",
+    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
+    "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "50021",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD1",
+    "UMask": "0x08",
+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
+    "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD1",
+    "UMask": "0x10",
+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
+    "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "50021",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD1",
+    "UMask": "0x20",
+    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
+    "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
+    "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD1",
+    "UMask": "0x40",
+    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
+    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD2",
+    "UMask": "0x01",
+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
+    "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "20011",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD2",
+    "UMask": "0x02",
+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
+    "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "20011",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD2",
+    "UMask": "0x04",
+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
+    "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3). ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "20011",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD2",
+    "UMask": "0x08",
+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
+    "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xD3",
+    "UMask": "0x01",
+    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
+    "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
+    "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100007",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "1",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3c",
+    "UMask": "0x00",
+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",
+    "BriefDescription": "Thread cycles when thread is not in halt state",
+    "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf0",
+    "UMask": "0x01",
+    "EventName": "L2_TRANS.DEMAND_DATA_RD",
+    "BriefDescription": "Demand Data Read requests that access L2 cache",
+    "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf0",
+    "UMask": "0x02",
+    "EventName": "L2_TRANS.RFO",
+    "BriefDescription": "RFO requests that access L2 cache",
+    "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf0",
+    "UMask": "0x04",
+    "EventName": "L2_TRANS.CODE_RD",
+    "BriefDescription": "L2 cache accesses when fetching instructions",
+    "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf0",
+    "UMask": "0x08",
+    "EventName": "L2_TRANS.ALL_PF",
+    "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
+    "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf0",
+    "UMask": "0x10",
+    "EventName": "L2_TRANS.L1D_WB",
+    "BriefDescription": "L1D writebacks that access L2 cache",
+    "PublicDescription": "This event counts L1D writebacks that access L2 cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf0",
+    "UMask": "0x20",
+    "EventName": "L2_TRANS.L2_FILL",
+    "BriefDescription": "L2 fill requests that access L2 cache",
+    "PublicDescription": "This event counts L2 fill requests that access L2 cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf0",
+    "UMask": "0x40",
+    "EventName": "L2_TRANS.L2_WB",
+    "BriefDescription": "L2 writebacks that access L2 cache",
+    "PublicDescription": "This event counts L2 writebacks that access L2 cache.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf0",
+    "UMask": "0x80",
+    "EventName": "L2_TRANS.ALL_REQUESTS",
+    "BriefDescription": "Transactions accessing L2 pipe",
+    "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf1",
+    "UMask": "0x01",
+    "EventName": "L2_LINES_IN.I",
+    "BriefDescription": "L2 cache lines in I state filling L2",
+    "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf1",
+    "UMask": "0x02",
+    "EventName": "L2_LINES_IN.S",
+    "BriefDescription": "L2 cache lines in S state filling L2",
+    "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xf1",
+    "UMask": "0x04",
+    "EventName": "L2_LINES_IN.E",
+    "BriefDescription": "L2 cache lines in E state filling L2",
+    "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xF1",
+    "UMask": "0x07",
+    "EventName": "L2_LINES_IN.ALL",
+    "BriefDescription": "L2 cache lines filling L2",
+    "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xF2",
+    "UMask": "0x05",
+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
+    "BriefDescription": "Clean L2 cache lines evicted by demand",
+    "PublicDescription": "Clean L2 cache lines evicted by demand",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0xA0",
+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
+    "BriefDescription": "Taken speculative and retired mispredicted indirect calls",
+    "PublicDescription": "Taken speculative and retired mispredicted indirect calls",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x01",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
+    "BriefDescription": "Cycles per core when uops are exectuted in port 0",
+    "PublicDescription": "Cycles per core when uops are exectuted in port 0",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x02",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
+    "BriefDescription": "Cycles per core when uops are exectuted in port 1",
+    "PublicDescription": "Cycles per core when uops are exectuted in port 1",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x04",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
+    "BriefDescription": "Cycles per core when uops are dispatched to port 2",
+    "PublicDescription": "Cycles per core when uops are dispatched to port 2",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x08",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
+    "BriefDescription": "Cycles per core when uops are dispatched to port 3",
+    "PublicDescription": "Cycles per core when uops are dispatched to port 3",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x10",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
+    "BriefDescription": "Cycles per core when uops are exectuted in port 4",
+    "PublicDescription": "Cycles per core when uops are exectuted in port 4",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x20",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
+    "BriefDescription": "Cycles per core when uops are exectuted in port 5",
+    "PublicDescription": "Cycles per core when uops are exectuted in port 5",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x40",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
+    "BriefDescription": "Cycles per core when uops are exectuted in port 6",
+    "PublicDescription": "Cycles per core when uops are exectuted in port 6",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x80",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
+    "BriefDescription": "Cycles per core when uops are dispatched to port 7",
+    "PublicDescription": "Cycles per core when uops are dispatched to port 7",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC5",
+    "UMask": "0x20",
+    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
+    "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
+    "PublicDescription": "number of near branch instructions retired that were mispredicted and taken.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "400009",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x08",
+    "UMask": "0x0e",
+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x08",
+    "UMask": "0x60",
+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
+    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
+    "PublicDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x42",
+    "EventName": "L2_RQSTS.RFO_HIT",
+    "BriefDescription": "RFO requests that hit L2 cache",
+    "PublicDescription": "RFO requests that hit L2 cache",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x22",
+    "EventName": "L2_RQSTS.RFO_MISS",
+    "BriefDescription": "RFO requests that miss L2 cache",
+    "PublicDescription": "RFO requests that miss L2 cache",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x44",
+    "EventName": "L2_RQSTS.CODE_RD_HIT",
+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x24",
+    "EventName": "L2_RQSTS.CODE_RD_MISS",
+    "BriefDescription": "L2 cache misses when fetching instructions",
+    "PublicDescription": "L2 cache misses when fetching instructions",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x27",
+    "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
+    "BriefDescription": "Demand requests that miss L2 cache",
+    "PublicDescription": "Demand requests that miss L2 cache",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0xe7",
+    "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
+    "BriefDescription": "Demand requests to L2 cache",
+    "PublicDescription": "Demand requests to L2 cache",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0x3F",
+    "EventName": "L2_RQSTS.MISS",
+    "BriefDescription": "All requests that miss L2 cache",
+    "PublicDescription": "All requests that miss L2 cache",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x24",
+    "UMask": "0xFF",
+    "EventName": "L2_RQSTS.REFERENCES",
+    "BriefDescription": "All L2 requests",
+    "PublicDescription": "All L2 requests",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x49",
+    "UMask": "0x0e",
+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x49",
+    "UMask": "0x60",
+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",
+    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
+    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x85",
+    "UMask": "0x0e",
+    "EventName": "ITLB_MISSES.WALK_COMPLETED",
+    "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
+    "PublicDescription": "Misses in all ITLB levels that cause completed page walks",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x85",
+    "UMask": "0x60",
+    "EventName": "ITLB_MISSES.STLB_HIT",
+    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
+    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB1",
+    "UMask": "0x01",
+    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
+    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
+    "PublicDescription": "Cycles where at least 1 uop was executed per-thread",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB1",
+    "UMask": "0x01",
+    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
+    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
+    "PublicDescription": "Cycles where at least 2 uops were executed per-thread",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "2",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB1",
+    "UMask": "0x01",
+    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
+    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
+    "PublicDescription": "Cycles where at least 3 uops were executed per-thread",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "3",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB1",
+    "UMask": "0x01",
+    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
+    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
+    "PublicDescription": "Cycles where at least 4 uops were executed per-thread",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "4",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xe6",
+    "UMask": "0x1f",
+    "EventName": "BACLEARS.ANY",
+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB7, 0xBB",
+    "UMask": "0x01",
+    "EventName": "OFFCORE_RESPONSE",
+    "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xc7",
+    "UMask": "0x20",
+    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
+    "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+    "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x79",
+    "UMask": "0x30",
+    "EventName": "IDQ.MS_SWITCHES",
+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "1",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x08",
+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
+    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
+    "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.",
+    "Counter": "2",
+    "CounterHTOff": "2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "8",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x01",
+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
+    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
+    "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x02",
+    "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
+    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
+    "PublicDescription": "Cycles while memory subsystem has an outstanding load.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "2",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x04",
+    "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
+    "BriefDescription": "Total execution stalls.",
+    "PublicDescription": "Total execution stalls.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "4",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x0C",
+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
+    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
+    "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
+    "Counter": "2",
+    "CounterHTOff": "2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "12",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x05",
+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
+    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
+    "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "5",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA3",
+    "UMask": "0x06",
+    "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
+    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
+    "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "6",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC3",
+    "UMask": "0x01",
+    "EventName": "MACHINE_CLEARS.COUNT",
+    "BriefDescription": "Number of machine clears (nukes) of any type.",
+    "PublicDescription": "Number of machine clears (nukes) of any type.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "100003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "1",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA8",
+    "UMask": "0x01",
+    "EventName": "LSD.CYCLES_4_UOPS",
+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "4",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5E",
+    "UMask": "0x01",
+    "EventName": "RS_EVENTS.EMPTY_END",
+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "200003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "1",
+    "AnyThread": "0",
+    "EdgeDetect": "1",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA8",
+    "UMask": "0x01",
+    "EventName": "LSD.CYCLES_ACTIVE",
+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",
+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x01",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_0",
+    "BriefDescription": "Cycles per thread when uops are executed in port 0",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x02",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_1",
+    "BriefDescription": "Cycles per thread when uops are executed in port 1",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x04",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_2",
+    "BriefDescription": "Cycles per thread when uops are executed in port 2",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x08",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_3",
+    "BriefDescription": "Cycles per thread when uops are executed in port 3",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x10",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_4",
+    "BriefDescription": "Cycles per thread when uops are executed in port 4",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x20",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_5",
+    "BriefDescription": "Cycles per thread when uops are executed in port 5",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x40",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_6",
+    "BriefDescription": "Cycles per thread when uops are executed in port 6",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA1",
+    "UMask": "0x80",
+    "EventName": "UOPS_EXECUTED_PORT.PORT_7",
+    "BriefDescription": "Cycles per thread when uops are executed in port 7",
+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA0",
+    "UMask": "0x03",
+    "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
+    "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
+    "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more information.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x03",
+    "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
+    "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+    "PublicDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x3C",
+    "EventName": "FP_ARITH_INST_RETIRED.PACKED",
+    "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
+    "PublicDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000004",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x15",
+    "EventName": "FP_ARITH_INST_RETIRED.SINGLE",
+    "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?",
+    "PublicDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000005",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x2A",
+    "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
+    "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?",
+    "PublicDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3",
+    "SampleAfterValue": "2000006",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x00",
+    "UMask": "0x02",
+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",
+    "Counter": "Fixed counter 2",
+    "CounterHTOff": "Fixed counter 2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3C",
+    "UMask": "0x00",
+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3C",
+    "UMask": "0x01",
+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x0D",
+    "UMask": "0x03",
+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb1",
+    "UMask": "0x02",
+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb1",
+    "UMask": "0x02",
+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "2",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb1",
+    "UMask": "0x02",
+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "3",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb1",
+    "UMask": "0x02",
+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "4",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xb1",
+    "UMask": "0x02",
+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "0",
+    "Invert": "1",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0x01",
+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "6",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x48",
+    "UMask": "0x01",
+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
+    "Counter": "2",
+    "CounterHTOff": "2",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "1",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x48",
+    "UMask": "0x02",
+    "EventName": "L1D_PEND_MISS.FB_FULL",
+    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
+    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
+    "Counter": "0,1,2,3",
+    "CounterHTOff": "0,1,2,3,4,5,6,7",
+    "SampleAfterValue": "2000003",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "TakenAlone": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Data_LA": "0",
+    "L1_Hit_Indication": "0",
+    "Errata": "null",
+    "ELLC": "0",
+    "Offcore": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/BDW-DE/BroadwellDE_core_V1.tsv b/x86data/perfmon_data/BDW-DE/BroadwellDE_core_V1.tsv
new file mode 100644
index 0000000..1af9c6e
--- /dev/null
+++ b/x86data/perfmon_data/BDW-DE/BroadwellDE_core_V1.tsv
@@ -0,0 +1,323 @@
+# Performance Monitoring Events for  - V1
+# 7/22/2015 2:51:40 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata	ELLC
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	Cases when loads get true Block-on-Store blocking code preventing store forwarding	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x03	0x08	LD_BLOCKS.NO_SR	This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x01	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Load misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x10	DTLB_LOAD_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x20	DTLB_LOAD_MISSES.STLB_HIT_4K	Load misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0D	0x08	INT_MISC.RAT_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0E	0x10	UOPS_ISSUED.FLAGS_MERGE	Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0E	0x20	UOPS_ISSUED.SLOW_LEA	Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0E	0x40	UOPS_ISSUED.SINGLE_MUL	Number of Multiply packed/scalar single precision uops allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null	0
+0x14	0x01	ARITH.FPU_DIV_ACTIVE	Cycles when divider is busy executing divide operations	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x21	L2_RQSTS.DEMAND_DATA_RD_MISS	Demand Data Read miss L2, no rejects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x41	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x30	L2_RQSTS.L2_PF_MISS	L2 prefetch requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x50	L2_RQSTS.L2_PF_HIT	L2 prefetch requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xE1	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xE2	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xE4	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xF8	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x27	0x50	L2_DEMAND_RQSTS.WB_HIT	Not rejected writebacks that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x2e	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x2e	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x3c	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x3c	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other thread is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	2	2	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding.	2	2	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Store miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x10	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x20	DTLB_STORE_MISSES.STLB_HIT_4K	Store misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x4c	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x4f	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x01	TX_MEM.ABORT_CONFLICT	Number of times a TSX line had a cache conflict	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x02	TX_MEM.ABORT_CAPACITY_WRITE	Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x04	TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK	Number of times a TSX Abort was triggered due to a non-release/commit store to lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x08	TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY	Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x10	TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH	Number of times a TSX Abort was triggered due to release/commit but data and address mismatch	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x20	TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT	Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x40	TX_MEM.HLE_ELISION_BUFFER_FULL	Number of times we could not allocate Lock Buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x58	0x01	MOVE_ELIMINATION.INT_ELIMINATED	Number of integer Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x58	0x02	MOVE_ELIMINATION.SIMD_ELIMINATED	Number of SIMD Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x58	0x04	MOVE_ELIMINATION.INT_NOT_ELIMINATED	Number of integer Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x58	0x08	MOVE_ELIMINATION.SIMD_NOT_ELIMINATED	Number of SIMD Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	1	0	0	1	0	0	0	null	0
+0x5d	0x01	TX_EXEC.MISC1	Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5d	0x02	TX_EXEC.MISC2	Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5d	0x04	TX_EXEC.MISC3	Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5d	0x08	TX_EXEC.MISC4	Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5d	0x10	TX_EXEC.MISC5	Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null	0
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x80	0x02	ICACHE.MISSES	Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x80	0x04	ICACHE.IFDATA_STALL	Cycles where a code fetch is stalled due to L1 instruction-cache miss.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x02	ITLB_MISSES.WALK_COMPLETED_4K	Code miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x10	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x20	ITLB_MISSES.STLB_HIT_4K	Core misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x9c	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null	0
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x04	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x08	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x10	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x20	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Cycles while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Cycles while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	8	0	0	0	0	0	0	null	0
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_LDM_PENDING	Cycles while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null	0
+0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_EXECUTE	Total execution stalls	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Execution stalls while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	0	null	0
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_LDM_PENDING	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3	2000003	0	0	0	6	0	0	0	0	0	0	null	0
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Execution stalls while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	12	0	0	0	0	0	0	null	0
+0xa8	0x01	LSD.UOPS	Number of Uops delivered by the LSD. Read more on LSD under LSD_REPLAY.REPLAY	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xae	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0	null	0
+0xb0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb1	0x01	UOPS_EXECUTED.THREAD	Counts the number of uops to be executed per-thread each cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE	Number of uops executed on the core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xB1	0x01	UOPS_EXECUTED.STALL_CYCLES	Counts number of cycles no uops were dispatched to be executed on this thread.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null	0
+0xb2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Offcore requests buffer cannot take more entries for this thread core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x11	PAGE_WALKER_LOADS.DTLB_L1	Number of DTLB page walker hits in the L1+FB	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x21	PAGE_WALKER_LOADS.ITLB_L1	Number of ITLB page walker hits in the L1+FB	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x12	PAGE_WALKER_LOADS.DTLB_L2	Number of DTLB page walker hits in the L2	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x22	PAGE_WALKER_LOADS.ITLB_L2	Number of ITLB page walker hits in the L2	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x14	PAGE_WALKER_LOADS.DTLB_L3	Number of DTLB page walker hits in the L3 + XSNP	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x24	PAGE_WALKER_LOADS.ITLB_L3	Number of ITLB page walker hits in the L3 + XSNP	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x18	PAGE_WALKER_LOADS.DTLB_MEMORY	Number of DTLB page walker hits in Memory	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC0	0x02	INST_RETIRED.X87	FP operations  retired. X87 FP operations that have no exceptions:	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC0	0x01	INST_RETIRED.PREC_DIST	Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution	1	1	2000003	0	0	0	0	0	0	0	2	0	0	null	0
+0xC1	0x08	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC1	0x10	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC1	0x40	OTHER_ASSISTS.ANY_WB_ASSIST	Number of times any microcode assist is invoked by HW upon uop writeback.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	1	0	null	0
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null	0
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	0	null	0
+0xC3	0x01	MACHINE_CLEARS.CYCLES	Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null	0
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null	0
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null	0
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null	0
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null	0
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null	0
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0	null	0
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. (Precise Event - PEBS)	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null	0
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3).	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null	0
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null	0
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null	0
+0xC5	0x08	BR_MISP_RETIRED.RET	This event counts the number of mispredicted ret instructions retired. Non PEBS	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null	0
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. (Precise Event - PEBS)	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null	0
+0xC7	0x01	FP_ARITH_INST_RETIRED.SCALAR_DOUBLE	Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC7	0x02	FP_ARITH_INST_RETIRED.SCALAR_SINGLE	Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC7	0x04	FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE	Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC7	0x08	FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE	Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC7	0x10	FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE	Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xc8	0x01	HLE_RETIRED.START	Number of times we entered an HLE region; does not count nested transactions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x02	HLE_RETIRED.COMMIT	Number of times HLE commit succeeded	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x04	HLE_RETIRED.ABORTED	Number of times HLE abort was triggered	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xc8	0x08	HLE_RETIRED.ABORTED_MISC1	Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x10	HLE_RETIRED.ABORTED_MISC2	Number of times an HLE execution aborted due to uncommon conditions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x20	HLE_RETIRED.ABORTED_MISC3	Number of times an HLE execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x40	HLE_RETIRED.ABORTED_MISC4	Number of times an HLE execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x80	HLE_RETIRED.ABORTED_MISC5	Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x01	RTM_RETIRED.START	Number of times we entered an RTM region; does not count nested transactions	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x02	RTM_RETIRED.COMMIT	Number of times RTM commit succeeded	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x04	RTM_RETIRED.ABORTED	Number of times RTM abort was triggered	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xc9	0x08	RTM_RETIRED.ABORTED_MISC1	Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x10	RTM_RETIRED.ABORTED_MISC2	Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x20	RTM_RETIRED.ABORTED_MISC3	Number of times an RTM execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x40	RTM_RETIRED.ABORTED_MISC4	Number of times an RTM execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x80	RTM_RETIRED.ABORTED_MISC5	Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	0	null	0
+0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32	3	3	100007	0x3F6	0x20	1	0	0	0	0	2	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	0	null	0
+0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null	0
+0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	null	0
+0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null	0
+0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null	0
+0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	null	0
+0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	null	0
+0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	1	null	0
+0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	null	0
+0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null	0
+0xD1	0x04	MEM_LOAD_UOPS_RETIRED.L3_HIT	Retired load uops which data sources were data hits in L3 without snoops required.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	null	0
+0xD1	0x08	MEM_LOAD_UOPS_RETIRED.L1_MISS	Retired load uops misses in L1 cache as data sources.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null	0
+0xD1	0x10	MEM_LOAD_UOPS_RETIRED.L2_MISS	Miss in mid-level (L2) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	null	0
+0xD1	0x20	MEM_LOAD_UOPS_RETIRED.L3_MISS	Miss in last-level (L3) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null	0
+0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null	0
+0xD2	0x01	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null	0
+0xD2	0x02	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null	0
+0xD2	0x04	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared L3.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null	0
+0xD2	0x08	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in L3 without snoops required.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null	0
+0xD3	0x01	MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM	Data from local DRAM either Snoop not needed or Snoop Miss (RspI)	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null	0
+0x3c	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x08	L2_TRANS.ALL_PF	L2 or L3 HW prefetches that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xF2	0x05	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x01	UOPS_EXECUTED_PORT.PORT_0_CORE	Cycles per core when uops are exectuted in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x02	UOPS_EXECUTED_PORT.PORT_1_CORE	Cycles per core when uops are exectuted in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x04	UOPS_EXECUTED_PORT.PORT_2_CORE	Cycles per core when uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x08	UOPS_EXECUTED_PORT.PORT_3_CORE	Cycles per core when uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x10	UOPS_EXECUTED_PORT.PORT_4_CORE	Cycles per core when uops are exectuted in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x20	UOPS_EXECUTED_PORT.PORT_5_CORE	Cycles per core when uops are exectuted in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x40	UOPS_EXECUTED_PORT.PORT_6_CORE	Cycles per core when uops are exectuted in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x80	UOPS_EXECUTED_PORT.PORT_7_CORE	Cycles per core when uops are dispatched to port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xC5	0x20	BR_MISP_RETIRED.NEAR_TAKEN	number of near branch instructions retired that were mispredicted and taken.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null	0
+0x08	0x0e	DTLB_LOAD_MISSES.WALK_COMPLETED	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x60	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x42	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x22	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x44	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x24	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x27	L2_RQSTS.ALL_DEMAND_MISS	Demand requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xe7	L2_RQSTS.ALL_DEMAND_REFERENCES	Demand requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x3F	L2_RQSTS.MISS	All requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x0e	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x60	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x0e	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x60	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC	Cycles where at least 1 uop was executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC	Cycles where at least 2 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null	0
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC	Cycles where at least 3 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0	null	0
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC	Cycles where at least 4 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0xe6	0x1f	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE	Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc7	0x20	FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE	Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null	0
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_MISS	Cycles while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	8	0	0	0	0	0	0	null	0
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_MISS	Cycles while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_MEM_ANY	Cycles while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null	0
+0xA3	0x04	CYCLE_ACTIVITY.STALLS_TOTAL	Total execution stalls.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_MISS	Execution stalls while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	12	0	0	0	0	0	0	null	0
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_MISS	Execution stalls while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	5	0	0	0	0	0	0	null	0
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_MEM_ANY	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null	0
+0xC3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0	null	0
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	1	1	0	1	0	0	0	null	0
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xA1	0x01	UOPS_EXECUTED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x02	UOPS_EXECUTED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x04	UOPS_EXECUTED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x08	UOPS_EXECUTED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x10	UOPS_EXECUTED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x20	UOPS_EXECUTED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x40	UOPS_EXECUTED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x80	UOPS_EXECUTED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA0	0x03	UOP_DISPATCHES_CANCELLED.SIMD_PRF	Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC7	0x03	FP_ARITH_INST_RETIRED.SCALAR	Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC7	0x3C	FP_ARITH_INST_RETIRED.PACKED	Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. 	0,1,2,3	0,1,2,3	2000004	0	0	0	0	0	0	0	0	0	0	null	0
+0xC7	0x15	FP_ARITH_INST_RETIRED.SINGLE	Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?	0,1,2,3	0,1,2,3	2000005	0	0	0	0	0	0	0	0	0	0	null	0
+0xC7	0x2A	FP_ARITH_INST_RETIRED.DOUBLE	Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?	0,1,2,3	0,1,2,3	2000006	0	0	0	0	0	0	0	0	0	0	null	0
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	1	0	0	0	0	0	null	0
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null	0
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	2	2	2000003	0	0	0	1	0	1	0	0	0	0	null	0
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
diff --git a/x86data/perfmon_data/BDW-DE/BroadwellDE_uncore_V1.json b/x86data/perfmon_data/BDW-DE/BroadwellDE_uncore_V1.json
new file mode 100644
index 0000000..c12885d
--- /dev/null
+++ b/x86data/perfmon_data/BDW-DE/BroadwellDE_uncore_V1.json
@@ -0,0 +1,10802 @@
+[
+  {
+    "Unit": "CBO",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_C_BOUNCE_CONTROL",
+    "BriefDescription": "Bounce Control",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_C_CLOCKTICKS",
+    "BriefDescription": "Uncore Clocks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1F",
+    "UMask": "0x0",
+    "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+    "BriefDescription": "Counter 0 Occupancy",
+    "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_C_FAST_ASSERTED",
+    "BriefDescription": "FaST wire asserted",
+    "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted.  Incoming distress includes both up and dn.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x3",
+    "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+    "BriefDescription": "Cache Lookups; Data Read Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x5",
+    "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+    "BriefDescription": "Cache Lookups; Write Requests",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x9",
+    "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+    "BriefDescription": "Cache Lookups; External Snoop Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x11",
+    "EventName": "UNC_C_LLC_LOOKUP.ANY",
+    "BriefDescription": "Cache Lookups; Any Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x41",
+    "EventName": "UNC_C_LLC_LOOKUP.NID",
+    "BriefDescription": "Cache Lookups; Lookups that Match NID",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x21",
+    "EventName": "UNC_C_LLC_LOOKUP.READ",
+    "BriefDescription": "Cache Lookups; Any Read Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[22:18]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x1",
+    "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+    "BriefDescription": "Lines Victimized; Lines in M state",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x2",
+    "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+    "BriefDescription": "Lines Victimized; Lines in E state",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x4",
+    "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
+    "BriefDescription": "Lines Victimized; Lines in S State",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x8",
+    "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
+    "BriefDescription": "Lines Victimized",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x40",
+    "EventName": "UNC_C_LLC_VICTIMS.NID",
+    "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x10",
+    "EventName": "UNC_C_LLC_VICTIMS.MISS",
+    "BriefDescription": "Lines Victimized",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x1",
+    "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+    "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x2",
+    "EventName": "UNC_C_MISC.WC_ALIASING",
+    "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x4",
+    "EventName": "UNC_C_MISC.STARTED",
+    "BriefDescription": "Cbo Misc",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x8",
+    "EventName": "UNC_C_MISC.RFO_HIT_S",
+    "BriefDescription": "Cbo Misc; RFO HitS",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state.  This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x10",
+    "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+    "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x20",
+    "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+    "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x1",
+    "EventName": "UNC_C_QLRU.AGE0",
+    "BriefDescription": "LRU Queue; LRU Age 0",
+    "PublicDescription": "How often age was set to 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x2",
+    "EventName": "UNC_C_QLRU.AGE1",
+    "BriefDescription": "LRU Queue; LRU Age 1",
+    "PublicDescription": "How often age was set to 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x4",
+    "EventName": "UNC_C_QLRU.AGE2",
+    "BriefDescription": "LRU Queue; LRU Age 2",
+    "PublicDescription": "How often age was set to 2",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x8",
+    "EventName": "UNC_C_QLRU.AGE3",
+    "BriefDescription": "LRU Queue; LRU Age 3",
+    "PublicDescription": "How often age was set to 3",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x10",
+    "EventName": "UNC_C_QLRU.LRU_DECREMENT",
+    "BriefDescription": "LRU Queue; LRU Bits Decremented",
+    "PublicDescription": "How often all LRU bits were decremented by 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x20",
+    "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
+    "BriefDescription": "LRU Queue; Non-0 Aged Victim",
+    "PublicDescription": "How often we picked a victim that had a non-zero age",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+    "BriefDescription": "AD Ring In Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_AD_USED.UP_ODD",
+    "BriefDescription": "AD Ring In Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
+    "BriefDescription": "AD Ring In Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
+    "BriefDescription": "AD Ring In Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_AD_USED.CW",
+    "BriefDescription": "AD Ring In Use; Up",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_AD_USED.CCW",
+    "BriefDescription": "AD Ring In Use; Down",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_AD_USED.ALL",
+    "BriefDescription": "AD Ring In Use; All",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
+    "BriefDescription": "AK Ring In Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_AK_USED.UP_ODD",
+    "BriefDescription": "AK Ring In Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
+    "BriefDescription": "AK Ring In Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
+    "BriefDescription": "AK Ring In Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_AK_USED.CW",
+    "BriefDescription": "AK Ring In Use; Up",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_AK_USED.CCW",
+    "BriefDescription": "AK Ring In Use; Down",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_AK_USED.ALL",
+    "BriefDescription": "AK Ring In Use; All",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
+    "BriefDescription": "BL Ring in Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BL_USED.UP_ODD",
+    "BriefDescription": "BL Ring in Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
+    "BriefDescription": "BL Ring in Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
+    "BriefDescription": "BL Ring in Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_BL_USED.CW",
+    "BriefDescription": "BL Ring in Use; Up",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_BL_USED.CCW",
+    "BriefDescription": "BL Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_BL_USED.ALL",
+    "BriefDescription": "BL Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_BOUNCES.AD",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BOUNCES.AK",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BOUNCES.BL",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RING_BOUNCES.IV",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1E",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_IV_USED.ANY",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1E",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_IV_USED.UP",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1E",
+    "UMask": "0xCC",
+    "EventName": "UNC_C_RING_IV_USED.DOWN",
+    "BriefDescription": "BL Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1E",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_IV_USED.DN",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_SINK_STARVED.AD",
+    "BriefDescription": "AD",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_SINK_STARVED.AK",
+    "BriefDescription": "AK",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_SINK_STARVED.IV",
+    "BriefDescription": "IV",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_SINK_STARVED.BL",
+    "BriefDescription": "BL",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_C_RING_SRC_THRTL",
+    "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ",
+    "BriefDescription": "Ingress Allocations; IRQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
+    "BriefDescription": "Ingress Allocations; IRQ Rejected",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_INSERTS.IPQ",
+    "BriefDescription": "Ingress Allocations; IPQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_INSERTS.PRQ",
+    "BriefDescription": "Ingress Allocations; PRQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
+    "BriefDescription": "Ingress Allocations; PRQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
+    "BriefDescription": "Probe Queue Retries; Any Reject",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject.  TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
+    "BriefDescription": "Probe Queue Retries; No Egress Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full.  IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
+    "BriefDescription": "Probe Queue Retries; Address Conflict",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts.  Address conflicts out of the IPQ should be rare.  They will generally only occur if two different sockets are sending requests to the same address at the same time.  This is a true 'conflict' case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "Probe Queue Retries; No QPI Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
+    "BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x28",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
+    "BriefDescription": "Probe Queue Retries; Target Node Filter",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
+    "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
+    "PublicDescription": "Counts the number of IRQ retries that occur.  Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons.  Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
+    "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
+    "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress.  The egress is the buffer that queues up for allocating onto the ring.  IRQ requests can make use of all four rings and all four Egresses.  If any of the queues that a given request needs to make use of are full, the request will be retried.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+    "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+    "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR.  In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo.  Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete.  This comes up most commonly with prefetches.  Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC.  Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+    "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
+    "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available.  RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory.  If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available.  Note that there are multiple RTID pools for the different sockets.  There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available.  This event does not provide any filtering for this case.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
+    "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits.  These credits are required in order to send transactions to the QPI agent.  Please see the QPI_IGR_CREDITS events for more information.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
+    "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
+    "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
+    "BriefDescription": "Ingress Request Queue Rejects",
+    "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
+    "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
+    "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
+    "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
+    "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x29",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
+    "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
+    "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
+    "BriefDescription": "ISMQ Retries; Any Reject",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject.  ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries).  ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID.  Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
+    "BriefDescription": "ISMQ Retries; No Egress Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring.  If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+    "BriefDescription": "ISMQ Retries; No RTIDs",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs.  M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory.  If no RTIDs are available, they will be retried.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "ISMQ Retries; No QPI Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+    "BriefDescription": "ISMQ Retries; No IIO Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x80",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
+    "BriefDescription": "ISMQ Retries",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
+    "BriefDescription": "ISMQ Retries",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2A",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
+    "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
+    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2A",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
+    "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
+    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2A",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
+    "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
+    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
+    "BriefDescription": "Ingress Occupancy; IRQ",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
+    "BriefDescription": "Ingress Occupancy; IRQ Rejected",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+    "BriefDescription": "Ingress Occupancy; IPQ",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ",
+    "BriefDescription": "Ingress Occupancy; PRQ Rejects",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3D",
+    "UMask": "0x1",
+    "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3D",
+    "UMask": "0x2",
+    "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3E",
+    "UMask": "0x1",
+    "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3E",
+    "UMask": "0x2",
+    "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TOR_INSERTS.OPCODE",
+    "BriefDescription": "TOR Inserts; Opcode Match",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TOR_INSERTS.EVICTION",
+    "BriefDescription": "TOR Inserts; Evictions",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Eviction transactions inserted into the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TOR_INSERTS.ALL",
+    "BriefDescription": "TOR Inserts; All",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR.    This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TOR_INSERTS.WB",
+    "BriefDescription": "TOR Inserts; Writebacks",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Write transactions inserted into the TOR.   This does not include 'RFO', but actual operations that contain data being sent from the core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x3",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
+    "BriefDescription": "TOR Inserts; Miss Opcode Match",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x41",
+    "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
+    "BriefDescription": "TOR Inserts; NID and Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x44",
+    "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
+    "BriefDescription": "TOR Inserts; NID Matched Evictions",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x48",
+    "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
+    "BriefDescription": "TOR Inserts; NID Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.  In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x50",
+    "EventName": "UNC_C_TOR_INSERTS.NID_WB",
+    "BriefDescription": "TOR Inserts; NID Matched Writebacks",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched write transactions inserted into the TOR.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x43",
+    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+    "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x4A",
+    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+    "BriefDescription": "TOR Inserts; NID Matched Miss All",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x2A",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
+    "BriefDescription": "TOR Inserts; Misses to Local Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x8A",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
+    "BriefDescription": "TOR Inserts; Misses to Remote Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x28",
+    "EventName": "UNC_C_TOR_INSERTS.LOCAL",
+    "BriefDescription": "TOR Inserts; Local Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x88",
+    "EventName": "UNC_C_TOR_INSERTS.REMOTE",
+    "BriefDescription": "TOR Inserts; Remote Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x23",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
+    "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x83",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
+    "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x21",
+    "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
+    "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x81",
+    "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
+    "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+    "BriefDescription": "TOR Occupancy; Opcode Match",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
+    "BriefDescription": "TOR Occupancy; Evictions",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+    "BriefDescription": "TOR Occupancy; Any",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries.  This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x3",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
+    "BriefDescription": "TOR Occupancy; Miss Opcode Match",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0xA",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
+    "BriefDescription": "TOR Occupancy; Miss All",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x41",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+    "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x44",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
+    "BriefDescription": "TOR Occupancy; NID Matched Evictions",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x48",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+    "BriefDescription": "TOR Occupancy; NID Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x43",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
+    "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x4A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
+    "BriefDescription": "TOR Occupancy; NID Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x2A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x8A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x28",
+    "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x88",
+    "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x23",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
+    "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x83",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+    "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x21",
+    "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
+    "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x81",
+    "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
+    "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TOR_OCCUPANCY.WB",
+    "BriefDescription": "TOR Occupancy; Writebacks",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR.   This does not include 'RFO', but actual operations that contain data being sent from the core.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x50",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
+    "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TxR_ADS_USED.AD",
+    "BriefDescription": "Onto AD Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_ADS_USED.AK",
+    "BriefDescription": "Onto AK Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_ADS_USED.BL",
+    "BriefDescription": "Onto BL Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
+    "BriefDescription": "Egress Allocations; AD - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
+    "BriefDescription": "Egress Allocations; AK - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
+    "BriefDescription": "Egress Allocations; BL - Cacheno",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
+    "BriefDescription": "Egress Allocations; IV - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring.  This is commonly used for snoops to the cores.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
+    "BriefDescription": "Egress Allocations; AD - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring.  This is commonly used for outbound requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x20",
+    "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
+    "BriefDescription": "Egress Allocations; AK - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring.  This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x40",
+    "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
+    "BriefDescription": "Egress Allocations; BL - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring.  This is commonly used for transfering writeback data to the cache.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
+    "BriefDescription": "Injection Starvation; Onto AK Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
+    "BriefDescription": "Injection Starvation; Onto BL Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TxR_STARVED.IV",
+    "BriefDescription": "Injection Starvation; Onto IV Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TxR_STARVED.AD_CORE",
+    "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x3",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
+    "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x1",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
+    "BriefDescription": "QPI Address/Opcode Match; Address",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x2",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
+    "BriefDescription": "QPI Address/Opcode Match; Opcode",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x4",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
+    "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x8",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
+    "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x10",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
+    "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_H_BT_CYCLES_NE",
+    "BriefDescription": "BT Cycles Not Empty",
+    "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x4",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x8",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x10",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_H_BYPASS_IMC.TAKEN",
+    "BriefDescription": "HA to iMC Bypass; Taken",
+    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
+    "BriefDescription": "HA to iMC Bypass; Not Taken",
+    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_H_CLOCKTICKS",
+    "BriefDescription": "uclks",
+    "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x11",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_COUNT",
+    "BriefDescription": "Direct2Core Messages Sent",
+    "PublicDescription": "Number of Direct2Core messages sent",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
+    "BriefDescription": "Cycles when Direct2Core was Disabled",
+    "PublicDescription": "Number of cycles in which Direct2Core was disabled",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x13",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
+    "BriefDescription": "Number of Reads that had Direct2Core Overridden",
+    "PublicDescription": "Number of Reads where Direct2Core overridden",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x41",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECTORY_LAT_OPT",
+    "BriefDescription": "Directory Lat Opt Return",
+    "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xC",
+    "UMask": "0x1",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
+    "BriefDescription": "Directory Lookups; Snoop Needed",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xC",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
+    "BriefDescription": "Directory Lookups; Snoop Not Needed",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xD",
+    "UMask": "0x1",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
+    "BriefDescription": "Directory Updates; Directory Set",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory sets.  This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xD",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
+    "BriefDescription": "Directory Updates; Directory Clear",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory clears.  This occurs when snoops were sent and all returned with RspI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xD",
+    "UMask": "0x3",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
+    "BriefDescription": "Directory Updates; Any Directory Update",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x1",
+    "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x2",
+    "EventName": "UNC_H_HITME_HIT.WBMTOI",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x4",
+    "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x8",
+    "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x10",
+    "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x20",
+    "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x40",
+    "EventName": "UNC_H_HITME_HIT.RSPFWDS",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x80",
+    "EventName": "UNC_H_HITME_HIT.RSP",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x70",
+    "EventName": "UNC_H_HITME_HIT.ALLOCS",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x42",
+    "EventName": "UNC_H_HITME_HIT.EVICTS",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x26",
+    "EventName": "UNC_H_HITME_HIT.INVALS",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0xFF",
+    "EventName": "UNC_H_HITME_HIT.ALL",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0xF",
+    "EventName": "UNC_H_HITME_HIT.HOM",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x1",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x2",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x4",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x8",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x10",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x20",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x40",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x80",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0xFF",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0xF",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x1",
+    "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x2",
+    "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x4",
+    "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x8",
+    "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x10",
+    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x20",
+    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x40",
+    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x80",
+    "EventName": "UNC_H_HITME_LOOKUP.RSP",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x70",
+    "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x26",
+    "EventName": "UNC_H_HITME_LOOKUP.INVALS",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0xFF",
+    "EventName": "UNC_H_HITME_LOOKUP.ALL",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0xF",
+    "EventName": "UNC_H_HITME_LOOKUP.HOM",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
+    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
+    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x8",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x10",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x20",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IMC_READS.NORMAL",
+    "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
+    "PublicDescription": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1E",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IMC_RETRY",
+    "BriefDescription": "Retry Events",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IMC_WRITES.FULL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0x8",
+    "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0xF",
+    "EventName": "UNC_H_IMC_WRITES.ALL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x61",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
+    "BriefDescription": "IOT Backpressure",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x61",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
+    "BriefDescription": "IOT Backpressure",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x64",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x64",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x65",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IOT_CTS_HI.CTS2",
+    "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x65",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IOT_CTS_HI.CTS3",
+    "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x62",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x62",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x2",
+    "EventName": "UNC_H_OSB.READS_LOCAL",
+    "BriefDescription": "OSB Snoop Broadcast; Local Reads",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x4",
+    "EventName": "UNC_H_OSB.INVITOE_LOCAL",
+    "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x8",
+    "EventName": "UNC_H_OSB.REMOTE",
+    "BriefDescription": "OSB Snoop Broadcast; Remote",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x10",
+    "EventName": "UNC_H_OSB.CANCELLED",
+    "BriefDescription": "OSB Snoop Broadcast; Cancelled",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x20",
+    "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
+    "BriefDescription": "OSB Snoop Broadcast; Reads Local -  Useful",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x40",
+    "EventName": "UNC_H_OSB.REMOTE_USEFUL",
+    "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x1",
+    "EventName": "UNC_H_OSB_EDR.ALL",
+    "BriefDescription": "OSB Early Data Return; All",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x2",
+    "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
+    "BriefDescription": "OSB Early Data Return; Reads to Local  I",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x4",
+    "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
+    "BriefDescription": "OSB Early Data Return; Reads to Remote I",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x8",
+    "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
+    "BriefDescription": "OSB Early Data Return; Reads to Local S",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x10",
+    "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
+    "BriefDescription": "OSB Early Data Return; Reads to Remote S",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x3",
+    "EventName": "UNC_H_REQUESTS.READS",
+    "BriefDescription": "Read and Write Requests; Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests.  This is a good proxy for LLC Read Misses (including RFOs).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0xC",
+    "EventName": "UNC_H_REQUESTS.WRITES",
+    "BriefDescription": "Read and Write Requests; Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket.  This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_H_REQUESTS.READS_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket.  This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x10",
+    "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local InvItoEs",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x20",
+    "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote InvItoEs",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_AD_USED.CW_ODD",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x3",
+    "EventName": "UNC_H_RING_AD_USED.CW",
+    "BriefDescription": "HA AD Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0xC",
+    "EventName": "UNC_H_RING_AD_USED.CCW",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_AK_USED.CW_ODD",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x3",
+    "EventName": "UNC_H_RING_AK_USED.CW",
+    "BriefDescription": "HA AK Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0xC",
+    "EventName": "UNC_H_RING_AK_USED.CCW",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0xF",
+    "EventName": "UNC_H_RING_AK_USED.ALL",
+    "BriefDescription": "HA AK Ring in Use; All",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_BL_USED.CW_ODD",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x3",
+    "EventName": "UNC_H_RING_BL_USED.CW",
+    "BriefDescription": "HA BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0xC",
+    "EventName": "UNC_H_RING_BL_USED.CCW",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0xF",
+    "EventName": "UNC_H_RING_BL_USED.ALL",
+    "BriefDescription": "HA BL Ring in Use; All",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x68",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x68",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6A",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6A",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x69",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x69",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6B",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6B",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xA",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
+    "BriefDescription": "Data beat the Snoop Responses; Local Requests",
+    "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xA",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
+    "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
+    "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
+    "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
+    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
+    "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
+    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x8",
+    "UMask": "0x3",
+    "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
+    "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
+    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
+    "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
+    "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
+    "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
+    "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOP_RESP.RSPI",
+    "BriefDescription": "Snoop Responses Received; RspI",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOP_RESP.RSPS",
+    "BriefDescription": "Snoop Responses Received; RspS",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x4",
+    "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+    "BriefDescription": "Snoop Responses Received; RspIFwd",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x8",
+    "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+    "BriefDescription": "Snoop Responses Received; RspSFwd",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x10",
+    "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+    "BriefDescription": "Snoop Responses Received; Rsp*WB",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x20",
+    "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+    "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x40",
+    "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+    "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
+    "BriefDescription": "Snoop Responses Received Local; RspI",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
+    "BriefDescription": "Snoop Responses Received Local; RspS",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x4",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
+    "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x8",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
+    "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x10",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
+    "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x20",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
+    "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x40",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
+    "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x80",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
+    "BriefDescription": "Snoop Responses Received Local; Other",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for all other snoop responses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6C",
+    "UMask": "0x1",
+    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6C",
+    "UMask": "0x2",
+    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6C",
+    "UMask": "0x4",
+    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6C",
+    "UMask": "0x8",
+    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x10",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x20",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x40",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x80",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1C",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1C",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1C",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1C",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
+    "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used.  It will not return valid count when BT is disabled.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
+    "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries.  It will not return valid count when BT is disabled.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
+    "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
+    "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
+    "BriefDescription": "Tracker Cycles Not Empty; All Requests",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
+    "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
+    "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x10",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
+    "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x20",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
+    "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x40",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+    "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x80",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
+    "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x5",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
+    "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
+    "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
+    "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
+    "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xF",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TxR_AD.HOM",
+    "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
+    "PublicDescription": "Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring.  NDR stands for 'non-data response' and is generally used for completions that do not include data.  AD NDR is used for transactions to remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2A",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
+    "BriefDescription": "AD Egress Full; Scheduler 0",
+    "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2A",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
+    "BriefDescription": "AD Egress Full; Scheduler 1",
+    "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2A",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+    "BriefDescription": "AD Egress Full; All",
+    "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
+    "BriefDescription": "AD Egress Not Empty; Scheduler 0",
+    "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
+    "BriefDescription": "AD Egress Not Empty; Scheduler 1",
+    "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+    "BriefDescription": "AD Egress Not Empty; All",
+    "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
+    "BriefDescription": "AD Egress Allocations; Scheduler 0",
+    "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
+    "BriefDescription": "AD Egress Allocations; Scheduler 1",
+    "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+    "BriefDescription": "AD Egress Allocations; All",
+    "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
+    "BriefDescription": "AK Egress Full; Scheduler 0",
+    "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
+    "BriefDescription": "AK Egress Full; Scheduler 1",
+    "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+    "BriefDescription": "AK Egress Full; All",
+    "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
+    "BriefDescription": "AK Egress Not Empty; Scheduler 0",
+    "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
+    "BriefDescription": "AK Egress Not Empty; Scheduler 1",
+    "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+    "BriefDescription": "AK Egress Not Empty; All",
+    "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2F",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
+    "BriefDescription": "AK Egress Allocations; Scheduler 0",
+    "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2F",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
+    "BriefDescription": "AK Egress Allocations; Scheduler 1",
+    "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2F",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
+    "BriefDescription": "AK Egress Allocations; All",
+    "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL.DRS_CACHE",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to the cache.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL.DRS_CORE",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TxR_BL.DRS_QPI",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
+    "BriefDescription": "BL Egress Full; Scheduler 0",
+    "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
+    "BriefDescription": "BL Egress Full; Scheduler 1",
+    "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+    "BriefDescription": "BL Egress Full; All",
+    "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
+    "BriefDescription": "BL Egress Not Empty; Scheduler 0",
+    "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
+    "BriefDescription": "BL Egress Not Empty; Scheduler 1",
+    "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+    "BriefDescription": "BL Egress Not Empty; All",
+    "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
+    "BriefDescription": "BL Egress Allocations; Scheduler 0",
+    "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
+    "BriefDescription": "BL Egress Allocations; Scheduler 1",
+    "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
+    "BriefDescription": "BL Egress Allocations; All",
+    "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6D",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_STARVED.AK",
+    "BriefDescription": "Injection Starvation; For AK Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6D",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_STARVED.BL",
+    "BriefDescription": "Injection Starvation; For BL Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x1",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x2",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x4",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x8",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x1",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x2",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x4",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x8",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+    "BriefDescription": "Total Write Cache Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
+    "BriefDescription": "Total Write Cache Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_I_CLOCKTICKS",
+    "BriefDescription": "Clocks in the IRP",
+    "PublicDescription": "Number of clocks in the IRP.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+    "BriefDescription": "Coherent Ops; PCIRdCur",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_I_COHERENT_OPS.CRD",
+    "BriefDescription": "Coherent Ops; CRd",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_I_COHERENT_OPS.DRD",
+    "BriefDescription": "Coherent Ops; DRd",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_I_COHERENT_OPS.RFO",
+    "BriefDescription": "Coherent Ops; RFO",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+    "BriefDescription": "Coherent Ops; PCIItoM",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+    "BriefDescription": "Coherent Ops; PCIDCAHin5t",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x40",
+    "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+    "BriefDescription": "Coherent Ops; WbMtoI",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x80",
+    "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+    "BriefDescription": "Coherent Ops; CLFlush",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_I_MISC0.FAST_REQ",
+    "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_I_MISC0.FAST_REJ",
+    "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x4",
+    "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x8",
+    "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x10",
+    "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x20",
+    "EventName": "UNC_I_MISC0.FAST_XFER",
+    "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x40",
+    "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+    "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x80",
+    "EventName": "UNC_I_MISC0.PF_TIMEOUT",
+    "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
+    "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch.   This happens in the case of a prefetch TimeOut",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_I_MISC1.SLOW_I",
+    "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
+    "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_I_MISC1.SLOW_S",
+    "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
+    "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_I_MISC1.SLOW_E",
+    "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
+    "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_I_MISC1.SLOW_M",
+    "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
+    "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x10",
+    "EventName": "UNC_I_MISC1.LOST_FWD",
+    "BriefDescription": "Misc Events - Set 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x20",
+    "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+    "BriefDescription": "Misc Events - Set 1; Received Invalid",
+    "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x40",
+    "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+    "BriefDescription": "Misc Events - Set 1; Received Valid",
+    "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x80",
+    "EventName": "UNC_I_MISC1.DATA_THROTTLE",
+    "BriefDescription": "Misc Events - Set 1; Data Throttled",
+    "PublicDescription": "IRP throttled switch data",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_AK_INSERTS",
+    "BriefDescription": "AK Ingress Occupancy",
+    "PublicDescription": "Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - DRS",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x2",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - NCB",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x8",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x3",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - NCS",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_I_SNOOP_RESP.MISS",
+    "BriefDescription": "Snoop Responses; Miss",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x2",
+    "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+    "BriefDescription": "Snoop Responses; Hit I",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x4",
+    "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+    "BriefDescription": "Snoop Responses; Hit E or S",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x8",
+    "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+    "BriefDescription": "Snoop Responses; Hit M",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x10",
+    "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+    "BriefDescription": "Snoop Responses; SnpCode",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x20",
+    "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+    "BriefDescription": "Snoop Responses; SnpData",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x40",
+    "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+    "BriefDescription": "Snoop Responses; SnpInv",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_I_TRANSACTIONS.READS",
+    "BriefDescription": "Inbound Transaction Count; Reads",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_I_TRANSACTIONS.WRITES",
+    "BriefDescription": "Inbound Transaction Count; Writes",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x4",
+    "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
+    "BriefDescription": "Inbound Transaction Count; Read Prefetches",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x8",
+    "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+    "BriefDescription": "Inbound Transaction Count; Write Prefetches",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x10",
+    "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+    "BriefDescription": "Inbound Transaction Count; Atomic",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x20",
+    "EventName": "UNC_I_TRANSACTIONS.OTHER",
+    "BriefDescription": "Inbound Transaction Count; Other",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x40",
+    "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+    "BriefDescription": "Inbound Transaction Count; Select Source",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.  If this bit is not set, then requests from all sources will be counted.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "IRPFilter[4:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x18",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
+    "BriefDescription": "No AD Egress Credit Stalls",
+    "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x19",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
+    "BriefDescription": "No BL Egress Credit Stalls",
+    "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xE",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
+    "BriefDescription": "Outbound Read Requests",
+    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xF",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
+    "BriefDescription": "Outbound Read Requests",
+    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xD",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
+    "BriefDescription": "Outbound Request Queue Occupancy",
+    "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CLOCKTICKS",
+    "BriefDescription": "pclk Cycles",
+    "PublicDescription": "The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x60",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6A",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6B",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6C",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6D",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6E",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6F",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x70",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x71",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x61",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x62",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x63",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x64",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x65",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x66",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x67",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x68",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x69",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x30",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE0",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x31",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE1",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3A",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE10",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3B",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE11",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3C",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE12",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3D",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE13",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3E",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE14",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3F",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE15",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x40",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE16",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x41",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE17",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x32",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE2",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x33",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE3",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x34",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE4",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x35",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE5",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x36",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE6",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x37",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE7",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE8",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x39",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE9",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
+    "BriefDescription": "Thermal Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
+    "BriefDescription": "OS Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
+    "BriefDescription": "Power Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x73",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
+    "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x74",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_TRANS_CYCLES",
+    "BriefDescription": "Cycles spent changing Frequency",
+    "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2F",
+    "UMask": "0x0",
+    "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
+    "BriefDescription": "Memory Phase Shedding Cycles",
+    "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2A",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
+    "BriefDescription": "Package C State Residency - C0",
+    "PublicDescription": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x4E",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+    "BriefDescription": "Package C State Residency - C1E",
+    "PublicDescription": "Counts the number of cycles when the package was in C1E.  This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2B",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
+    "BriefDescription": "Package C State Residency - C2E",
+    "PublicDescription": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2C",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
+    "BriefDescription": "Package C State Residency - C3",
+    "PublicDescription": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2D",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
+    "BriefDescription": "Package C State Residency - C6",
+    "PublicDescription": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2E",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
+    "BriefDescription": "Package C7 State Residency",
+    "PublicDescription": "Counts the number of cycles when the package was in C7.  This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0x40",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+    "BriefDescription": "Number of cores in C-State; C0 and C1",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0x80",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+    "BriefDescription": "Number of cores in C-State; C3",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0xC0",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+    "BriefDescription": "Number of cores in C-State; C6 and C7",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+    "BriefDescription": "External Prochot",
+    "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+    "BriefDescription": "Internal Prochot",
+    "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x72",
+    "UMask": "0x0",
+    "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+    "BriefDescription": "Total Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x79",
+    "UMask": "0x0",
+    "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Ring GV with same final and initial frequency",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VR_HOT_CYCLES",
+    "BriefDescription": "VR Hot",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_R2_CLOCKTICKS",
+    "BriefDescription": "Number of uclks in domain",
+    "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2D",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2D",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2D",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2D",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
+    "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
+    "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
+    "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x3",
+    "EventName": "UNC_R2_RING_AD_USED.CW",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0xC",
+    "EventName": "UNC_R2_RING_AD_USED.CCW",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0xF",
+    "EventName": "UNC_R2_RING_AD_USED.ALL",
+    "BriefDescription": "R2 AD Ring in Use; All",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
+    "BriefDescription": "AK Ingress Bounced; Up",
+    "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AK_BOUNCES.DN",
+    "BriefDescription": "AK Ingress Bounced; Dn",
+    "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x3",
+    "EventName": "UNC_R2_RING_AK_USED.CW",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0xC",
+    "EventName": "UNC_R2_RING_AK_USED.CCW",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0xF",
+    "EventName": "UNC_R2_RING_AK_USED.ALL",
+    "BriefDescription": "R2 AK Ring in Use; All",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x3",
+    "EventName": "UNC_R2_RING_BL_USED.CW",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0xC",
+    "EventName": "UNC_R2_RING_BL_USED.CCW",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0xF",
+    "EventName": "UNC_R2_RING_BL_USED.ALL",
+    "BriefDescription": "R2 BL Ring in Use; All",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xA",
+    "UMask": "0x3",
+    "EventName": "UNC_R2_RING_IV_USED.CW",
+    "BriefDescription": "R2 IV Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xA",
+    "UMask": "0xC",
+    "EventName": "UNC_R2_RING_IV_USED.CCW",
+    "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xA",
+    "UMask": "0xF",
+    "EventName": "UNC_R2_RING_IV_USED.ANY",
+    "BriefDescription": "R2 IV Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
+    "BriefDescription": "Ingress Cycles Not Empty; NCB",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
+    "BriefDescription": "Ingress Cycles Not Empty; NCS",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RxR_INSERTS.NCB",
+    "BriefDescription": "Ingress Allocations; NCB",
+    "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RxR_INSERTS.NCS",
+    "BriefDescription": "Ingress Allocations; NCS",
+    "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
+    "BriefDescription": "Ingress Occupancy Accumulator; DRS",
+    "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2A",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2A",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2C",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2C",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2C",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2C",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
+    "BriefDescription": "Egress Cycles Full; AD",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
+    "BriefDescription": "Egress Cycles Full; AK",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
+    "BriefDescription": "Egress Cycles Full; BL",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.AD",
+    "BriefDescription": "Egress Cycles Not Empty; AD",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AD Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.AK",
+    "BriefDescription": "Egress Cycles Not Empty; AK",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AK Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.BL",
+    "BriefDescription": "Egress Cycles Not Empty; BL",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; BL Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
+    "BriefDescription": "Egress CCW NACK; AD CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
+    "BriefDescription": "Egress CCW NACK; BL CCW",
+    "PublicDescription": "BL CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
+    "BriefDescription": "Egress CCW NACK; AK CCW",
+    "PublicDescription": "AK CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
+    "BriefDescription": "Egress CCW NACK; AK CCW",
+    "PublicDescription": "BL CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
+    "BriefDescription": "Egress CCW NACK; BL CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
+    "BriefDescription": "Egress CCW NACK; BL CW",
+    "PublicDescription": "AD Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x8",
+    "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x1",
+    "EventName": "UNC_U_FILTER_MATCH.ENABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "UBoxFilter[3:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x2",
+    "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x4",
+    "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "UBoxFilter[3:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x8",
+    "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x45",
+    "UMask": "0x1",
+    "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+    "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+    "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x46",
+    "UMask": "0x0",
+    "EventName": "UNC_U_RACU_REQUESTS",
+    "BriefDescription": "RACU Request",
+    "PublicDescription": "Number outstanding register requests within message channel tracker",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x1",
+    "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
+    "BriefDescription": "Monitor Sent to T0; Monitor T0",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x2",
+    "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+    "BriefDescription": "Monitor Sent to T0; Monitor T1",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x4",
+    "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
+    "BriefDescription": "Monitor Sent to T0; Livelock",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x8",
+    "EventName": "UNC_U_U2C_EVENTS.LTERROR",
+    "BriefDescription": "Monitor Sent to T0; LTError",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x10",
+    "EventName": "UNC_U_U2C_EVENTS.CMC",
+    "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x20",
+    "EventName": "UNC_U_U2C_EVENTS.UMC",
+    "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x40",
+    "EventName": "UNC_U_U2C_EVENTS.TRAP",
+    "BriefDescription": "Monitor Sent to T0; Trap",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x80",
+    "EventName": "UNC_U_U2C_EVENTS.OTHER",
+    "BriefDescription": "Monitor Sent to T0; Other",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_M_ACT_COUNT.RD",
+    "BriefDescription": "DRAM Activate Count; Activate due to Read",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_M_ACT_COUNT.WR",
+    "BriefDescription": "DRAM Activate Count; Activate due to Write",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_M_ACT_COUNT.BYP",
+    "BriefDescription": "DRAM Activate Count; Activate due to Write",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA1",
+    "UMask": "0x1",
+    "EventName": "UNC_M_BYP_CMDS.ACT",
+    "BriefDescription": "ACT command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA1",
+    "UMask": "0x2",
+    "EventName": "UNC_M_BYP_CMDS.CAS",
+    "BriefDescription": "CAS command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA1",
+    "UMask": "0x4",
+    "EventName": "UNC_M_BYP_CMDS.PRE",
+    "BriefDescription": "PRE command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x1",
+    "EventName": "UNC_M_CAS_COUNT.RD_REG",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x2",
+    "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller.  This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ.  While it is possible for underfills to be issed in both WMM and RMM, this event counts both.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x3",
+    "EventName": "UNC_M_CAS_COUNT.RD",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x8",
+    "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic' DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0xC",
+    "EventName": "UNC_M_CAS_COUNT.WR",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0xF",
+    "EventName": "UNC_M_CAS_COUNT.ALL",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x10",
+    "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x20",
+    "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_M_DCLOCKTICKS",
+    "BriefDescription": "DRAM Clockticks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_M_DRAM_PRE_ALL",
+    "BriefDescription": "DRAM Precharge All Commands",
+    "PublicDescription": "Counts the number of times that the precharge all command was sent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+    "BriefDescription": "Number of DRAM Refreshes Issued",
+    "PublicDescription": "Counts the number of refreshes issued.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+    "BriefDescription": "Number of DRAM Refreshes Issued",
+    "PublicDescription": "Counts the number of refreshes issued.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
+    "BriefDescription": "ECC Correctable Errors",
+    "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_M_MAJOR_MODES.READ",
+    "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_M_MAJOR_MODES.WRITE",
+    "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+    "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+    "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x84",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
+    "BriefDescription": "Channel DLLOFF Cycles",
+    "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x85",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CHANNEL_PPD",
+    "BriefDescription": "Channel PPD Cycles",
+    "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x1",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x2",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x4",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x8",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x10",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x20",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x40",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x80",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x86",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
+    "BriefDescription": "Critical Throttle Cycles",
+    "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_PCU_THROTTLING",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x43",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_SELF_REFRESH",
+    "BriefDescription": "Clock-Enabled Self-Refresh",
+    "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x1",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x2",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x4",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x8",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x10",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x20",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x40",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x80",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
+    "BriefDescription": "Read Preemption Count; Read over Read Preemption",
+    "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
+    "BriefDescription": "Read Preemption Count; Read over Write Preemption",
+    "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+    "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses.  This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode.  This does not include PRE commands sent as a result of the page close counter expiration.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_M_PRE_COUNT.RD",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to read",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_M_PRE_COUNT.WR",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to write",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_M_PRE_COUNT.BYP",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_RD_CAS_PRIO.LOW",
+    "BriefDescription": "Read CAS issued with LOW priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_RD_CAS_PRIO.MED",
+    "BriefDescription": "Read CAS issued with MEDIUM priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
+    "BriefDescription": "Read CAS issued with HIGH priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA0",
+    "UMask": "0x8",
+    "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
+    "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x8",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x10",
+    "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+    "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x3",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x5",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x6",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x7",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x9",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0xA",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
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+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0xA",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0xB",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0xC",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0xD",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0xE",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0xF",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0x11",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0x12",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0x13",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB7",
+    "UMask": "0x14",
+    "EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
+    "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x11",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_CYCLES_NE",
+    "BriefDescription": "Read Pending Queue Not Empty",
+    "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x10",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_INSERTS",
+    "BriefDescription": "Read Pending Queue Allocations",
+    "PublicDescription": "Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x91",
+    "UMask": "0x0",
+    "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
+    "BriefDescription": "VMSE MXB write buffer occupancy",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x90",
+    "UMask": "0x1",
+    "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
+    "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x90",
+    "UMask": "0x2",
+    "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
+    "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xC0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xC0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WMM_TO_RMM.STARVE",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xC0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x22",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_CYCLES_FULL",
+    "BriefDescription": "Write Pending Queue Full Cycles",
+    "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x21",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_CYCLES_NE",
+    "BriefDescription": "Write Pending Queue Not Empty",
+    "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x23",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_READ_HIT",
+    "BriefDescription": "Write Pending Queue CAM Match",
+    "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x24",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_WRITE_HIT",
+    "BriefDescription": "Write Pending Queue CAM Match",
+    "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xC1",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WRONG_MM",
+    "BriefDescription": "Not getting the requested Major Mode",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x8",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x10",
+    "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+    "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x3",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x5",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x6",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x7",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x9",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xA",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xB",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xC",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xD",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xE",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xF",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x11",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x12",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x13",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x14",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x8",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
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+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBD",
+    "UMask": "0xE",
+    "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
+    "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBD",
+    "UMask": "0xF",
+    "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
+    "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBD",
+    "UMask": "0x11",
+    "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
+    "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBD",
+    "UMask": "0x12",
+    "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
+    "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBD",
+    "UMask": "0x13",
+    "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
+    "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBD",
+    "UMask": "0x14",
+    "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
+    "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x8",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x10",
+    "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+    "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x3",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x5",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x6",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x7",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x9",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xA",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xB",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xC",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xD",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xE",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xF",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x11",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x12",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x13",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x14",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x8",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x10",
+    "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
+    "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x3",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x5",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x6",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x7",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x9",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xA",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xB",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xC",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xD",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xE",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xF",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x11",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x12",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x13",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x14",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/BDW-DE/BroadwellDE_uncore_V1.tsv b/x86data/perfmon_data/BDW-DE/BroadwellDE_uncore_V1.tsv
new file mode 100644
index 0000000..f26c16b
--- /dev/null
+++ b/x86data/perfmon_data/BDW-DE/BroadwellDE_uncore_V1.tsv
@@ -0,0 +1,904 @@
+# Performance Monitoring Events for  - V1
+# 7/22/2015 2:51:39 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+Unit	EventCode	UMask	EventName	Description	Counter	MSRValue	Filter	Internal
+CBO	0xA	0x0	UNC_C_BOUNCE_CONTROL	Bounce Control	0,1,2,3	0	null	0
+CBO	0x0	0x0	UNC_C_CLOCKTICKS	Uncore Clocks	0,1,2,3	0	null	0
+CBO	0x1F	0x0	UNC_C_COUNTER0_OCCUPANCY	Counter 0 Occupancy	0,1,2,3	0	null	0
+CBO	0x9	0x0	UNC_C_FAST_ASSERTED	FaST wire asserted	0,1	0	null	0
+CBO	0x34	0x3	UNC_C_LLC_LOOKUP.DATA_READ	Cache Lookups; Data Read Request	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x5	UNC_C_LLC_LOOKUP.WRITE	Cache Lookups; Write Requests	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x9	UNC_C_LLC_LOOKUP.REMOTE_SNOOP	Cache Lookups; External Snoop Request	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x11	UNC_C_LLC_LOOKUP.ANY	Cache Lookups; Any Request	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x41	UNC_C_LLC_LOOKUP.NID	Cache Lookups; Lookups that Match NID	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x21	UNC_C_LLC_LOOKUP.READ	Cache Lookups; Any Read Request	0,1,2,3	0	CBoFilter0[22:18]	0
+CBO	0x37	0x1	UNC_C_LLC_VICTIMS.M_STATE	Lines Victimized; Lines in M state	0,1,2,3	0	null	0
+CBO	0x37	0x2	UNC_C_LLC_VICTIMS.E_STATE	Lines Victimized; Lines in E state	0,1,2,3	0	null	0
+CBO	0x37	0x4	UNC_C_LLC_VICTIMS.I_STATE	Lines Victimized; Lines in S State	0,1,2,3	0	null	0
+CBO	0x37	0x8	UNC_C_LLC_VICTIMS.F_STATE	Lines Victimized	0,1,2,3	0	null	0
+CBO	0x37	0x40	UNC_C_LLC_VICTIMS.NID	Lines Victimized; Victimized Lines that Match NID	0,1,2,3	0	CBoFilter1[17:10]	0
+CBO	0x37	0x10	UNC_C_LLC_VICTIMS.MISS	Lines Victimized	0,1,2,3	0	null	0
+CBO	0x39	0x1	UNC_C_MISC.RSPI_WAS_FSE	Cbo Misc; Silent Snoop Eviction	0,1,2,3	0	null	0
+CBO	0x39	0x2	UNC_C_MISC.WC_ALIASING	Cbo Misc; Write Combining Aliasing	0,1,2,3	0	null	0
+CBO	0x39	0x4	UNC_C_MISC.STARTED	Cbo Misc	0,1,2,3	0	null	0
+CBO	0x39	0x8	UNC_C_MISC.RFO_HIT_S	Cbo Misc; RFO HitS	0,1,2,3	0	null	0
+CBO	0x39	0x10	UNC_C_MISC.CVZERO_PREFETCH_VICTIM	Cbo Misc; Clean Victim with raw CV=0	0,1,2,3	0	null	0
+CBO	0x39	0x20	UNC_C_MISC.CVZERO_PREFETCH_MISS	Cbo Misc; DRd hitting non-M with raw CV=0	0,1,2,3	0	null	0
+CBO	0x3C	0x1	UNC_C_QLRU.AGE0	LRU Queue; LRU Age 0	0,1,2,3	0	null	0
+CBO	0x3C	0x2	UNC_C_QLRU.AGE1	LRU Queue; LRU Age 1	0,1,2,3	0	null	0
+CBO	0x3C	0x4	UNC_C_QLRU.AGE2	LRU Queue; LRU Age 2	0,1,2,3	0	null	0
+CBO	0x3C	0x8	UNC_C_QLRU.AGE3	LRU Queue; LRU Age 3	0,1,2,3	0	null	0
+CBO	0x3C	0x10	UNC_C_QLRU.LRU_DECREMENT	LRU Queue; LRU Bits Decremented	0,1,2,3	0	null	0
+CBO	0x3C	0x20	UNC_C_QLRU.VICTIM_NON_ZERO	LRU Queue; Non-0 Aged Victim	0,1,2,3	0	null	0
+CBO	0x1B	0x1	UNC_C_RING_AD_USED.UP_EVEN	AD Ring In Use; Up and Even	0,1,2,3	0	null	0
+CBO	0x1B	0x2	UNC_C_RING_AD_USED.UP_ODD	AD Ring In Use; Up and Odd	0,1,2,3	0	null	0
+CBO	0x1B	0x4	UNC_C_RING_AD_USED.DOWN_EVEN	AD Ring In Use; Down and Even	0,1,2,3	0	null	0
+CBO	0x1B	0x8	UNC_C_RING_AD_USED.DOWN_ODD	AD Ring In Use; Down and Odd	0,1,2,3	0	null	0
+CBO	0x1B	0x3	UNC_C_RING_AD_USED.CW	AD Ring In Use; Up	0,1,2,3	0	null	0
+CBO	0x1B	0xC	UNC_C_RING_AD_USED.CCW	AD Ring In Use; Down	0,1,2,3	0	null	0
+CBO	0x1B	0xF	UNC_C_RING_AD_USED.ALL	AD Ring In Use; All	0,1,2,3	0	null	0
+CBO	0x1C	0x1	UNC_C_RING_AK_USED.UP_EVEN	AK Ring In Use; Up and Even	0,1,2,3	0	null	0
+CBO	0x1C	0x2	UNC_C_RING_AK_USED.UP_ODD	AK Ring In Use; Up and Odd	0,1,2,3	0	null	0
+CBO	0x1C	0x4	UNC_C_RING_AK_USED.DOWN_EVEN	AK Ring In Use; Down and Even	0,1,2,3	0	null	0
+CBO	0x1C	0x8	UNC_C_RING_AK_USED.DOWN_ODD	AK Ring In Use; Down and Odd	0,1,2,3	0	null	0
+CBO	0x1C	0x3	UNC_C_RING_AK_USED.CW	AK Ring In Use; Up	0,1,2,3	0	null	0
+CBO	0x1C	0xC	UNC_C_RING_AK_USED.CCW	AK Ring In Use; Down	0,1,2,3	0	null	0
+CBO	0x1C	0xF	UNC_C_RING_AK_USED.ALL	AK Ring In Use; All	0,1,2,3	0	null	0
+CBO	0x1D	0x1	UNC_C_RING_BL_USED.UP_EVEN	BL Ring in Use; Up and Even	0,1,2,3	0	null	0
+CBO	0x1D	0x2	UNC_C_RING_BL_USED.UP_ODD	BL Ring in Use; Up and Odd	0,1,2,3	0	null	0
+CBO	0x1D	0x4	UNC_C_RING_BL_USED.DOWN_EVEN	BL Ring in Use; Down and Even	0,1,2,3	0	null	0
+CBO	0x1D	0x8	UNC_C_RING_BL_USED.DOWN_ODD	BL Ring in Use; Down and Odd	0,1,2,3	0	null	0
+CBO	0x1D	0x3	UNC_C_RING_BL_USED.CW	BL Ring in Use; Up	0,1,2,3	0	null	0
+CBO	0x1D	0xC	UNC_C_RING_BL_USED.CCW	BL Ring in Use; Down	0,1,2,3	0	null	0
+CBO	0x1D	0xF	UNC_C_RING_BL_USED.ALL	BL Ring in Use; Down	0,1,2,3	0	null	0
+CBO	0x5	0x1	UNC_C_RING_BOUNCES.AD	Number of LLC responses that bounced on the Ring.; AD	0,1,2,3	0	null	0
+CBO	0x5	0x2	UNC_C_RING_BOUNCES.AK	Number of LLC responses that bounced on the Ring.; AK	0,1,2,3	0	null	0
+CBO	0x5	0x4	UNC_C_RING_BOUNCES.BL	Number of LLC responses that bounced on the Ring.; BL	0,1,2,3	0	null	0
+CBO	0x5	0x10	UNC_C_RING_BOUNCES.IV	Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.	0,1,2,3	0	null	0
+CBO	0x1E	0xF	UNC_C_RING_IV_USED.ANY	BL Ring in Use; Any	0,1,2,3	0	null	0
+CBO	0x1E	0x3	UNC_C_RING_IV_USED.UP	BL Ring in Use; Any	0,1,2,3	0	null	0
+CBO	0x1E	0xCC	UNC_C_RING_IV_USED.DOWN	BL Ring in Use; Down	0,1,2,3	0	null	0
+CBO	0x1E	0xC	UNC_C_RING_IV_USED.DN	BL Ring in Use; Any	0,1,2,3	0	null	0
+CBO	0x6	0x1	UNC_C_RING_SINK_STARVED.AD	AD	0,1,2,3	0	null	0
+CBO	0x6	0x2	UNC_C_RING_SINK_STARVED.AK	AK	0,1,2,3	0	null	0
+CBO	0x6	0x8	UNC_C_RING_SINK_STARVED.IV	IV	0,1,2,3	0	null	0
+CBO	0x6	0x4	UNC_C_RING_SINK_STARVED.BL	BL	0,1,2,3	0	null	0
+CBO	0x7	0x0	UNC_C_RING_SRC_THRTL	Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.	0,1,2,3	0	null	0
+CBO	0x12	0x1	UNC_C_RxR_EXT_STARVED.IRQ	Ingress Arbiter Blocking Cycles; IPQ	0,1,2,3	0	null	0
+CBO	0x12	0x2	UNC_C_RxR_EXT_STARVED.IPQ	Ingress Arbiter Blocking Cycles; IRQ	0,1,2,3	0	null	0
+CBO	0x12	0x4	UNC_C_RxR_EXT_STARVED.PRQ	Ingress Arbiter Blocking Cycles; PRQ	0,1,2,3	0	null	0
+CBO	0x12	0x8	UNC_C_RxR_EXT_STARVED.ISMQ_BIDS	Ingress Arbiter Blocking Cycles; ISMQ_BID	0,1,2,3	0	null	0
+CBO	0x13	0x1	UNC_C_RxR_INSERTS.IRQ	Ingress Allocations; IRQ	0,1,2,3	0	null	0
+CBO	0x13	0x2	UNC_C_RxR_INSERTS.IRQ_REJ	Ingress Allocations; IRQ Rejected	0,1,2,3	0	null	0
+CBO	0x13	0x4	UNC_C_RxR_INSERTS.IPQ	Ingress Allocations; IPQ	0,1,2,3	0	null	0
+CBO	0x13	0x10	UNC_C_RxR_INSERTS.PRQ	Ingress Allocations; PRQ	0,1,2,3	0	null	0
+CBO	0x13	0x20	UNC_C_RxR_INSERTS.PRQ_REJ	Ingress Allocations; PRQ	0,1,2,3	0	null	0
+CBO	0x14	0x1	UNC_C_RxR_INT_STARVED.IRQ	Ingress Internal Starvation Cycles; IRQ	0,1,2,3	0	null	0
+CBO	0x14	0x4	UNC_C_RxR_INT_STARVED.IPQ	Ingress Internal Starvation Cycles; IPQ	0,1,2,3	0	null	0
+CBO	0x14	0x8	UNC_C_RxR_INT_STARVED.ISMQ	Ingress Internal Starvation Cycles; ISMQ	0,1,2,3	0	null	0
+CBO	0x14	0x10	UNC_C_RxR_INT_STARVED.PRQ	Ingress Internal Starvation Cycles; PRQ	0,1,2,3	0	null	0
+CBO	0x31	0x1	UNC_C_RxR_IPQ_RETRY.ANY	Probe Queue Retries; Any Reject	0,1,2,3	0	null	0
+CBO	0x31	0x2	UNC_C_RxR_IPQ_RETRY.FULL	Probe Queue Retries; No Egress Credits	0,1,2,3	0	null	0
+CBO	0x31	0x4	UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT	Probe Queue Retries; Address Conflict	0,1,2,3	0	null	0
+CBO	0x31	0x10	UNC_C_RxR_IPQ_RETRY.QPI_CREDITS	Probe Queue Retries; No QPI Credits	0,1,2,3	0	null	0
+CBO	0x28	0x1	UNC_C_RxR_IPQ_RETRY2.AD_SBO	Probe Queue Retries; No AD Sbo Credits	0,1,2,3	0	null	0
+CBO	0x28	0x40	UNC_C_RxR_IPQ_RETRY2.TARGET	Probe Queue Retries; Target Node Filter	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x32	0x1	UNC_C_RxR_IRQ_RETRY.ANY	Ingress Request Queue Rejects; Any Reject	0,1,2,3	0	null	0
+CBO	0x32	0x2	UNC_C_RxR_IRQ_RETRY.FULL	Ingress Request Queue Rejects; No Egress Credits	0,1,2,3	0	null	0
+CBO	0x32	0x4	UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT	Ingress Request Queue Rejects; Address Conflict	0,1,2,3	0	null	0
+CBO	0x32	0x8	UNC_C_RxR_IRQ_RETRY.RTID	Ingress Request Queue Rejects; No RTIDs	0,1,2,3	0	null	0
+CBO	0x32	0x10	UNC_C_RxR_IRQ_RETRY.QPI_CREDITS	Ingress Request Queue Rejects; No QPI Credits	0,1,2,3	0	null	0
+CBO	0x32	0x20	UNC_C_RxR_IRQ_RETRY.IIO_CREDITS	Ingress Request Queue Rejects; No IIO Credits	0,1,2,3	0	null	0
+CBO	0x32	0x40	UNC_C_RxR_IRQ_RETRY.NID	Ingress Request Queue Rejects	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x29	0x1	UNC_C_RxR_IRQ_RETRY2.AD_SBO	Ingress Request Queue Rejects; No AD Sbo Credits	0,1,2,3	0	null	0
+CBO	0x29	0x2	UNC_C_RxR_IRQ_RETRY2.BL_SBO	Ingress Request Queue Rejects; No BL Sbo Credits	0,1,2,3	0	null	0
+CBO	0x29	0x40	UNC_C_RxR_IRQ_RETRY2.TARGET	Ingress Request Queue Rejects; Target Node Filter	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x33	0x1	UNC_C_RxR_ISMQ_RETRY.ANY	ISMQ Retries; Any Reject	0,1,2,3	0	null	0
+CBO	0x33	0x2	UNC_C_RxR_ISMQ_RETRY.FULL	ISMQ Retries; No Egress Credits	0,1,2,3	0	null	0
+CBO	0x33	0x8	UNC_C_RxR_ISMQ_RETRY.RTID	ISMQ Retries; No RTIDs	0,1,2,3	0	null	0
+CBO	0x33	0x10	UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS	ISMQ Retries; No QPI Credits	0,1,2,3	0	null	0
+CBO	0x33	0x20	UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS	ISMQ Retries; No IIO Credits	0,1,2,3	0	null	0
+CBO	0x33	0x80	UNC_C_RxR_ISMQ_RETRY.WB_CREDITS	ISMQ Retries	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x33	0x40	UNC_C_RxR_ISMQ_RETRY.NID	ISMQ Retries	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x2A	0x1	UNC_C_RxR_ISMQ_RETRY2.AD_SBO	ISMQ Request Queue Rejects; No AD Sbo Credits	0,1,2,3	0	null	0
+CBO	0x2A	0x2	UNC_C_RxR_ISMQ_RETRY2.BL_SBO	ISMQ Request Queue Rejects; No BL Sbo Credits	0,1,2,3	0	null	0
+CBO	0x2A	0x40	UNC_C_RxR_ISMQ_RETRY2.TARGET	ISMQ Request Queue Rejects; Target Node Filter	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x11	0x1	UNC_C_RxR_OCCUPANCY.IRQ	Ingress Occupancy; IRQ	0	0	null	0
+CBO	0x11	0x2	UNC_C_RxR_OCCUPANCY.IRQ_REJ	Ingress Occupancy; IRQ Rejected	0	0	null	0
+CBO	0x11	0x4	UNC_C_RxR_OCCUPANCY.IPQ	Ingress Occupancy; IPQ	0	0	null	0
+CBO	0x11	0x20	UNC_C_RxR_OCCUPANCY.PRQ_REJ	Ingress Occupancy; PRQ Rejects	0	0	null	0
+CBO	0x3D	0x1	UNC_C_SBO_CREDITS_ACQUIRED.AD	SBo Credits Acquired; For AD Ring	0,1,2,3	0	null	0
+CBO	0x3D	0x2	UNC_C_SBO_CREDITS_ACQUIRED.BL	SBo Credits Acquired; For BL Ring	0,1,2,3	0	null	0
+CBO	0x3E	0x1	UNC_C_SBO_CREDIT_OCCUPANCY.AD	SBo Credits Occupancy; For AD Ring	0	0	null	0
+CBO	0x3E	0x2	UNC_C_SBO_CREDIT_OCCUPANCY.BL	SBo Credits Occupancy; For BL Ring	0	0	null	0
+CBO	0x35	0x1	UNC_C_TOR_INSERTS.OPCODE	TOR Inserts; Opcode Match	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x4	UNC_C_TOR_INSERTS.EVICTION	TOR Inserts; Evictions	0,1,2,3	0	null	0
+CBO	0x35	0x8	UNC_C_TOR_INSERTS.ALL	TOR Inserts; All	0,1,2,3	0	null	0
+CBO	0x35	0x10	UNC_C_TOR_INSERTS.WB	TOR Inserts; Writebacks	0,1,2,3	0	null	0
+CBO	0x35	0x3	UNC_C_TOR_INSERTS.MISS_OPCODE	TOR Inserts; Miss Opcode Match	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x41	UNC_C_TOR_INSERTS.NID_OPCODE	TOR Inserts; NID and Opcode Matched	0,1,2,3	0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x35	0x44	UNC_C_TOR_INSERTS.NID_EVICTION	TOR Inserts; NID Matched Evictions	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x35	0x48	UNC_C_TOR_INSERTS.NID_ALL	TOR Inserts; NID Matched	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x35	0x50	UNC_C_TOR_INSERTS.NID_WB	TOR Inserts; NID Matched Writebacks	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x35	0x43	UNC_C_TOR_INSERTS.NID_MISS_OPCODE	TOR Inserts; NID and Opcode Matched Miss	0,1,2,3	0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x35	0x4A	UNC_C_TOR_INSERTS.NID_MISS_ALL	TOR Inserts; NID Matched Miss All	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x35	0x2A	UNC_C_TOR_INSERTS.MISS_LOCAL	TOR Inserts; Misses to Local Memory	0,1,2,3	0	null	0
+CBO	0x35	0x8A	UNC_C_TOR_INSERTS.MISS_REMOTE	TOR Inserts; Misses to Remote Memory	0,1,2,3	0	null	0
+CBO	0x35	0x28	UNC_C_TOR_INSERTS.LOCAL	TOR Inserts; Local Memory	0,1,2,3	0	null	0
+CBO	0x35	0x88	UNC_C_TOR_INSERTS.REMOTE	TOR Inserts; Remote Memory	0,1,2,3	0	null	0
+CBO	0x35	0x23	UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE	TOR Inserts; Misses to Local Memory - Opcode Matched	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x83	UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE	TOR Inserts; Misses to Remote Memory - Opcode Matched	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x21	UNC_C_TOR_INSERTS.LOCAL_OPCODE	TOR Inserts; Local Memory - Opcode Matched	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x81	UNC_C_TOR_INSERTS.REMOTE_OPCODE	TOR Inserts; Remote Memory - Opcode Matched	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x36	0x1	UNC_C_TOR_OCCUPANCY.OPCODE	TOR Occupancy; Opcode Match	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x4	UNC_C_TOR_OCCUPANCY.EVICTION	TOR Occupancy; Evictions	0	0	null	0
+CBO	0x36	0x8	UNC_C_TOR_OCCUPANCY.ALL	TOR Occupancy; Any	0	0	null	0
+CBO	0x36	0x3	UNC_C_TOR_OCCUPANCY.MISS_OPCODE	TOR Occupancy; Miss Opcode Match	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0xA	UNC_C_TOR_OCCUPANCY.MISS_ALL	TOR Occupancy; Miss All	0	0	null	0
+CBO	0x36	0x41	UNC_C_TOR_OCCUPANCY.NID_OPCODE	TOR Occupancy; NID and Opcode Matched	0	0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x36	0x44	UNC_C_TOR_OCCUPANCY.NID_EVICTION	TOR Occupancy; NID Matched Evictions	0	0	CBoFilter1[15:0]	0
+CBO	0x36	0x48	UNC_C_TOR_OCCUPANCY.NID_ALL	TOR Occupancy; NID Matched	0	0	CBoFilter1[15:0]	0
+CBO	0x36	0x43	UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE	TOR Occupancy; NID and Opcode Matched Miss	0	0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x36	0x4A	UNC_C_TOR_OCCUPANCY.NID_MISS_ALL	TOR Occupancy; NID Matched	0	0	CBoFilter1[15:0]	0
+CBO	0x36	0x2A	UNC_C_TOR_OCCUPANCY.MISS_LOCAL	TOR Occupancy	0	0	null	0
+CBO	0x36	0x8A	UNC_C_TOR_OCCUPANCY.MISS_REMOTE	TOR Occupancy	0	0	null	0
+CBO	0x36	0x28	UNC_C_TOR_OCCUPANCY.LOCAL	TOR Occupancy	0	0	null	0
+CBO	0x36	0x88	UNC_C_TOR_OCCUPANCY.REMOTE	TOR Occupancy	0	0	null	0
+CBO	0x36	0x23	UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE	TOR Occupancy; Misses to Local Memory - Opcode Matched	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x83	UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE	TOR Occupancy; Misses to Remote Memory - Opcode Matched	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x21	UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE	TOR Occupancy; Local Memory - Opcode Matched	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x81	UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE	TOR Occupancy; Remote Memory - Opcode Matched	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x10	UNC_C_TOR_OCCUPANCY.WB	TOR Occupancy; Writebacks	0	0	null	0
+CBO	0x36	0x50	UNC_C_TOR_OCCUPANCY.NID_WB	TOR Occupancy; NID Matched Writebacks	0	0	CBoFilter1[15:0]	0
+CBO	0x4	0x1	UNC_C_TxR_ADS_USED.AD	Onto AD Ring	0,1,2,3	0	null	0
+CBO	0x4	0x2	UNC_C_TxR_ADS_USED.AK	Onto AK Ring	0,1,2,3	0	null	0
+CBO	0x4	0x4	UNC_C_TxR_ADS_USED.BL	Onto BL Ring	0,1,2,3	0	null	0
+CBO	0x2	0x1	UNC_C_TxR_INSERTS.AD_CACHE	Egress Allocations; AD - Cachebo	0,1,2,3	0	null	0
+CBO	0x2	0x2	UNC_C_TxR_INSERTS.AK_CACHE	Egress Allocations; AK - Cachebo	0,1,2,3	0	null	0
+CBO	0x2	0x4	UNC_C_TxR_INSERTS.BL_CACHE	Egress Allocations; BL - Cacheno	0,1,2,3	0	null	0
+CBO	0x2	0x8	UNC_C_TxR_INSERTS.IV_CACHE	Egress Allocations; IV - Cachebo	0,1,2,3	0	null	0
+CBO	0x2	0x10	UNC_C_TxR_INSERTS.AD_CORE	Egress Allocations; AD - Corebo	0,1,2,3	0	null	0
+CBO	0x2	0x20	UNC_C_TxR_INSERTS.AK_CORE	Egress Allocations; AK - Corebo	0,1,2,3	0	null	0
+CBO	0x2	0x40	UNC_C_TxR_INSERTS.BL_CORE	Egress Allocations; BL - Corebo	0,1,2,3	0	null	0
+CBO	0x3	0x2	UNC_C_TxR_STARVED.AK_BOTH	Injection Starvation; Onto AK Ring	0,1,2,3	0	null	0
+CBO	0x3	0x4	UNC_C_TxR_STARVED.BL_BOTH	Injection Starvation; Onto BL Ring	0,1,2,3	0	null	0
+CBO	0x3	0x8	UNC_C_TxR_STARVED.IV	Injection Starvation; Onto IV Ring	0,1,2,3	0	null	0
+CBO	0x3	0x10	UNC_C_TxR_STARVED.AD_CORE	Injection Starvation; Onto AD Ring (to core)	0,1,2,3	0	null	0
+HA	0x20	0x3	UNC_H_ADDR_OPC_MATCH.FILT	QPI Address/Opcode Match; Address & Opcode Match	0,1,2,3	0	HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]	0
+HA	0x20	0x1	UNC_H_ADDR_OPC_MATCH.ADDR	QPI Address/Opcode Match; Address	0,1,2,3	0	HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]	0
+HA	0x20	0x2	UNC_H_ADDR_OPC_MATCH.OPC	QPI Address/Opcode Match; Opcode	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x4	UNC_H_ADDR_OPC_MATCH.AD	QPI Address/Opcode Match; AD Opcodes	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x8	UNC_H_ADDR_OPC_MATCH.BL	QPI Address/Opcode Match; BL Opcodes	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x10	UNC_H_ADDR_OPC_MATCH.AK	QPI Address/Opcode Match; AK Opcodes	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x42	0x0	UNC_H_BT_CYCLES_NE	BT Cycles Not Empty	0,1,2,3	0	null	0
+HA	0x51	0x2	UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD	BT to HT Not Issued; Incoming Snoop Hazard	0,1,2,3	0	null	0
+HA	0x51	0x4	UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD	BT to HT Not Issued; Incoming Data Hazard	0,1,2,3	0	null	0
+HA	0x51	0x8	UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD	BT to HT Not Issued; Incoming Data Hazard	0,1,2,3	0	null	0
+HA	0x51	0x10	UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD	BT to HT Not Issued; Incoming Data Hazard	0,1,2,3	0	null	0
+HA	0x14	0x1	UNC_H_BYPASS_IMC.TAKEN	HA to iMC Bypass; Taken	0,1,2,3	0	null	0
+HA	0x14	0x2	UNC_H_BYPASS_IMC.NOT_TAKEN	HA to iMC Bypass; Not Taken	0,1,2,3	0	null	0
+HA	0x0	0x0	UNC_H_CLOCKTICKS	uclks	0,1,2,3	0	null	0
+HA	0x11	0x0	UNC_H_DIRECT2CORE_COUNT	Direct2Core Messages Sent	0,1,2,3	0	null	0
+HA	0x12	0x0	UNC_H_DIRECT2CORE_CYCLES_DISABLED	Cycles when Direct2Core was Disabled	0,1,2,3	0	null	0
+HA	0x13	0x0	UNC_H_DIRECT2CORE_TXN_OVERRIDE	Number of Reads that had Direct2Core Overridden	0,1,2,3	0	null	0
+HA	0x41	0x0	UNC_H_DIRECTORY_LAT_OPT	Directory Lat Opt Return	0,1,2,3	0	null	0
+HA	0xC	0x1	UNC_H_DIRECTORY_LOOKUP.SNP	Directory Lookups; Snoop Needed	0,1,2,3	0	null	0
+HA	0xC	0x2	UNC_H_DIRECTORY_LOOKUP.NO_SNP	Directory Lookups; Snoop Not Needed	0,1,2,3	0	null	0
+HA	0xD	0x1	UNC_H_DIRECTORY_UPDATE.SET	Directory Updates; Directory Set	0,1,2,3	0	null	0
+HA	0xD	0x2	UNC_H_DIRECTORY_UPDATE.CLEAR	Directory Updates; Directory Clear	0,1,2,3	0	null	0
+HA	0xD	0x3	UNC_H_DIRECTORY_UPDATE.ANY	Directory Updates; Any Directory Update	0,1,2,3	0	null	0
+HA	0x71	0x1	UNC_H_HITME_HIT.READ_OR_INVITOE	Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE	0,1,2,3	0	null	0
+HA	0x71	0x2	UNC_H_HITME_HIT.WBMTOI	Counts Number of Hits in HitMe Cache; op is WbMtoI	0,1,2,3	0	null	0
+HA	0x71	0x4	UNC_H_HITME_HIT.ACKCNFLTWBI	Counts Number of Hits in HitMe Cache; op is AckCnfltWbI	0,1,2,3	0	null	0
+HA	0x71	0x8	UNC_H_HITME_HIT.WBMTOE_OR_S	Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS	0,1,2,3	0	null	0
+HA	0x71	0x10	UNC_H_HITME_HIT.RSPFWDI_REMOTE	Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request	0,1,2,3	0	null	0
+HA	0x71	0x20	UNC_H_HITME_HIT.RSPFWDI_LOCAL	Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request	0,1,2,3	0	null	0
+HA	0x71	0x40	UNC_H_HITME_HIT.RSPFWDS	Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb	0,1,2,3	0	null	0
+HA	0x71	0x80	UNC_H_HITME_HIT.RSP	Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI	0,1,2,3	0	null	0
+HA	0x71	0x70	UNC_H_HITME_HIT.ALLOCS	Counts Number of Hits in HitMe Cache; Allocations	0,1,2,3	0	null	0
+HA	0x71	0x42	UNC_H_HITME_HIT.EVICTS	Counts Number of Hits in HitMe Cache; Allocations	0,1,2,3	0	null	0
+HA	0x71	0x26	UNC_H_HITME_HIT.INVALS	Counts Number of Hits in HitMe Cache; Invalidations	0,1,2,3	0	null	0
+HA	0x71	0xFF	UNC_H_HITME_HIT.ALL	Counts Number of Hits in HitMe Cache; All Requests	0,1,2,3	0	null	0
+HA	0x71	0xF	UNC_H_HITME_HIT.HOM	Counts Number of Hits in HitMe Cache; HOM Requests	0,1,2,3	0	null	0
+HA	0x72	0x1	UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE	Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE	0,1,2,3	0	null	0
+HA	0x72	0x2	UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI	Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI	0,1,2,3	0	null	0
+HA	0x72	0x4	UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI	Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI	0,1,2,3	0	null	0
+HA	0x72	0x8	UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S	Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS	0,1,2,3	0	null	0
+HA	0x72	0x10	UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE	Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request	0,1,2,3	0	null	0
+HA	0x72	0x20	UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL	Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request	0,1,2,3	0	null	0
+HA	0x72	0x40	UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS	Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb	0,1,2,3	0	null	0
+HA	0x72	0x80	UNC_H_HITME_HIT_PV_BITS_SET.RSP	Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI	0,1,2,3	0	null	0
+HA	0x72	0xFF	UNC_H_HITME_HIT_PV_BITS_SET.ALL	Accumulates Number of PV bits set on HitMe Cache Hits; All Requests	0,1,2,3	0	null	0
+HA	0x72	0xF	UNC_H_HITME_HIT_PV_BITS_SET.HOM	Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests	0,1,2,3	0	null	0
+HA	0x70	0x1	UNC_H_HITME_LOOKUP.READ_OR_INVITOE	Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE	0,1,2,3	0	null	0
+HA	0x70	0x2	UNC_H_HITME_LOOKUP.WBMTOI	Counts Number of times HitMe Cache is accessed; op is WbMtoI	0,1,2,3	0	null	0
+HA	0x70	0x4	UNC_H_HITME_LOOKUP.ACKCNFLTWBI	Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI	0,1,2,3	0	null	0
+HA	0x70	0x8	UNC_H_HITME_LOOKUP.WBMTOE_OR_S	Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS	0,1,2,3	0	null	0
+HA	0x70	0x10	UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE	Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request	0,1,2,3	0	null	0
+HA	0x70	0x20	UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL	Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request	0,1,2,3	0	null	0
+HA	0x70	0x40	UNC_H_HITME_LOOKUP.RSPFWDS	Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb	0,1,2,3	0	null	0
+HA	0x70	0x80	UNC_H_HITME_LOOKUP.RSP	Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI	0,1,2,3	0	null	0
+HA	0x70	0x70	UNC_H_HITME_LOOKUP.ALLOCS	Counts Number of times HitMe Cache is accessed; Allocations	0,1,2,3	0	null	0
+HA	0x70	0x26	UNC_H_HITME_LOOKUP.INVALS	Counts Number of times HitMe Cache is accessed; Invalidations	0,1,2,3	0	null	0
+HA	0x70	0xFF	UNC_H_HITME_LOOKUP.ALL	Counts Number of times HitMe Cache is accessed; All Requests	0,1,2,3	0	null	0
+HA	0x70	0xF	UNC_H_HITME_LOOKUP.HOM	Counts Number of times HitMe Cache is accessed; HOM Requests	0,1,2,3	0	null	0
+HA	0x22	0x1	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0	Cycles without QPI Ingress Credits; AD to QPI Link 0	0,1,2,3	0	null	0
+HA	0x22	0x2	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1	Cycles without QPI Ingress Credits; AD to QPI Link 1	0,1,2,3	0	null	0
+HA	0x22	0x4	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0	Cycles without QPI Ingress Credits; BL to QPI Link 0	0,1,2,3	0	null	0
+HA	0x22	0x8	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1	Cycles without QPI Ingress Credits; BL to QPI Link 1	0,1,2,3	0	null	0
+HA	0x22	0x10	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2	Cycles without QPI Ingress Credits; BL to QPI Link 0	0,1,2,3	0	null	0
+HA	0x22	0x20	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2	Cycles without QPI Ingress Credits; BL to QPI Link 1	0,1,2,3	0	null	0
+HA	0x17	0x1	UNC_H_IMC_READS.NORMAL	HA to iMC Normal Priority Reads Issued; Normal Priority	0,1,2,3	0	null	0
+HA	0x1E	0x0	UNC_H_IMC_RETRY	Retry Events	0,1,2,3	0	null	0
+HA	0x1A	0x1	UNC_H_IMC_WRITES.FULL	HA to iMC Full Line Writes Issued; Full Line Non-ISOCH	0,1,2,3	0	null	0
+HA	0x1A	0x2	UNC_H_IMC_WRITES.PARTIAL	HA to iMC Full Line Writes Issued; Partial Non-ISOCH	0,1,2,3	0	null	0
+HA	0x1A	0x4	UNC_H_IMC_WRITES.FULL_ISOCH	HA to iMC Full Line Writes Issued; ISOCH Full Line	0,1,2,3	0	null	0
+HA	0x1A	0x8	UNC_H_IMC_WRITES.PARTIAL_ISOCH	HA to iMC Full Line Writes Issued; ISOCH Partial	0,1,2,3	0	null	0
+HA	0x1A	0xF	UNC_H_IMC_WRITES.ALL	HA to iMC Full Line Writes Issued; All Writes	0,1,2,3	0	null	0
+HA	0x61	0x1	UNC_H_IOT_BACKPRESSURE.SAT	IOT Backpressure	0,1,2	0	null	0
+HA	0x61	0x2	UNC_H_IOT_BACKPRESSURE.HUB	IOT Backpressure	0,1,2	0	null	0
+HA	0x64	0x1	UNC_H_IOT_CTS_EAST_LO.CTS0	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+HA	0x64	0x2	UNC_H_IOT_CTS_EAST_LO.CTS1	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+HA	0x65	0x1	UNC_H_IOT_CTS_HI.CTS2	IOT Common Trigger Sequencer - Hi	0,1,2	0	null	0
+HA	0x65	0x2	UNC_H_IOT_CTS_HI.CTS3	IOT Common Trigger Sequencer - Hi	0,1,2	0	null	0
+HA	0x62	0x1	UNC_H_IOT_CTS_WEST_LO.CTS0	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+HA	0x62	0x2	UNC_H_IOT_CTS_WEST_LO.CTS1	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+HA	0x53	0x2	UNC_H_OSB.READS_LOCAL	OSB Snoop Broadcast; Local Reads	0,1,2,3	0	null	0
+HA	0x53	0x4	UNC_H_OSB.INVITOE_LOCAL	OSB Snoop Broadcast; Local InvItoE	0,1,2,3	0	null	0
+HA	0x53	0x8	UNC_H_OSB.REMOTE	OSB Snoop Broadcast; Remote	0,1,2,3	0	null	0
+HA	0x53	0x10	UNC_H_OSB.CANCELLED	OSB Snoop Broadcast; Cancelled	0,1,2,3	0	null	0
+HA	0x53	0x20	UNC_H_OSB.READS_LOCAL_USEFUL	OSB Snoop Broadcast; Reads Local -  Useful	0,1,2,3	0	null	0
+HA	0x53	0x40	UNC_H_OSB.REMOTE_USEFUL	OSB Snoop Broadcast; Remote - Useful	0,1,2,3	0	null	0
+HA	0x54	0x1	UNC_H_OSB_EDR.ALL	OSB Early Data Return; All	0,1,2,3	0	null	0
+HA	0x54	0x2	UNC_H_OSB_EDR.READS_LOCAL_I	OSB Early Data Return; Reads to Local  I	0,1,2,3	0	null	0
+HA	0x54	0x4	UNC_H_OSB_EDR.READS_REMOTE_I	OSB Early Data Return; Reads to Remote I	0,1,2,3	0	null	0
+HA	0x54	0x8	UNC_H_OSB_EDR.READS_LOCAL_S	OSB Early Data Return; Reads to Local S	0,1,2,3	0	null	0
+HA	0x54	0x10	UNC_H_OSB_EDR.READS_REMOTE_S	OSB Early Data Return; Reads to Remote S	0,1,2,3	0	null	0
+HA	0x1	0x3	UNC_H_REQUESTS.READS	Read and Write Requests; Reads	0,1,2,3	0	null	0
+HA	0x1	0xC	UNC_H_REQUESTS.WRITES	Read and Write Requests; Writes	0,1,2,3	0	null	0
+HA	0x1	0x1	UNC_H_REQUESTS.READS_LOCAL	Read and Write Requests; Local Reads	0,1,2,3	0	null	0
+HA	0x1	0x2	UNC_H_REQUESTS.READS_REMOTE	Read and Write Requests; Remote Reads	0,1,2,3	0	null	0
+HA	0x1	0x4	UNC_H_REQUESTS.WRITES_LOCAL	Read and Write Requests; Local Writes	0,1,2,3	0	null	0
+HA	0x1	0x8	UNC_H_REQUESTS.WRITES_REMOTE	Read and Write Requests; Remote Writes	0,1,2,3	0	null	0
+HA	0x1	0x10	UNC_H_REQUESTS.INVITOE_LOCAL	Read and Write Requests; Local InvItoEs	0,1,2,3	0	null	0
+HA	0x1	0x20	UNC_H_REQUESTS.INVITOE_REMOTE	Read and Write Requests; Remote InvItoEs	0,1,2,3	0	null	0
+HA	0x3E	0x1	UNC_H_RING_AD_USED.CW_EVEN	HA AD Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+HA	0x3E	0x2	UNC_H_RING_AD_USED.CW_ODD	HA AD Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+HA	0x3E	0x4	UNC_H_RING_AD_USED.CCW_EVEN	HA AD Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+HA	0x3E	0x8	UNC_H_RING_AD_USED.CCW_ODD	HA AD Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+HA	0x3E	0x3	UNC_H_RING_AD_USED.CW	HA AD Ring in Use; Clockwise	0,1,2,3	0	null	0
+HA	0x3E	0xC	UNC_H_RING_AD_USED.CCW	HA AD Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+HA	0x3F	0x1	UNC_H_RING_AK_USED.CW_EVEN	HA AK Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+HA	0x3F	0x2	UNC_H_RING_AK_USED.CW_ODD	HA AK Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+HA	0x3F	0x4	UNC_H_RING_AK_USED.CCW_EVEN	HA AK Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+HA	0x3F	0x8	UNC_H_RING_AK_USED.CCW_ODD	HA AK Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+HA	0x3F	0x3	UNC_H_RING_AK_USED.CW	HA AK Ring in Use; Clockwise	0,1,2,3	0	null	0
+HA	0x3F	0xC	UNC_H_RING_AK_USED.CCW	HA AK Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+HA	0x3F	0xF	UNC_H_RING_AK_USED.ALL	HA AK Ring in Use; All	0,1,2,3	0	null	0
+HA	0x40	0x1	UNC_H_RING_BL_USED.CW_EVEN	HA BL Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+HA	0x40	0x2	UNC_H_RING_BL_USED.CW_ODD	HA BL Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+HA	0x40	0x4	UNC_H_RING_BL_USED.CCW_EVEN	HA BL Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+HA	0x40	0x8	UNC_H_RING_BL_USED.CCW_ODD	HA BL Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+HA	0x40	0x3	UNC_H_RING_BL_USED.CW	HA BL Ring in Use; Clockwise	0,1,2,3	0	null	0
+HA	0x40	0xC	UNC_H_RING_BL_USED.CCW	HA BL Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+HA	0x40	0xF	UNC_H_RING_BL_USED.ALL	HA BL Ring in Use; All	0,1,2,3	0	null	0
+HA	0x15	0x1	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0	iMC RPQ Credits Empty - Regular; Channel 0	0,1,2,3	0	null	0
+HA	0x15	0x2	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1	iMC RPQ Credits Empty - Regular; Channel 1	0,1,2,3	0	null	0
+HA	0x15	0x4	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2	iMC RPQ Credits Empty - Regular; Channel 2	0,1,2,3	0	null	0
+HA	0x15	0x8	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3	iMC RPQ Credits Empty - Regular; Channel 3	0,1,2,3	0	null	0
+HA	0x16	0x1	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0	iMC RPQ Credits Empty - Special; Channel 0	0,1,2,3	0	null	0
+HA	0x16	0x2	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1	iMC RPQ Credits Empty - Special; Channel 1	0,1,2,3	0	null	0
+HA	0x16	0x4	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2	iMC RPQ Credits Empty - Special; Channel 2	0,1,2,3	0	null	0
+HA	0x16	0x8	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3	iMC RPQ Credits Empty - Special; Channel 3	0,1,2,3	0	null	0
+HA	0x68	0x1	UNC_H_SBO0_CREDITS_ACQUIRED.AD	SBo0 Credits Acquired; For AD Ring	0,1,2,3	0	null	0
+HA	0x68	0x2	UNC_H_SBO0_CREDITS_ACQUIRED.BL	SBo0 Credits Acquired; For BL Ring	0,1,2,3	0	null	0
+HA	0x6A	0x1	UNC_H_SBO0_CREDIT_OCCUPANCY.AD	SBo0 Credits Occupancy; For AD Ring	0,1,2,3	0	null	0
+HA	0x6A	0x2	UNC_H_SBO0_CREDIT_OCCUPANCY.BL	SBo0 Credits Occupancy; For BL Ring	0,1,2,3	0	null	0
+HA	0x69	0x1	UNC_H_SBO1_CREDITS_ACQUIRED.AD	SBo1 Credits Acquired; For AD Ring	0,1,2,3	0	null	0
+HA	0x69	0x2	UNC_H_SBO1_CREDITS_ACQUIRED.BL	SBo1 Credits Acquired; For BL Ring	0,1,2,3	0	null	0
+HA	0x6B	0x1	UNC_H_SBO1_CREDIT_OCCUPANCY.AD	SBo1 Credits Occupancy; For AD Ring	0,1,2,3	0	null	0
+HA	0x6B	0x2	UNC_H_SBO1_CREDIT_OCCUPANCY.BL	SBo1 Credits Occupancy; For BL Ring	0,1,2,3	0	null	0
+HA	0xA	0x1	UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL	Data beat the Snoop Responses; Local Requests	0,1,2,3	0	null	0
+HA	0xA	0x2	UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE	Data beat the Snoop Responses; Remote Requests	0,1,2,3	0	null	0
+HA	0x8	0x1	UNC_H_SNOOP_CYCLES_NE.LOCAL	Cycles with Snoops Outstanding; Local Requests	0,1,2,3	0	null	0
+HA	0x8	0x2	UNC_H_SNOOP_CYCLES_NE.REMOTE	Cycles with Snoops Outstanding; Remote Requests	0,1,2,3	0	null	0
+HA	0x8	0x3	UNC_H_SNOOP_CYCLES_NE.ALL	Cycles with Snoops Outstanding; All Requests	0,1,2,3	0	null	0
+HA	0x9	0x1	UNC_H_SNOOP_OCCUPANCY.LOCAL	Tracker Snoops Outstanding Accumulator; Local Requests	0,1,2,3	0	null	0
+HA	0x9	0x2	UNC_H_SNOOP_OCCUPANCY.REMOTE	Tracker Snoops Outstanding Accumulator; Remote Requests	0,1,2,3	0	null	0
+HA	0x21	0x1	UNC_H_SNOOP_RESP.RSPI	Snoop Responses Received; RspI	0,1,2,3	0	null	0
+HA	0x21	0x2	UNC_H_SNOOP_RESP.RSPS	Snoop Responses Received; RspS	0,1,2,3	0	null	0
+HA	0x21	0x4	UNC_H_SNOOP_RESP.RSPIFWD	Snoop Responses Received; RspIFwd	0,1,2,3	0	null	0
+HA	0x21	0x8	UNC_H_SNOOP_RESP.RSPSFWD	Snoop Responses Received; RspSFwd	0,1,2,3	0	null	0
+HA	0x21	0x10	UNC_H_SNOOP_RESP.RSP_WB	Snoop Responses Received; Rsp*WB	0,1,2,3	0	null	0
+HA	0x21	0x20	UNC_H_SNOOP_RESP.RSP_FWD_WB	Snoop Responses Received; Rsp*Fwd*WB	0,1,2,3	0	null	0
+HA	0x21	0x40	UNC_H_SNOOP_RESP.RSPCNFLCT	Snoop Responses Received; RSPCNFLCT*	0,1,2,3	0	null	0
+HA	0x60	0x1	UNC_H_SNP_RESP_RECV_LOCAL.RSPI	Snoop Responses Received Local; RspI	0,1,2,3	0	null	0
+HA	0x60	0x2	UNC_H_SNP_RESP_RECV_LOCAL.RSPS	Snoop Responses Received Local; RspS	0,1,2,3	0	null	0
+HA	0x60	0x4	UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD	Snoop Responses Received Local; RspIFwd	0,1,2,3	0	null	0
+HA	0x60	0x8	UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD	Snoop Responses Received Local; RspSFwd	0,1,2,3	0	null	0
+HA	0x60	0x10	UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB	Snoop Responses Received Local; Rsp*WB	0,1,2,3	0	null	0
+HA	0x60	0x20	UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB	Snoop Responses Received Local; Rsp*FWD*WB	0,1,2,3	0	null	0
+HA	0x60	0x40	UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT	Snoop Responses Received Local; RspCnflct	0,1,2,3	0	null	0
+HA	0x60	0x80	UNC_H_SNP_RESP_RECV_LOCAL.OTHER	Snoop Responses Received Local; Other	0,1,2,3	0	null	0
+HA	0x6C	0x1	UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD	Stall on No Sbo Credits; For SBo0, AD Ring	0,1,2,3	0	null	0
+HA	0x6C	0x2	UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD	Stall on No Sbo Credits; For SBo1, AD Ring	0,1,2,3	0	null	0
+HA	0x6C	0x4	UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL	Stall on No Sbo Credits; For SBo0, BL Ring	0,1,2,3	0	null	0
+HA	0x6C	0x8	UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL	Stall on No Sbo Credits; For SBo1, BL Ring	0,1,2,3	0	null	0
+HA	0x1B	0x1	UNC_H_TAD_REQUESTS_G0.REGION0	HA Requests to a TAD Region - Group 0; TAD Region 0	0,1,2,3	0	null	0
+HA	0x1B	0x2	UNC_H_TAD_REQUESTS_G0.REGION1	HA Requests to a TAD Region - Group 0; TAD Region 1	0,1,2,3	0	null	0
+HA	0x1B	0x4	UNC_H_TAD_REQUESTS_G0.REGION2	HA Requests to a TAD Region - Group 0; TAD Region 2	0,1,2,3	0	null	0
+HA	0x1B	0x8	UNC_H_TAD_REQUESTS_G0.REGION3	HA Requests to a TAD Region - Group 0; TAD Region 3	0,1,2,3	0	null	0
+HA	0x1B	0x10	UNC_H_TAD_REQUESTS_G0.REGION4	HA Requests to a TAD Region - Group 0; TAD Region 4	0,1,2,3	0	null	0
+HA	0x1B	0x20	UNC_H_TAD_REQUESTS_G0.REGION5	HA Requests to a TAD Region - Group 0; TAD Region 5	0,1,2,3	0	null	0
+HA	0x1B	0x40	UNC_H_TAD_REQUESTS_G0.REGION6	HA Requests to a TAD Region - Group 0; TAD Region 6	0,1,2,3	0	null	0
+HA	0x1B	0x80	UNC_H_TAD_REQUESTS_G0.REGION7	HA Requests to a TAD Region - Group 0; TAD Region 7	0,1,2,3	0	null	0
+HA	0x1C	0x1	UNC_H_TAD_REQUESTS_G1.REGION8	HA Requests to a TAD Region - Group 1; TAD Region 8	0,1,2,3	0	null	0
+HA	0x1C	0x2	UNC_H_TAD_REQUESTS_G1.REGION9	HA Requests to a TAD Region - Group 1; TAD Region 9	0,1,2,3	0	null	0
+HA	0x1C	0x4	UNC_H_TAD_REQUESTS_G1.REGION10	HA Requests to a TAD Region - Group 1; TAD Region 10	0,1,2,3	0	null	0
+HA	0x1C	0x8	UNC_H_TAD_REQUESTS_G1.REGION11	HA Requests to a TAD Region - Group 1; TAD Region 11	0,1,2,3	0	null	0
+HA	0x2	0x1	UNC_H_TRACKER_CYCLES_FULL.GP	Tracker Cycles Full; Cycles GP Completely Used	0,1,2,3	0	null	0
+HA	0x2	0x2	UNC_H_TRACKER_CYCLES_FULL.ALL	Tracker Cycles Full; Cycles Completely Used	0,1,2,3	0	null	0
+HA	0x3	0x1	UNC_H_TRACKER_CYCLES_NE.LOCAL	Tracker Cycles Not Empty; Local Requests	0,1,2,3	0	null	0
+HA	0x3	0x2	UNC_H_TRACKER_CYCLES_NE.REMOTE	Tracker Cycles Not Empty; Remote Requests	0,1,2,3	0	null	0
+HA	0x3	0x3	UNC_H_TRACKER_CYCLES_NE.ALL	Tracker Cycles Not Empty; All Requests	0,1,2,3	0	null	0
+HA	0x4	0x4	UNC_H_TRACKER_OCCUPANCY.READS_LOCAL	Tracker Occupancy Accumultor; Local Read Requests	0,1,2,3	0	null	0
+HA	0x4	0x8	UNC_H_TRACKER_OCCUPANCY.READS_REMOTE	Tracker Occupancy Accumultor; Remote Read Requests	0,1,2,3	0	null	0
+HA	0x4	0x10	UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL	Tracker Occupancy Accumultor; Local Write Requests	0,1,2,3	0	null	0
+HA	0x4	0x20	UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE	Tracker Occupancy Accumultor; Remote Write Requests	0,1,2,3	0	null	0
+HA	0x4	0x40	UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL	Tracker Occupancy Accumultor; Local InvItoE Requests	0,1,2,3	0	null	0
+HA	0x4	0x80	UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE	Tracker Occupancy Accumultor; Remote InvItoE Requests	0,1,2,3	0	null	0
+HA	0x5	0x1	UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL	Data Pending Occupancy Accumultor; Local Requests	0,1,2,3	0	null	0
+HA	0x5	0x2	UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE	Data Pending Occupancy Accumultor; Remote Requests	0,1,2,3	0	null	0
+HA	0xF	0x4	UNC_H_TxR_AD.HOM	Outbound NDR Ring Transactions; Non-data Responses	0,1,2,3	0	null	0
+HA	0x2A	0x1	UNC_H_TxR_AD_CYCLES_FULL.SCHED0	AD Egress Full; Scheduler 0	0,1,2,3	0	null	0
+HA	0x2A	0x2	UNC_H_TxR_AD_CYCLES_FULL.SCHED1	AD Egress Full; Scheduler 1	0,1,2,3	0	null	0
+HA	0x2A	0x3	UNC_H_TxR_AD_CYCLES_FULL.ALL	AD Egress Full; All	0,1,2,3	0	null	0
+HA	0x29	0x1	UNC_H_TxR_AD_CYCLES_NE.SCHED0	AD Egress Not Empty; Scheduler 0	0,1,2,3	0	null	0
+HA	0x29	0x2	UNC_H_TxR_AD_CYCLES_NE.SCHED1	AD Egress Not Empty; Scheduler 1	0,1,2,3	0	null	0
+HA	0x29	0x3	UNC_H_TxR_AD_CYCLES_NE.ALL	AD Egress Not Empty; All	0,1,2,3	0	null	0
+HA	0x27	0x1	UNC_H_TxR_AD_INSERTS.SCHED0	AD Egress Allocations; Scheduler 0	0,1,2,3	0	null	0
+HA	0x27	0x2	UNC_H_TxR_AD_INSERTS.SCHED1	AD Egress Allocations; Scheduler 1	0,1,2,3	0	null	0
+HA	0x27	0x3	UNC_H_TxR_AD_INSERTS.ALL	AD Egress Allocations; All	0,1,2,3	0	null	0
+HA	0x32	0x1	UNC_H_TxR_AK_CYCLES_FULL.SCHED0	AK Egress Full; Scheduler 0	0,1,2,3	0	null	0
+HA	0x32	0x2	UNC_H_TxR_AK_CYCLES_FULL.SCHED1	AK Egress Full; Scheduler 1	0,1,2,3	0	null	0
+HA	0x32	0x3	UNC_H_TxR_AK_CYCLES_FULL.ALL	AK Egress Full; All	0,1,2,3	0	null	0
+HA	0x31	0x1	UNC_H_TxR_AK_CYCLES_NE.SCHED0	AK Egress Not Empty; Scheduler 0	0,1,2,3	0	null	0
+HA	0x31	0x2	UNC_H_TxR_AK_CYCLES_NE.SCHED1	AK Egress Not Empty; Scheduler 1	0,1,2,3	0	null	0
+HA	0x31	0x3	UNC_H_TxR_AK_CYCLES_NE.ALL	AK Egress Not Empty; All	0,1,2,3	0	null	0
+HA	0x2F	0x1	UNC_H_TxR_AK_INSERTS.SCHED0	AK Egress Allocations; Scheduler 0	0,1,2,3	0	null	0
+HA	0x2F	0x2	UNC_H_TxR_AK_INSERTS.SCHED1	AK Egress Allocations; Scheduler 1	0,1,2,3	0	null	0
+HA	0x2F	0x3	UNC_H_TxR_AK_INSERTS.ALL	AK Egress Allocations; All	0,1,2,3	0	null	0
+HA	0x10	0x1	UNC_H_TxR_BL.DRS_CACHE	Outbound DRS Ring Transactions to Cache; Data to Cache	0,1,2,3	0	null	0
+HA	0x10	0x2	UNC_H_TxR_BL.DRS_CORE	Outbound DRS Ring Transactions to Cache; Data to Core	0,1,2,3	0	null	0
+HA	0x10	0x4	UNC_H_TxR_BL.DRS_QPI	Outbound DRS Ring Transactions to Cache; Data to QPI	0,1,2,3	0	null	0
+HA	0x36	0x1	UNC_H_TxR_BL_CYCLES_FULL.SCHED0	BL Egress Full; Scheduler 0	0,1,2,3	0	null	0
+HA	0x36	0x2	UNC_H_TxR_BL_CYCLES_FULL.SCHED1	BL Egress Full; Scheduler 1	0,1,2,3	0	null	0
+HA	0x36	0x3	UNC_H_TxR_BL_CYCLES_FULL.ALL	BL Egress Full; All	0,1,2,3	0	null	0
+HA	0x35	0x1	UNC_H_TxR_BL_CYCLES_NE.SCHED0	BL Egress Not Empty; Scheduler 0	0,1,2,3	0	null	0
+HA	0x35	0x2	UNC_H_TxR_BL_CYCLES_NE.SCHED1	BL Egress Not Empty; Scheduler 1	0,1,2,3	0	null	0
+HA	0x35	0x3	UNC_H_TxR_BL_CYCLES_NE.ALL	BL Egress Not Empty; All	0,1,2,3	0	null	0
+HA	0x33	0x1	UNC_H_TxR_BL_INSERTS.SCHED0	BL Egress Allocations; Scheduler 0	0,1,2,3	0	null	0
+HA	0x33	0x2	UNC_H_TxR_BL_INSERTS.SCHED1	BL Egress Allocations; Scheduler 1	0,1,2,3	0	null	0
+HA	0x33	0x3	UNC_H_TxR_BL_INSERTS.ALL	BL Egress Allocations; All	0,1,2,3	0	null	0
+HA	0x6D	0x1	UNC_H_TxR_STARVED.AK	Injection Starvation; For AK Ring	0,1,2,3	0	null	0
+HA	0x6D	0x2	UNC_H_TxR_STARVED.BL	Injection Starvation; For BL Ring	0,1,2,3	0	null	0
+HA	0x18	0x1	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0	HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0	0,1,2,3	0	null	0
+HA	0x18	0x2	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1	HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1	0,1,2,3	0	null	0
+HA	0x18	0x4	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2	HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2	0,1,2,3	0	null	0
+HA	0x18	0x8	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3	HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3	0,1,2,3	0	null	0
+HA	0x19	0x1	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0	HA iMC CHN0 WPQ Credits Empty - Special; Channel 0	0,1,2,3	0	null	0
+HA	0x19	0x2	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1	HA iMC CHN0 WPQ Credits Empty - Special; Channel 1	0,1,2,3	0	null	0
+HA	0x19	0x4	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2	HA iMC CHN0 WPQ Credits Empty - Special; Channel 2	0,1,2,3	0	null	0
+HA	0x19	0x8	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3	HA iMC CHN0 WPQ Credits Empty - Special; Channel 3	0,1,2,3	0	null	0
+IRP	0x12	0x1	UNC_I_CACHE_TOTAL_OCCUPANCY.ANY	Total Write Cache Occupancy; Any Source	0,1	0	null	0
+IRP	0x12	0x2	UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE	Total Write Cache Occupancy; Select Source	0,1	0	null	0
+IRP	0x0	0x0	UNC_I_CLOCKTICKS	Clocks in the IRP	0,1	0	null	0
+IRP	0x13	0x1	UNC_I_COHERENT_OPS.PCIRDCUR	Coherent Ops; PCIRdCur	0,1	0	null	0
+IRP	0x13	0x2	UNC_I_COHERENT_OPS.CRD	Coherent Ops; CRd	0,1	0	null	0
+IRP	0x13	0x4	UNC_I_COHERENT_OPS.DRD	Coherent Ops; DRd	0,1	0	null	0
+IRP	0x13	0x8	UNC_I_COHERENT_OPS.RFO	Coherent Ops; RFO	0,1	0	null	0
+IRP	0x13	0x10	UNC_I_COHERENT_OPS.PCITOM	Coherent Ops; PCIItoM	0,1	0	null	0
+IRP	0x13	0x20	UNC_I_COHERENT_OPS.PCIDCAHINT	Coherent Ops; PCIDCAHin5t	0,1	0	null	0
+IRP	0x13	0x40	UNC_I_COHERENT_OPS.WBMTOI	Coherent Ops; WbMtoI	0,1	0	null	0
+IRP	0x13	0x80	UNC_I_COHERENT_OPS.CLFLUSH	Coherent Ops; CLFlush	0,1	0	null	0
+IRP	0x14	0x1	UNC_I_MISC0.FAST_REQ	Misc Events - Set 0; Fastpath Requests	0,1	0	null	0
+IRP	0x14	0x2	UNC_I_MISC0.FAST_REJ	Misc Events - Set 0; Fastpath Rejects	0,1	0	null	0
+IRP	0x14	0x4	UNC_I_MISC0.2ND_RD_INSERT	Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary	0,1	0	null	0
+IRP	0x14	0x8	UNC_I_MISC0.2ND_WR_INSERT	Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary	0,1	0	null	0
+IRP	0x14	0x10	UNC_I_MISC0.2ND_ATOMIC_INSERT	Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary	0,1	0	null	0
+IRP	0x14	0x20	UNC_I_MISC0.FAST_XFER	Misc Events - Set 0; Fastpath Transfers From Primary to Secondary	0,1	0	null	0
+IRP	0x14	0x40	UNC_I_MISC0.PF_ACK_HINT	Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary	0,1	0	null	0
+IRP	0x14	0x80	UNC_I_MISC0.PF_TIMEOUT	Misc Events - Set 0; Prefetch TimeOut	0,1	0	null	0
+IRP	0x15	0x1	UNC_I_MISC1.SLOW_I	Misc Events - Set 1; Slow Transfer of I Line	0,1	0	null	0
+IRP	0x15	0x2	UNC_I_MISC1.SLOW_S	Misc Events - Set 1; Slow Transfer of S Line	0,1	0	null	0
+IRP	0x15	0x4	UNC_I_MISC1.SLOW_E	Misc Events - Set 1; Slow Transfer of E Line	0,1	0	null	0
+IRP	0x15	0x8	UNC_I_MISC1.SLOW_M	Misc Events - Set 1; Slow Transfer of M Line	0,1	0	null	0
+IRP	0x15	0x10	UNC_I_MISC1.LOST_FWD	Misc Events - Set 1	0,1	0	null	0
+IRP	0x15	0x20	UNC_I_MISC1.SEC_RCVD_INVLD	Misc Events - Set 1; Received Invalid	0,1	0	null	0
+IRP	0x15	0x40	UNC_I_MISC1.SEC_RCVD_VLD	Misc Events - Set 1; Received Valid	0,1	0	null	0
+IRP	0x15	0x80	UNC_I_MISC1.DATA_THROTTLE	Misc Events - Set 1; Data Throttled	0,1	0	null	0
+IRP	0xA	0x0	UNC_I_RxR_AK_INSERTS	AK Ingress Occupancy	0,1	0	null	0
+IRP	0x4	0x0	UNC_I_RxR_BL_DRS_CYCLES_FULL	tbd	0,1	0	null	0
+IRP	0x1	0x0	UNC_I_RxR_BL_DRS_INSERTS	BL Ingress Occupancy - DRS	0,1	0	null	0
+IRP	0x7	0x0	UNC_I_RxR_BL_DRS_OCCUPANCY	tbd	0,1	0	null	0
+IRP	0x5	0x0	UNC_I_RxR_BL_NCB_CYCLES_FULL	tbd	0,1	0	null	0
+IRP	0x2	0x0	UNC_I_RxR_BL_NCB_INSERTS	BL Ingress Occupancy - NCB	0,1	0	null	0
+IRP	0x8	0x0	UNC_I_RxR_BL_NCB_OCCUPANCY	tbd	0,1	0	null	0
+IRP	0x6	0x0	UNC_I_RxR_BL_NCS_CYCLES_FULL	tbd	0,1	0	null	0
+IRP	0x3	0x0	UNC_I_RxR_BL_NCS_INSERTS	BL Ingress Occupancy - NCS	0,1	0	null	0
+IRP	0x9	0x0	UNC_I_RxR_BL_NCS_OCCUPANCY	tbd	0,1	0	null	0
+IRP	0x17	0x1	UNC_I_SNOOP_RESP.MISS	Snoop Responses; Miss	0,1	0	null	0
+IRP	0x17	0x2	UNC_I_SNOOP_RESP.HIT_I	Snoop Responses; Hit I	0,1	0	null	0
+IRP	0x17	0x4	UNC_I_SNOOP_RESP.HIT_ES	Snoop Responses; Hit E or S	0,1	0	null	0
+IRP	0x17	0x8	UNC_I_SNOOP_RESP.HIT_M	Snoop Responses; Hit M	0,1	0	null	0
+IRP	0x17	0x10	UNC_I_SNOOP_RESP.SNPCODE	Snoop Responses; SnpCode	0,1	0	null	0
+IRP	0x17	0x20	UNC_I_SNOOP_RESP.SNPDATA	Snoop Responses; SnpData	0,1	0	null	0
+IRP	0x17	0x40	UNC_I_SNOOP_RESP.SNPINV	Snoop Responses; SnpInv	0,1	0	null	0
+IRP	0x16	0x1	UNC_I_TRANSACTIONS.READS	Inbound Transaction Count; Reads	0,1	0	null	0
+IRP	0x16	0x2	UNC_I_TRANSACTIONS.WRITES	Inbound Transaction Count; Writes	0,1	0	null	0
+IRP	0x16	0x4	UNC_I_TRANSACTIONS.RD_PREF	Inbound Transaction Count; Read Prefetches	0,1	0	null	0
+IRP	0x16	0x8	UNC_I_TRANSACTIONS.WR_PREF	Inbound Transaction Count; Write Prefetches	0,1	0	null	0
+IRP	0x16	0x10	UNC_I_TRANSACTIONS.ATOMIC	Inbound Transaction Count; Atomic	0,1	0	null	0
+IRP	0x16	0x20	UNC_I_TRANSACTIONS.OTHER	Inbound Transaction Count; Other	0,1	0	null	0
+IRP	0x16	0x40	UNC_I_TRANSACTIONS.ORDERINGQ	Inbound Transaction Count; Select Source	0,1	0	IRPFilter[4:0]	0
+IRP	0x18	0x0	UNC_I_TxR_AD_STALL_CREDIT_CYCLES	No AD Egress Credit Stalls	0,1	0	null	0
+IRP	0x19	0x0	UNC_I_TxR_BL_STALL_CREDIT_CYCLES	No BL Egress Credit Stalls	0,1	0	null	0
+IRP	0xE	0x0	UNC_I_TxR_DATA_INSERTS_NCB	Outbound Read Requests	0,1	0	null	0
+IRP	0xF	0x0	UNC_I_TxR_DATA_INSERTS_NCS	Outbound Read Requests	0,1	0	null	0
+IRP	0xD	0x0	UNC_I_TxR_REQUEST_OCCUPANCY	Outbound Request Queue Occupancy	0,1	0	null	0
+PCU	0x0	0x0	UNC_P_CLOCKTICKS	pclk Cycles	0,1,2,3	0	null	0
+PCU	0x60	0x0	UNC_P_CORE0_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6A	0x0	UNC_P_CORE10_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6B	0x0	UNC_P_CORE11_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6C	0x0	UNC_P_CORE12_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6D	0x0	UNC_P_CORE13_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6E	0x0	UNC_P_CORE14_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6F	0x0	UNC_P_CORE15_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x70	0x0	UNC_P_CORE16_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x71	0x0	UNC_P_CORE17_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x61	0x0	UNC_P_CORE1_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x62	0x0	UNC_P_CORE2_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x63	0x0	UNC_P_CORE3_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x64	0x0	UNC_P_CORE4_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x65	0x0	UNC_P_CORE5_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x66	0x0	UNC_P_CORE6_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x67	0x0	UNC_P_CORE7_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x68	0x0	UNC_P_CORE8_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x69	0x0	UNC_P_CORE9_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x30	0x0	UNC_P_DEMOTIONS_CORE0	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x31	0x0	UNC_P_DEMOTIONS_CORE1	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3A	0x0	UNC_P_DEMOTIONS_CORE10	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3B	0x0	UNC_P_DEMOTIONS_CORE11	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3C	0x0	UNC_P_DEMOTIONS_CORE12	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3D	0x0	UNC_P_DEMOTIONS_CORE13	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3E	0x0	UNC_P_DEMOTIONS_CORE14	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3F	0x0	UNC_P_DEMOTIONS_CORE15	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x40	0x0	UNC_P_DEMOTIONS_CORE16	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x41	0x0	UNC_P_DEMOTIONS_CORE17	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x32	0x0	UNC_P_DEMOTIONS_CORE2	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x33	0x0	UNC_P_DEMOTIONS_CORE3	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x34	0x0	UNC_P_DEMOTIONS_CORE4	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x35	0x0	UNC_P_DEMOTIONS_CORE5	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x36	0x0	UNC_P_DEMOTIONS_CORE6	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x37	0x0	UNC_P_DEMOTIONS_CORE7	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x38	0x0	UNC_P_DEMOTIONS_CORE8	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x39	0x0	UNC_P_DEMOTIONS_CORE9	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x4	0x0	UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES	Thermal Strongest Upper Limit Cycles	0,1,2,3	0	null	0
+PCU	0x6	0x0	UNC_P_FREQ_MAX_OS_CYCLES	OS Strongest Upper Limit Cycles	0,1,2,3	0	null	0
+PCU	0x5	0x0	UNC_P_FREQ_MAX_POWER_CYCLES	Power Strongest Upper Limit Cycles	0,1,2,3	0	null	0
+PCU	0x73	0x0	UNC_P_FREQ_MIN_IO_P_CYCLES	IO P Limit Strongest Lower Limit Cycles	0,1,2,3	0	null	0
+PCU	0x74	0x0	UNC_P_FREQ_TRANS_CYCLES	Cycles spent changing Frequency	0,1,2,3	0	null	0
+PCU	0x2F	0x0	UNC_P_MEMORY_PHASE_SHEDDING_CYCLES	Memory Phase Shedding Cycles	0,1,2,3	0	null	0
+PCU	0x2A	0x0	UNC_P_PKG_RESIDENCY_C0_CYCLES	Package C State Residency - C0	0,1,2,3	0	null	0
+PCU	0x4E	0x0	UNC_P_PKG_RESIDENCY_C1E_CYCLES	Package C State Residency - C1E	0,1,2,3	0	null	0
+PCU	0x2B	0x0	UNC_P_PKG_RESIDENCY_C2E_CYCLES	Package C State Residency - C2E	0,1,2,3	0	null	0
+PCU	0x2C	0x0	UNC_P_PKG_RESIDENCY_C3_CYCLES	Package C State Residency - C3	0,1,2,3	0	null	0
+PCU	0x2D	0x0	UNC_P_PKG_RESIDENCY_C6_CYCLES	Package C State Residency - C6	0,1,2,3	0	null	0
+PCU	0x2E	0x0	UNC_P_PKG_RESIDENCY_C7_CYCLES	Package C7 State Residency	0,1,2,3	0	null	0
+PCU	0x80	0x40	UNC_P_POWER_STATE_OCCUPANCY.CORES_C0	Number of cores in C-State; C0 and C1	0,1,2,3	0	null	0
+PCU	0x80	0x80	UNC_P_POWER_STATE_OCCUPANCY.CORES_C3	Number of cores in C-State; C3	0,1,2,3	0	null	0
+PCU	0x80	0xC0	UNC_P_POWER_STATE_OCCUPANCY.CORES_C6	Number of cores in C-State; C6 and C7	0,1,2,3	0	null	0
+PCU	0xA	0x0	UNC_P_PROCHOT_EXTERNAL_CYCLES	External Prochot	0,1,2,3	0	null	0
+PCU	0x9	0x0	UNC_P_PROCHOT_INTERNAL_CYCLES	Internal Prochot	0,1,2,3	0	null	0
+PCU	0x72	0x0	UNC_P_TOTAL_TRANSITION_CYCLES	Total Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x79	0x0	UNC_P_UFS_TRANSITIONS_RING_GV	tbd	0,1,2,3	0	null	0
+PCU	0x42	0x0	UNC_P_VR_HOT_CYCLES	VR Hot	0,1,2,3	0	null	0
+R2PCIe	0x1	0x0	UNC_R2_CLOCKTICKS	Number of uclks in domain	0,1,2,3	0	null	0
+R2PCIe	0x2D	0x1	UNC_R2_IIO_CREDIT.PRQ_QPI0	tbd	0,1	0	null	0
+R2PCIe	0x2D	0x2	UNC_R2_IIO_CREDIT.PRQ_QPI1	tbd	0,1	0	null	0
+R2PCIe	0x2D	0x4	UNC_R2_IIO_CREDIT.ISOCH_QPI0	tbd	0,1	0	null	0
+R2PCIe	0x2D	0x8	UNC_R2_IIO_CREDIT.ISOCH_QPI1	tbd	0,1	0	null	0
+R2PCIe	0x33	0x8	UNC_R2_IIO_CREDITS_ACQUIRED.DRS	R2PCIe IIO Credit Acquired; DRS	0,1	0	null	0
+R2PCIe	0x33	0x10	UNC_R2_IIO_CREDITS_ACQUIRED.NCB	R2PCIe IIO Credit Acquired; NCB	0,1	0	null	0
+R2PCIe	0x33	0x20	UNC_R2_IIO_CREDITS_ACQUIRED.NCS	R2PCIe IIO Credit Acquired; NCS	0,1	0	null	0
+R2PCIe	0x32	0x8	UNC_R2_IIO_CREDITS_USED.DRS	R2PCIe IIO Credits in Use; DRS	0,1	0	null	0
+R2PCIe	0x32	0x10	UNC_R2_IIO_CREDITS_USED.NCB	R2PCIe IIO Credits in Use; NCB	0,1	0	null	0
+R2PCIe	0x32	0x20	UNC_R2_IIO_CREDITS_USED.NCS	R2PCIe IIO Credits in Use; NCS	0,1	0	null	0
+R2PCIe	0x7	0x1	UNC_R2_RING_AD_USED.CW_EVEN	R2 AD Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x7	0x2	UNC_R2_RING_AD_USED.CW_ODD	R2 AD Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x7	0x4	UNC_R2_RING_AD_USED.CCW_EVEN	R2 AD Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x7	0x8	UNC_R2_RING_AD_USED.CCW_ODD	R2 AD Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x7	0x3	UNC_R2_RING_AD_USED.CW	R2 AD Ring in Use; Clockwise	0,1,2,3	0	null	0
+R2PCIe	0x7	0xC	UNC_R2_RING_AD_USED.CCW	R2 AD Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+R2PCIe	0x7	0xF	UNC_R2_RING_AD_USED.ALL	R2 AD Ring in Use; All	0,1,2,3	0	null	0
+R2PCIe	0x12	0x1	UNC_R2_RING_AK_BOUNCES.UP	AK Ingress Bounced; Up	0,1,2,3	0	null	0
+R2PCIe	0x12	0x2	UNC_R2_RING_AK_BOUNCES.DN	AK Ingress Bounced; Dn	0,1,2,3	0	null	0
+R2PCIe	0x8	0x1	UNC_R2_RING_AK_USED.CW_EVEN	R2 AK Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x8	0x2	UNC_R2_RING_AK_USED.CW_ODD	R2 AK Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x8	0x4	UNC_R2_RING_AK_USED.CCW_EVEN	R2 AK Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x8	0x8	UNC_R2_RING_AK_USED.CCW_ODD	R2 AK Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x8	0x3	UNC_R2_RING_AK_USED.CW	R2 AK Ring in Use; Clockwise	0,1,2,3	0	null	0
+R2PCIe	0x8	0xC	UNC_R2_RING_AK_USED.CCW	R2 AK Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+R2PCIe	0x8	0xF	UNC_R2_RING_AK_USED.ALL	R2 AK Ring in Use; All	0,1,2,3	0	null	0
+R2PCIe	0x9	0x1	UNC_R2_RING_BL_USED.CW_EVEN	R2 BL Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x9	0x2	UNC_R2_RING_BL_USED.CW_ODD	R2 BL Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x9	0x4	UNC_R2_RING_BL_USED.CCW_EVEN	R2 BL Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x9	0x8	UNC_R2_RING_BL_USED.CCW_ODD	R2 BL Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x9	0x3	UNC_R2_RING_BL_USED.CW	R2 BL Ring in Use; Clockwise	0,1,2,3	0	null	0
+R2PCIe	0x9	0xC	UNC_R2_RING_BL_USED.CCW	R2 BL Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+R2PCIe	0x9	0xF	UNC_R2_RING_BL_USED.ALL	R2 BL Ring in Use; All	0,1,2,3	0	null	0
+R2PCIe	0xA	0x3	UNC_R2_RING_IV_USED.CW	R2 IV Ring in Use; Clockwise	0,1,2,3	0	null	0
+R2PCIe	0xA	0xC	UNC_R2_RING_IV_USED.CCW	R2 IV Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+R2PCIe	0xA	0xF	UNC_R2_RING_IV_USED.ANY	R2 IV Ring in Use; Any	0,1,2,3	0	null	0
+R2PCIe	0x10	0x10	UNC_R2_RxR_CYCLES_NE.NCB	Ingress Cycles Not Empty; NCB	0,1	0	null	0
+R2PCIe	0x10	0x20	UNC_R2_RxR_CYCLES_NE.NCS	Ingress Cycles Not Empty; NCS	0,1	0	null	0
+R2PCIe	0x11	0x10	UNC_R2_RxR_INSERTS.NCB	Ingress Allocations; NCB	0,1	0	null	0
+R2PCIe	0x11	0x20	UNC_R2_RxR_INSERTS.NCS	Ingress Allocations; NCS	0,1	0	null	0
+R2PCIe	0x13	0x8	UNC_R2_RxR_OCCUPANCY.DRS	Ingress Occupancy Accumulator; DRS	0	0	null	0
+R2PCIe	0x28	0x1	UNC_R2_SBO0_CREDITS_ACQUIRED.AD	SBo0 Credits Acquired; For AD Ring	0,1	0	null	0
+R2PCIe	0x28	0x2	UNC_R2_SBO0_CREDITS_ACQUIRED.BL	SBo0 Credits Acquired; For BL Ring	0,1	0	null	0
+R2PCIe	0x2A	0x1	UNC_R2_SBO0_CREDIT_OCCUPANCY.AD	SBo0 Credits Occupancy; For AD Ring	0	0	null	0
+R2PCIe	0x2A	0x2	UNC_R2_SBO0_CREDIT_OCCUPANCY.BL	SBo0 Credits Occupancy; For BL Ring	0	0	null	0
+R2PCIe	0x2C	0x1	UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD	Stall on No Sbo Credits; For SBo0, AD Ring	0,1	0	null	0
+R2PCIe	0x2C	0x2	UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD	Stall on No Sbo Credits; For SBo1, AD Ring	0,1	0	null	0
+R2PCIe	0x2C	0x4	UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL	Stall on No Sbo Credits; For SBo0, BL Ring	0,1	0	null	0
+R2PCIe	0x2C	0x8	UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL	Stall on No Sbo Credits; For SBo1, BL Ring	0,1	0	null	0
+R2PCIe	0x25	0x1	UNC_R2_TxR_CYCLES_FULL.AD	Egress Cycles Full; AD	0	0	null	0
+R2PCIe	0x25	0x2	UNC_R2_TxR_CYCLES_FULL.AK	Egress Cycles Full; AK	0	0	null	0
+R2PCIe	0x25	0x4	UNC_R2_TxR_CYCLES_FULL.BL	Egress Cycles Full; BL	0	0	null	0
+R2PCIe	0x23	0x1	UNC_R2_TxR_CYCLES_NE.AD	Egress Cycles Not Empty; AD	0	0	null	0
+R2PCIe	0x23	0x2	UNC_R2_TxR_CYCLES_NE.AK	Egress Cycles Not Empty; AK	0	0	null	0
+R2PCIe	0x23	0x4	UNC_R2_TxR_CYCLES_NE.BL	Egress Cycles Not Empty; BL	0	0	null	0
+R2PCIe	0x26	0x1	UNC_R2_TxR_NACK_CW.DN_AD	Egress CCW NACK; AD CCW	0,1	0	null	0
+R2PCIe	0x26	0x2	UNC_R2_TxR_NACK_CW.DN_BL	Egress CCW NACK; BL CCW	0,1	0	null	0
+R2PCIe	0x26	0x4	UNC_R2_TxR_NACK_CW.DN_AK	Egress CCW NACK; AK CCW	0,1	0	null	0
+R2PCIe	0x26	0x8	UNC_R2_TxR_NACK_CW.UP_AD	Egress CCW NACK; AK CCW	0,1	0	null	0
+R2PCIe	0x26	0x10	UNC_R2_TxR_NACK_CW.UP_BL	Egress CCW NACK; BL CCW	0,1	0	null	0
+R2PCIe	0x26	0x20	UNC_R2_TxR_NACK_CW.UP_AK	Egress CCW NACK; BL CW	0,1	0	null	0
+UBOX	0x42	0x8	UNC_U_EVENT_MSG.DOORBELL_RCVD	VLW Received	0,1	0	null	0
+UBOX	0x41	0x1	UNC_U_FILTER_MATCH.ENABLE	Filter Match	0,1	0	UBoxFilter[3:0]	0
+UBOX	0x41	0x2	UNC_U_FILTER_MATCH.DISABLE	Filter Match	0,1	0	null	0
+UBOX	0x41	0x4	UNC_U_FILTER_MATCH.U2C_ENABLE	Filter Match	0,1	0	UBoxFilter[3:0]	0
+UBOX	0x41	0x8	UNC_U_FILTER_MATCH.U2C_DISABLE	Filter Match	0,1	0	null	0
+UBOX	0x45	0x1	UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK	Cycles PHOLD Assert to Ack; Assert to ACK	0,1	0	null	0
+UBOX	0x46	0x0	UNC_U_RACU_REQUESTS	RACU Request	0,1	0	null	0
+UBOX	0x43	0x1	UNC_U_U2C_EVENTS.MONITOR_T0	Monitor Sent to T0; Monitor T0	0,1	0	null	0
+UBOX	0x43	0x2	UNC_U_U2C_EVENTS.MONITOR_T1	Monitor Sent to T0; Monitor T1	0,1	0	null	0
+UBOX	0x43	0x4	UNC_U_U2C_EVENTS.LIVELOCK	Monitor Sent to T0; Livelock	0,1	0	null	0
+UBOX	0x43	0x8	UNC_U_U2C_EVENTS.LTERROR	Monitor Sent to T0; LTError	0,1	0	null	0
+UBOX	0x43	0x10	UNC_U_U2C_EVENTS.CMC	Monitor Sent to T0; Correctable Machine Check	0,1	0	null	0
+UBOX	0x43	0x20	UNC_U_U2C_EVENTS.UMC	Monitor Sent to T0; Uncorrectable Machine Check	0,1	0	null	0
+UBOX	0x43	0x40	UNC_U_U2C_EVENTS.TRAP	Monitor Sent to T0; Trap	0,1	0	null	0
+UBOX	0x43	0x80	UNC_U_U2C_EVENTS.OTHER	Monitor Sent to T0; Other	0,1	0	null	0
+iMC	0x1	0x1	UNC_M_ACT_COUNT.RD	DRAM Activate Count; Activate due to Read	0,1,2,3	0	null	0
+iMC	0x1	0x2	UNC_M_ACT_COUNT.WR	DRAM Activate Count; Activate due to Write	0,1,2,3	0	null	0
+iMC	0x1	0x8	UNC_M_ACT_COUNT.BYP	DRAM Activate Count; Activate due to Write	0,1,2,3	0	null	0
+iMC	0xA1	0x1	UNC_M_BYP_CMDS.ACT	ACT command issued by 2 cycle bypass	0,1,2,3	0	null	0
+iMC	0xA1	0x2	UNC_M_BYP_CMDS.CAS	CAS command issued by 2 cycle bypass	0,1,2,3	0	null	0
+iMC	0xA1	0x4	UNC_M_BYP_CMDS.PRE	PRE command issued by 2 cycle bypass	0,1,2,3	0	null	0
+iMC	0x4	0x1	UNC_M_CAS_COUNT.RD_REG	DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)	0,1,2,3	0	null	0
+iMC	0x4	0x2	UNC_M_CAS_COUNT.RD_UNDERFILL	DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued	0,1,2,3	0	null	0
+iMC	0x4	0x3	UNC_M_CAS_COUNT.RD	DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)	0,1,2,3	0	null	0
+iMC	0x4	0x4	UNC_M_CAS_COUNT.WR_WMM	DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode	0,1,2,3	0	null	0
+iMC	0x4	0x8	UNC_M_CAS_COUNT.WR_RMM	DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode	0,1,2,3	0	null	0
+iMC	0x4	0xC	UNC_M_CAS_COUNT.WR	DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)	0,1,2,3	0	null	0
+iMC	0x4	0xF	UNC_M_CAS_COUNT.ALL	DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)	0,1,2,3	0	null	0
+iMC	0x4	0x10	UNC_M_CAS_COUNT.RD_WMM	DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM	0,1,2,3	0	null	0
+iMC	0x4	0x20	UNC_M_CAS_COUNT.RD_RMM	DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM	0,1,2,3	0	null	0
+iMC	0x0	0x0	UNC_M_DCLOCKTICKS	DRAM Clockticks	0,1,2,3	0	null	0
+iMC	0x6	0x0	UNC_M_DRAM_PRE_ALL	DRAM Precharge All Commands	0,1,2,3	0	null	0
+iMC	0x5	0x2	UNC_M_DRAM_REFRESH.PANIC	Number of DRAM Refreshes Issued	0,1,2,3	0	null	0
+iMC	0x5	0x4	UNC_M_DRAM_REFRESH.HIGH	Number of DRAM Refreshes Issued	0,1,2,3	0	null	0
+iMC	0x9	0x0	UNC_M_ECC_CORRECTABLE_ERRORS	ECC Correctable Errors	0,1,2,3	0	null	0
+iMC	0x7	0x1	UNC_M_MAJOR_MODES.READ	Cycles in a Major Mode; Read Major Mode	0,1,2,3	0	null	0
+iMC	0x7	0x2	UNC_M_MAJOR_MODES.WRITE	Cycles in a Major Mode; Write Major Mode	0,1,2,3	0	null	0
+iMC	0x7	0x4	UNC_M_MAJOR_MODES.PARTIAL	Cycles in a Major Mode; Partial Major Mode	0,1,2,3	0	null	0
+iMC	0x7	0x8	UNC_M_MAJOR_MODES.ISOCH	Cycles in a Major Mode; Isoch Major Mode	0,1,2,3	0	null	0
+iMC	0x84	0x0	UNC_M_POWER_CHANNEL_DLLOFF	Channel DLLOFF Cycles	0,1,2,3	0	null	0
+iMC	0x85	0x0	UNC_M_POWER_CHANNEL_PPD	Channel PPD Cycles	0,1,2,3	0	null	0
+iMC	0x83	0x1	UNC_M_POWER_CKE_CYCLES.RANK0	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x2	UNC_M_POWER_CKE_CYCLES.RANK1	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x4	UNC_M_POWER_CKE_CYCLES.RANK2	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x8	UNC_M_POWER_CKE_CYCLES.RANK3	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x10	UNC_M_POWER_CKE_CYCLES.RANK4	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x20	UNC_M_POWER_CKE_CYCLES.RANK5	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x40	UNC_M_POWER_CKE_CYCLES.RANK6	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x80	UNC_M_POWER_CKE_CYCLES.RANK7	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x86	0x0	UNC_M_POWER_CRITICAL_THROTTLE_CYCLES	Critical Throttle Cycles	0,1,2,3	0	null	0
+iMC	0x42	0x0	UNC_M_POWER_PCU_THROTTLING	tbd	0,1,2,3	0	null	0
+iMC	0x43	0x0	UNC_M_POWER_SELF_REFRESH	Clock-Enabled Self-Refresh	0,1,2,3	0	null	0
+iMC	0x41	0x1	UNC_M_POWER_THROTTLE_CYCLES.RANK0	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x2	UNC_M_POWER_THROTTLE_CYCLES.RANK1	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x4	UNC_M_POWER_THROTTLE_CYCLES.RANK2	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x8	UNC_M_POWER_THROTTLE_CYCLES.RANK3	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x10	UNC_M_POWER_THROTTLE_CYCLES.RANK4	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x20	UNC_M_POWER_THROTTLE_CYCLES.RANK5	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x40	UNC_M_POWER_THROTTLE_CYCLES.RANK6	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x80	UNC_M_POWER_THROTTLE_CYCLES.RANK7	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x8	0x1	UNC_M_PREEMPTION.RD_PREEMPT_RD	Read Preemption Count; Read over Read Preemption	0,1,2,3	0	null	0
+iMC	0x8	0x2	UNC_M_PREEMPTION.RD_PREEMPT_WR	Read Preemption Count; Read over Write Preemption	0,1,2,3	0	null	0
+iMC	0x2	0x1	UNC_M_PRE_COUNT.PAGE_MISS	DRAM Precharge commands.; Precharges due to page miss	0,1,2,3	0	null	0
+iMC	0x2	0x2	UNC_M_PRE_COUNT.PAGE_CLOSE	DRAM Precharge commands.; Precharge due to timer expiration	0,1,2,3	0	null	0
+iMC	0x2	0x4	UNC_M_PRE_COUNT.RD	DRAM Precharge commands.; Precharge due to read	0,1,2,3	0	null	0
+iMC	0x2	0x8	UNC_M_PRE_COUNT.WR	DRAM Precharge commands.; Precharge due to write	0,1,2,3	0	null	0
+iMC	0x2	0x10	UNC_M_PRE_COUNT.BYP	DRAM Precharge commands.; Precharge due to bypass	0,1,2,3	0	null	0
+iMC	0xA0	0x1	UNC_M_RD_CAS_PRIO.LOW	Read CAS issued with LOW priority	0,1,2,3	0	null	0
+iMC	0xA0	0x2	UNC_M_RD_CAS_PRIO.MED	Read CAS issued with MEDIUM priority	0,1,2,3	0	null	0
+iMC	0xA0	0x4	UNC_M_RD_CAS_PRIO.HIGH	Read CAS issued with HIGH priority	0,1,2,3	0	null	0
+iMC	0xA0	0x8	UNC_M_RD_CAS_PRIO.PANIC	Read CAS issued with PANIC NON ISOCH priority (starved)	0,1,2,3	0	null	0
+iMC	0xB0	0x1	UNC_M_RD_CAS_RANK0.BANK1	RD_CAS Access to Rank 0; Bank 1	0,1,2,3	0	null	0
+iMC	0xB0	0x2	UNC_M_RD_CAS_RANK0.BANK2	RD_CAS Access to Rank 0; Bank 2	0,1,2,3	0	null	0
+iMC	0xB0	0x4	UNC_M_RD_CAS_RANK0.BANK4	RD_CAS Access to Rank 0; Bank 4	0,1,2,3	0	null	0
+iMC	0xB0	0x8	UNC_M_RD_CAS_RANK0.BANK8	RD_CAS Access to Rank 0; Bank 8	0,1,2,3	0	null	0
+iMC	0xB0	0x10	UNC_M_RD_CAS_RANK0.ALLBANKS	RD_CAS Access to Rank 0; All Banks	0,1,2,3	0	null	0
+iMC	0xB0	0x0	UNC_M_RD_CAS_RANK0.BANK0	RD_CAS Access to Rank 0; Bank 0	0,1,2,3	0	null	0
+iMC	0xB0	0x3	UNC_M_RD_CAS_RANK0.BANK3	RD_CAS Access to Rank 0; Bank 3	0,1,2,3	0	null	0
+iMC	0xB0	0x5	UNC_M_RD_CAS_RANK0.BANK5	RD_CAS Access to Rank 0; Bank 5	0,1,2,3	0	null	0
+iMC	0xB0	0x6	UNC_M_RD_CAS_RANK0.BANK6	RD_CAS Access to Rank 0; Bank 6	0,1,2,3	0	null	0
+iMC	0xB0	0x7	UNC_M_RD_CAS_RANK0.BANK7	RD_CAS Access to Rank 0; Bank 7	0,1,2,3	0	null	0
+iMC	0xB0	0x9	UNC_M_RD_CAS_RANK0.BANK9	RD_CAS Access to Rank 0; Bank 9	0,1,2,3	0	null	0
+iMC	0xB0	0xA	UNC_M_RD_CAS_RANK0.BANK10	RD_CAS Access to Rank 0; Bank 10	0,1,2,3	0	null	0
+iMC	0xB0	0xB	UNC_M_RD_CAS_RANK0.BANK11	RD_CAS Access to Rank 0; Bank 11	0,1,2,3	0	null	0
+iMC	0xB0	0xC	UNC_M_RD_CAS_RANK0.BANK12	RD_CAS Access to Rank 0; Bank 12	0,1,2,3	0	null	0
+iMC	0xB0	0xD	UNC_M_RD_CAS_RANK0.BANK13	RD_CAS Access to Rank 0; Bank 13	0,1,2,3	0	null	0
+iMC	0xB0	0xE	UNC_M_RD_CAS_RANK0.BANK14	RD_CAS Access to Rank 0; Bank 14	0,1,2,3	0	null	0
+iMC	0xB0	0xF	UNC_M_RD_CAS_RANK0.BANK15	RD_CAS Access to Rank 0; Bank 15	0,1,2,3	0	null	0
+iMC	0xB0	0x11	UNC_M_RD_CAS_RANK0.BANKG0	RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB0	0x12	UNC_M_RD_CAS_RANK0.BANKG1	RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB0	0x13	UNC_M_RD_CAS_RANK0.BANKG2	RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB0	0x14	UNC_M_RD_CAS_RANK0.BANKG3	RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB1	0x1	UNC_M_RD_CAS_RANK1.BANK1	RD_CAS Access to Rank 1; Bank 1	0,1,2,3	0	null	0
+iMC	0xB1	0x2	UNC_M_RD_CAS_RANK1.BANK2	RD_CAS Access to Rank 1; Bank 2	0,1,2,3	0	null	0
+iMC	0xB1	0x4	UNC_M_RD_CAS_RANK1.BANK4	RD_CAS Access to Rank 1; Bank 4	0,1,2,3	0	null	0
+iMC	0xB1	0x8	UNC_M_RD_CAS_RANK1.BANK8	RD_CAS Access to Rank 1; Bank 8	0,1,2,3	0	null	0
+iMC	0xB1	0x10	UNC_M_RD_CAS_RANK1.ALLBANKS	RD_CAS Access to Rank 1; All Banks	0,1,2,3	0	null	0
+iMC	0xB1	0x0	UNC_M_RD_CAS_RANK1.BANK0	RD_CAS Access to Rank 1; Bank 0	0,1,2,3	0	null	0
+iMC	0xB1	0x3	UNC_M_RD_CAS_RANK1.BANK3	RD_CAS Access to Rank 1; Bank 3	0,1,2,3	0	null	0
+iMC	0xB1	0x5	UNC_M_RD_CAS_RANK1.BANK5	RD_CAS Access to Rank 1; Bank 5	0,1,2,3	0	null	0
+iMC	0xB1	0x6	UNC_M_RD_CAS_RANK1.BANK6	RD_CAS Access to Rank 1; Bank 6	0,1,2,3	0	null	0
+iMC	0xB1	0x7	UNC_M_RD_CAS_RANK1.BANK7	RD_CAS Access to Rank 1; Bank 7	0,1,2,3	0	null	0
+iMC	0xB1	0x9	UNC_M_RD_CAS_RANK1.BANK9	RD_CAS Access to Rank 1; Bank 9	0,1,2,3	0	null	0
+iMC	0xB1	0xA	UNC_M_RD_CAS_RANK1.BANK10	RD_CAS Access to Rank 1; Bank 10	0,1,2,3	0	null	0
+iMC	0xB1	0xB	UNC_M_RD_CAS_RANK1.BANK11	RD_CAS Access to Rank 1; Bank 11	0,1,2,3	0	null	0
+iMC	0xB1	0xC	UNC_M_RD_CAS_RANK1.BANK12	RD_CAS Access to Rank 1; Bank 12	0,1,2,3	0	null	0
+iMC	0xB1	0xD	UNC_M_RD_CAS_RANK1.BANK13	RD_CAS Access to Rank 1; Bank 13	0,1,2,3	0	null	0
+iMC	0xB1	0xE	UNC_M_RD_CAS_RANK1.BANK14	RD_CAS Access to Rank 1; Bank 14	0,1,2,3	0	null	0
+iMC	0xB1	0xF	UNC_M_RD_CAS_RANK1.BANK15	RD_CAS Access to Rank 1; Bank 15	0,1,2,3	0	null	0
+iMC	0xB1	0x11	UNC_M_RD_CAS_RANK1.BANKG0	RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB1	0x12	UNC_M_RD_CAS_RANK1.BANKG1	RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB1	0x13	UNC_M_RD_CAS_RANK1.BANKG2	RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB1	0x14	UNC_M_RD_CAS_RANK1.BANKG3	RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB2	0x0	UNC_M_RD_CAS_RANK2.BANK0	RD_CAS Access to Rank 2; Bank 0	0,1,2,3	0	null	0
+iMC	0xB4	0x1	UNC_M_RD_CAS_RANK4.BANK1	RD_CAS Access to Rank 4; Bank 1	0,1,2,3	0	null	0
+iMC	0xB4	0x2	UNC_M_RD_CAS_RANK4.BANK2	RD_CAS Access to Rank 4; Bank 2	0,1,2,3	0	null	0
+iMC	0xB4	0x4	UNC_M_RD_CAS_RANK4.BANK4	RD_CAS Access to Rank 4; Bank 4	0,1,2,3	0	null	0
+iMC	0xB4	0x8	UNC_M_RD_CAS_RANK4.BANK8	RD_CAS Access to Rank 4; Bank 8	0,1,2,3	0	null	0
+iMC	0xB4	0x10	UNC_M_RD_CAS_RANK4.ALLBANKS	RD_CAS Access to Rank 4; All Banks	0,1,2,3	0	null	0
+iMC	0xB4	0x0	UNC_M_RD_CAS_RANK4.BANK0	RD_CAS Access to Rank 4; Bank 0	0,1,2,3	0	null	0
+iMC	0xB4	0x3	UNC_M_RD_CAS_RANK4.BANK3	RD_CAS Access to Rank 4; Bank 3	0,1,2,3	0	null	0
+iMC	0xB4	0x5	UNC_M_RD_CAS_RANK4.BANK5	RD_CAS Access to Rank 4; Bank 5	0,1,2,3	0	null	0
+iMC	0xB4	0x6	UNC_M_RD_CAS_RANK4.BANK6	RD_CAS Access to Rank 4; Bank 6	0,1,2,3	0	null	0
+iMC	0xB4	0x7	UNC_M_RD_CAS_RANK4.BANK7	RD_CAS Access to Rank 4; Bank 7	0,1,2,3	0	null	0
+iMC	0xB4	0x9	UNC_M_RD_CAS_RANK4.BANK9	RD_CAS Access to Rank 4; Bank 9	0,1,2,3	0	null	0
+iMC	0xB4	0xA	UNC_M_RD_CAS_RANK4.BANK10	RD_CAS Access to Rank 4; Bank 10	0,1,2,3	0	null	0
+iMC	0xB4	0xB	UNC_M_RD_CAS_RANK4.BANK11	RD_CAS Access to Rank 4; Bank 11	0,1,2,3	0	null	0
+iMC	0xB4	0xC	UNC_M_RD_CAS_RANK4.BANK12	RD_CAS Access to Rank 4; Bank 12	0,1,2,3	0	null	0
+iMC	0xB4	0xD	UNC_M_RD_CAS_RANK4.BANK13	RD_CAS Access to Rank 4; Bank 13	0,1,2,3	0	null	0
+iMC	0xB4	0xE	UNC_M_RD_CAS_RANK4.BANK14	RD_CAS Access to Rank 4; Bank 14	0,1,2,3	0	null	0
+iMC	0xB4	0xF	UNC_M_RD_CAS_RANK4.BANK15	RD_CAS Access to Rank 4; Bank 15	0,1,2,3	0	null	0
+iMC	0xB4	0x11	UNC_M_RD_CAS_RANK4.BANKG0	RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB4	0x12	UNC_M_RD_CAS_RANK4.BANKG1	RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB4	0x13	UNC_M_RD_CAS_RANK4.BANKG2	RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB4	0x14	UNC_M_RD_CAS_RANK4.BANKG3	RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB5	0x1	UNC_M_RD_CAS_RANK5.BANK1	RD_CAS Access to Rank 5; Bank 1	0,1,2,3	0	null	0
+iMC	0xB5	0x2	UNC_M_RD_CAS_RANK5.BANK2	RD_CAS Access to Rank 5; Bank 2	0,1,2,3	0	null	0
+iMC	0xB5	0x4	UNC_M_RD_CAS_RANK5.BANK4	RD_CAS Access to Rank 5; Bank 4	0,1,2,3	0	null	0
+iMC	0xB5	0x8	UNC_M_RD_CAS_RANK5.BANK8	RD_CAS Access to Rank 5; Bank 8	0,1,2,3	0	null	0
+iMC	0xB5	0x10	UNC_M_RD_CAS_RANK5.ALLBANKS	RD_CAS Access to Rank 5; All Banks	0,1,2,3	0	null	0
+iMC	0xB5	0x0	UNC_M_RD_CAS_RANK5.BANK0	RD_CAS Access to Rank 5; Bank 0	0,1,2,3	0	null	0
+iMC	0xB5	0x3	UNC_M_RD_CAS_RANK5.BANK3	RD_CAS Access to Rank 5; Bank 3	0,1,2,3	0	null	0
+iMC	0xB5	0x5	UNC_M_RD_CAS_RANK5.BANK5	RD_CAS Access to Rank 5; Bank 5	0,1,2,3	0	null	0
+iMC	0xB5	0x6	UNC_M_RD_CAS_RANK5.BANK6	RD_CAS Access to Rank 5; Bank 6	0,1,2,3	0	null	0
+iMC	0xB5	0x7	UNC_M_RD_CAS_RANK5.BANK7	RD_CAS Access to Rank 5; Bank 7	0,1,2,3	0	null	0
+iMC	0xB5	0x9	UNC_M_RD_CAS_RANK5.BANK9	RD_CAS Access to Rank 5; Bank 9	0,1,2,3	0	null	0
+iMC	0xB5	0xA	UNC_M_RD_CAS_RANK5.BANK10	RD_CAS Access to Rank 5; Bank 10	0,1,2,3	0	null	0
+iMC	0xB5	0xB	UNC_M_RD_CAS_RANK5.BANK11	RD_CAS Access to Rank 5; Bank 11	0,1,2,3	0	null	0
+iMC	0xB5	0xC	UNC_M_RD_CAS_RANK5.BANK12	RD_CAS Access to Rank 5; Bank 12	0,1,2,3	0	null	0
+iMC	0xB5	0xD	UNC_M_RD_CAS_RANK5.BANK13	RD_CAS Access to Rank 5; Bank 13	0,1,2,3	0	null	0
+iMC	0xB5	0xE	UNC_M_RD_CAS_RANK5.BANK14	RD_CAS Access to Rank 5; Bank 14	0,1,2,3	0	null	0
+iMC	0xB5	0xF	UNC_M_RD_CAS_RANK5.BANK15	RD_CAS Access to Rank 5; Bank 15	0,1,2,3	0	null	0
+iMC	0xB5	0x11	UNC_M_RD_CAS_RANK5.BANKG0	RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB5	0x12	UNC_M_RD_CAS_RANK5.BANKG1	RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB5	0x13	UNC_M_RD_CAS_RANK5.BANKG2	RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB5	0x14	UNC_M_RD_CAS_RANK5.BANKG3	RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB6	0x1	UNC_M_RD_CAS_RANK6.BANK1	RD_CAS Access to Rank 6; Bank 1	0,1,2,3	0	null	0
+iMC	0xB6	0x2	UNC_M_RD_CAS_RANK6.BANK2	RD_CAS Access to Rank 6; Bank 2	0,1,2,3	0	null	0
+iMC	0xB6	0x4	UNC_M_RD_CAS_RANK6.BANK4	RD_CAS Access to Rank 6; Bank 4	0,1,2,3	0	null	0
+iMC	0xB6	0x8	UNC_M_RD_CAS_RANK6.BANK8	RD_CAS Access to Rank 6; Bank 8	0,1,2,3	0	null	0
+iMC	0xB6	0x10	UNC_M_RD_CAS_RANK6.ALLBANKS	RD_CAS Access to Rank 6; All Banks	0,1,2,3	0	null	0
+iMC	0xB6	0x0	UNC_M_RD_CAS_RANK6.BANK0	RD_CAS Access to Rank 6; Bank 0	0,1,2,3	0	null	0
+iMC	0xB6	0x3	UNC_M_RD_CAS_RANK6.BANK3	RD_CAS Access to Rank 6; Bank 3	0,1,2,3	0	null	0
+iMC	0xB6	0x5	UNC_M_RD_CAS_RANK6.BANK5	RD_CAS Access to Rank 6; Bank 5	0,1,2,3	0	null	0
+iMC	0xB6	0x6	UNC_M_RD_CAS_RANK6.BANK6	RD_CAS Access to Rank 6; Bank 6	0,1,2,3	0	null	0
+iMC	0xB6	0x7	UNC_M_RD_CAS_RANK6.BANK7	RD_CAS Access to Rank 6; Bank 7	0,1,2,3	0	null	0
+iMC	0xB6	0x9	UNC_M_RD_CAS_RANK6.BANK9	RD_CAS Access to Rank 6; Bank 9	0,1,2,3	0	null	0
+iMC	0xB6	0xA	UNC_M_RD_CAS_RANK6.BANK10	RD_CAS Access to Rank 6; Bank 10	0,1,2,3	0	null	0
+iMC	0xB6	0xB	UNC_M_RD_CAS_RANK6.BANK11	RD_CAS Access to Rank 6; Bank 11	0,1,2,3	0	null	0
+iMC	0xB6	0xC	UNC_M_RD_CAS_RANK6.BANK12	RD_CAS Access to Rank 6; Bank 12	0,1,2,3	0	null	0
+iMC	0xB6	0xD	UNC_M_RD_CAS_RANK6.BANK13	RD_CAS Access to Rank 6; Bank 13	0,1,2,3	0	null	0
+iMC	0xB6	0xE	UNC_M_RD_CAS_RANK6.BANK14	RD_CAS Access to Rank 6; Bank 14	0,1,2,3	0	null	0
+iMC	0xB6	0xF	UNC_M_RD_CAS_RANK6.BANK15	RD_CAS Access to Rank 6; Bank 15	0,1,2,3	0	null	0
+iMC	0xB6	0x11	UNC_M_RD_CAS_RANK6.BANKG0	RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB6	0x12	UNC_M_RD_CAS_RANK6.BANKG1	RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB6	0x13	UNC_M_RD_CAS_RANK6.BANKG2	RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB6	0x14	UNC_M_RD_CAS_RANK6.BANKG3	RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB7	0x1	UNC_M_RD_CAS_RANK7.BANK1	RD_CAS Access to Rank 7; Bank 1	0,1,2,3	0	null	0
+iMC	0xB7	0x2	UNC_M_RD_CAS_RANK7.BANK2	RD_CAS Access to Rank 7; Bank 2	0,1,2,3	0	null	0
+iMC	0xB7	0x4	UNC_M_RD_CAS_RANK7.BANK4	RD_CAS Access to Rank 7; Bank 4	0,1,2,3	0	null	0
+iMC	0xB7	0x8	UNC_M_RD_CAS_RANK7.BANK8	RD_CAS Access to Rank 7; Bank 8	0,1,2,3	0	null	0
+iMC	0xB7	0x10	UNC_M_RD_CAS_RANK7.ALLBANKS	RD_CAS Access to Rank 7; All Banks	0,1,2,3	0	null	0
+iMC	0xB7	0x0	UNC_M_RD_CAS_RANK7.BANK0	RD_CAS Access to Rank 7; Bank 0	0,1,2,3	0	null	0
+iMC	0xB7	0x3	UNC_M_RD_CAS_RANK7.BANK3	RD_CAS Access to Rank 7; Bank 3	0,1,2,3	0	null	0
+iMC	0xB7	0x5	UNC_M_RD_CAS_RANK7.BANK5	RD_CAS Access to Rank 7; Bank 5	0,1,2,3	0	null	0
+iMC	0xB7	0x6	UNC_M_RD_CAS_RANK7.BANK6	RD_CAS Access to Rank 7; Bank 6	0,1,2,3	0	null	0
+iMC	0xB7	0x7	UNC_M_RD_CAS_RANK7.BANK7	RD_CAS Access to Rank 7; Bank 7	0,1,2,3	0	null	0
+iMC	0xB7	0x9	UNC_M_RD_CAS_RANK7.BANK9	RD_CAS Access to Rank 7; Bank 9	0,1,2,3	0	null	0
+iMC	0xB7	0xA	UNC_M_RD_CAS_RANK7.BANK10	RD_CAS Access to Rank 7; Bank 10	0,1,2,3	0	null	0
+iMC	0xB7	0xB	UNC_M_RD_CAS_RANK7.BANK11	RD_CAS Access to Rank 7; Bank 11	0,1,2,3	0	null	0
+iMC	0xB7	0xC	UNC_M_RD_CAS_RANK7.BANK12	RD_CAS Access to Rank 7; Bank 12	0,1,2,3	0	null	0
+iMC	0xB7	0xD	UNC_M_RD_CAS_RANK7.BANK13	RD_CAS Access to Rank 7; Bank 13	0,1,2,3	0	null	0
+iMC	0xB7	0xE	UNC_M_RD_CAS_RANK7.BANK14	RD_CAS Access to Rank 7; Bank 14	0,1,2,3	0	null	0
+iMC	0xB7	0xF	UNC_M_RD_CAS_RANK7.BANK15	RD_CAS Access to Rank 7; Bank 15	0,1,2,3	0	null	0
+iMC	0xB7	0x11	UNC_M_RD_CAS_RANK7.BANKG0	RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB7	0x12	UNC_M_RD_CAS_RANK7.BANKG1	RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB7	0x13	UNC_M_RD_CAS_RANK7.BANKG2	RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB7	0x14	UNC_M_RD_CAS_RANK7.BANKG3	RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0x11	0x0	UNC_M_RPQ_CYCLES_NE	Read Pending Queue Not Empty	0,1,2,3	0	null	0
+iMC	0x10	0x0	UNC_M_RPQ_INSERTS	Read Pending Queue Allocations	0,1,2,3	0	null	0
+iMC	0x91	0x0	UNC_M_VMSE_MXB_WR_OCCUPANCY	VMSE MXB write buffer occupancy	0,1,2,3	0	null	0
+iMC	0x90	0x1	UNC_M_VMSE_WR_PUSH.WMM	VMSE WR PUSH issued; VMSE write PUSH issued in WMM	0,1,2,3	0	null	0
+iMC	0x90	0x2	UNC_M_VMSE_WR_PUSH.RMM	VMSE WR PUSH issued; VMSE write PUSH issued in RMM	0,1,2,3	0	null	0
+iMC	0xC0	0x1	UNC_M_WMM_TO_RMM.LOW_THRESH	Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter	0,1,2,3	0	null	0
+iMC	0xC0	0x2	UNC_M_WMM_TO_RMM.STARVE	Transition from WMM to RMM because of low threshold	0,1,2,3	0	null	0
+iMC	0xC0	0x4	UNC_M_WMM_TO_RMM.VMSE_RETRY	Transition from WMM to RMM because of low threshold	0,1,2,3	0	null	0
+iMC	0x22	0x0	UNC_M_WPQ_CYCLES_FULL	Write Pending Queue Full Cycles	0,1,2,3	0	null	0
+iMC	0x21	0x0	UNC_M_WPQ_CYCLES_NE	Write Pending Queue Not Empty	0,1,2,3	0	null	0
+iMC	0x23	0x0	UNC_M_WPQ_READ_HIT	Write Pending Queue CAM Match	0,1,2,3	0	null	0
+iMC	0x24	0x0	UNC_M_WPQ_WRITE_HIT	Write Pending Queue CAM Match	0,1,2,3	0	null	0
+iMC	0xC1	0x0	UNC_M_WRONG_MM	Not getting the requested Major Mode	0,1,2,3	0	null	0
+iMC	0xB8	0x1	UNC_M_WR_CAS_RANK0.BANK1	WR_CAS Access to Rank 0; Bank 1	0,1,2,3	0	null	0
+iMC	0xB8	0x2	UNC_M_WR_CAS_RANK0.BANK2	WR_CAS Access to Rank 0; Bank 2	0,1,2,3	0	null	0
+iMC	0xB8	0x4	UNC_M_WR_CAS_RANK0.BANK4	WR_CAS Access to Rank 0; Bank 4	0,1,2,3	0	null	0
+iMC	0xB8	0x8	UNC_M_WR_CAS_RANK0.BANK8	WR_CAS Access to Rank 0; Bank 8	0,1,2,3	0	null	0
+iMC	0xB8	0x10	UNC_M_WR_CAS_RANK0.ALLBANKS	WR_CAS Access to Rank 0; All Banks	0,1,2,3	0	null	0
+iMC	0xB8	0x0	UNC_M_WR_CAS_RANK0.BANK0	WR_CAS Access to Rank 0; Bank 0	0,1,2,3	0	null	0
+iMC	0xB8	0x3	UNC_M_WR_CAS_RANK0.BANK3	WR_CAS Access to Rank 0; Bank 3	0,1,2,3	0	null	0
+iMC	0xB8	0x5	UNC_M_WR_CAS_RANK0.BANK5	WR_CAS Access to Rank 0; Bank 5	0,1,2,3	0	null	0
+iMC	0xB8	0x6	UNC_M_WR_CAS_RANK0.BANK6	WR_CAS Access to Rank 0; Bank 6	0,1,2,3	0	null	0
+iMC	0xB8	0x7	UNC_M_WR_CAS_RANK0.BANK7	WR_CAS Access to Rank 0; Bank 7	0,1,2,3	0	null	0
+iMC	0xB8	0x9	UNC_M_WR_CAS_RANK0.BANK9	WR_CAS Access to Rank 0; Bank 9	0,1,2,3	0	null	0
+iMC	0xB8	0xA	UNC_M_WR_CAS_RANK0.BANK10	WR_CAS Access to Rank 0; Bank 10	0,1,2,3	0	null	0
+iMC	0xB8	0xB	UNC_M_WR_CAS_RANK0.BANK11	WR_CAS Access to Rank 0; Bank 11	0,1,2,3	0	null	0
+iMC	0xB8	0xC	UNC_M_WR_CAS_RANK0.BANK12	WR_CAS Access to Rank 0; Bank 12	0,1,2,3	0	null	0
+iMC	0xB8	0xD	UNC_M_WR_CAS_RANK0.BANK13	WR_CAS Access to Rank 0; Bank 13	0,1,2,3	0	null	0
+iMC	0xB8	0xE	UNC_M_WR_CAS_RANK0.BANK14	WR_CAS Access to Rank 0; Bank 14	0,1,2,3	0	null	0
+iMC	0xB8	0xF	UNC_M_WR_CAS_RANK0.BANK15	WR_CAS Access to Rank 0; Bank 15	0,1,2,3	0	null	0
+iMC	0xB8	0x11	UNC_M_WR_CAS_RANK0.BANKG0	WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB8	0x12	UNC_M_WR_CAS_RANK0.BANKG1	WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB8	0x13	UNC_M_WR_CAS_RANK0.BANKG2	WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB8	0x14	UNC_M_WR_CAS_RANK0.BANKG3	WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB9	0x1	UNC_M_WR_CAS_RANK1.BANK1	WR_CAS Access to Rank 1; Bank 1	0,1,2,3	0	null	0
+iMC	0xB9	0x2	UNC_M_WR_CAS_RANK1.BANK2	WR_CAS Access to Rank 1; Bank 2	0,1,2,3	0	null	0
+iMC	0xB9	0x4	UNC_M_WR_CAS_RANK1.BANK4	WR_CAS Access to Rank 1; Bank 4	0,1,2,3	0	null	0
+iMC	0xB9	0x8	UNC_M_WR_CAS_RANK1.BANK8	WR_CAS Access to Rank 1; Bank 8	0,1,2,3	0	null	0
+iMC	0xB9	0x10	UNC_M_WR_CAS_RANK1.ALLBANKS	WR_CAS Access to Rank 1; All Banks	0,1,2,3	0	null	0
+iMC	0xB9	0x0	UNC_M_WR_CAS_RANK1.BANK0	WR_CAS Access to Rank 1; Bank 0	0,1,2,3	0	null	0
+iMC	0xB9	0x3	UNC_M_WR_CAS_RANK1.BANK3	WR_CAS Access to Rank 1; Bank 3	0,1,2,3	0	null	0
+iMC	0xB9	0x5	UNC_M_WR_CAS_RANK1.BANK5	WR_CAS Access to Rank 1; Bank 5	0,1,2,3	0	null	0
+iMC	0xB9	0x6	UNC_M_WR_CAS_RANK1.BANK6	WR_CAS Access to Rank 1; Bank 6	0,1,2,3	0	null	0
+iMC	0xB9	0x7	UNC_M_WR_CAS_RANK1.BANK7	WR_CAS Access to Rank 1; Bank 7	0,1,2,3	0	null	0
+iMC	0xB9	0x9	UNC_M_WR_CAS_RANK1.BANK9	WR_CAS Access to Rank 1; Bank 9	0,1,2,3	0	null	0
+iMC	0xB9	0xA	UNC_M_WR_CAS_RANK1.BANK10	WR_CAS Access to Rank 1; Bank 10	0,1,2,3	0	null	0
+iMC	0xB9	0xB	UNC_M_WR_CAS_RANK1.BANK11	WR_CAS Access to Rank 1; Bank 11	0,1,2,3	0	null	0
+iMC	0xB9	0xC	UNC_M_WR_CAS_RANK1.BANK12	WR_CAS Access to Rank 1; Bank 12	0,1,2,3	0	null	0
+iMC	0xB9	0xD	UNC_M_WR_CAS_RANK1.BANK13	WR_CAS Access to Rank 1; Bank 13	0,1,2,3	0	null	0
+iMC	0xB9	0xE	UNC_M_WR_CAS_RANK1.BANK14	WR_CAS Access to Rank 1; Bank 14	0,1,2,3	0	null	0
+iMC	0xB9	0xF	UNC_M_WR_CAS_RANK1.BANK15	WR_CAS Access to Rank 1; Bank 15	0,1,2,3	0	null	0
+iMC	0xB9	0x11	UNC_M_WR_CAS_RANK1.BANKG0	WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB9	0x12	UNC_M_WR_CAS_RANK1.BANKG1	WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB9	0x13	UNC_M_WR_CAS_RANK1.BANKG2	WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB9	0x14	UNC_M_WR_CAS_RANK1.BANKG3	WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xBC	0x1	UNC_M_WR_CAS_RANK4.BANK1	WR_CAS Access to Rank 4; Bank 1	0,1,2,3	0	null	0
+iMC	0xBC	0x2	UNC_M_WR_CAS_RANK4.BANK2	WR_CAS Access to Rank 4; Bank 2	0,1,2,3	0	null	0
+iMC	0xBC	0x4	UNC_M_WR_CAS_RANK4.BANK4	WR_CAS Access to Rank 4; Bank 4	0,1,2,3	0	null	0
+iMC	0xBC	0x8	UNC_M_WR_CAS_RANK4.BANK8	WR_CAS Access to Rank 4; Bank 8	0,1,2,3	0	null	0
+iMC	0xBC	0x10	UNC_M_WR_CAS_RANK4.ALLBANKS	WR_CAS Access to Rank 4; All Banks	0,1,2,3	0	null	0
+iMC	0xBC	0x0	UNC_M_WR_CAS_RANK4.BANK0	WR_CAS Access to Rank 4; Bank 0	0,1,2,3	0	null	0
+iMC	0xBC	0x3	UNC_M_WR_CAS_RANK4.BANK3	WR_CAS Access to Rank 4; Bank 3	0,1,2,3	0	null	0
+iMC	0xBC	0x5	UNC_M_WR_CAS_RANK4.BANK5	WR_CAS Access to Rank 4; Bank 5	0,1,2,3	0	null	0
+iMC	0xBC	0x6	UNC_M_WR_CAS_RANK4.BANK6	WR_CAS Access to Rank 4; Bank 6	0,1,2,3	0	null	0
+iMC	0xBC	0x7	UNC_M_WR_CAS_RANK4.BANK7	WR_CAS Access to Rank 4; Bank 7	0,1,2,3	0	null	0
+iMC	0xBC	0x9	UNC_M_WR_CAS_RANK4.BANK9	WR_CAS Access to Rank 4; Bank 9	0,1,2,3	0	null	0
+iMC	0xBC	0xA	UNC_M_WR_CAS_RANK4.BANK10	WR_CAS Access to Rank 4; Bank 10	0,1,2,3	0	null	0
+iMC	0xBC	0xB	UNC_M_WR_CAS_RANK4.BANK11	WR_CAS Access to Rank 4; Bank 11	0,1,2,3	0	null	0
+iMC	0xBC	0xC	UNC_M_WR_CAS_RANK4.BANK12	WR_CAS Access to Rank 4; Bank 12	0,1,2,3	0	null	0
+iMC	0xBC	0xD	UNC_M_WR_CAS_RANK4.BANK13	WR_CAS Access to Rank 4; Bank 13	0,1,2,3	0	null	0
+iMC	0xBC	0xE	UNC_M_WR_CAS_RANK4.BANK14	WR_CAS Access to Rank 4; Bank 14	0,1,2,3	0	null	0
+iMC	0xBC	0xF	UNC_M_WR_CAS_RANK4.BANK15	WR_CAS Access to Rank 4; Bank 15	0,1,2,3	0	null	0
+iMC	0xBC	0x11	UNC_M_WR_CAS_RANK4.BANKG0	WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xBC	0x12	UNC_M_WR_CAS_RANK4.BANKG1	WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xBC	0x13	UNC_M_WR_CAS_RANK4.BANKG2	WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xBC	0x14	UNC_M_WR_CAS_RANK4.BANKG3	WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xBD	0x1	UNC_M_WR_CAS_RANK5.BANK1	WR_CAS Access to Rank 5; Bank 1	0,1,2,3	0	null	0
+iMC	0xBD	0x2	UNC_M_WR_CAS_RANK5.BANK2	WR_CAS Access to Rank 5; Bank 2	0,1,2,3	0	null	0
+iMC	0xBD	0x4	UNC_M_WR_CAS_RANK5.BANK4	WR_CAS Access to Rank 5; Bank 4	0,1,2,3	0	null	0
+iMC	0xBD	0x8	UNC_M_WR_CAS_RANK5.BANK8	WR_CAS Access to Rank 5; Bank 8	0,1,2,3	0	null	0
+iMC	0xBD	0x10	UNC_M_WR_CAS_RANK5.ALLBANKS	WR_CAS Access to Rank 5; All Banks	0,1,2,3	0	null	0
+iMC	0xBD	0x0	UNC_M_WR_CAS_RANK5.BANK0	WR_CAS Access to Rank 5; Bank 0	0,1,2,3	0	null	0
+iMC	0xBD	0x3	UNC_M_WR_CAS_RANK5.BANK3	WR_CAS Access to Rank 5; Bank 3	0,1,2,3	0	null	0
+iMC	0xBD	0x5	UNC_M_WR_CAS_RANK5.BANK5	WR_CAS Access to Rank 5; Bank 5	0,1,2,3	0	null	0
+iMC	0xBD	0x6	UNC_M_WR_CAS_RANK5.BANK6	WR_CAS Access to Rank 5; Bank 6	0,1,2,3	0	null	0
+iMC	0xBD	0x7	UNC_M_WR_CAS_RANK5.BANK7	WR_CAS Access to Rank 5; Bank 7	0,1,2,3	0	null	0
+iMC	0xBD	0x9	UNC_M_WR_CAS_RANK5.BANK9	WR_CAS Access to Rank 5; Bank 9	0,1,2,3	0	null	0
+iMC	0xBD	0xA	UNC_M_WR_CAS_RANK5.BANK10	WR_CAS Access to Rank 5; Bank 10	0,1,2,3	0	null	0
+iMC	0xBD	0xB	UNC_M_WR_CAS_RANK5.BANK11	WR_CAS Access to Rank 5; Bank 11	0,1,2,3	0	null	0
+iMC	0xBD	0xC	UNC_M_WR_CAS_RANK5.BANK12	WR_CAS Access to Rank 5; Bank 12	0,1,2,3	0	null	0
+iMC	0xBD	0xD	UNC_M_WR_CAS_RANK5.BANK13	WR_CAS Access to Rank 5; Bank 13	0,1,2,3	0	null	0
+iMC	0xBD	0xE	UNC_M_WR_CAS_RANK5.BANK14	WR_CAS Access to Rank 5; Bank 14	0,1,2,3	0	null	0
+iMC	0xBD	0xF	UNC_M_WR_CAS_RANK5.BANK15	WR_CAS Access to Rank 5; Bank 15	0,1,2,3	0	null	0
+iMC	0xBD	0x11	UNC_M_WR_CAS_RANK5.BANKG0	WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xBD	0x12	UNC_M_WR_CAS_RANK5.BANKG1	WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xBD	0x13	UNC_M_WR_CAS_RANK5.BANKG2	WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xBD	0x14	UNC_M_WR_CAS_RANK5.BANKG3	WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xBE	0x1	UNC_M_WR_CAS_RANK6.BANK1	WR_CAS Access to Rank 6; Bank 1	0,1,2,3	0	null	0
+iMC	0xBE	0x2	UNC_M_WR_CAS_RANK6.BANK2	WR_CAS Access to Rank 6; Bank 2	0,1,2,3	0	null	0
+iMC	0xBE	0x4	UNC_M_WR_CAS_RANK6.BANK4	WR_CAS Access to Rank 6; Bank 4	0,1,2,3	0	null	0
+iMC	0xBE	0x8	UNC_M_WR_CAS_RANK6.BANK8	WR_CAS Access to Rank 6; Bank 8	0,1,2,3	0	null	0
+iMC	0xBE	0x10	UNC_M_WR_CAS_RANK6.ALLBANKS	WR_CAS Access to Rank 6; All Banks	0,1,2,3	0	null	0
+iMC	0xBE	0x0	UNC_M_WR_CAS_RANK6.BANK0	WR_CAS Access to Rank 6; Bank 0	0,1,2,3	0	null	0
+iMC	0xBE	0x3	UNC_M_WR_CAS_RANK6.BANK3	WR_CAS Access to Rank 6; Bank 3	0,1,2,3	0	null	0
+iMC	0xBE	0x5	UNC_M_WR_CAS_RANK6.BANK5	WR_CAS Access to Rank 6; Bank 5	0,1,2,3	0	null	0
+iMC	0xBE	0x6	UNC_M_WR_CAS_RANK6.BANK6	WR_CAS Access to Rank 6; Bank 6	0,1,2,3	0	null	0
+iMC	0xBE	0x7	UNC_M_WR_CAS_RANK6.BANK7	WR_CAS Access to Rank 6; Bank 7	0,1,2,3	0	null	0
+iMC	0xBE	0x9	UNC_M_WR_CAS_RANK6.BANK9	WR_CAS Access to Rank 6; Bank 9	0,1,2,3	0	null	0
+iMC	0xBE	0xA	UNC_M_WR_CAS_RANK6.BANK10	WR_CAS Access to Rank 6; Bank 10	0,1,2,3	0	null	0
+iMC	0xBE	0xB	UNC_M_WR_CAS_RANK6.BANK11	WR_CAS Access to Rank 6; Bank 11	0,1,2,3	0	null	0
+iMC	0xBE	0xC	UNC_M_WR_CAS_RANK6.BANK12	WR_CAS Access to Rank 6; Bank 12	0,1,2,3	0	null	0
+iMC	0xBE	0xD	UNC_M_WR_CAS_RANK6.BANK13	WR_CAS Access to Rank 6; Bank 13	0,1,2,3	0	null	0
+iMC	0xBE	0xE	UNC_M_WR_CAS_RANK6.BANK14	WR_CAS Access to Rank 6; Bank 14	0,1,2,3	0	null	0
+iMC	0xBE	0xF	UNC_M_WR_CAS_RANK6.BANK15	WR_CAS Access to Rank 6; Bank 15	0,1,2,3	0	null	0
+iMC	0xBE	0x11	UNC_M_WR_CAS_RANK6.BANKG0	WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xBE	0x12	UNC_M_WR_CAS_RANK6.BANKG1	WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xBE	0x13	UNC_M_WR_CAS_RANK6.BANKG2	WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xBE	0x14	UNC_M_WR_CAS_RANK6.BANKG3	WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xBF	0x1	UNC_M_WR_CAS_RANK7.BANK1	WR_CAS Access to Rank 7; Bank 1	0,1,2,3	0	null	0
+iMC	0xBF	0x2	UNC_M_WR_CAS_RANK7.BANK2	WR_CAS Access to Rank 7; Bank 2	0,1,2,3	0	null	0
+iMC	0xBF	0x4	UNC_M_WR_CAS_RANK7.BANK4	WR_CAS Access to Rank 7; Bank 4	0,1,2,3	0	null	0
+iMC	0xBF	0x8	UNC_M_WR_CAS_RANK7.BANK8	WR_CAS Access to Rank 7; Bank 8	0,1,2,3	0	null	0
+iMC	0xBF	0x10	UNC_M_WR_CAS_RANK7.ALLBANKS	WR_CAS Access to Rank 7; All Banks	0,1,2,3	0	null	0
+iMC	0xBF	0x0	UNC_M_WR_CAS_RANK7.BANK0	WR_CAS Access to Rank 7; Bank 0	0,1,2,3	0	null	0
+iMC	0xBF	0x3	UNC_M_WR_CAS_RANK7.BANK3	WR_CAS Access to Rank 7; Bank 3	0,1,2,3	0	null	0
+iMC	0xBF	0x5	UNC_M_WR_CAS_RANK7.BANK5	WR_CAS Access to Rank 7; Bank 5	0,1,2,3	0	null	0
+iMC	0xBF	0x6	UNC_M_WR_CAS_RANK7.BANK6	WR_CAS Access to Rank 7; Bank 6	0,1,2,3	0	null	0
+iMC	0xBF	0x7	UNC_M_WR_CAS_RANK7.BANK7	WR_CAS Access to Rank 7; Bank 7	0,1,2,3	0	null	0
+iMC	0xBF	0x9	UNC_M_WR_CAS_RANK7.BANK9	WR_CAS Access to Rank 7; Bank 9	0,1,2,3	0	null	0
+iMC	0xBF	0xA	UNC_M_WR_CAS_RANK7.BANK10	WR_CAS Access to Rank 7; Bank 10	0,1,2,3	0	null	0
+iMC	0xBF	0xB	UNC_M_WR_CAS_RANK7.BANK11	WR_CAS Access to Rank 7; Bank 11	0,1,2,3	0	null	0
+iMC	0xBF	0xC	UNC_M_WR_CAS_RANK7.BANK12	WR_CAS Access to Rank 7; Bank 12	0,1,2,3	0	null	0
+iMC	0xBF	0xD	UNC_M_WR_CAS_RANK7.BANK13	WR_CAS Access to Rank 7; Bank 13	0,1,2,3	0	null	0
+iMC	0xBF	0xE	UNC_M_WR_CAS_RANK7.BANK14	WR_CAS Access to Rank 7; Bank 14	0,1,2,3	0	null	0
+iMC	0xBF	0xF	UNC_M_WR_CAS_RANK7.BANK15	WR_CAS Access to Rank 7; Bank 15	0,1,2,3	0	null	0
+iMC	0xBF	0x11	UNC_M_WR_CAS_RANK7.BANKG0	WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xBF	0x12	UNC_M_WR_CAS_RANK7.BANKG1	WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xBF	0x13	UNC_M_WR_CAS_RANK7.BANKG2	WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xBF	0x14	UNC_M_WR_CAS_RANK7.BANKG3	WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
diff --git a/x86data/perfmon_data/BDW/Broadwell_FP_ARITH_INST_V11.json b/x86data/perfmon_data/BDW/Broadwell_FP_ARITH_INST_V11.json
new file mode 100644
index 0000000..f896a9d
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_FP_ARITH_INST_V11.json
@@ -0,0 +1,38 @@
+[
+  {
+    "BitName": "SCALAR_DOUBLE",
+    "BitIndex": 0,
+    "FlopsMultiplier": 1,
+    "Description": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "SCALAR_SINGLE",
+    "BitIndex": 1,
+    "FlopsMultiplier": 1,
+    "Description": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "128BIT_PACKED_DOUBLE",
+    "BitIndex": 2,
+    "FlopsMultiplier": 2,
+    "Description": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "128BIT_PACKED_SINGLE",
+    "BitIndex": 3,
+    "FlopsMultiplier": 4,
+    "Description": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "256BIT_PACKED_DOUBLE",
+    "BitIndex": 4,
+    "FlopsMultiplier": 4,
+    "Description": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "256BIT_PACKED_SINGLE",
+    "BitIndex": 5,
+    "FlopsMultiplier": 8,
+    "Description": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/BDW/Broadwell_FP_ARITH_INST_V11.tsv b/x86data/perfmon_data/BDW/Broadwell_FP_ARITH_INST_V11.tsv
new file mode 100644
index 0000000..fb2c181
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_FP_ARITH_INST_V11.tsv
@@ -0,0 +1,10 @@
+# Performance Monitoring Events for the Fifth Generation Intel Core Processors Based on the Broadwell Microarchitecture - V11
+# 7/22/2015 2:19:57 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	FlopsMultiplier	Description
+SCALAR_DOUBLE	0	1	Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+SCALAR_SINGLE	1	1	Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+128BIT_PACKED_DOUBLE	2	2	Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+128BIT_PACKED_SINGLE	3	4	Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+256BIT_PACKED_DOUBLE	4	4	Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+256BIT_PACKED_SINGLE	5	8	Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
diff --git a/x86data/perfmon_data/BDW/Broadwell_core_V11.json b/x86data/perfmon_data/BDW/Broadwell_core_V11.json
new file mode 100644
index 0000000..22e5c82
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_core_V11.json
@@ -0,0 +1,15864 @@
+[

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired from execution.",

+    "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions...",

+    "Counter": "Fixed counter 1",

+    "CounterHTOff": "Fixed counter 1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Core cycles when the thread is not in halt state",

+    "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events...",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Reference cycles when the core is not in halt state.",

+    "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case....",

+    "Counter": "Fixed counter 3",

+    "CounterHTOff": "Fixed counter 3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "LD_BLOCKS.STORE_FORWARD",

+    "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",

+    "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS.NO_SR",

+    "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "PublicDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "MISALIGN_MEM_REF.LOADS",

+    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "MISALIGN_MEM_REF.STORES",

+    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies in MOB due to partial compare",

+    "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x01",

+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Load misses in all DTLB levels that cause page walks",

+    "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x02",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",

+    "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x08",

+    "EventName": "INT_MISC.RAT_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",

+    "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES",

+    "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x10",

+    "EventName": "UOPS_ISSUED.FLAGS_MERGE",

+    "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",

+    "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x20",

+    "EventName": "UOPS_ISSUED.SLOW_LEA",

+    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x40",

+    "EventName": "UOPS_ISSUED.SINGLE_MUL",

+    "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "PublicDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x01",

+    "EventName": "ARITH.FPU_DIV_ACTIVE",

+    "BriefDescription": "Cycles when divider is busy executing divide operations",

+    "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x21",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",

+    "BriefDescription": "Demand Data Read miss L2, no rejects",

+    "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x41",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",

+    "BriefDescription": "Demand Data Read requests that hit L2 cache",

+    "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.L2_PF_MISS",

+    "BriefDescription": "L2 prefetch requests that miss L2 cache",

+    "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x50",

+    "EventName": "L2_RQSTS.L2_PF_HIT",

+    "BriefDescription": "L2 prefetch requests that hit L2 cache",

+    "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE1",

+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests",

+    "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE2",

+    "EventName": "L2_RQSTS.ALL_RFO",

+    "BriefDescription": "RFO requests to L2 cache",

+    "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE4",

+    "EventName": "L2_RQSTS.ALL_CODE_RD",

+    "BriefDescription": "L2 code requests",

+    "PublicDescription": "This event counts the total number of L2 code requests.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xF8",

+    "EventName": "L2_RQSTS.ALL_PF",

+    "BriefDescription": "Requests from L2 hardware prefetchers",

+    "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x50",

+    "EventName": "L2_DEMAND_RQSTS.WB_HIT",

+    "BriefDescription": "Not rejected writebacks that hit L2 cache",

+    "PublicDescription": "This event counts the number of WB requests that hit L2 cache. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2e",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Core-originated cacheable demand requests missed L3",

+    "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2e",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Core-originated cacheable demand requests that refer to L3",

+    "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",

+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",

+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",

+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING",

+    "BriefDescription": "L1D miss oustandings duration in cycles",

+    "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",

+    "BriefDescription": "Cycles with L1D load Misses outstanding.",

+    "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x01",

+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",

+    "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x02",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",

+    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x20",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4c",

+    "UMask": "0x02",

+    "EventName": "LOAD_HIT_PRE.HW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4f",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Cycle count for an Extended Page table walk.",

+    "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x01",

+    "EventName": "L1D.REPLACEMENT",

+    "BriefDescription": "L1D data line replacements",

+    "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x01",

+    "EventName": "TX_MEM.ABORT_CONFLICT",

+    "BriefDescription": "Number of times a TSX line had a cache conflict",

+    "PublicDescription": "Number of times a TSX line had a cache conflict",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x02",

+    "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",

+    "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",

+    "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x04",

+    "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",

+    "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",

+    "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x08",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",

+    "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",

+    "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x10",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",

+    "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",

+    "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x20",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",

+    "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",

+    "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x40",

+    "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",

+    "BriefDescription": "Number of times we could not allocate Lock Buffer",

+    "PublicDescription": "Number of times we could not allocate Lock Buffer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x01",

+    "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x02",

+    "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x04",

+    "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x08",

+    "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0",

+    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

+    "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x02",

+    "EventName": "CPL_CYCLES.RING123",

+    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0_TRANS",

+    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x01",

+    "EventName": "TX_EXEC.MISC1",

+    "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",

+    "PublicDescription": "Unfriendly TSX abort triggered by  a flowmarker",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x02",

+    "EventName": "TX_EXEC.MISC2",

+    "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",

+    "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x04",

+    "EventName": "TX_EXEC.MISC3",

+    "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",

+    "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x08",

+    "EventName": "TX_EXEC.MISC4",

+    "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",

+    "PublicDescription": "RTM region detected inside HLE",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x10",

+    "EventName": "TX_EXEC.MISC5",

+    "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",

+    "PublicDescription": "# HLE inside HLE+",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_CYCLES",

+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",

+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",

+    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x01",

+    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x02",

+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1D is locked",

+    "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x02",

+    "EventName": "IDQ.EMPTY",

+    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_UOPS",

+    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x20",

+    "EventName": "IDQ.MS_MITE_UOPS",

+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_CYCLES",

+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_OCCUR",

+    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "PublicDescription": "This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "PublicDescription": "This event counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles MITE is delivering 4 Uops",

+    "PublicDescription": "This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles MITE is delivering any Uop",

+    "PublicDescription": "This event counts the number of cycles  uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x3c",

+    "EventName": "IDQ.MITE_ALL_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x01",

+    "EventName": "ICACHE.HIT",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x02",

+    "EventName": "ICACHE.MISSES",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",

+    "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x04",

+    "EventName": "ICACHE.IFDATA_STALL",

+    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x01",

+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Misses at all ITLB levels that cause page walks",

+    "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x02",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",

+    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x10",

+    "EventName": "ITLB_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x01",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

+    "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x41",

+    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken macro-conditional branches",

+    "PublicDescription": "This event counts not taken macro-conditional branch instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x81",

+    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired macro-conditional branches",

+    "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x82",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",

+    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x84",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x88",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x90",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired direct near calls",

+    "PublicDescription": "This event counts taken speculative and retired direct near calls.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xA0",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired indirect calls",

+    "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC1",

+    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired macro-conditional branches",

+    "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC2",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",

+    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC4",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC8",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Speculative and retired indirect return branches.",

+    "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xD0",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired direct near calls",

+    "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xFF",

+    "EventName": "BR_INST_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired  branches",

+    "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x41",

+    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x81",

+    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x84",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC1",

+    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC4",

+    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xFF",

+    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9c",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",

+    "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is  delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are executed in port 0",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are executed in port 1",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when uops are executed in port 2",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when uops are executed in port 3",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are executed in port 4",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are executed in port 5",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_6",

+    "BriefDescription": "Cycles per thread when uops are executed in port 6",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_7",

+    "BriefDescription": "Cycles per thread when uops are executed in port 7",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x01",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource-related stall cycles",

+    "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x04",

+    "EventName": "RESOURCE_STALLS.RS",

+    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",

+    "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x08",

+    "EventName": "RESOURCE_STALLS.SB",

+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB",

+    "BriefDescription": "Cycles stalled due to re-order buffer full.",

+    "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",

+    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",

+    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand* load request missing the L2 cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",

+    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand load request missing the L1 data cache.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",

+    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",

+    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand load request (that is cycles with non-completed load waiting for its data from memory subsystem)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",

+    "BriefDescription": "Total execution stalls",

+    "PublicDescription": "Counts number of cycles nothing is executed on any execution port.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",

+    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",

+    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.\r\n\r\n(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",

+    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",

+    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xa8",

+    "UMask": "0x01",

+    "EventName": "LSD.UOPS",

+    "BriefDescription": "Number of Uops delivered by the LSD. Read more on LSD under LSD_REPLAY.REPLAY",

+    "PublicDescription": "Number of Uops delivered by the LSD. Read more on LSD under LSD_REPLAY.REPLAY",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x02",

+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

+    "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xae",

+    "UMask": "0x01",

+    "EventName": "ITLB.ITLB_FLUSH",

+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests sent to uncore",

+    "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

+    "BriefDescription": "Cacheable and noncachaeble code read requests",

+    "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",

+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",

+    "BriefDescription": "Demand and prefetch data reads",

+    "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable \"Demands\" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.THREAD",

+    "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",

+    "PublicDescription": "Number of uops to be executed per-thread each cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE",

+    "BriefDescription": "Number of uops executed on the core.",

+    "PublicDescription": "Number of uops executed from any thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.STALL_CYCLES",

+    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb2",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",

+    "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",

+    "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x11",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L1",

+    "BriefDescription": "Number of DTLB page walker hits in the L1+FB",

+    "PublicDescription": "Number of DTLB page walker hits in the L1+FB",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x21",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L1",

+    "BriefDescription": "Number of ITLB page walker hits in the L1+FB",

+    "PublicDescription": "Number of ITLB page walker hits in the L1+FB",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x12",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L2",

+    "BriefDescription": "Number of DTLB page walker hits in the L2",

+    "PublicDescription": "Number of DTLB page walker hits in the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x22",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L2",

+    "BriefDescription": "Number of ITLB page walker hits in the L2",

+    "PublicDescription": "Number of ITLB page walker hits in the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x14",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L3",

+    "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",

+    "PublicDescription": "Number of DTLB page walker hits in the L3 + XSNP",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x24",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L3",

+    "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",

+    "PublicDescription": "Number of ITLB page walker hits in the L3 + XSNP",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x18",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",

+    "BriefDescription": "Number of DTLB page walker hits in Memory",

+    "PublicDescription": "Number of DTLB page walker hits in Memory",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",

+    "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x02",

+    "EventName": "INST_RETIRED.X87",

+    "BriefDescription": "FP operations  retired. X87 FP operations that have no exceptions:",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.PREC_DIST",

+    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.",

+    "Counter": "1",

+    "CounterHTOff": "1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x08",

+    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

+    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x10",

+    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

+    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x40",

+    "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",

+    "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "PublicDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.ALL",

+    "BriefDescription": "Actually retired uops.",

+    "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x02",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Cycles with less than 10 actually retired uops.",

+    "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.  ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "10",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.CYCLES",

+    "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",

+    "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-modifying code (SMC) detected.",

+    "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x20",

+    "EventName": "MACHINE_CLEARS.MASKMOV",

+    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",

+    "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x01",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Conditional branch instructions retired.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x02",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect near call instructions retired.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All (macro) branch instructions retired.",

+    "PublicDescription": "This event counts all (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x08",

+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",

+    "BriefDescription": "Return instructions retired.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x10",

+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Not taken branch instructions retired.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x20",

+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "Taken branch instructions retired.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x40",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Far branch instructions retired.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x04",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",

+    "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x01",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional branch instructions retired.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All mispredicted macro branch instructions retired.",

+    "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x08",

+    "EventName": "BR_MISP_RETIRED.RET",

+    "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x04",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",

+    "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x01",

+    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

+    "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",

+    "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x02",

+    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

+    "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x04",

+    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

+    "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ",

+    "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x08",

+    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

+    "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",

+    "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x10",

+    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

+    "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",

+    "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x01",

+    "EventName": "HLE_RETIRED.START",

+    "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",

+    "PublicDescription": "Number of times we entered an HLE region; does not count nested transactions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x02",

+    "EventName": "HLE_RETIRED.COMMIT",

+    "BriefDescription": "Number of times HLE commit succeeded",

+    "PublicDescription": "Number of times HLE commit succeeded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x04",

+    "EventName": "HLE_RETIRED.ABORTED",

+    "BriefDescription": "Number of times HLE abort was triggered",

+    "PublicDescription": "Number of times HLE abort was triggered",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x08",

+    "EventName": "HLE_RETIRED.ABORTED_MISC1",

+    "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x10",

+    "EventName": "HLE_RETIRED.ABORTED_MISC2",

+    "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",

+    "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x20",

+    "EventName": "HLE_RETIRED.ABORTED_MISC3",

+    "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",

+    "PublicDescription": "Number of times a disallowed operation caused an HLE abort",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x40",

+    "EventName": "HLE_RETIRED.ABORTED_MISC4",

+    "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",

+    "PublicDescription": "Number of times HLE caused a fault",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x80",

+    "EventName": "HLE_RETIRED.ABORTED_MISC5",

+    "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",

+    "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x01",

+    "EventName": "RTM_RETIRED.START",

+    "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",

+    "PublicDescription": "Number of times we entered an RTM region; does not count nested transactions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x02",

+    "EventName": "RTM_RETIRED.COMMIT",

+    "BriefDescription": "Number of times RTM commit succeeded",

+    "PublicDescription": "Number of times RTM commit succeeded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x04",

+    "EventName": "RTM_RETIRED.ABORTED",

+    "BriefDescription": "Number of times RTM abort was triggered",

+    "PublicDescription": "Number of times RTM abort was triggered ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x08",

+    "EventName": "RTM_RETIRED.ABORTED_MISC1",

+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",

+    "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x10",

+    "EventName": "RTM_RETIRED.ABORTED_MISC2",

+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x20",

+    "EventName": "RTM_RETIRED.ABORTED_MISC3",

+    "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",

+    "PublicDescription": "Number of times a disallowed operation caused an RTM abort",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x40",

+    "EventName": "RTM_RETIRED.ABORTED_MISC4",

+    "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",

+    "PublicDescription": "Number of times a RTM caused a fault",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x80",

+    "EventName": "RTM_RETIRED.ABORTED_MISC5",

+    "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",

+    "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x02",

+    "EventName": "FP_ASSIST.X87_OUTPUT",

+    "BriefDescription": "Number of X87 assists due to output value.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x04",

+    "EventName": "FP_ASSIST.X87_INPUT",

+    "BriefDescription": "Number of X87 assists due to input value.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x08",

+    "EventName": "FP_ASSIST.SIMD_OUTPUT",

+    "BriefDescription": "Number of SIMD FP assists due to Output values",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x10",

+    "EventName": "FP_ASSIST.SIMD_INPUT",

+    "BriefDescription": "Number of SIMD FP assists due to input values",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x1E",

+    "EventName": "FP_ASSIST.ANY",

+    "BriefDescription": "Cycles with any input/output SSE or FP assist",

+    "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x20",

+    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",

+    "BriefDescription": "Count cases of saving new LBR",

+    "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

+    "BriefDescription": "Loads with latency value being above 4",

+    "PublicDescription": "This event counts loads with latency value being above four.",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

+    "BriefDescription": "Loads with latency value being above 8",

+    "PublicDescription": "This event counts loads with latency value being above eight.",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

+    "BriefDescription": "Loads with latency value being above 16",

+    "PublicDescription": "This event counts loads with latency value being above 16.",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

+    "BriefDescription": "Loads with latency value being above 32",

+    "PublicDescription": "This event counts loads with latency value being above 32.",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

+    "BriefDescription": "Loads with latency value being above 64",

+    "PublicDescription": "This event counts loads with latency value being above 64.",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

+    "BriefDescription": "Loads with latency value being above 128",

+    "PublicDescription": "This event counts loads with latency value being above 128.",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "1009",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

+    "BriefDescription": "Loads with latency value being above 256",

+    "PublicDescription": "This event counts loads with latency value being above 256.",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "503",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

+    "BriefDescription": "Loads with latency value being above 512",

+    "PublicDescription": "This event counts loads with latency value being above 512.",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "101",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x11",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",

+    "BriefDescription": "Retired load uops that miss the STLB.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x12",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",

+    "BriefDescription": "Retired store uops that miss the STLB.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x21",

+    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",

+    "BriefDescription": "Retired load uops with locked access.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with locked access retired to the architected path.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x41",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",

+    "BriefDescription": "Retired load uops that split across a cacheline boundary.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x42",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",

+    "BriefDescription": "Retired store uops that split across a cacheline boundary.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x81",

+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

+    "BriefDescription": "All retired load uops.",

+    "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x82",

+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

+    "BriefDescription": "All retired store uops.",

+    "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",

+    "BriefDescription": "Retired load uops with L1 cache hits as data sources.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

+    "BriefDescription": "Retired load uops with L2 cache hits as data sources.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",

+    "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",

+    "BriefDescription": "Retired load uops misses in L1 cache as data sources.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",

+    "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",

+    "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",

+    "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",

+    "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",

+    "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3). ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",

+    "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",

+    "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Thread cycles when thread is not in halt state",

+    "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x01",

+    "EventName": "L2_TRANS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests that access L2 cache",

+    "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x02",

+    "EventName": "L2_TRANS.RFO",

+    "BriefDescription": "RFO requests that access L2 cache",

+    "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x04",

+    "EventName": "L2_TRANS.CODE_RD",

+    "BriefDescription": "L2 cache accesses when fetching instructions",

+    "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x08",

+    "EventName": "L2_TRANS.ALL_PF",

+    "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",

+    "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANS.L1D_WB",

+    "BriefDescription": "L1D writebacks that access L2 cache",

+    "PublicDescription": "This event counts L1D writebacks that access L2 cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANS.L2_FILL",

+    "BriefDescription": "L2 fill requests that access L2 cache",

+    "PublicDescription": "This event counts L2 fill requests that access L2 cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANS.L2_WB",

+    "BriefDescription": "L2 writebacks that access L2 cache",

+    "PublicDescription": "This event counts L2 writebacks that access L2 cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANS.ALL_REQUESTS",

+    "BriefDescription": "Transactions accessing L2 pipe",

+    "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_IN.I",

+    "BriefDescription": "L2 cache lines in I state filling L2",

+    "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_IN.S",

+    "BriefDescription": "L2 cache lines in S state filling L2",

+    "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_IN.E",

+    "BriefDescription": "L2 cache lines in E state filling L2",

+    "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x07",

+    "EventName": "L2_LINES_IN.ALL",

+    "BriefDescription": "L2 cache lines filling L2",

+    "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x05",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by demand",

+    "PublicDescription": "Clean L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xA0",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect calls",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 0",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 1",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 2",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 3",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 4",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 5",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 6",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 7",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 7",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",

+    "PublicDescription": "number of near branch instructions retired that were mispredicted and taken.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x0e",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x60",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x42",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "RFO requests that hit L2 cache",

+    "PublicDescription": "RFO requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x22",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "RFO requests that miss L2 cache",

+    "PublicDescription": "RFO requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x44",

+    "EventName": "L2_RQSTS.CODE_RD_HIT",

+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",

+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x24",

+    "EventName": "L2_RQSTS.CODE_RD_MISS",

+    "BriefDescription": "L2 cache misses when fetching instructions",

+    "PublicDescription": "L2 cache misses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x27",

+    "EventName": "L2_RQSTS.ALL_DEMAND_MISS",

+    "BriefDescription": "Demand requests that miss L2 cache",

+    "PublicDescription": "Demand requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xe7",

+    "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",

+    "BriefDescription": "Demand requests to L2 cache",

+    "PublicDescription": "Demand requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3F",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All requests that miss L2 cache",

+    "PublicDescription": "All requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "PublicDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x0e",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x60",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",

+    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x0e",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Misses in all ITLB levels that cause completed page walks",

+    "PublicDescription": "Misses in all ITLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x60",

+    "EventName": "ITLB_MISSES.STLB_HIT",

+    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",

+    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",

+    "PublicDescription": "Cycles where at least 1 uop was executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 2 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 3 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 4 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xe6",

+    "UMask": "0x1f",

+    "EventName": "BACLEARS.ANY",

+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE",

+    "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc7",

+    "UMask": "0x20",

+    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

+    "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_SWITCHES",

+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",

+    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",

+    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",

+    "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",

+    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",

+    "PublicDescription": "Cycles while memory subsystem has an outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",

+    "BriefDescription": "Total execution stalls.",

+    "PublicDescription": "Total execution stalls.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",

+    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",

+    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",

+    "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",

+    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.COUNT",

+    "BriefDescription": "Number of machine clears (nukes) of any type.",

+    "PublicDescription": "Number of machine clears (nukes) of any type.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_4_UOPS",

+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_END",

+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_ACTIVE",

+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are executed in port 0",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are executed in port 1",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when uops are executed in port 2",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when uops are executed in port 3",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are executed in port 4",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are executed in port 5",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_6",

+    "BriefDescription": "Cycles per thread when uops are executed in port 6",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_7",

+    "BriefDescription": "Cycles per thread when uops are executed in port 7",

+    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA0",

+    "UMask": "0x03",

+    "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",

+    "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",

+    "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more information.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x03",

+    "EventName": "FP_ARITH_INST_RETIRED.SCALAR",

+    "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "PublicDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x3C",

+    "EventName": "FP_ARITH_INST_RETIRED.PACKED",

+    "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",

+    "PublicDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000004",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x15",

+    "EventName": "FP_ARITH_INST_RETIRED.SINGLE",

+    "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?",

+    "PublicDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000005",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x2A",

+    "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",

+    "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?",

+    "PublicDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000006",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",

+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",

+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",

+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",

+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",

+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",

+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",

+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",

+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.FB_FULL",

+    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts demand data reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts demand data reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand data reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts demand data reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts demand data reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts demand data reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all demand code reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all demand code reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all demand code reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts writebacks (modified to exclusive) that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000008 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000010 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000020 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000040 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000200 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",

+    "BriefDescription": "Counts any other requests that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000018000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts any other requests that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts any other requests that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts any other requests that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts any other requests that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts any other requests that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts any other requests that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch data reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch data reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch data reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all prefetch data reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch data reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch data reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000090 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch RFOs that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts prefetch RFOs that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch RFOs that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts prefetch RFOs that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts prefetch RFOs that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch RFOs that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000120 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch code reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch code reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch code reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all prefetch code reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all prefetch code reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all prefetch code reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch code reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000240 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000091 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f80020122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00803c0122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01003c0122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02003c0122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the target was non-DRAM system address.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20003c0122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f84000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 with no details on snoop-related information.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 with a snoop miss response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000122 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/BDW/Broadwell_core_V11.tsv b/x86data/perfmon_data/BDW/Broadwell_core_V11.tsv
new file mode 100644
index 0000000..ab8ff83
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_core_V11.tsv
@@ -0,0 +1,323 @@
+# Performance Monitoring Events for the Fifth Generation Intel Core Processors Based on the Broadwell Microarchitecture - V11
+# 7/22/2015 2:19:56 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	Cases when loads get true Block-on-Store blocking code preventing store forwarding	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x03	0x08	LD_BLOCKS.NO_SR	This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x01	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Load misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x10	DTLB_LOAD_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x20	DTLB_LOAD_MISSES.STLB_HIT_4K	Load misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0D	0x08	INT_MISC.RAT_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x10	UOPS_ISSUED.FLAGS_MERGE	Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x20	UOPS_ISSUED.SLOW_LEA	Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x40	UOPS_ISSUED.SINGLE_MUL	Number of Multiply packed/scalar single precision uops allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null
+0x14	0x01	ARITH.FPU_DIV_ACTIVE	Cycles when divider is busy executing divide operations	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x21	L2_RQSTS.DEMAND_DATA_RD_MISS	Demand Data Read miss L2, no rejects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x41	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x30	L2_RQSTS.L2_PF_MISS	L2 prefetch requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x50	L2_RQSTS.L2_PF_HIT	L2 prefetch requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE1	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE2	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE4	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xF8	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x27	0x50	L2_DEMAND_RQSTS.WB_HIT	Not rejected writebacks that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x2e	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x2e	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x3c	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x3c	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other thread is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	2	2	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding.	2	2	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Store miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x10	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x20	DTLB_STORE_MISSES.STLB_HIT_4K	Store misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x4c	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x4f	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x01	TX_MEM.ABORT_CONFLICT	Number of times a TSX line had a cache conflict	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x02	TX_MEM.ABORT_CAPACITY_WRITE	Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x04	TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK	Number of times a TSX Abort was triggered due to a non-release/commit store to lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x08	TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY	Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x10	TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH	Number of times a TSX Abort was triggered due to release/commit but data and address mismatch	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x20	TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT	Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x40	TX_MEM.HLE_ELISION_BUFFER_FULL	Number of times we could not allocate Lock Buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x58	0x01	MOVE_ELIMINATION.INT_ELIMINATED	Number of integer Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null
+0x58	0x02	MOVE_ELIMINATION.SIMD_ELIMINATED	Number of SIMD Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null
+0x58	0x04	MOVE_ELIMINATION.INT_NOT_ELIMINATED	Number of integer Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null
+0x58	0x08	MOVE_ELIMINATION.SIMD_NOT_ELIMINATED	Number of SIMD Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	1	0	0	1	0	0	0	null
+0x5d	0x01	TX_EXEC.MISC1	Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x02	TX_EXEC.MISC2	Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x04	TX_EXEC.MISC3	Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x08	TX_EXEC.MISC4	Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x10	TX_EXEC.MISC5	Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x80	0x02	ICACHE.MISSES	Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x80	0x04	ICACHE.IFDATA_STALL	Cycles where a code fetch is stalled due to L1 instruction-cache miss.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x02	ITLB_MISSES.WALK_COMPLETED_4K	Code miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x10	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x20	ITLB_MISSES.STLB_HIT_4K	Core misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x9c	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x04	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x08	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x10	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x20	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Cycles while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Cycles while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	8	0	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_LDM_PENDING	Cycles while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_EXECUTE	Total execution stalls	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Execution stalls while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_LDM_PENDING	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3	2000003	0	0	0	6	0	0	0	0	0	0	null
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Execution stalls while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	12	0	0	0	0	0	0	null
+0xa8	0x01	LSD.UOPS	Number of Uops delivered by the LSD. Read more on LSD under LSD_REPLAY.REPLAY	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xae	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0	null
+0xb0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb1	0x01	UOPS_EXECUTED.THREAD	Counts the number of uops to be executed per-thread each cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE	Number of uops executed on the core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.STALL_CYCLES	Counts number of cycles no uops were dispatched to be executed on this thread.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xb2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Offcore requests buffer cannot take more entries for this thread core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x11	PAGE_WALKER_LOADS.DTLB_L1	Number of DTLB page walker hits in the L1+FB	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x21	PAGE_WALKER_LOADS.ITLB_L1	Number of ITLB page walker hits in the L1+FB	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x12	PAGE_WALKER_LOADS.DTLB_L2	Number of DTLB page walker hits in the L2	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x22	PAGE_WALKER_LOADS.ITLB_L2	Number of ITLB page walker hits in the L2	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x14	PAGE_WALKER_LOADS.DTLB_L3	Number of DTLB page walker hits in the L3 + XSNP	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x24	PAGE_WALKER_LOADS.ITLB_L3	Number of ITLB page walker hits in the L3 + XSNP	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x18	PAGE_WALKER_LOADS.DTLB_MEMORY	Number of DTLB page walker hits in Memory	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC0	0x02	INST_RETIRED.X87	FP operations  retired. X87 FP operations that have no exceptions:	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC0	0x01	INST_RETIRED.PREC_DIST	Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution	1	1	2000003	0	0	0	0	0	0	0	2	0	0	null
+0xC1	0x08	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC1	0x10	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC1	0x40	OTHER_ASSISTS.ANY_WB_ASSIST	Number of times any microcode assist is invoked by HW upon uop writeback.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	1	0	null
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	0	null
+0xC3	0x01	MACHINE_CLEARS.CYCLES	Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. (Precise Event - PEBS)	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3).	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC5	0x08	BR_MISP_RETIRED.RET	This event counts the number of mispredicted ret instructions retired. Non PEBS	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. (Precise Event - PEBS)	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null
+0xC7	0x01	FP_ARITH_INST_RETIRED.SCALAR_DOUBLE	Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xC7	0x02	FP_ARITH_INST_RETIRED.SCALAR_SINGLE	Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xC7	0x04	FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE	Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xC7	0x08	FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE	Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xC7	0x10	FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE	Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xc8	0x01	HLE_RETIRED.START	Number of times we entered an HLE region; does not count nested transactions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x02	HLE_RETIRED.COMMIT	Number of times HLE commit succeeded	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x04	HLE_RETIRED.ABORTED	Number of times HLE abort was triggered	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xc8	0x08	HLE_RETIRED.ABORTED_MISC1	Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x10	HLE_RETIRED.ABORTED_MISC2	Number of times an HLE execution aborted due to uncommon conditions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x20	HLE_RETIRED.ABORTED_MISC3	Number of times an HLE execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x40	HLE_RETIRED.ABORTED_MISC4	Number of times an HLE execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x80	HLE_RETIRED.ABORTED_MISC5	Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x01	RTM_RETIRED.START	Number of times we entered an RTM region; does not count nested transactions	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x02	RTM_RETIRED.COMMIT	Number of times RTM commit succeeded	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x04	RTM_RETIRED.ABORTED	Number of times RTM abort was triggered	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xc9	0x08	RTM_RETIRED.ABORTED_MISC1	Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x10	RTM_RETIRED.ABORTED_MISC2	Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x20	RTM_RETIRED.ABORTED_MISC3	Number of times an RTM execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x40	RTM_RETIRED.ABORTED_MISC4	Number of times an RTM execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x80	RTM_RETIRED.ABORTED_MISC5	Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	0	null
+0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32	3	3	100007	0x3F6	0x20	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	0	null
+0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	null
+0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null
+0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	null
+0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	null
+0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	1	null
+0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x04	MEM_LOAD_UOPS_RETIRED.L3_HIT	Retired load uops which data sources were data hits in L3 without snoops required.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x08	MEM_LOAD_UOPS_RETIRED.L1_MISS	Retired load uops misses in L1 cache as data sources.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x10	MEM_LOAD_UOPS_RETIRED.L2_MISS	Miss in mid-level (L2) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x20	MEM_LOAD_UOPS_RETIRED.L3_MISS	Miss in last-level (L3) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD2	0x01	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null
+0xD2	0x02	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null
+0xD2	0x04	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared L3.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null
+0xD2	0x08	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in L3 without snoops required.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD3	0x01	MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM	Data from local DRAM either Snoop not needed or Snoop Miss (RspI)	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null
+0x3c	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x08	L2_TRANS.ALL_PF	L2 or L3 HW prefetches that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xf1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xf1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xF2	0x05	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x01	UOPS_EXECUTED_PORT.PORT_0_CORE	Cycles per core when uops are exectuted in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x02	UOPS_EXECUTED_PORT.PORT_1_CORE	Cycles per core when uops are exectuted in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x04	UOPS_EXECUTED_PORT.PORT_2_CORE	Cycles per core when uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x08	UOPS_EXECUTED_PORT.PORT_3_CORE	Cycles per core when uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x10	UOPS_EXECUTED_PORT.PORT_4_CORE	Cycles per core when uops are exectuted in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x20	UOPS_EXECUTED_PORT.PORT_5_CORE	Cycles per core when uops are exectuted in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x40	UOPS_EXECUTED_PORT.PORT_6_CORE	Cycles per core when uops are exectuted in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x80	UOPS_EXECUTED_PORT.PORT_7_CORE	Cycles per core when uops are dispatched to port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xC5	0x20	BR_MISP_RETIRED.NEAR_TAKEN	number of near branch instructions retired that were mispredicted and taken.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0x08	0x0e	DTLB_LOAD_MISSES.WALK_COMPLETED	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x60	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x42	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x22	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x44	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x24	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x27	L2_RQSTS.ALL_DEMAND_MISS	Demand requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xe7	L2_RQSTS.ALL_DEMAND_REFERENCES	Demand requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x3F	L2_RQSTS.MISS	All requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x0e	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x60	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x0e	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x60	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC	Cycles where at least 1 uop was executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC	Cycles where at least 2 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC	Cycles where at least 3 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC	Cycles where at least 4 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xe6	0x1f	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE	Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	0	0	0	null
+0xc7	0x20	FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE	Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_MISS	Cycles while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	8	0	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_MISS	Cycles while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_MEM_ANY	Cycles while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.STALLS_TOTAL	Total execution stalls.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_MISS	Execution stalls while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	12	0	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_MISS	Execution stalls while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	5	0	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_MEM_ANY	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null
+0xC3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0	null
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	1	1	0	1	0	0	0	null
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xA1	0x01	UOPS_EXECUTED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_EXECUTED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x04	UOPS_EXECUTED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x08	UOPS_EXECUTED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x10	UOPS_EXECUTED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x20	UOPS_EXECUTED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_EXECUTED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_EXECUTED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA0	0x03	UOP_DISPATCHES_CANCELLED.SIMD_PRF	Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x03	FP_ARITH_INST_RETIRED.SCALAR	Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x3C	FP_ARITH_INST_RETIRED.PACKED	Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. 	0,1,2,3	0,1,2,3	2000004	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x15	FP_ARITH_INST_RETIRED.SINGLE	Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?	0,1,2,3	0,1,2,3	2000005	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x2A	FP_ARITH_INST_RETIRED.DOUBLE	Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?	0,1,2,3	0,1,2,3	2000006	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	1	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	2	2	2000003	0	0	0	1	0	1	0	0	0	0	null
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/BDW/Broadwell_matrix_V11.json b/x86data/perfmon_data/BDW/Broadwell_matrix_V11.json
new file mode 100644
index 0000000..a340086
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_matrix_V11.json
@@ -0,0 +1,296 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand data reads"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand data writes (RFOs)"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand code reads"
+  },
+  {
+    "MATRIX_REQUEST": "COREWB",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000008",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts writebacks (modified to exclusive)"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000010",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to L2) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000020",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to L2) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000040",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L3_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L3_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L3_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000200",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "OTHER",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any other requests"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000090",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000120",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000240",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000091",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000122",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "ANY_RESPONSE",
+    "MATRIX_VALUE": "0x0000010000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "have any response type."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_NONE",
+    "MATRIX_VALUE": "0x0080020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x0100020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0200020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x0400020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_HITM",
+    "MATRIX_VALUE": "0x1000020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x2000020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3f80020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_NONE",
+    "MATRIX_VALUE": "0x00803c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 with no details on snoop-related information."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x01003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_MISS",
+    "MATRIX_VALUE": "0x02003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 with a snoop miss response."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x04003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_HITM",
+    "MATRIX_VALUE": "0x10003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x20003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the target was non-DRAM system address."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3f803c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_NONE",
+    "MATRIX_VALUE": "0x0084000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x0104000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0204000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x0404000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_HITM",
+    "MATRIX_VALUE": "0x1004000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x2004000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3f84000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_NONE",
+    "MATRIX_VALUE": "0x00bc000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the L3 with no details on snoop-related information."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x013c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_MISS",
+    "MATRIX_VALUE": "0x023c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the L3 with a snoop miss response."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x043c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/BDW/Broadwell_matrix_V11.tsv b/x86data/perfmon_data/BDW/Broadwell_matrix_V11.tsv
new file mode 100644
index 0000000..9b1d03a
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_matrix_V11.tsv
@@ -0,0 +1,46 @@
+# Performance Monitoring Events for the Fifth Generation Intel Core Processors Based on the Broadwell Microarchitecture - V11
+# 7/22/2015 2:19:56 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand data reads
+DEMAND_RFO	Null	0x0002	0,1	Counts all demand data writes (RFOs)
+DEMAND_CODE_RD	Null	0x0004	0,1	Counts all demand code reads
+COREWB	Null	0x0008	0,1	Counts writebacks (modified to exclusive)
+PF_L2_DATA_RD	Null	0x0010	0,1	Counts prefetch (that bring data to L2) data reads
+PF_L2_RFO	Null	0x0020	0,1	Counts all prefetch (that bring data to L2) RFOs
+PF_L2_CODE_RD	Null	0x0040	0,1	Counts all prefetch (that bring data to LLC only) code reads
+PF_L3_DATA_RD	Null	0x0080	0,1	Counts all prefetch (that bring data to LLC only) data reads
+PF_L3_RFO	Null	0x0100	0,1	Counts all prefetch (that bring data to LLC only) RFOs
+PF_L3_CODE_RD	Null	0x0200	0,1	Counts prefetch (that bring data to LLC only) code reads
+OTHER	Null	0x8000	0,1	Counts any other requests
+ALL_PF_DATA_RD	Null	0x0090	0,1	Counts all prefetch data reads
+ALL_PF_RFO	Null	0x0120	0,1	Counts prefetch RFOs
+ALL_PF_CODE_RD	Null	0x0240	0,1	Counts all prefetch code reads
+ALL_DATA_RD	Null	0x0091	0,1	Counts all demand & prefetch data reads
+ALL_RFO	Null	0x0122	0,1	Counts all demand & prefetch RFOs
+Null	ANY_RESPONSE	0x000001	0,1	have any response type.
+Null	SUPPLIER_NONE.SNOOP_NONE	0x008002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_NOT_NEEDED	0x010002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_MISS	0x020002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_HIT_NO_FWD	0x040002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_HITM	0x100002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_NON_DRAM	0x200002	0,1	tbd
+Null	SUPPLIER_NONE.ANY_SNOOP	0x3f8002	0,1	tbd
+Null	L3_HIT.SNOOP_NONE	0x00803c	0,1	hit in the L3 with no details on snoop-related information.
+Null	L3_HIT.SNOOP_NOT_NEEDED	0x01003c	0,1	hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
+Null	L3_HIT.SNOOP_MISS	0x02003c	0,1	hit in the L3 with a snoop miss response.
+Null	L3_HIT.SNOOP_HIT_NO_FWD	0x04003c	0,1	hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
+Null	L3_HIT.SNOOP_HITM	0x10003c	0,1	tbd
+Null	L3_HIT.SNOOP_NON_DRAM	0x20003c	0,1	hit in the L3 and the target was non-DRAM system address.
+Null	L3_HIT.ANY_SNOOP	0x3f803c	0,1	hit in the L3.
+Null	L3_MISS_LOCAL_DRAM.SNOOP_NONE	0x008400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	0x010400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_MISS	0x020400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	0x040400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_HITM	0x100400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	0x200400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.ANY_SNOOP	0x3f8400	0,1	tbd
+Null	L3_MISS.SNOOP_NONE	0x00bc00	0,1	miss the L3 with no details on snoop-related information.
+Null	L3_MISS.SNOOP_NOT_NEEDED	0x013c00	0,1	tbd
+Null	L3_MISS.SNOOP_MISS	0x023c00	0,1	miss the L3 with a snoop miss response.
+Null	L3_MISS.SNOOP_HIT_NO_FWD	0x043c00	0,1	tbd
diff --git a/x86data/perfmon_data/BDW/Broadwell_matrix_bit_definitions_V11.json b/x86data/perfmon_data/BDW/Broadwell_matrix_bit_definitions_V11.json
new file mode 100644
index 0000000..3f1fc86
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_matrix_bit_definitions_V11.json
@@ -0,0 +1,254 @@
+[
+  {
+    "BitName": "DEMAND_DATA_RD",
+    "BitIndex": "0",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_RFO",
+    "BitIndex": "1",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_CODE_RD",
+    "BitIndex": "2",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "COREWB",
+    "BitIndex": "3",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_DATA_RD",
+    "BitIndex": "4",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_RFO",
+    "BitIndex": "5",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_CODE_RD",
+    "BitIndex": "6",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_DATA_RD",
+    "BitIndex": "7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_RFO",
+    "BitIndex": "8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_CODE_RD",
+    "BitIndex": "9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "OTHER",
+    "BitIndex": "15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_DATA_RD",
+    "BitIndex": "4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_RFO",
+    "BitIndex": "5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_CODE_RD",
+    "BitIndex": "6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_DATA_RD",
+    "BitIndex": "0,4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_RFO",
+    "BitIndex": "1,5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_CODE_RD",
+    "BitIndex": "2,6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_READS",
+    "BitIndex": "0,1,2,4,5,6,7,8,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_REQUESTS",
+    "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_RESPONSE",
+    "BitIndex": "16",
+    "Type": "2",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SUPPLIER_NONE",
+    "BitIndex": "17",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_M",
+    "BitIndex": "18",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_E",
+    "BitIndex": "19",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_S",
+    "BitIndex": "20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_F",
+    "BitIndex": "21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT",
+    "BitIndex": "18,19,20,21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_LOCAL_DRAM",
+    "BitIndex": "26",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS",
+    "BitIndex": "26,27,28,29",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NONE",
+    "BitIndex": "31",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NOT_NEEDED",
+    "BitIndex": "32",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_MISS",
+    "BitIndex": "33",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_NO_FWD",
+    "BitIndex": "34",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_WITH_FWD",
+    "BitIndex": "35",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "18,19,20,21"
+  },
+  {
+    "BitName": "SNOOP_HITM",
+    "BitIndex": "36",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NON_DRAM",
+    "BitIndex": "37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_SNOOP",
+    "BitIndex": "31,32,33,34,35,36,37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/BDW/Broadwell_matrix_bit_definitions_V11.tsv b/x86data/perfmon_data/BDW/Broadwell_matrix_bit_definitions_V11.tsv
new file mode 100644
index 0000000..112b67f
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_matrix_bit_definitions_V11.tsv
@@ -0,0 +1,40 @@
+# Performance Monitoring Events for the Fifth Generation Intel Core Processors Based on the Broadwell Microarchitecture - V11
+# 7/22/2015 2:19:57 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	Type	MATRIX_REG	BitsNotCombinedWith
+DEMAND_DATA_RD	0	1	0,1	Null
+DEMAND_RFO	1	1	0,1	Null
+DEMAND_CODE_RD	2	1	0,1	Null
+COREWB	3	1	0,1	Null
+PF_L2_DATA_RD	4	1	0,1	Null
+PF_L2_RFO	5	1	0,1	Null
+PF_L2_CODE_RD	6	1	0,1	Null
+PF_L3_DATA_RD	7	1	0,1	Null
+PF_L3_RFO	8	1	0,1	Null
+PF_L3_CODE_RD	9	1	0,1	Null
+OTHER	15	1	0,1	Null
+ALL_PF_DATA_RD	4,7	1	0,1	Null
+ALL_PF_RFO	5,8	1	0,1	Null
+ALL_PF_CODE_RD	6,9	1	0,1	Null
+ALL_DATA_RD	0,4,7	1	0,1	Null
+ALL_RFO	1,5,8	1	0,1	Null
+ALL_CODE_RD	2,6,9	1	0,1	Null
+ALL_READS	0,1,2,4,5,6,7,8,9	1	0,1	Null
+ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	0,1	Null
+ANY_RESPONSE	16	2	0,1	Null
+SUPPLIER_NONE	17	3	0,1	Null
+L3_HIT_M	18	3	0,1	Null
+L3_HIT_E	19	3	0,1	Null
+L3_HIT_S	20	3	0,1	Null
+L3_HIT_F	21	3	0,1	Null
+L3_HIT	18,19,20,21	3	0,1	Null
+L3_MISS_LOCAL_DRAM	26	3	0,1	Null
+L3_MISS	26,27,28,29	3	0,1	Null
+SNOOP_NONE	31	4	0,1	Null
+SNOOP_NOT_NEEDED	32	4	0,1	Null
+SNOOP_MISS	33	4	0,1	Null
+SNOOP_HIT_NO_FWD	34	4	0,1	Null
+SNOOP_HIT_WITH_FWD	35	4	0,1	18,19,20,21
+SNOOP_HITM	36	4	0,1	Null
+SNOOP_NON_DRAM	37	4	0,1	Null
+ANY_SNOOP	31,32,33,34,35,36,37	4	0,1	Null
diff --git a/x86data/perfmon_data/BDW/Broadwell_offcore_V11.tsv b/x86data/perfmon_data/BDW/Broadwell_offcore_V11.tsv
new file mode 100644
index 0000000..e840292
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_offcore_V11.tsv
@@ -0,0 +1,407 @@
+# Performance Monitoring Events for the Fifth Generation Intel Core Processors Based on the Broadwell Microarchitecture - V11
+# 7/22/2015 2:19:57 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand data reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE	Counts demand data reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS	Counts demand data reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM	Counts demand data reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP	Counts demand data reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE	Counts demand data reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS	Counts demand data reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE	Counts all demand data writes (RFOs) that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE	Counts all demand data writes (RFOs) that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS	Counts all demand data writes (RFOs) that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM	Counts all demand data writes (RFOs) that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP	Counts all demand data writes (RFOs) that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE	Counts all demand data writes (RFOs) that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS	Counts all demand data writes (RFOs) that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE	Counts all demand code reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE	Counts all demand code reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS	Counts all demand code reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM	Counts all demand code reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP	Counts all demand code reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE	Counts all demand code reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS	Counts all demand code reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE	Counts writebacks (modified to exclusive) that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE	Counts writebacks (modified to exclusive) that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED	Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS	Counts writebacks (modified to exclusive) that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD	Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NON_DRAM	Counts writebacks (modified to exclusive) that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP	Counts writebacks (modified to exclusive) that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE	Counts writebacks (modified to exclusive) that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS	Counts writebacks (modified to exclusive) that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000008 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE	Counts prefetch (that bring data to L2) data reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE	Counts prefetch (that bring data to L2) data reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS	Counts prefetch (that bring data to L2) data reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NON_DRAM	Counts prefetch (that bring data to L2) data reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP	Counts prefetch (that bring data to L2) data reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE	Counts prefetch (that bring data to L2) data reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS	Counts prefetch (that bring data to L2) data reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000010 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE	Counts all prefetch (that bring data to L2) RFOs that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE	Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS	Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NON_DRAM	Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP	Counts all prefetch (that bring data to L2) RFOs that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE	Counts all prefetch (that bring data to L2) RFOs that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS	Counts all prefetch (that bring data to L2) RFOs that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000020 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) code reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE	Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS	Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NON_DRAM	Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_SNOOP	Counts all prefetch (that bring data to LLC only) code reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NONE	Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS	Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000040 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) data reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE	Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS	Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) RFOs that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE	Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS	Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE	Counts prefetch (that bring data to LLC only) code reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE	Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS	Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NON_DRAM	Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP	Counts prefetch (that bring data to LLC only) code reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE	Counts prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS	Counts prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000200 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.ANY_RESPONSE	Counts any other requests that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000018000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE	Counts any other requests that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED	Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS	Counts any other requests that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD	Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM	Counts any other requests that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP	Counts any other requests that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE	Counts any other requests that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS	Counts any other requests that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE	Counts all prefetch data reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE	Counts all prefetch data reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS	Counts all prefetch data reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NON_DRAM	Counts all prefetch data reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP	Counts all prefetch data reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE	Counts all prefetch data reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS	Counts all prefetch data reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000090 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE	Counts prefetch RFOs that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE	Counts prefetch RFOs that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS	Counts prefetch RFOs that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NON_DRAM	Counts prefetch RFOs that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP	Counts prefetch RFOs that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE	Counts prefetch RFOs that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS	Counts prefetch RFOs that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000120 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE	Counts all prefetch code reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE	Counts all prefetch code reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS	Counts all prefetch code reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRAM	Counts all prefetch code reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP	Counts all prefetch code reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE	Counts all prefetch code reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS	Counts all prefetch code reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000240 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE	Counts all demand & prefetch data reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE	Counts all demand & prefetch data reads that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS	Counts all demand & prefetch data reads that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM	Counts all demand & prefetch data reads that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP	Counts all demand & prefetch data reads that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE	Counts all demand & prefetch data reads that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS	Counts all demand & prefetch data reads that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000091 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE	Counts all demand & prefetch RFOs that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f80020122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE	Counts all demand & prefetch RFOs that hit in the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00803c0122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01003c0122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS	Counts all demand & prefetch RFOs that hit in the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02003c0122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM	Counts all demand & prefetch RFOs that hit in the L3 and the target was non-DRAM system address.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20003c0122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP	Counts all demand & prefetch RFOs that hit in the L3.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f84000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE	Counts all demand & prefetch RFOs that miss the L3 with no details on snoop-related information.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS	Counts all demand & prefetch RFOs that miss the L3 with a snoop miss response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000122 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000122 	0	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/BDW/Broadwell_uncore_V11.json b/x86data/perfmon_data/BDW/Broadwell_uncore_V11.json
new file mode 100644
index 0000000..d2ac711
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_uncore_V11.json
@@ -0,0 +1,242 @@
+[
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x41",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
+    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
+    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x81",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
+    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
+    "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x44",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
+    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
+    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x48",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
+    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
+    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x11",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
+    "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
+    "PublicDescription": "L3 Lookup read request that access cache and found line in M-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x21",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
+    "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
+    "PublicDescription": "L3 Lookup write request that access cache and found line in M-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x81",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
+    "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
+    "PublicDescription": "L3 Lookup any request that access cache and found line in M-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x18",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
+    "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
+    "PublicDescription": "L3 Lookup read request that access cache and found line in I-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x88",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
+    "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
+    "PublicDescription": "L3 Lookup any request that access cache and found line in I-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x1f",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
+    "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
+    "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x2f",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
+    "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
+    "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x8f",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
+    "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
+    "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x86",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
+    "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
+    "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x16",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
+    "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
+    "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x26",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
+    "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
+    "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+    "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
+    "PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
+    "Counter": "0,",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x81",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+    "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
+    "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x81",
+    "UMask": "0x20",
+    "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
+    "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
+    "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x84",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+    "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
+    "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "NCU",
+    "EventCode": "0x0",
+    "UMask": "0x01",
+    "EventName": "UNC_CLOCK.SOCKET",
+    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
+    "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles",
+    "Counter": "FIXED",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/BDW/Broadwell_uncore_V11.tsv b/x86data/perfmon_data/BDW/Broadwell_uncore_V11.tsv
new file mode 100644
index 0000000..544e008
--- /dev/null
+++ b/x86data/perfmon_data/BDW/Broadwell_uncore_V11.tsv
@@ -0,0 +1,24 @@
+# Performance Monitoring Events for the Fifth Generation Intel Core Processors Based on the Broadwell Microarchitecture - V11
+# 8/17/2015 12:18:44 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+Unit	EventCode	UMask	EventName	Description	Counter	CounterMask	Invert	EdgeDetect
+CBO	0x22	0x41	UNC_CBO_XSNP_RESPONSE.MISS_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.	0,1	0	0	0
+CBO	0x22	0x81	UNC_CBO_XSNP_RESPONSE.MISS_EVICTION	A cross-core snoop resulted from L3 Eviction which misses in some processor core.	0,1	0	0	0
+CBO	0x22	0x44	UNC_CBO_XSNP_RESPONSE.HIT_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.	0,1	0	0	0
+CBO	0x22	0x48	UNC_CBO_XSNP_RESPONSE.HITM_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.	0,1	0	0	0
+CBO	0x34	0x11	UNC_CBO_CACHE_LOOKUP.READ_M	L3 Lookup read request that access cache and found line in M-state	0,1	0	0	0
+CBO	0x34	0x21	UNC_CBO_CACHE_LOOKUP.WRITE_M	L3 Lookup write request that access cache and found line in M-state	0,1	0	0	0
+CBO	0x34	0x81	UNC_CBO_CACHE_LOOKUP.ANY_M	L3 Lookup any request that access cache and found line in M-state	0,1	0	0	0
+CBO	0x34	0x18	UNC_CBO_CACHE_LOOKUP.READ_I	L3 Lookup read request that access cache and found line in I-state	0,1	0	0	0
+CBO	0x34	0x88	UNC_CBO_CACHE_LOOKUP.ANY_I	L3 Lookup any request that access cache and found line in I-state	0,1	0	0	0
+CBO	0x34	0x1f	UNC_CBO_CACHE_LOOKUP.READ_MESI	L3 Lookup read request that access cache and found line in any MESI-state	0,1	0	0	0
+CBO	0x34	0x2f	UNC_CBO_CACHE_LOOKUP.WRITE_MESI	L3 Lookup write request that access cache and found line in MESI-state	0,1	0	0	0
+CBO	0x34	0x8f	UNC_CBO_CACHE_LOOKUP.ANY_MESI	L3 Lookup any request that access cache and found line in MESI-state	0,1	0	0	0
+CBO	0x34	0x86	UNC_CBO_CACHE_LOOKUP.ANY_ES	L3 Lookup any request that access cache and found line in E or S-state	0,1	0	0	0
+CBO	0x34	0x16	UNC_CBO_CACHE_LOOKUP.READ_ES	L3 Lookup read request that access cache and found line in E or S-state	0,1	0	0	0
+CBO	0x34	0x26	UNC_CBO_CACHE_LOOKUP.WRITE_ES	L3 Lookup write request that access cache and found line in E or S-state	0,1	0	0	0
+iMPH-U	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.ALL	Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.	0,	0	0	0
+iMPH-U	0x81	0x01	UNC_ARB_TRK_REQUESTS.ALL	Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.	0,1	0	0	0
+iMPH-U	0x81	0x20	UNC_ARB_TRK_REQUESTS.WRITES	Number of Writes allocated - any write transactions: full/partials writes and evictions.	0,1	0	0	0
+iMPH-U	0x84	0x01	UNC_ARB_COH_TRK_REQUESTS.ALL	Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.	0,1	0	0	0
+NCU	0x0	0x01	UNC_CLOCK.SOCKET	This 48-bit fixed counter counts the UCLK cycles	FIXED	0	0	0
diff --git a/x86data/perfmon_data/BNL/Bonnell_core_V1.json b/x86data/perfmon_data/BNL/Bonnell_core_V1.json
new file mode 100644
index 0000000..54396fa
--- /dev/null
+++ b/x86data/perfmon_data/BNL/Bonnell_core_V1.json
@@ -0,0 +1,4898 @@
+[
+  {
+    "EventCode": "0x2",
+    "UMask": "0x83",
+    "EventName": "STORE_FORWARDS.ANY",
+    "BriefDescription": "All store forwards",
+    "PublicDescription": "All store forwards",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2",
+    "UMask": "0x81",
+    "EventName": "STORE_FORWARDS.GOOD",
+    "BriefDescription": "Good store forwards",
+    "PublicDescription": "Good store forwards",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3",
+    "UMask": "0x7F",
+    "EventName": "REISSUE.ANY",
+    "BriefDescription": "Micro-op reissues for any cause",
+    "PublicDescription": "Micro-op reissues for any cause",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3",
+    "UMask": "0xFF",
+    "EventName": "REISSUE.ANY.AR",
+    "BriefDescription": "Micro-op reissues for any cause (At Retirement)",
+    "PublicDescription": "Micro-op reissues for any cause (At Retirement)",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x5",
+    "UMask": "0xF",
+    "EventName": "MISALIGN_MEM_REF.SPLIT",
+    "BriefDescription": "Memory references that cross an 8-byte boundary.",
+    "PublicDescription": "Memory references that cross an 8-byte boundary.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "Errata": "null",
+    "Offcore": "0"
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+  {
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+    "UMask": "0x9",
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+    "BriefDescription": "Load splits",
+    "PublicDescription": "Load splits",
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+    "PEBS": "0",
+    "Errata": "null",
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+  {
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+    "UMask": "0xA",
+    "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
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+    "PublicDescription": "Store splits",
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+  {
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+    "UMask": "0x8F",
+    "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
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+    "PublicDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
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+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
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+  {
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+    "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
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+    "PublicDescription": "Load splits (At Retirement)",
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+    "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
+    "BriefDescription": "Store splits (Ar Retirement)",
+    "PublicDescription": "Store splits (Ar Retirement)",
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+  },
+  {
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+    "UMask": "0x8C",
+    "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
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+    "Errata": "null",
+    "Offcore": "0"
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+    "UMask": "0x97",
+    "EventName": "MISALIGN_MEM_REF.BUBBLE",
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+    "PublicDescription": "Nonzero segbase 1 bubble",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
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+  },
+  {
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+    "UMask": "0x91",
+    "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
+    "BriefDescription": "Nonzero segbase load 1 bubble",
+    "PublicDescription": "Nonzero segbase load 1 bubble",
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+    "SampleAfterValue": "200000",
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+    "MSRValue": "0",
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+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
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+    "UMask": "0x92",
+    "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
+    "BriefDescription": "Nonzero segbase store 1 bubble",
+    "PublicDescription": "Nonzero segbase store 1 bubble",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
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+    "MSRValue": "0",
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+    "PEBS": "0",
+    "Errata": "null",
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+  },
+  {
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+    "UMask": "0x94",
+    "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
+    "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
+    "PublicDescription": "Nonzero segbase ld-op-st 1 bubble",
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+    "SampleAfterValue": "200000",
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+    "Offcore": "0"
+  },
+  {
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+    "UMask": "0x80",
+    "EventName": "SEGMENT_REG_LOADS.ANY",
+    "BriefDescription": "Number of segment register loads.",
+    "PublicDescription": "Number of segment register loads.",
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+    "SampleAfterValue": "200000",
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+    "MSRValue": "0",
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+  {
+    "EventCode": "0x7",
+    "UMask": "0x81",
+    "EventName": "PREFETCH.PREFETCHT0",
+    "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
+    "PublicDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
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+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
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+  },
+  {
+    "EventCode": "0x7",
+    "UMask": "0x82",
+    "EventName": "PREFETCH.PREFETCHT1",
+    "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
+    "PublicDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
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+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7",
+    "UMask": "0x84",
+    "EventName": "PREFETCH.PREFETCHT2",
+    "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
+    "PublicDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
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+    "EdgeDetect": "0",
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+  },
+  {
+    "EventCode": "0x7",
+    "UMask": "0x86",
+    "EventName": "PREFETCH.SW_L2",
+    "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+    "PublicDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7",
+    "UMask": "0x88",
+    "EventName": "PREFETCH.PREFETCHNTA",
+    "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
+    "PublicDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7",
+    "UMask": "0x10",
+    "EventName": "PREFETCH.HW_PREFETCH",
+    "BriefDescription": "L1 hardware prefetch request",
+    "PublicDescription": "L1 hardware prefetch request",
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+    "SampleAfterValue": "2000000",
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+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7",
+    "UMask": "0xF",
+    "EventName": "PREFETCH.SOFTWARE_PREFETCH",
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+    "PublicDescription": "Any Software prefetch",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
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+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7",
+    "UMask": "0x8F",
+    "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
+    "BriefDescription": "Any Software prefetch",
+    "PublicDescription": "Any Software prefetch",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
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+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x8",
+    "UMask": "0x7",
+    "EventName": "DATA_TLB_MISSES.DTLB_MISS",
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+    "PublicDescription": "Memory accesses that missed the DTLB.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
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+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x8",
+    "UMask": "0x5",
+    "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
+    "BriefDescription": "DTLB misses due to load operations.",
+    "PublicDescription": "DTLB misses due to load operations.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
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+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x8",
+    "UMask": "0x9",
+    "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
+    "BriefDescription": "L0 DTLB misses due to load operations.",
+    "PublicDescription": "L0 DTLB misses due to load operations.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
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+  },
+  {
+    "EventCode": "0x8",
+    "UMask": "0x6",
+    "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
+    "BriefDescription": "DTLB misses due to store operations.",
+    "PublicDescription": "DTLB misses due to store operations.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
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+    "EdgeDetect": "0",
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+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x8",
+    "UMask": "0xA",
+    "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
+    "BriefDescription": "L0 DTLB misses due to store operations",
+    "PublicDescription": "L0 DTLB misses due to store operations",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
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+    "CounterMask": "0",
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+    "EdgeDetect": "0",
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+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x9",
+    "UMask": "0x20",
+    "EventName": "DISPATCH_BLOCKED.ANY",
+    "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
+    "PublicDescription": "Memory cluster signals to block micro-op dispatch for any reason",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
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+    "CounterMask": "0",
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+    "EdgeDetect": "0",
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+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC",
+    "UMask": "0x3",
+    "EventName": "PAGE_WALKS.WALKS",
+    "BriefDescription": "Number of page-walks executed.",
+    "PublicDescription": "Number of page-walks executed.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
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+    "EdgeDetect": "0",
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+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC",
+    "UMask": "0x3",
+    "EventName": "PAGE_WALKS.CYCLES",
+    "BriefDescription": "Duration of page-walks in core cycles",
+    "PublicDescription": "Duration of page-walks in core cycles",
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+    "SampleAfterValue": "2000000",
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+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC",
+    "UMask": "0x1",
+    "EventName": "PAGE_WALKS.D_SIDE_WALKS",
+    "BriefDescription": "Number of D-side only page walks",
+    "PublicDescription": "Number of D-side only page walks",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
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+    "EdgeDetect": "0",
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+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC",
+    "UMask": "0x1",
+    "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
+    "BriefDescription": "Duration of D-side only page walks",
+    "PublicDescription": "Duration of D-side only page walks",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
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+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC",
+    "UMask": "0x2",
+    "EventName": "PAGE_WALKS.I_SIDE_WALKS",
+    "BriefDescription": "Number of I-Side page walks",
+    "PublicDescription": "Number of I-Side page walks",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
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+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC",
+    "UMask": "0x2",
+    "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
+    "BriefDescription": "Duration of I-Side page walks",
+    "PublicDescription": "Duration of I-Side page walks",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "X87_COMP_OPS_EXE.ANY.S",
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+    "PublicDescription": "Floating point computational micro-ops executed.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
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+    "CounterMask": "0",
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+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x10",
+    "UMask": "0x81",
+    "EventName": "X87_COMP_OPS_EXE.ANY.AR",
+    "BriefDescription": "Floating point computational micro-ops retired.",
+    "PublicDescription": "Floating point computational micro-ops retired.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "X87_COMP_OPS_EXE.FXCH.S",
+    "BriefDescription": "FXCH uops executed.",
+    "PublicDescription": "FXCH uops executed.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x10",
+    "UMask": "0x82",
+    "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
+    "BriefDescription": "FXCH uops retired.",
+    "PublicDescription": "FXCH uops retired.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
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+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "FP_ASSIST.S",
+    "BriefDescription": "Floating point assists.",
+    "PublicDescription": "Floating point assists.",
+    "Counter": "0,1",
+    "SampleAfterValue": "10000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x11",
+    "UMask": "0x81",
+    "EventName": "FP_ASSIST.AR",
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+    "PublicDescription": "Floating point assists for retired operations.",
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+    "UMask": "0x5F",
+    "EventName": "L2_LD.SELF.PREFETCH.MESI",
+    "BriefDescription": "L2 cache reads",
+    "PublicDescription": "L2 cache reads",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2A",
+    "UMask": "0x44",
+    "EventName": "L2_ST.SELF.E_STATE",
+    "BriefDescription": "L2 store requests",
+    "PublicDescription": "L2 store requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2A",
+    "UMask": "0x41",
+    "EventName": "L2_ST.SELF.I_STATE",
+    "BriefDescription": "L2 store requests",
+    "PublicDescription": "L2 store requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2A",
+    "UMask": "0x48",
+    "EventName": "L2_ST.SELF.M_STATE",
+    "BriefDescription": "L2 store requests",
+    "PublicDescription": "L2 store requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2A",
+    "UMask": "0x42",
+    "EventName": "L2_ST.SELF.S_STATE",
+    "BriefDescription": "L2 store requests",
+    "PublicDescription": "L2 store requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2A",
+    "UMask": "0x4F",
+    "EventName": "L2_ST.SELF.MESI",
+    "BriefDescription": "L2 store requests",
+    "PublicDescription": "L2 store requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2B",
+    "UMask": "0x44",
+    "EventName": "L2_LOCK.SELF.E_STATE",
+    "BriefDescription": "L2 locked accesses",
+    "PublicDescription": "L2 locked accesses",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2B",
+    "UMask": "0x41",
+    "EventName": "L2_LOCK.SELF.I_STATE",
+    "BriefDescription": "L2 locked accesses",
+    "PublicDescription": "L2 locked accesses",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2B",
+    "UMask": "0x48",
+    "EventName": "L2_LOCK.SELF.M_STATE",
+    "BriefDescription": "L2 locked accesses",
+    "PublicDescription": "L2 locked accesses",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2B",
+    "UMask": "0x42",
+    "EventName": "L2_LOCK.SELF.S_STATE",
+    "BriefDescription": "L2 locked accesses",
+    "PublicDescription": "L2 locked accesses",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2B",
+    "UMask": "0x4F",
+    "EventName": "L2_LOCK.SELF.MESI",
+    "BriefDescription": "L2 locked accesses",
+    "PublicDescription": "L2 locked accesses",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2C",
+    "UMask": "0x44",
+    "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
+    "BriefDescription": "All data requests from the L1 data cache",
+    "PublicDescription": "All data requests from the L1 data cache",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2C",
+    "UMask": "0x41",
+    "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
+    "BriefDescription": "All data requests from the L1 data cache",
+    "PublicDescription": "All data requests from the L1 data cache",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2C",
+    "UMask": "0x48",
+    "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
+    "BriefDescription": "All data requests from the L1 data cache",
+    "PublicDescription": "All data requests from the L1 data cache",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2C",
+    "UMask": "0x42",
+    "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
+    "BriefDescription": "All data requests from the L1 data cache",
+    "PublicDescription": "All data requests from the L1 data cache",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2C",
+    "UMask": "0x4F",
+    "EventName": "L2_DATA_RQSTS.SELF.MESI",
+    "BriefDescription": "All data requests from the L1 data cache",
+    "PublicDescription": "All data requests from the L1 data cache",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2D",
+    "UMask": "0x44",
+    "EventName": "L2_LD_IFETCH.SELF.E_STATE",
+    "BriefDescription": "All read requests from L1 instruction and data caches",
+    "PublicDescription": "All read requests from L1 instruction and data caches",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2D",
+    "UMask": "0x41",
+    "EventName": "L2_LD_IFETCH.SELF.I_STATE",
+    "BriefDescription": "All read requests from L1 instruction and data caches",
+    "PublicDescription": "All read requests from L1 instruction and data caches",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2D",
+    "UMask": "0x48",
+    "EventName": "L2_LD_IFETCH.SELF.M_STATE",
+    "BriefDescription": "All read requests from L1 instruction and data caches",
+    "PublicDescription": "All read requests from L1 instruction and data caches",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2D",
+    "UMask": "0x42",
+    "EventName": "L2_LD_IFETCH.SELF.S_STATE",
+    "BriefDescription": "All read requests from L1 instruction and data caches",
+    "PublicDescription": "All read requests from L1 instruction and data caches",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2D",
+    "UMask": "0x4F",
+    "EventName": "L2_LD_IFETCH.SELF.MESI",
+    "BriefDescription": "All read requests from L1 instruction and data caches",
+    "PublicDescription": "All read requests from L1 instruction and data caches",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x74",
+    "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x71",
+    "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x78",
+    "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x72",
+    "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x7F",
+    "EventName": "L2_RQSTS.SELF.ANY.MESI",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
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+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x44",
+    "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x41",
+    "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x48",
+    "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x42",
+    "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x4F",
+    "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x54",
+    "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x51",
+    "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x58",
+    "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x52",
+    "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x5F",
+    "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
+    "BriefDescription": "L2 cache requests",
+    "PublicDescription": "L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x41",
+    "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
+    "BriefDescription": "L2 cache demand requests from this core that missed the L2",
+    "PublicDescription": "L2 cache demand requests from this core that missed the L2",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x2E",
+    "UMask": "0x4F",
+    "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
+    "BriefDescription": "L2 cache demand requests from this core",
+    "PublicDescription": "L2 cache demand requests from this core",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x74",
+    "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x71",
+    "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x78",
+    "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x72",
+    "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x7F",
+    "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x44",
+    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x41",
+    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x48",
+    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x42",
+    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x4F",
+    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x54",
+    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x51",
+    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x58",
+    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x52",
+    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x30",
+    "UMask": "0x5F",
+    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
+    "BriefDescription": "Rejected L2 cache requests",
+    "PublicDescription": "Rejected L2 cache requests",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x32",
+    "UMask": "0x40",
+    "EventName": "L2_NO_REQ.SELF",
+    "BriefDescription": "Cycles no L2 cache requests are pending",
+    "PublicDescription": "Cycles no L2 cache requests are pending",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3A",
+    "UMask": "0x0",
+    "EventName": "EIST_TRANS",
+    "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
+    "PublicDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3B",
+    "UMask": "0xC0",
+    "EventName": "THERMAL_TRIP",
+    "BriefDescription": "Number of thermal trips",
+    "PublicDescription": "Number of thermal trips",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3C",
+    "UMask": "0x0",
+    "EventName": "CPU_CLK_UNHALTED.CORE_P",
+    "BriefDescription": "Core cycles when core is not halted",
+    "PublicDescription": "Core cycles when core is not halted",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3C",
+    "UMask": "0x1",
+    "EventName": "CPU_CLK_UNHALTED.BUS",
+    "BriefDescription": "Bus cycles when core is not halted",
+    "PublicDescription": "Bus cycles when core is not halted",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "CPU_CLK_UNHALTED.CORE",
+    "BriefDescription": "Core cycles when core is not halted",
+    "PublicDescription": "Core cycles when core is not halted",
+    "Counter": "Fixed counter 2",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "CPU_CLK_UNHALTED.REF",
+    "BriefDescription": "Reference cycles when core is not halted.",
+    "PublicDescription": "Reference cycles when core is not halted.",
+    "Counter": "Fixed counter 3",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x40",
+    "UMask": "0xA1",
+    "EventName": "L1D_CACHE.LD",
+    "BriefDescription": "L1 Cacheable Data Reads",
+    "PublicDescription": "L1 Cacheable Data Reads",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x40",
+    "UMask": "0xA2",
+    "EventName": "L1D_CACHE.ST",
+    "BriefDescription": "L1 Cacheable Data Writes",
+    "PublicDescription": "L1 Cacheable Data Writes",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x40",
+    "UMask": "0x83",
+    "EventName": "L1D_CACHE.ALL_REF",
+    "BriefDescription": "L1 Data reads and writes",
+    "PublicDescription": "L1 Data reads and writes",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x40",
+    "UMask": "0xA3",
+    "EventName": "L1D_CACHE.ALL_CACHE_REF",
+    "BriefDescription": "L1 Data Cacheable reads and writes",
+    "PublicDescription": "L1 Data Cacheable reads and writes",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x40",
+    "UMask": "0x8",
+    "EventName": "L1D_CACHE.REPL",
+    "BriefDescription": "L1 Data line replacements",
+    "PublicDescription": "L1 Data line replacements",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x40",
+    "UMask": "0x48",
+    "EventName": "L1D_CACHE.REPLM",
+    "BriefDescription": "Modified cache lines allocated in the L1 data cache",
+    "PublicDescription": "Modified cache lines allocated in the L1 data cache",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x40",
+    "UMask": "0x10",
+    "EventName": "L1D_CACHE.EVICT",
+    "BriefDescription": "Modified cache lines evicted from the L1 data cache",
+    "PublicDescription": "Modified cache lines evicted from the L1 data cache",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0xE0",
+    "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
+    "BriefDescription": "Outstanding cacheable data read bus requests duration.",
+    "PublicDescription": "Outstanding cacheable data read bus requests duration.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x60",
+    "UMask": "0x40",
+    "EventName": "BUS_REQUEST_OUTSTANDING.SELF",
+    "BriefDescription": "Outstanding cacheable data read bus requests duration.",
+    "PublicDescription": "Outstanding cacheable data read bus requests duration.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x61",
+    "UMask": "0x20",
+    "EventName": "BUS_BNR_DRV.ALL_AGENTS",
+    "BriefDescription": "Number of Bus Not Ready signals asserted.",
+    "PublicDescription": "Number of Bus Not Ready signals asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x61",
+    "UMask": "0x0",
+    "EventName": "BUS_BNR_DRV.THIS_AGENT",
+    "BriefDescription": "Number of Bus Not Ready signals asserted.",
+    "PublicDescription": "Number of Bus Not Ready signals asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x62",
+    "UMask": "0x20",
+    "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
+    "BriefDescription": "Bus cycles when data is sent on the bus.",
+    "PublicDescription": "Bus cycles when data is sent on the bus.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x62",
+    "UMask": "0x0",
+    "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
+    "BriefDescription": "Bus cycles when data is sent on the bus.",
+    "PublicDescription": "Bus cycles when data is sent on the bus.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x63",
+    "UMask": "0xE0",
+    "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
+    "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
+    "PublicDescription": "Bus cycles when a LOCK signal is asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x63",
+    "UMask": "0x40",
+    "EventName": "BUS_LOCK_CLOCKS.SELF",
+    "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
+    "PublicDescription": "Bus cycles when a LOCK signal is asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x64",
+    "UMask": "0x40",
+    "EventName": "BUS_DATA_RCV.SELF",
+    "BriefDescription": "Bus cycles while processor receives data.",
+    "PublicDescription": "Bus cycles while processor receives data.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x65",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_BRD.ALL_AGENTS",
+    "BriefDescription": "Burst read bus transactions.",
+    "PublicDescription": "Burst read bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x65",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_BRD.SELF",
+    "BriefDescription": "Burst read bus transactions.",
+    "PublicDescription": "Burst read bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x66",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_RFO.ALL_AGENTS",
+    "BriefDescription": "RFO bus transactions.",
+    "PublicDescription": "RFO bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x66",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_RFO.SELF",
+    "BriefDescription": "RFO bus transactions.",
+    "PublicDescription": "RFO bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x67",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_WB.ALL_AGENTS",
+    "BriefDescription": "Explicit writeback bus transactions.",
+    "PublicDescription": "Explicit writeback bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x67",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_WB.SELF",
+    "BriefDescription": "Explicit writeback bus transactions.",
+    "PublicDescription": "Explicit writeback bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x68",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
+    "BriefDescription": "Instruction-fetch bus transactions.",
+    "PublicDescription": "Instruction-fetch bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x68",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_IFETCH.SELF",
+    "BriefDescription": "Instruction-fetch bus transactions.",
+    "PublicDescription": "Instruction-fetch bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x69",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
+    "BriefDescription": "Invalidate bus transactions.",
+    "PublicDescription": "Invalidate bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x69",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_INVAL.SELF",
+    "BriefDescription": "Invalidate bus transactions.",
+    "PublicDescription": "Invalidate bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6A",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_PWR.ALL_AGENTS",
+    "BriefDescription": "Partial write bus transaction.",
+    "PublicDescription": "Partial write bus transaction.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6A",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_PWR.SELF",
+    "BriefDescription": "Partial write bus transaction.",
+    "PublicDescription": "Partial write bus transaction.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6B",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_P.ALL_AGENTS",
+    "BriefDescription": "Partial bus transactions.",
+    "PublicDescription": "Partial bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6B",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_P.SELF",
+    "BriefDescription": "Partial bus transactions.",
+    "PublicDescription": "Partial bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6C",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_IO.ALL_AGENTS",
+    "BriefDescription": "IO bus transactions.",
+    "PublicDescription": "IO bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6C",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_IO.SELF",
+    "BriefDescription": "IO bus transactions.",
+    "PublicDescription": "IO bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6D",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_DEF.ALL_AGENTS",
+    "BriefDescription": "Deferred bus transactions.",
+    "PublicDescription": "Deferred bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6D",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_DEF.SELF",
+    "BriefDescription": "Deferred bus transactions.",
+    "PublicDescription": "Deferred bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6E",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_BURST.ALL_AGENTS",
+    "BriefDescription": "Burst (full cache-line) bus transactions.",
+    "PublicDescription": "Burst (full cache-line) bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6E",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_BURST.SELF",
+    "BriefDescription": "Burst (full cache-line) bus transactions.",
+    "PublicDescription": "Burst (full cache-line) bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6F",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_MEM.ALL_AGENTS",
+    "BriefDescription": "Memory bus transactions.",
+    "PublicDescription": "Memory bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x6F",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_MEM.SELF",
+    "BriefDescription": "Memory bus transactions.",
+    "PublicDescription": "Memory bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x70",
+    "UMask": "0xE0",
+    "EventName": "BUS_TRANS_ANY.ALL_AGENTS",
+    "BriefDescription": "All bus transactions.",
+    "PublicDescription": "All bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x70",
+    "UMask": "0x40",
+    "EventName": "BUS_TRANS_ANY.SELF",
+    "BriefDescription": "All bus transactions.",
+    "PublicDescription": "All bus transactions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x77",
+    "UMask": "0xB",
+    "EventName": "EXT_SNOOP.THIS_AGENT.ANY",
+    "BriefDescription": "External snoops.",
+    "PublicDescription": "External snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x77",
+    "UMask": "0x1",
+    "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
+    "BriefDescription": "External snoops.",
+    "PublicDescription": "External snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x77",
+    "UMask": "0x2",
+    "EventName": "EXT_SNOOP.THIS_AGENT.HIT",
+    "BriefDescription": "External snoops.",
+    "PublicDescription": "External snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x77",
+    "UMask": "0x8",
+    "EventName": "EXT_SNOOP.THIS_AGENT.HITM",
+    "BriefDescription": "External snoops.",
+    "PublicDescription": "External snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x77",
+    "UMask": "0x2B",
+    "EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
+    "BriefDescription": "External snoops.",
+    "PublicDescription": "External snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x77",
+    "UMask": "0x21",
+    "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
+    "BriefDescription": "External snoops.",
+    "PublicDescription": "External snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x77",
+    "UMask": "0x22",
+    "EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
+    "BriefDescription": "External snoops.",
+    "PublicDescription": "External snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x77",
+    "UMask": "0x28",
+    "EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
+    "BriefDescription": "External snoops.",
+    "PublicDescription": "External snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7A",
+    "UMask": "0x20",
+    "EventName": "BUS_HIT_DRV.ALL_AGENTS",
+    "BriefDescription": "HIT signal asserted.",
+    "PublicDescription": "HIT signal asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7A",
+    "UMask": "0x0",
+    "EventName": "BUS_HIT_DRV.THIS_AGENT",
+    "BriefDescription": "HIT signal asserted.",
+    "PublicDescription": "HIT signal asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7B",
+    "UMask": "0x20",
+    "EventName": "BUS_HITM_DRV.ALL_AGENTS",
+    "BriefDescription": "HITM signal asserted.",
+    "PublicDescription": "HITM signal asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7B",
+    "UMask": "0x0",
+    "EventName": "BUS_HITM_DRV.THIS_AGENT",
+    "BriefDescription": "HITM signal asserted.",
+    "PublicDescription": "HITM signal asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7D",
+    "UMask": "0x40",
+    "EventName": "BUSQ_EMPTY.SELF",
+    "BriefDescription": "Bus queue is empty.",
+    "PublicDescription": "Bus queue is empty.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7E",
+    "UMask": "0xE0",
+    "EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
+    "BriefDescription": "Bus stalled for snoops.",
+    "PublicDescription": "Bus stalled for snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7E",
+    "UMask": "0x40",
+    "EventName": "SNOOP_STALL_DRV.SELF",
+    "BriefDescription": "Bus stalled for snoops.",
+    "PublicDescription": "Bus stalled for snoops.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x7F",
+    "UMask": "0x40",
+    "EventName": "BUS_IO_WAIT.SELF",
+    "BriefDescription": "IO requests waiting in the bus queue.",
+    "PublicDescription": "IO requests waiting in the bus queue.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x80",
+    "UMask": "0x3",
+    "EventName": "ICACHE.ACCESSES",
+    "BriefDescription": "Instruction fetches.",
+    "PublicDescription": "Instruction fetches.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x80",
+    "UMask": "0x1",
+    "EventName": "ICACHE.HIT",
+    "BriefDescription": "Icache hit",
+    "PublicDescription": "Icache hit",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x80",
+    "UMask": "0x2",
+    "EventName": "ICACHE.MISSES",
+    "BriefDescription": "Icache miss",
+    "PublicDescription": "Icache miss",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x82",
+    "UMask": "0x1",
+    "EventName": "ITLB.HIT",
+    "BriefDescription": "ITLB hits.",
+    "PublicDescription": "ITLB hits.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x82",
+    "UMask": "0x4",
+    "EventName": "ITLB.FLUSH",
+    "BriefDescription": "ITLB flushes.",
+    "PublicDescription": "ITLB flushes.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x82",
+    "UMask": "0x2",
+    "EventName": "ITLB.MISSES",
+    "BriefDescription": "ITLB misses.",
+    "PublicDescription": "ITLB misses.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x86",
+    "UMask": "0x1",
+    "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
+    "BriefDescription": "Cycles during which instruction fetches are  stalled.",
+    "PublicDescription": "Cycles during which instruction fetches are  stalled.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x87",
+    "UMask": "0x1",
+    "EventName": "DECODE_STALL.PFB_EMPTY",
+    "BriefDescription": "Decode stall due to PFB empty",
+    "PublicDescription": "Decode stall due to PFB empty",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x87",
+    "UMask": "0x2",
+    "EventName": "DECODE_STALL.IQ_FULL",
+    "BriefDescription": "Decode stall due to IQ full",
+    "PublicDescription": "Decode stall due to IQ full",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x1",
+    "EventName": "BR_INST_TYPE_RETIRED.COND",
+    "BriefDescription": "All macro conditional branch instructions.",
+    "PublicDescription": "All macro conditional branch instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x2",
+    "EventName": "BR_INST_TYPE_RETIRED.UNCOND",
+    "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
+    "PublicDescription": "All macro unconditional branch instructions, excluding calls and indirects",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x4",
+    "EventName": "BR_INST_TYPE_RETIRED.IND",
+    "BriefDescription": "All indirect branches that are not calls.",
+    "PublicDescription": "All indirect branches that are not calls.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x8",
+    "EventName": "BR_INST_TYPE_RETIRED.RET",
+    "BriefDescription": "All indirect branches that have a return mnemonic",
+    "PublicDescription": "All indirect branches that have a return mnemonic",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x10",
+    "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
+    "BriefDescription": "All non-indirect calls",
+    "PublicDescription": "All non-indirect calls",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x20",
+    "EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
+    "BriefDescription": "All indirect calls, including both register and memory indirect.",
+    "PublicDescription": "All indirect calls, including both register and memory indirect.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x88",
+    "UMask": "0x41",
+    "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
+    "BriefDescription": "Only taken macro conditional branch instructions",
+    "PublicDescription": "Only taken macro conditional branch instructions",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0x1",
+    "EventName": "BR_MISSP_TYPE_RETIRED.COND",
+    "BriefDescription": "Mispredicted cond branch instructions retired",
+    "PublicDescription": "Mispredicted cond branch instructions retired",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0x2",
+    "EventName": "BR_MISSP_TYPE_RETIRED.IND",
+    "BriefDescription": "Mispredicted ind branches that are not calls",
+    "PublicDescription": "Mispredicted ind branches that are not calls",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0x4",
+    "EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
+    "BriefDescription": "Mispredicted return branches",
+    "PublicDescription": "Mispredicted return branches",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0x8",
+    "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
+    "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect. ",
+    "PublicDescription": "Mispredicted indirect calls, including both register and memory indirect. ",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x89",
+    "UMask": "0x11",
+    "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
+    "BriefDescription": "Mispredicted and taken cond branch instructions retired",
+    "PublicDescription": "Mispredicted and taken cond branch instructions retired",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xAA",
+    "UMask": "0x1",
+    "EventName": "MACRO_INSTS.NON_CISC_DECODED",
+    "BriefDescription": "Non-CISC nacro instructions decoded",
+    "PublicDescription": "Non-CISC nacro instructions decoded",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xAA",
+    "UMask": "0x2",
+    "EventName": "MACRO_INSTS.CISC_DECODED",
+    "BriefDescription": "CISC macro instructions decoded",
+    "PublicDescription": "CISC macro instructions decoded",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xAA",
+    "UMask": "0x3",
+    "EventName": "MACRO_INSTS.ALL_DECODED",
+    "BriefDescription": "All Instructions decoded",
+    "PublicDescription": "All Instructions decoded",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB0",
+    "UMask": "0x0",
+    "EventName": "SIMD_UOPS_EXEC.S",
+    "BriefDescription": "SIMD micro-ops executed (excluding stores).",
+    "PublicDescription": "SIMD micro-ops executed (excluding stores).",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB0",
+    "UMask": "0x80",
+    "EventName": "SIMD_UOPS_EXEC.AR",
+    "BriefDescription": "SIMD micro-ops retired (excluding stores).",
+    "PublicDescription": "SIMD micro-ops retired (excluding stores).",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB1",
+    "UMask": "0x0",
+    "EventName": "SIMD_SAT_UOP_EXEC.S",
+    "BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
+    "PublicDescription": "SIMD saturated arithmetic micro-ops executed.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB1",
+    "UMask": "0x80",
+    "EventName": "SIMD_SAT_UOP_EXEC.AR",
+    "BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
+    "PublicDescription": "SIMD saturated arithmetic micro-ops retired.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x1",
+    "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
+    "BriefDescription": "SIMD packed multiply micro-ops executed",
+    "PublicDescription": "SIMD packed multiply micro-ops executed",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x81",
+    "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
+    "BriefDescription": "SIMD packed multiply micro-ops retired",
+    "PublicDescription": "SIMD packed multiply micro-ops retired",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x2",
+    "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
+    "BriefDescription": "SIMD packed shift micro-ops executed",
+    "PublicDescription": "SIMD packed shift micro-ops executed",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x82",
+    "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
+    "BriefDescription": "SIMD packed shift micro-ops retired",
+    "PublicDescription": "SIMD packed shift micro-ops retired",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x4",
+    "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
+    "BriefDescription": "SIMD packed micro-ops executed",
+    "PublicDescription": "SIMD packed micro-ops executed",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x84",
+    "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
+    "BriefDescription": "SIMD packed micro-ops retired",
+    "PublicDescription": "SIMD packed micro-ops retired",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x8",
+    "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
+    "BriefDescription": "SIMD unpacked micro-ops executed",
+    "PublicDescription": "SIMD unpacked micro-ops executed",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x88",
+    "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
+    "BriefDescription": "SIMD unpacked micro-ops retired",
+    "PublicDescription": "SIMD unpacked micro-ops retired",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x10",
+    "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
+    "BriefDescription": "SIMD packed logical micro-ops executed",
+    "PublicDescription": "SIMD packed logical micro-ops executed",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x90",
+    "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
+    "BriefDescription": "SIMD packed logical micro-ops retired",
+    "PublicDescription": "SIMD packed logical micro-ops retired",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0x20",
+    "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
+    "BriefDescription": "SIMD packed arithmetic micro-ops executed",
+    "PublicDescription": "SIMD packed arithmetic micro-ops executed",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xB3",
+    "UMask": "0xA0",
+    "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
+    "BriefDescription": "SIMD packed arithmetic micro-ops retired",
+    "PublicDescription": "SIMD packed arithmetic micro-ops retired",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC0",
+    "UMask": "0x0",
+    "EventName": "INST_RETIRED.ANY_P",
+    "BriefDescription": "Instructions retired (precise event).",
+    "PublicDescription": "Instructions retired (precise event).",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "2",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "INST_RETIRED.ANY",
+    "BriefDescription": "Instructions retired.",
+    "PublicDescription": "Instructions retired.",
+    "Counter": "Fixed counter 1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC2",
+    "UMask": "0x10",
+    "EventName": "UOPS_RETIRED.ANY",
+    "BriefDescription": "Micro-ops retired.",
+    "PublicDescription": "Micro-ops retired.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC2",
+    "UMask": "0x10",
+    "EventName": "UOPS_RETIRED.STALLED_CYCLES",
+    "BriefDescription": "Cycles no micro-ops retired.",
+    "PublicDescription": "Cycles no micro-ops retired.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC2",
+    "UMask": "0x10",
+    "EventName": "UOPS_RETIRED.STALLS",
+    "BriefDescription": "Periods no micro-ops retired.",
+    "PublicDescription": "Periods no micro-ops retired.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xA9",
+    "UMask": "0x1",
+    "EventName": "UOPS.MS_CYCLES",
+    "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ",
+    "PublicDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "1",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC3",
+    "UMask": "0x1",
+    "EventName": "MACHINE_CLEARS.SMC",
+    "BriefDescription": "Self-Modifying Code detected.",
+    "PublicDescription": "Self-Modifying Code detected.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x0",
+    "EventName": "BR_INST_RETIRED.ANY",
+    "BriefDescription": "Retired branch instructions.",
+    "PublicDescription": "Retired branch instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x1",
+    "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
+    "BriefDescription": "Retired branch instructions that were predicted not-taken.",
+    "PublicDescription": "Retired branch instructions that were predicted not-taken.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x2",
+    "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
+    "BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
+    "PublicDescription": "Retired branch instructions that were mispredicted not-taken.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x4",
+    "EventName": "BR_INST_RETIRED.PRED_TAKEN",
+    "BriefDescription": "Retired branch instructions that were predicted taken.",
+    "PublicDescription": "Retired branch instructions that were predicted taken.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0x8",
+    "EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
+    "BriefDescription": "Retired branch instructions that were mispredicted taken.",
+    "PublicDescription": "Retired branch instructions that were mispredicted taken.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0xC",
+    "EventName": "BR_INST_RETIRED.TAKEN",
+    "BriefDescription": "Retired taken branch instructions.",
+    "PublicDescription": "Retired taken branch instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC4",
+    "UMask": "0xF",
+    "EventName": "BR_INST_RETIRED.ANY1",
+    "BriefDescription": "Retired branch instructions.",
+    "PublicDescription": "Retired branch instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC5",
+    "UMask": "0x0",
+    "EventName": "BR_INST_RETIRED.MISPRED",
+    "BriefDescription": "Retired mispredicted branch instructions (precise event).",
+    "PublicDescription": "Retired mispredicted branch instructions (precise event).",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC6",
+    "UMask": "0x1",
+    "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
+    "BriefDescription": "Cycles during which interrupts are disabled.",
+    "PublicDescription": "Cycles during which interrupts are disabled.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC6",
+    "UMask": "0x2",
+    "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
+    "BriefDescription": "Cycles during which interrupts are pending and disabled.",
+    "PublicDescription": "Cycles during which interrupts are pending and disabled.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x1",
+    "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
+    "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
+    "PublicDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x2",
+    "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
+    "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
+    "PublicDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x8",
+    "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
+    "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+    "PublicDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC7",
+    "UMask": "0x10",
+    "EventName": "SIMD_INST_RETIRED.VECTOR",
+    "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
+    "PublicDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xC8",
+    "UMask": "0x0",
+    "EventName": "HW_INT_RCV",
+    "BriefDescription": "Hardware interrupts received.",
+    "PublicDescription": "Hardware interrupts received.",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCA",
+    "UMask": "0x1",
+    "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
+    "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
+    "PublicDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCA",
+    "UMask": "0x2",
+    "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
+    "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
+    "PublicDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCA",
+    "UMask": "0x8",
+    "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
+    "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+    "PublicDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCB",
+    "UMask": "0x1",
+    "EventName": "MEM_LOAD_RETIRED.L2_HIT",
+    "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
+    "PublicDescription": "Retired loads that hit the L2 cache (precise event).",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCB",
+    "UMask": "0x2",
+    "EventName": "MEM_LOAD_RETIRED.L2_MISS",
+    "BriefDescription": "Retired loads that miss the L2 cache",
+    "PublicDescription": "Retired loads that miss the L2 cache",
+    "Counter": "0,1",
+    "SampleAfterValue": "10000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCB",
+    "UMask": "0x4",
+    "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
+    "BriefDescription": "Retired loads that miss the DTLB (precise event).",
+    "PublicDescription": "Retired loads that miss the DTLB (precise event).",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "1",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCD",
+    "UMask": "0x0",
+    "EventName": "SIMD_ASSIST",
+    "BriefDescription": "SIMD assists invoked.",
+    "PublicDescription": "SIMD assists invoked.",
+    "Counter": "0,1",
+    "SampleAfterValue": "100000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCE",
+    "UMask": "0x0",
+    "EventName": "SIMD_INSTR_RETIRED",
+    "BriefDescription": "SIMD Instructions retired.",
+    "PublicDescription": "SIMD Instructions retired.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xCF",
+    "UMask": "0x0",
+    "EventName": "SIMD_SAT_INSTR_RETIRED",
+    "BriefDescription": "Saturated arithmetic instructions retired.",
+    "PublicDescription": "Saturated arithmetic instructions retired.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xDC",
+    "UMask": "0x2",
+    "EventName": "RESOURCE_STALLS.DIV_BUSY",
+    "BriefDescription": "Cycles issue is stalled due to div busy.",
+    "PublicDescription": "Cycles issue is stalled due to div busy.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xE0",
+    "UMask": "0x1",
+    "EventName": "BR_INST_DECODED",
+    "BriefDescription": "Branch instructions decoded",
+    "PublicDescription": "Branch instructions decoded",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xE4",
+    "UMask": "0x1",
+    "EventName": "BOGUS_BR",
+    "BriefDescription": "Bogus branches",
+    "PublicDescription": "Bogus branches",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0xE6",
+    "UMask": "0x1",
+    "EventName": "BACLEARS.ANY",
+    "BriefDescription": "BACLEARS asserted.",
+    "PublicDescription": "BACLEARS asserted.",
+    "Counter": "0,1",
+    "SampleAfterValue": "2000000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "REISSUE.OVERLAP_STORE",
+    "BriefDescription": "Micro-op reissues on a store-load collision",
+    "PublicDescription": "Micro-op reissues on a store-load collision",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  },
+  {
+    "EventCode": "0x3",
+    "UMask": "0x81",
+    "EventName": "REISSUE.OVERLAP_STORE.AR",
+    "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
+    "PublicDescription": "Micro-op reissues on a store-load collision (At Retirement)",
+    "Counter": "0,1",
+    "SampleAfterValue": "200000",
+    "MSRIndex": "0",
+    "MSRValue": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "AnyThread": "0",
+    "EdgeDetect": "0",
+    "PEBS": "0",
+    "Errata": "null",
+    "Offcore": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/BNL/Bonnell_core_V1.tsv b/x86data/perfmon_data/BNL/Bonnell_core_V1.tsv
new file mode 100644
index 0000000..8a80950
--- /dev/null
+++ b/x86data/perfmon_data/BNL/Bonnell_core_V1.tsv
@@ -0,0 +1,275 @@
+# Performance Monitoring Events for Intel Atom Processors - V1
+# 10/22/2013 11:51:49 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Errata	
+0x2	0x83	STORE_FORWARDS.ANY	All store forwards	0,1	200000	0	0	0	0	0	0	0	null	
+0x2	0x81	STORE_FORWARDS.GOOD	Good store forwards	0,1	200000	0	0	0	0	0	0	0	null	
+0x3	0x7F	REISSUE.ANY	Micro-op reissues for any cause	0,1	200000	0	0	0	0	0	0	0	null	
+0x3	0xFF	REISSUE.ANY.AR	Micro-op reissues for any cause (At Retirement)	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0xF	MISALIGN_MEM_REF.SPLIT	Memory references that cross an 8-byte boundary.	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x9	MISALIGN_MEM_REF.LD_SPLIT	Load splits	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0xA	MISALIGN_MEM_REF.ST_SPLIT	Store splits	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x8F	MISALIGN_MEM_REF.SPLIT.AR	Memory references that cross an 8-byte boundary (At Retirement)	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x89	MISALIGN_MEM_REF.LD_SPLIT.AR	Load splits (At Retirement)	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x8A	MISALIGN_MEM_REF.ST_SPLIT.AR	Store splits (Ar Retirement)	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x8C	MISALIGN_MEM_REF.RMW_SPLIT	ld-op-st splits	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x97	MISALIGN_MEM_REF.BUBBLE	Nonzero segbase 1 bubble	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x91	MISALIGN_MEM_REF.LD_BUBBLE	Nonzero segbase load 1 bubble	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x92	MISALIGN_MEM_REF.ST_BUBBLE	Nonzero segbase store 1 bubble	0,1	200000	0	0	0	0	0	0	0	null	
+0x5	0x94	MISALIGN_MEM_REF.RMW_BUBBLE	Nonzero segbase ld-op-st 1 bubble	0,1	200000	0	0	0	0	0	0	0	null	
+0x6	0x80	SEGMENT_REG_LOADS.ANY	Number of segment register loads.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7	0x81	PREFETCH.PREFETCHT0	Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7	0x82	PREFETCH.PREFETCHT1	Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7	0x84	PREFETCH.PREFETCHT2	Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7	0x86	PREFETCH.SW_L2	Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed	0,1	200000	0	0	0	0	0	0	0	null	
+0x7	0x88	PREFETCH.PREFETCHNTA	Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed	0,1	200000	0	0	0	0	0	0	0	null	
+0x7	0x10	PREFETCH.HW_PREFETCH	L1 hardware prefetch request	0,1	2000000	0	0	0	0	0	0	0	null	
+0x7	0xF	PREFETCH.SOFTWARE_PREFETCH	Any Software prefetch	0,1	200000	0	0	0	0	0	0	0	null	
+0x7	0x8F	PREFETCH.SOFTWARE_PREFETCH.AR	Any Software prefetch	0,1	200000	0	0	0	0	0	0	0	null	
+0x8	0x7	DATA_TLB_MISSES.DTLB_MISS	Memory accesses that missed the DTLB.	0,1	200000	0	0	0	0	0	0	0	null	
+0x8	0x5	DATA_TLB_MISSES.DTLB_MISS_LD	DTLB misses due to load operations.	0,1	200000	0	0	0	0	0	0	0	null	
+0x8	0x9	DATA_TLB_MISSES.L0_DTLB_MISS_LD	L0 DTLB misses due to load operations.	0,1	200000	0	0	0	0	0	0	0	null	
+0x8	0x6	DATA_TLB_MISSES.DTLB_MISS_ST	DTLB misses due to store operations.	0,1	200000	0	0	0	0	0	0	0	null	
+0x8	0xA	DATA_TLB_MISSES.L0_DTLB_MISS_ST	L0 DTLB misses due to store operations	0,1	200000	0	0	0	0	0	0	0	null	
+0x9	0x20	DISPATCH_BLOCKED.ANY	Memory cluster signals to block micro-op dispatch for any reason	0,1	200000	0	0	0	0	0	0	0	null	
+0xC	0x3	PAGE_WALKS.WALKS	Number of page-walks executed.	0,1	200000	0	0	0	0	0	0	0	null	
+0xC	0x3	PAGE_WALKS.CYCLES	Duration of page-walks in core cycles	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC	0x1	PAGE_WALKS.D_SIDE_WALKS	Number of D-side only page walks	0,1	200000	0	0	0	0	0	0	0	null	
+0xC	0x1	PAGE_WALKS.D_SIDE_CYCLES	Duration of D-side only page walks	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC	0x2	PAGE_WALKS.I_SIDE_WALKS	Number of I-Side page walks	0,1	200000	0	0	0	0	0	0	0	null	
+0xC	0x2	PAGE_WALKS.I_SIDE_CYCLES	Duration of I-Side page walks	0,1	2000000	0	0	0	0	0	0	0	null	
+0x10	0x1	X87_COMP_OPS_EXE.ANY.S	Floating point computational micro-ops executed.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x10	0x81	X87_COMP_OPS_EXE.ANY.AR	Floating point computational micro-ops retired.	0,1	2000000	0	0	0	0	0	0	2	null	
+0x10	0x2	X87_COMP_OPS_EXE.FXCH.S	FXCH uops executed.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x10	0x82	X87_COMP_OPS_EXE.FXCH.AR	FXCH uops retired.	0,1	2000000	0	0	0	0	0	0	2	null	
+0x11	0x1	FP_ASSIST.S	Floating point assists.	0,1	10000	0	0	0	0	0	0	0	null	
+0x11	0x81	FP_ASSIST.AR	Floating point assists for retired operations.	0,1	10000	0	0	0	0	0	0	0	null	
+0x12	0x1	MUL.S	Multiply operations executed.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x12	0x81	MUL.AR	Multiply operations retired	0,1	2000000	0	0	0	0	0	0	0	null	
+0x13	0x1	DIV.S	Divide operations executed.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x13	0x81	DIV.AR	Divide operations retired	0,1	2000000	0	0	0	0	0	0	0	null	
+0x14	0x1	CYCLES_DIV_BUSY	Cycles the divider is busy.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x21	0x40	L2_ADS.SELF	Cycles L2 address bus is in use.	0,1	200000	0	0	0	0	0	0	0	null	
+0x22	0x40	L2_DBUS_BUSY.SELF	Cycles the L2 cache data bus is busy.	0,1	200000	0	0	0	0	0	0	0	null	
+0x23	0x40	L2_DBUS_BUSY_RD.SELF	Cycles the L2 transfers data to the core.	0,1	200000	0	0	0	0	0	0	0	null	
+0x24	0x70	L2_LINES_IN.SELF.ANY	L2 cache misses.	0,1	200000	0	0	0	0	0	0	0	null	
+0x24	0x40	L2_LINES_IN.SELF.DEMAND	L2 cache misses.	0,1	200000	0	0	0	0	0	0	0	null	
+0x24	0x50	L2_LINES_IN.SELF.PREFETCH	L2 cache misses.	0,1	200000	0	0	0	0	0	0	0	null	
+0x25	0x40	L2_M_LINES_IN.SELF	L2 cache line modifications.	0,1	200000	0	0	0	0	0	0	0	null	
+0x26	0x70	L2_LINES_OUT.SELF.ANY	L2 cache lines evicted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x26	0x40	L2_LINES_OUT.SELF.DEMAND	L2 cache lines evicted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x26	0x50	L2_LINES_OUT.SELF.PREFETCH	L2 cache lines evicted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x27	0x70	L2_M_LINES_OUT.SELF.ANY	Modified lines evicted from the L2 cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x27	0x40	L2_M_LINES_OUT.SELF.DEMAND	Modified lines evicted from the L2 cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x27	0x50	L2_M_LINES_OUT.SELF.PREFETCH	Modified lines evicted from the L2 cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x28	0x44	L2_IFETCH.SELF.E_STATE	L2 cacheable instruction fetch requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x28	0x41	L2_IFETCH.SELF.I_STATE	L2 cacheable instruction fetch requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x28	0x48	L2_IFETCH.SELF.M_STATE	L2 cacheable instruction fetch requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x28	0x42	L2_IFETCH.SELF.S_STATE	L2 cacheable instruction fetch requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x28	0x4F	L2_IFETCH.SELF.MESI	L2 cacheable instruction fetch requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x74	L2_LD.SELF.ANY.E_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x71	L2_LD.SELF.ANY.I_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x78	L2_LD.SELF.ANY.M_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x72	L2_LD.SELF.ANY.S_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x7F	L2_LD.SELF.ANY.MESI	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x44	L2_LD.SELF.DEMAND.E_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x41	L2_LD.SELF.DEMAND.I_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x48	L2_LD.SELF.DEMAND.M_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x42	L2_LD.SELF.DEMAND.S_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x4F	L2_LD.SELF.DEMAND.MESI	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x54	L2_LD.SELF.PREFETCH.E_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x51	L2_LD.SELF.PREFETCH.I_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x58	L2_LD.SELF.PREFETCH.M_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x52	L2_LD.SELF.PREFETCH.S_STATE	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x29	0x5F	L2_LD.SELF.PREFETCH.MESI	L2 cache reads	0,1	200000	0	0	0	0	0	0	0	null	
+0x2A	0x44	L2_ST.SELF.E_STATE	L2 store requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2A	0x41	L2_ST.SELF.I_STATE	L2 store requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2A	0x48	L2_ST.SELF.M_STATE	L2 store requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2A	0x42	L2_ST.SELF.S_STATE	L2 store requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2A	0x4F	L2_ST.SELF.MESI	L2 store requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2B	0x44	L2_LOCK.SELF.E_STATE	L2 locked accesses	0,1	200000	0	0	0	0	0	0	0	null	
+0x2B	0x41	L2_LOCK.SELF.I_STATE	L2 locked accesses	0,1	200000	0	0	0	0	0	0	0	null	
+0x2B	0x48	L2_LOCK.SELF.M_STATE	L2 locked accesses	0,1	200000	0	0	0	0	0	0	0	null	
+0x2B	0x42	L2_LOCK.SELF.S_STATE	L2 locked accesses	0,1	200000	0	0	0	0	0	0	0	null	
+0x2B	0x4F	L2_LOCK.SELF.MESI	L2 locked accesses	0,1	200000	0	0	0	0	0	0	0	null	
+0x2C	0x44	L2_DATA_RQSTS.SELF.E_STATE	All data requests from the L1 data cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x2C	0x41	L2_DATA_RQSTS.SELF.I_STATE	All data requests from the L1 data cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x2C	0x48	L2_DATA_RQSTS.SELF.M_STATE	All data requests from the L1 data cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x2C	0x42	L2_DATA_RQSTS.SELF.S_STATE	All data requests from the L1 data cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x2C	0x4F	L2_DATA_RQSTS.SELF.MESI	All data requests from the L1 data cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x2D	0x44	L2_LD_IFETCH.SELF.E_STATE	All read requests from L1 instruction and data caches	0,1	200000	0	0	0	0	0	0	0	null	
+0x2D	0x41	L2_LD_IFETCH.SELF.I_STATE	All read requests from L1 instruction and data caches	0,1	200000	0	0	0	0	0	0	0	null	
+0x2D	0x48	L2_LD_IFETCH.SELF.M_STATE	All read requests from L1 instruction and data caches	0,1	200000	0	0	0	0	0	0	0	null	
+0x2D	0x42	L2_LD_IFETCH.SELF.S_STATE	All read requests from L1 instruction and data caches	0,1	200000	0	0	0	0	0	0	0	null	
+0x2D	0x4F	L2_LD_IFETCH.SELF.MESI	All read requests from L1 instruction and data caches	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x74	L2_RQSTS.SELF.ANY.E_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x71	L2_RQSTS.SELF.ANY.I_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x78	L2_RQSTS.SELF.ANY.M_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x72	L2_RQSTS.SELF.ANY.S_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x7F	L2_RQSTS.SELF.ANY.MESI	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x44	L2_RQSTS.SELF.DEMAND.E_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x41	L2_RQSTS.SELF.DEMAND.I_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x48	L2_RQSTS.SELF.DEMAND.M_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x42	L2_RQSTS.SELF.DEMAND.S_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x4F	L2_RQSTS.SELF.DEMAND.MESI	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x54	L2_RQSTS.SELF.PREFETCH.E_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x51	L2_RQSTS.SELF.PREFETCH.I_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x58	L2_RQSTS.SELF.PREFETCH.M_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x52	L2_RQSTS.SELF.PREFETCH.S_STATE	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x5F	L2_RQSTS.SELF.PREFETCH.MESI	L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x41	L2_RQSTS.SELF.DEMAND.I_STATE	L2 cache demand requests from this core that missed the L2	0,1	200000	0	0	0	0	0	0	0	null	
+0x2E	0x4F	L2_RQSTS.SELF.DEMAND.MESI	L2 cache demand requests from this core	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x74	L2_REJECT_BUSQ.SELF.ANY.E_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x71	L2_REJECT_BUSQ.SELF.ANY.I_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x78	L2_REJECT_BUSQ.SELF.ANY.M_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x72	L2_REJECT_BUSQ.SELF.ANY.S_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x7F	L2_REJECT_BUSQ.SELF.ANY.MESI	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x44	L2_REJECT_BUSQ.SELF.DEMAND.E_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x41	L2_REJECT_BUSQ.SELF.DEMAND.I_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x48	L2_REJECT_BUSQ.SELF.DEMAND.M_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x42	L2_REJECT_BUSQ.SELF.DEMAND.S_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x4F	L2_REJECT_BUSQ.SELF.DEMAND.MESI	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x54	L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x51	L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x58	L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x52	L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x30	0x5F	L2_REJECT_BUSQ.SELF.PREFETCH.MESI	Rejected L2 cache requests	0,1	200000	0	0	0	0	0	0	0	null	
+0x32	0x40	L2_NO_REQ.SELF	Cycles no L2 cache requests are pending	0,1	200000	0	0	0	0	0	0	0	null	
+0x3A	0x0	EIST_TRANS	Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions	0,1	200000	0	0	0	0	0	0	0	null	
+0x3B	0xC0	THERMAL_TRIP	Number of thermal trips	0,1	200000	0	0	0	0	0	0	0	null	
+0x3C	0x0	CPU_CLK_UNHALTED.CORE_P	Core cycles when core is not halted	0,1	2000000	0	0	0	0	0	0	0	null	
+0x3C	0x1	CPU_CLK_UNHALTED.BUS	Bus cycles when core is not halted	0,1	200000	0	0	0	0	0	0	0	null	
+0xA	0x0	CPU_CLK_UNHALTED.CORE	Core cycles when core is not halted	Fixed counter 2	2000000	0	0	0	0	0	0	0	null	
+0xA	0x0	CPU_CLK_UNHALTED.REF	Reference cycles when core is not halted.	Fixed counter 3	2000000	0	0	0	0	0	0	0	null	
+0x40	0xA1	L1D_CACHE.LD	L1 Cacheable Data Reads	0,1	2000000	0	0	0	0	0	0	0	null	
+0x40	0xA2	L1D_CACHE.ST	L1 Cacheable Data Writes	0,1	2000000	0	0	0	0	0	0	0	null	
+0x40	0x83	L1D_CACHE.ALL_REF	L1 Data reads and writes	0,1	2000000	0	0	0	0	0	0	0	null	
+0x40	0xA3	L1D_CACHE.ALL_CACHE_REF	L1 Data Cacheable reads and writes	0,1	2000000	0	0	0	0	0	0	0	null	
+0x40	0x8	L1D_CACHE.REPL	L1 Data line replacements	0,1	200000	0	0	0	0	0	0	0	null	
+0x40	0x48	L1D_CACHE.REPLM	Modified cache lines allocated in the L1 data cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x40	0x10	L1D_CACHE.EVICT	Modified cache lines evicted from the L1 data cache	0,1	200000	0	0	0	0	0	0	0	null	
+0x60	0xE0	BUS_REQUEST_OUTSTANDING.ALL_AGENTS	Outstanding cacheable data read bus requests duration.	0,1	200000	0	0	0	0	0	0	0	null	
+0x60	0x40	BUS_REQUEST_OUTSTANDING.SELF	Outstanding cacheable data read bus requests duration.	0,1	200000	0	0	0	0	0	0	0	null	
+0x61	0x20	BUS_BNR_DRV.ALL_AGENTS	Number of Bus Not Ready signals asserted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x61	0x0	BUS_BNR_DRV.THIS_AGENT	Number of Bus Not Ready signals asserted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x62	0x20	BUS_DRDY_CLOCKS.ALL_AGENTS	Bus cycles when data is sent on the bus.	0,1	200000	0	0	0	0	0	0	0	null	
+0x62	0x0	BUS_DRDY_CLOCKS.THIS_AGENT	Bus cycles when data is sent on the bus.	0,1	200000	0	0	0	0	0	0	0	null	
+0x63	0xE0	BUS_LOCK_CLOCKS.ALL_AGENTS	Bus cycles when a LOCK signal is asserted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x63	0x40	BUS_LOCK_CLOCKS.SELF	Bus cycles when a LOCK signal is asserted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x64	0x40	BUS_DATA_RCV.SELF	Bus cycles while processor receives data.	0,1	200000	0	0	0	0	0	0	0	null	
+0x65	0xE0	BUS_TRANS_BRD.ALL_AGENTS	Burst read bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x65	0x40	BUS_TRANS_BRD.SELF	Burst read bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x66	0xE0	BUS_TRANS_RFO.ALL_AGENTS	RFO bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x66	0x40	BUS_TRANS_RFO.SELF	RFO bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x67	0xE0	BUS_TRANS_WB.ALL_AGENTS	Explicit writeback bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x67	0x40	BUS_TRANS_WB.SELF	Explicit writeback bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x68	0xE0	BUS_TRANS_IFETCH.ALL_AGENTS	Instruction-fetch bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x68	0x40	BUS_TRANS_IFETCH.SELF	Instruction-fetch bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x69	0xE0	BUS_TRANS_INVAL.ALL_AGENTS	Invalidate bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x69	0x40	BUS_TRANS_INVAL.SELF	Invalidate bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6A	0xE0	BUS_TRANS_PWR.ALL_AGENTS	Partial write bus transaction.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6A	0x40	BUS_TRANS_PWR.SELF	Partial write bus transaction.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6B	0xE0	BUS_TRANS_P.ALL_AGENTS	Partial bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6B	0x40	BUS_TRANS_P.SELF	Partial bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6C	0xE0	BUS_TRANS_IO.ALL_AGENTS	IO bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6C	0x40	BUS_TRANS_IO.SELF	IO bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6D	0xE0	BUS_TRANS_DEF.ALL_AGENTS	Deferred bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6D	0x40	BUS_TRANS_DEF.SELF	Deferred bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6E	0xE0	BUS_TRANS_BURST.ALL_AGENTS	Burst (full cache-line) bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6E	0x40	BUS_TRANS_BURST.SELF	Burst (full cache-line) bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6F	0xE0	BUS_TRANS_MEM.ALL_AGENTS	Memory bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x6F	0x40	BUS_TRANS_MEM.SELF	Memory bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x70	0xE0	BUS_TRANS_ANY.ALL_AGENTS	All bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x70	0x40	BUS_TRANS_ANY.SELF	All bus transactions.	0,1	200000	0	0	0	0	0	0	0	null	
+0x77	0xB	EXT_SNOOP.THIS_AGENT.ANY	External snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x77	0x1	EXT_SNOOP.THIS_AGENT.CLEAN	External snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x77	0x2	EXT_SNOOP.THIS_AGENT.HIT	External snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x77	0x8	EXT_SNOOP.THIS_AGENT.HITM	External snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x77	0x2B	EXT_SNOOP.ALL_AGENTS.ANY	External snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x77	0x21	EXT_SNOOP.ALL_AGENTS.CLEAN	External snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x77	0x22	EXT_SNOOP.ALL_AGENTS.HIT	External snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x77	0x28	EXT_SNOOP.ALL_AGENTS.HITM	External snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7A	0x20	BUS_HIT_DRV.ALL_AGENTS	HIT signal asserted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7A	0x0	BUS_HIT_DRV.THIS_AGENT	HIT signal asserted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7B	0x20	BUS_HITM_DRV.ALL_AGENTS	HITM signal asserted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7B	0x0	BUS_HITM_DRV.THIS_AGENT	HITM signal asserted.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7D	0x40	BUSQ_EMPTY.SELF	Bus queue is empty.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7E	0xE0	SNOOP_STALL_DRV.ALL_AGENTS	Bus stalled for snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7E	0x40	SNOOP_STALL_DRV.SELF	Bus stalled for snoops.	0,1	200000	0	0	0	0	0	0	0	null	
+0x7F	0x40	BUS_IO_WAIT.SELF	IO requests waiting in the bus queue.	0,1	200000	0	0	0	0	0	0	0	null	
+0x80	0x3	ICACHE.ACCESSES	Instruction fetches.	0,1	200000	0	0	0	0	0	0	0	null	
+0x80	0x1	ICACHE.HIT	Icache hit	0,1	200000	0	0	0	0	0	0	0	null	
+0x80	0x2	ICACHE.MISSES	Icache miss	0,1	200000	0	0	0	0	0	0	0	null	
+0x82	0x1	ITLB.HIT	ITLB hits.	0,1	200000	0	0	0	0	0	0	0	null	
+0x82	0x4	ITLB.FLUSH	ITLB flushes.	0,1	200000	0	0	0	0	0	0	0	null	
+0x82	0x2	ITLB.MISSES	ITLB misses.	0,1	200000	0	0	0	0	0	0	2	null	
+0x86	0x1	CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED	Cycles during which instruction fetches are  stalled.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x87	0x1	DECODE_STALL.PFB_EMPTY	Decode stall due to PFB empty	0,1	2000000	0	0	0	0	0	0	0	null	
+0x87	0x2	DECODE_STALL.IQ_FULL	Decode stall due to IQ full	0,1	2000000	0	0	0	0	0	0	0	null	
+0x88	0x1	BR_INST_TYPE_RETIRED.COND	All macro conditional branch instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x88	0x2	BR_INST_TYPE_RETIRED.UNCOND	All macro unconditional branch instructions, excluding calls and indirects	0,1	2000000	0	0	0	0	0	0	0	null	
+0x88	0x4	BR_INST_TYPE_RETIRED.IND	All indirect branches that are not calls.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x88	0x8	BR_INST_TYPE_RETIRED.RET	All indirect branches that have a return mnemonic	0,1	2000000	0	0	0	0	0	0	0	null	
+0x88	0x10	BR_INST_TYPE_RETIRED.DIR_CALL	All non-indirect calls	0,1	2000000	0	0	0	0	0	0	0	null	
+0x88	0x20	BR_INST_TYPE_RETIRED.IND_CALL	All indirect calls, including both register and memory indirect.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x88	0x41	BR_INST_TYPE_RETIRED.COND_TAKEN	Only taken macro conditional branch instructions	0,1	2000000	0	0	0	0	0	0	0	null	
+0x89	0x1	BR_MISSP_TYPE_RETIRED.COND	Mispredicted cond branch instructions retired	0,1	200000	0	0	0	0	0	0	0	null	
+0x89	0x2	BR_MISSP_TYPE_RETIRED.IND	Mispredicted ind branches that are not calls	0,1	200000	0	0	0	0	0	0	0	null	
+0x89	0x4	BR_MISSP_TYPE_RETIRED.RETURN	Mispredicted return branches	0,1	200000	0	0	0	0	0	0	0	null	
+0x89	0x8	BR_MISSP_TYPE_RETIRED.IND_CALL	Mispredicted indirect calls, including both register and memory indirect. 	0,1	200000	0	0	0	0	0	0	0	null	
+0x89	0x11	BR_MISSP_TYPE_RETIRED.COND_TAKEN	Mispredicted and taken cond branch instructions retired	0,1	200000	0	0	0	0	0	0	0	null	
+0xAA	0x1	MACRO_INSTS.NON_CISC_DECODED	Non-CISC nacro instructions decoded	0,1	2000000	0	0	0	0	0	0	0	null	
+0xAA	0x2	MACRO_INSTS.CISC_DECODED	CISC macro instructions decoded	0,1	2000000	0	0	0	0	0	0	0	null	
+0xAA	0x3	MACRO_INSTS.ALL_DECODED	All Instructions decoded	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB0	0x0	SIMD_UOPS_EXEC.S	SIMD micro-ops executed (excluding stores).	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB0	0x80	SIMD_UOPS_EXEC.AR	SIMD micro-ops retired (excluding stores).	0,1	2000000	0	0	0	0	0	0	2	null	
+0xB1	0x0	SIMD_SAT_UOP_EXEC.S	SIMD saturated arithmetic micro-ops executed.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB1	0x80	SIMD_SAT_UOP_EXEC.AR	SIMD saturated arithmetic micro-ops retired.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x1	SIMD_UOP_TYPE_EXEC.MUL.S	SIMD packed multiply micro-ops executed	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x81	SIMD_UOP_TYPE_EXEC.MUL.AR	SIMD packed multiply micro-ops retired	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x2	SIMD_UOP_TYPE_EXEC.SHIFT.S	SIMD packed shift micro-ops executed	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x82	SIMD_UOP_TYPE_EXEC.SHIFT.AR	SIMD packed shift micro-ops retired	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x4	SIMD_UOP_TYPE_EXEC.PACK.S	SIMD packed micro-ops executed	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x84	SIMD_UOP_TYPE_EXEC.PACK.AR	SIMD packed micro-ops retired	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x8	SIMD_UOP_TYPE_EXEC.UNPACK.S	SIMD unpacked micro-ops executed	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x88	SIMD_UOP_TYPE_EXEC.UNPACK.AR	SIMD unpacked micro-ops retired	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x10	SIMD_UOP_TYPE_EXEC.LOGICAL.S	SIMD packed logical micro-ops executed	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x90	SIMD_UOP_TYPE_EXEC.LOGICAL.AR	SIMD packed logical micro-ops retired	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0x20	SIMD_UOP_TYPE_EXEC.ARITHMETIC.S	SIMD packed arithmetic micro-ops executed	0,1	2000000	0	0	0	0	0	0	0	null	
+0xB3	0xA0	SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR	SIMD packed arithmetic micro-ops retired	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC0	0x0	INST_RETIRED.ANY_P	Instructions retired (precise event).	0,1	2000000	0	0	0	0	0	0	2	null	
+0xA	0x0	INST_RETIRED.ANY	Instructions retired.	Fixed counter 1	2000000	0	0	0	0	0	0	0	null	
+0xC2	0x10	UOPS_RETIRED.ANY	Micro-ops retired.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC2	0x10	UOPS_RETIRED.STALLED_CYCLES	Cycles no micro-ops retired.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC2	0x10	UOPS_RETIRED.STALLS	Periods no micro-ops retired.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xA9	0x1	UOPS.MS_CYCLES	This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. 	0,1	2000000	0	0	1	0	0	0	0	null	
+0xC3	0x1	MACHINE_CLEARS.SMC	Self-Modifying Code detected.	0,1	200000	0	0	0	0	0	0	0	null	
+0xC4	0x0	BR_INST_RETIRED.ANY	Retired branch instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC4	0x1	BR_INST_RETIRED.PRED_NOT_TAKEN	Retired branch instructions that were predicted not-taken.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC4	0x2	BR_INST_RETIRED.MISPRED_NOT_TAKEN	Retired branch instructions that were mispredicted not-taken.	0,1	200000	0	0	0	0	0	0	0	null	
+0xC4	0x4	BR_INST_RETIRED.PRED_TAKEN	Retired branch instructions that were predicted taken.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC4	0x8	BR_INST_RETIRED.MISPRED_TAKEN	Retired branch instructions that were mispredicted taken.	0,1	200000	0	0	0	0	0	0	0	null	
+0xC4	0xC	BR_INST_RETIRED.TAKEN	Retired taken branch instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC4	0xF	BR_INST_RETIRED.ANY1	Retired branch instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC5	0x0	BR_INST_RETIRED.MISPRED	Retired mispredicted branch instructions (precise event).	0,1	200000	0	0	0	0	0	0	1	null	
+0xC6	0x1	CYCLES_INT_MASKED.CYCLES_INT_MASKED	Cycles during which interrupts are disabled.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC6	0x2	CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED	Cycles during which interrupts are pending and disabled.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC7	0x1	SIMD_INST_RETIRED.PACKED_SINGLE	Retired Streaming SIMD Extensions (SSE) packed-single instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC7	0x2	SIMD_INST_RETIRED.SCALAR_SINGLE	Retired Streaming SIMD Extensions (SSE) scalar-single instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC7	0x8	SIMD_INST_RETIRED.SCALAR_DOUBLE	Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC7	0x10	SIMD_INST_RETIRED.VECTOR	Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xC8	0x0	HW_INT_RCV	Hardware interrupts received.	0,1	200000	0	0	0	0	0	0	0	null	
+0xCA	0x1	SIMD_COMP_INST_RETIRED.PACKED_SINGLE	Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xCA	0x2	SIMD_COMP_INST_RETIRED.SCALAR_SINGLE	Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xCA	0x8	SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE	Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xCB	0x1	MEM_LOAD_RETIRED.L2_HIT	Retired loads that hit the L2 cache (precise event).	0,1	200000	0	0	0	0	0	0	0	null	
+0xCB	0x2	MEM_LOAD_RETIRED.L2_MISS	Retired loads that miss the L2 cache	0,1	10000	0	0	0	0	0	0	0	null	
+0xCB	0x4	MEM_LOAD_RETIRED.DTLB_MISS	Retired loads that miss the DTLB (precise event).	0,1	200000	0	0	0	0	0	0	1	null	
+0xCD	0x0	SIMD_ASSIST	SIMD assists invoked.	0,1	100000	0	0	0	0	0	0	0	null	
+0xCE	0x0	SIMD_INSTR_RETIRED	SIMD Instructions retired.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xCF	0x0	SIMD_SAT_INSTR_RETIRED	Saturated arithmetic instructions retired.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xDC	0x2	RESOURCE_STALLS.DIV_BUSY	Cycles issue is stalled due to div busy.	0,1	2000000	0	0	0	0	0	0	0	null	
+0xE0	0x1	BR_INST_DECODED	Branch instructions decoded	0,1	2000000	0	0	0	0	0	0	0	null	
+0xE4	0x1	BOGUS_BR	Bogus branches	0,1	2000000	0	0	0	0	0	0	0	null	
+0xE6	0x1	BACLEARS.ANY	BACLEARS asserted.	0,1	2000000	0	0	0	0	0	0	0	null	
+0x3	0x1	REISSUE.OVERLAP_STORE	Micro-op reissues on a store-load collision	0,1	200000	0	0	0	0	0	0	0	null	
+0x3	0x81	REISSUE.OVERLAP_STORE.AR	Micro-op reissues on a store-load collision (At Retirement)	0,1	200000	0	0	0	0	0	0	0	null	
diff --git a/x86data/perfmon_data/HSW/Haswell_core_V20.json b/x86data/perfmon_data/HSW/Haswell_core_V20.json
new file mode 100644
index 0000000..47cbe2e
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_core_V20.json
@@ -0,0 +1,8032 @@
+[

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired from execution.",

+    "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.\n",

+    "Counter": "Fixed counter 1",

+    "CounterHTOff": "Fixed counter 1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Core cycles when the thread is not in halt state.",

+    "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. \n",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Reference cycles when the core is not in halt state.",

+    "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.",

+    "Counter": "Fixed counter 3",

+    "CounterHTOff": "Fixed counter 3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "LD_BLOCKS.STORE_FORWARD",

+    "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded",

+    "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS.NO_SR",

+    "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",

+    "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "MISALIGN_MEM_REF.LOADS",

+    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "MISALIGN_MEM_REF.STORES",

+    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies in MOB due to partial compare on address.",

+    "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x01",

+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Load misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Load misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x02",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x04",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x40",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",

+    "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M)",

+    "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x80",

+    "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",

+    "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",

+    "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES",

+    "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.... ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x10",

+    "EventName": "UOPS_ISSUED.FLAGS_MERGE",

+    "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",

+    "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x20",

+    "EventName": "UOPS_ISSUED.SLOW_LEA",

+    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x40",

+    "EventName": "UOPS_ISSUED.SINGLE_MUL",

+    "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "PublicDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x02",

+    "EventName": "ARITH.DIVIDER_UOPS",

+    "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",

+    "PublicDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x21",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",

+    "BriefDescription": "Demand Data Read miss L2, no rejects",

+    "PublicDescription": "Demand Data Read miss L2, no rejects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x41",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",

+    "BriefDescription": "Demand Data Read requests that hit L2 cache",

+    "PublicDescription": "Demand Data Read requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.L2_PF_MISS",

+    "BriefDescription": "L2 prefetch requests that miss L2 cache",

+    "PublicDescription": "L2 prefetch requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x50",

+    "EventName": "L2_RQSTS.L2_PF_HIT",

+    "BriefDescription": "L2 prefetch requests that hit L2 cache",

+    "PublicDescription": "L2 prefetch requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE1",

+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests",

+    "PublicDescription": "Demand Data Read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE2",

+    "EventName": "L2_RQSTS.ALL_RFO",

+    "BriefDescription": "RFO requests to L2 cache",

+    "PublicDescription": "RFO requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE4",

+    "EventName": "L2_RQSTS.ALL_CODE_RD",

+    "BriefDescription": "L2 code requests",

+    "PublicDescription": "L2 code requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xF8",

+    "EventName": "L2_RQSTS.ALL_PF",

+    "BriefDescription": "Requests from L2 hardware prefetchers",

+    "PublicDescription": "Requests from L2 hardware prefetchers",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x50",

+    "EventName": "L2_DEMAND_RQSTS.WB_HIT",

+    "BriefDescription": "Not rejected writebacks that hit L2 cache",

+    "PublicDescription": "Not rejected writebacks that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2e",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Core-originated cacheable demand requests missed L3",

+    "PublicDescription": "Core-originated cacheable demand requests missed L3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2e",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Core-originated cacheable demand requests that refer to L3",

+    "PublicDescription": "Core-originated cacheable demand requests that refer to L3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",

+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",

+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",

+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING",

+    "BriefDescription": "L1D miss oustandings duration in cycles",

+    "PublicDescription": "L1D miss oustandings duration in cycles",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",

+    "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e",

+    "PublicDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",

+    "BriefDescription": "Cycles with L1D load Misses outstanding.",

+    "PublicDescription": "Cycles with L1D load Misses outstanding.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x01",

+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x02",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",

+    "PublicDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x04",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x20",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x40",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",

+    "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M)",

+    "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x80",

+    "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",

+    "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",

+    "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4c",

+    "UMask": "0x01",

+    "EventName": "LOAD_HIT_PRE.SW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4c",

+    "UMask": "0x02",

+    "EventName": "LOAD_HIT_PRE.HW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4f",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Cycle count for an Extended Page table walk.",

+    "PublicDescription": "Cycle count for an Extended Page table walk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x01",

+    "EventName": "L1D.REPLACEMENT",

+    "BriefDescription": "L1D data line replacements",

+    "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x01",

+    "EventName": "TX_MEM.ABORT_CONFLICT",

+    "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",

+    "PublicDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x02",

+    "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",

+    "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",

+    "PublicDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x04",

+    "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",

+    "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",

+    "PublicDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x08",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x10",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x20",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x40",

+    "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",

+    "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",

+    "PublicDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x01",

+    "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x02",

+    "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x04",

+    "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x08",

+    "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0",

+    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

+    "PublicDescription": "Unhalted core cycles when the thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x02",

+    "EventName": "CPL_CYCLES.RING123",

+    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "PublicDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0_TRANS",

+    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "PublicDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x01",

+    "EventName": "TX_EXEC.MISC1",

+    "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",

+    "PublicDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x02",

+    "EventName": "TX_EXEC.MISC2",

+    "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",

+    "PublicDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x04",

+    "EventName": "TX_EXEC.MISC3",

+    "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",

+    "PublicDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x08",

+    "EventName": "TX_EXEC.MISC4",

+    "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",

+    "PublicDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x10",

+    "EventName": "TX_EXEC.MISC5",

+    "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",

+    "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_CYCLES",

+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",

+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "PublicDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",

+    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x01",

+    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "PublicDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x02",

+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1D is locked",

+    "PublicDescription": "Cycles when L1D is locked",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x02",

+    "EventName": "IDQ.EMPTY",

+    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "PublicDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_UOPS",

+    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x20",

+    "EventName": "IDQ.MS_MITE_UOPS",

+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_CYCLES",

+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_OCCUR",

+    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles MITE is delivering 4 Uops",

+    "PublicDescription": "Cycles MITE is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles MITE is delivering any Uop",

+    "PublicDescription": "Cycles MITE is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x3c",

+    "EventName": "IDQ.MITE_ALL_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x01",

+    "EventName": "ICACHE.HIT",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x02",

+    "EventName": "ICACHE.MISSES",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",

+    "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x04",

+    "EventName": "ICACHE.IFETCH_STALL",

+    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x01",

+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Misses at all ITLB levels that cause page walks",

+    "PublicDescription": "Misses at all ITLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x02",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",

+    "PublicDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x04",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",

+    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",

+    "PublicDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x10",

+    "EventName": "ITLB_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x40",

+    "EventName": "ITLB_MISSES.STLB_HIT_2M",

+    "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M)",

+    "PublicDescription": "Code misses that miss the  DTLB and hit the STLB (2M)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x01",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

+    "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x04",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Stall cycles because IQ is full",

+    "PublicDescription": "Stall cycles because IQ is full",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x41",

+    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken macro-conditional branches",

+    "PublicDescription": "Not taken macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x81",

+    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired macro-conditional branches",

+    "PublicDescription": "Taken speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x82",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",

+    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x84",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x88",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x90",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired direct near calls",

+    "PublicDescription": "Taken speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xA0",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired indirect calls",

+    "PublicDescription": "Taken speculative and retired indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC1",

+    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired macro-conditional branches",

+    "PublicDescription": "Speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC2",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",

+    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC4",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC8",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Speculative and retired indirect return branches.",

+    "PublicDescription": "Speculative and retired indirect return branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xD0",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired direct near calls",

+    "PublicDescription": "Speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xFF",

+    "EventName": "BR_INST_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired  branches",

+    "PublicDescription": "Speculative and retired  branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x41",

+    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x81",

+    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x84",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x88",

+    "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC1",

+    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC4",

+    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xFF",

+    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9c",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",

+    "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled.  This event is counted on a per-core basis.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "PublicDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are executed in port 0",

+    "PublicDescription": "Cycles per thread when uops are executed in port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are executed in port 1",

+    "PublicDescription": "Cycles per thread when uops are executed in port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when uops are executed in port 2",

+    "PublicDescription": "Cycles per thread when uops are executed in port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when uops are executed in port 3",

+    "PublicDescription": "Cycles per thread when uops are executed in port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are executed in port 4",

+    "PublicDescription": "Cycles per thread when uops are executed in port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are executed in port 5",

+    "PublicDescription": "Cycles per thread when uops are executed in port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_6",

+    "BriefDescription": "Cycles per thread when uops are executed in port 6",

+    "PublicDescription": "Cycles per thread when uops are executed in port 6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_7",

+    "BriefDescription": "Cycles per thread when uops are executed in port 7",

+    "PublicDescription": "Cycles per thread when uops are executed in port 7",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x01",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource-related stall cycles",

+    "PublicDescription": "Resource-related stall cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x04",

+    "EventName": "RESOURCE_STALLS.RS",

+    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",

+    "PublicDescription": "Cycles stalled due to no eligible RS entry available.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x08",

+    "EventName": "RESOURCE_STALLS.SB",

+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB",

+    "BriefDescription": "Cycles stalled due to re-order buffer full.",

+    "PublicDescription": "Cycles stalled due to re-order buffer full.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",

+    "BriefDescription": "Cycles with pending L2 cache miss loads.",

+    "PublicDescription": "Cycles with pending L2 cache miss loads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",

+    "BriefDescription": "Cycles with pending L1 cache miss loads.",

+    "PublicDescription": "Cycles with pending L1 cache miss loads.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",

+    "BriefDescription": "Cycles with pending memory loads.",

+    "PublicDescription": "Cycles with pending memory loads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",

+    "BriefDescription": "Total execution stalls",

+    "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",

+    "BriefDescription": "Execution stalls due to L2 cache misses.",

+    "PublicDescription": "Execution stalls due to L2 cache misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",

+    "BriefDescription": "Execution stalls due to memory subsystem.",

+    "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",

+    "BriefDescription": "Execution stalls due to L1 data cache misses",

+    "PublicDescription": "Execution stalls due to L1 data cache misses",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xa8",

+    "UMask": "0x01",

+    "EventName": "LSD.UOPS",

+    "BriefDescription": "Number of Uops delivered by the LSD.",

+    "PublicDescription": "Number of Uops delivered by the LSD.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x02",

+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xae",

+    "UMask": "0x01",

+    "EventName": "ITLB.ITLB_FLUSH",

+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "PublicDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests sent to uncore",

+    "PublicDescription": "Demand Data Read requests sent to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

+    "BriefDescription": "Cacheable and noncachaeble code read requests",

+    "PublicDescription": "Cacheable and noncachaeble code read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",

+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "PublicDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",

+    "BriefDescription": "Demand and prefetch data reads",

+    "PublicDescription": "Demand and prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE",

+    "BriefDescription": "Number of uops executed on the core.",

+    "PublicDescription": "Number of uops executed on the core.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.STALL_CYCLES",

+    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "PublicDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb2",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",

+    "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",

+    "PublicDescription": "Offcore requests buffer cannot take more entries for this thread core.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x11",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L1",

+    "BriefDescription": "Number of DTLB page walker hits in the L1+FB",

+    "PublicDescription": "Number of DTLB page walker hits in the L1+FB",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x21",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L1",

+    "BriefDescription": "Number of ITLB page walker hits in the L1+FB",

+    "PublicDescription": "Number of ITLB page walker hits in the L1+FB",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x41",

+    "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x81",

+    "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x12",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L2",

+    "BriefDescription": "Number of DTLB page walker hits in the L2",

+    "PublicDescription": "Number of DTLB page walker hits in the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x22",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L2",

+    "BriefDescription": "Number of ITLB page walker hits in the L2",

+    "PublicDescription": "Number of ITLB page walker hits in the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x42",

+    "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x82",

+    "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x14",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L3",

+    "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",

+    "PublicDescription": "Number of DTLB page walker hits in the L3 + XSNP",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x24",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L3",

+    "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",

+    "PublicDescription": "Number of ITLB page walker hits in the L3 + XSNP",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x44",

+    "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x84",

+    "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x18",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",

+    "BriefDescription": "Number of DTLB page walker hits in Memory",

+    "PublicDescription": "Number of DTLB page walker hits in Memory",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x28",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",

+    "BriefDescription": "Number of ITLB page walker hits in Memory",

+    "PublicDescription": "Number of ITLB page walker hits in Memory",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x48",

+    "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x88",

+    "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x01",

+    "EventName": "TLB_FLUSH.DTLB_THREAD",

+    "BriefDescription": "DTLB flush attempts of the thread-specific entries",

+    "PublicDescription": "DTLB flush attempts of the thread-specific entries",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x20",

+    "EventName": "TLB_FLUSH.STLB_ANY",

+    "BriefDescription": "STLB flush attempts",

+    "PublicDescription": "STLB flush attempts",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",

+    "PublicDescription": "Number of instructions retired. General Counter   - architectural event",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.PREC_DIST",

+    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "Counter": "1",

+    "CounterHTOff": "1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x08",

+    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

+    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "PublicDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM57",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x10",

+    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

+    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "PublicDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM57",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x40",

+    "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",

+    "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "PublicDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.ALL",

+    "BriefDescription": "Actually retired uops.",

+    "PublicDescription": "Actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x02",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used.",

+    "PublicDescription": "This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops.",

+    "PublicDescription": "Cycles without actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Cycles with less than 10 actually retired uops.",

+    "PublicDescription": "Cycles with less than 10 actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "10",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops.",

+    "PublicDescription": "Cycles without actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.CYCLES",

+    "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",

+    "PublicDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-modifying code (SMC) detected.",

+    "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x20",

+    "EventName": "MACHINE_CLEARS.MASKMOV",

+    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",

+    "PublicDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x01",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Conditional branch instructions retired.",

+    "PublicDescription": "Conditional branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x02",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect near call instructions retired.",

+    "PublicDescription": "Direct and indirect near call instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All (macro) branch instructions retired.",

+    "PublicDescription": "All (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x08",

+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",

+    "BriefDescription": "Return instructions retired.",

+    "PublicDescription": "Return instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x10",

+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Not taken branch instructions retired.",

+    "PublicDescription": "Not taken branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x20",

+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "Taken branch instructions retired.",

+    "PublicDescription": "Taken branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x40",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Far branch instructions retired.",

+    "PublicDescription": "Far branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x04",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "All (macro) branch instructions retired. ",

+    "PublicDescription": "All (macro) branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x01",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional branch instructions retired.",

+    "PublicDescription": "Mispredicted conditional branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All mispredicted macro branch instructions retired.",

+    "PublicDescription": "All mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x04",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "Mispredicted macro branch instructions retired. ",

+    "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x01",

+    "EventName": "HLE_RETIRED.START",

+    "BriefDescription": "Number of times an HLE execution started.",

+    "PublicDescription": "Number of times an HLE execution started.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x02",

+    "EventName": "HLE_RETIRED.COMMIT",

+    "BriefDescription": "Number of times an HLE execution successfully committed",

+    "PublicDescription": "Number of times an HLE execution successfully committed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x04",

+    "EventName": "HLE_RETIRED.ABORTED",

+    "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",

+    "PublicDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x08",

+    "EventName": "HLE_RETIRED.ABORTED_MISC1",

+    "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "PublicDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x10",

+    "EventName": "HLE_RETIRED.ABORTED_MISC2",

+    "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",

+    "PublicDescription": "Number of times an HLE execution aborted due to uncommon conditions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x20",

+    "EventName": "HLE_RETIRED.ABORTED_MISC3",

+    "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",

+    "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x40",

+    "EventName": "HLE_RETIRED.ABORTED_MISC4",

+    "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",

+    "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x80",

+    "EventName": "HLE_RETIRED.ABORTED_MISC5",

+    "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",

+    "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x01",

+    "EventName": "RTM_RETIRED.START",

+    "BriefDescription": "Number of times an RTM execution started.",

+    "PublicDescription": "Number of times an RTM execution started.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x02",

+    "EventName": "RTM_RETIRED.COMMIT",

+    "BriefDescription": "Number of times an RTM execution successfully committed",

+    "PublicDescription": "Number of times an RTM execution successfully committed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x04",

+    "EventName": "RTM_RETIRED.ABORTED",

+    "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",

+    "PublicDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x08",

+    "EventName": "RTM_RETIRED.ABORTED_MISC1",

+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",

+    "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x10",

+    "EventName": "RTM_RETIRED.ABORTED_MISC2",

+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x20",

+    "EventName": "RTM_RETIRED.ABORTED_MISC3",

+    "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",

+    "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x40",

+    "EventName": "RTM_RETIRED.ABORTED_MISC4",

+    "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",

+    "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x80",

+    "EventName": "RTM_RETIRED.ABORTED_MISC5",

+    "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",

+    "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x02",

+    "EventName": "FP_ASSIST.X87_OUTPUT",

+    "BriefDescription": "Number of X87 assists due to output value.",

+    "PublicDescription": "Number of X87 assists due to output value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x04",

+    "EventName": "FP_ASSIST.X87_INPUT",

+    "BriefDescription": "Number of X87 assists due to input value.",

+    "PublicDescription": "Number of X87 assists due to input value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x08",

+    "EventName": "FP_ASSIST.SIMD_OUTPUT",

+    "BriefDescription": "Number of SIMD FP assists due to Output values",

+    "PublicDescription": "Number of SIMD FP assists due to Output values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x10",

+    "EventName": "FP_ASSIST.SIMD_INPUT",

+    "BriefDescription": "Number of SIMD FP assists due to input values",

+    "PublicDescription": "Number of SIMD FP assists due to input values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x1E",

+    "EventName": "FP_ASSIST.ANY",

+    "BriefDescription": "Cycles with any input/output SSE or FP assist",

+    "PublicDescription": "Cycles with any input/output SSE or FP assist",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x20",

+    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",

+    "BriefDescription": "Count cases of saving new LBR",

+    "PublicDescription": "Count cases of saving new LBR",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

+    "BriefDescription": "Loads with latency value being above 4",

+    "PublicDescription": "Loads with latency value being above 4",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

+    "BriefDescription": "Loads with latency value being above 8",

+    "PublicDescription": "Loads with latency value being above 8",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

+    "BriefDescription": "Loads with latency value being above 16",

+    "PublicDescription": "Loads with latency value being above 16",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

+    "BriefDescription": "Loads with latency value being above 32",

+    "PublicDescription": "Loads with latency value being above 32",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

+    "BriefDescription": "Loads with latency value being above 64",

+    "PublicDescription": "Loads with latency value being above 64",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

+    "BriefDescription": "Loads with latency value being above 128",

+    "PublicDescription": "Loads with latency value being above 128",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "1009",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

+    "BriefDescription": "Loads with latency value being above 256",

+    "PublicDescription": "Loads with latency value being above 256",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "503",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

+    "BriefDescription": "Loads with latency value being above 512",

+    "PublicDescription": "Loads with latency value being above 512",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "101",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x11",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",

+    "BriefDescription": "Retired load uops that miss the STLB.",

+    "PublicDescription": "Retired load uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x12",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",

+    "BriefDescription": "Retired store uops that miss the STLB.",

+    "PublicDescription": "Retired store uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x21",

+    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",

+    "BriefDescription": "Retired load uops with locked access.",

+    "PublicDescription": "Retired load uops with locked access.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x41",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",

+    "BriefDescription": "Retired load uops that split across a cacheline boundary.",

+    "PublicDescription": "Retired load uops that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x42",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",

+    "BriefDescription": "Retired store uops that split across a cacheline boundary.",

+    "PublicDescription": "Retired store uops that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x81",

+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

+    "BriefDescription": "All retired load uops.",

+    "PublicDescription": "All retired load uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x82",

+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

+    "BriefDescription": "All retired store uops.",

+    "PublicDescription": "All retired store uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",

+    "BriefDescription": "Retired load uops with L1 cache hits as data sources.",

+    "PublicDescription": "Retired load uops with L1 cache hits as data sources.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

+    "BriefDescription": "Retired load uops with L2 cache hits as data sources.",

+    "PublicDescription": "Retired load uops with L2 cache hits as data sources.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",

+    "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",

+    "PublicDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",

+    "BriefDescription": "Retired load uops misses in L1 cache as data sources.",

+    "PublicDescription": "Retired load uops misses in L1 cache as data sources.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",

+    "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",

+    "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",

+    "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",

+    "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",

+    "PublicDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",

+    "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",

+    "PublicDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",

+    "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",

+    "PublicDescription": "Retired load uops which data sources were HitM responses from shared L3.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",

+    "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",

+    "PublicDescription": "Retired load uops which data sources were hits in L3 without snoops required.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Thread cycles when thread is not in halt state",

+    "PublicDescription": "Thread cycles when thread is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x01",

+    "EventName": "L2_TRANS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests that access L2 cache",

+    "PublicDescription": "Demand Data Read requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x02",

+    "EventName": "L2_TRANS.RFO",

+    "BriefDescription": "RFO requests that access L2 cache",

+    "PublicDescription": "RFO requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x04",

+    "EventName": "L2_TRANS.CODE_RD",

+    "BriefDescription": "L2 cache accesses when fetching instructions",

+    "PublicDescription": "L2 cache accesses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x08",

+    "EventName": "L2_TRANS.ALL_PF",

+    "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",

+    "PublicDescription": "L2 or L3 HW prefetches that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANS.L1D_WB",

+    "BriefDescription": "L1D writebacks that access L2 cache",

+    "PublicDescription": "L1D writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANS.L2_FILL",

+    "BriefDescription": "L2 fill requests that access L2 cache",

+    "PublicDescription": "L2 fill requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANS.L2_WB",

+    "BriefDescription": "L2 writebacks that access L2 cache",

+    "PublicDescription": "L2 writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANS.ALL_REQUESTS",

+    "BriefDescription": "Transactions accessing L2 pipe",

+    "PublicDescription": "Transactions accessing L2 pipe",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_IN.I",

+    "BriefDescription": "L2 cache lines in I state filling L2",

+    "PublicDescription": "L2 cache lines in I state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_IN.S",

+    "BriefDescription": "L2 cache lines in S state filling L2",

+    "PublicDescription": "L2 cache lines in S state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_IN.E",

+    "BriefDescription": "L2 cache lines in E state filling L2",

+    "PublicDescription": "L2 cache lines in E state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x07",

+    "EventName": "L2_LINES_IN.ALL",

+    "BriefDescription": "L2 cache lines filling L2",

+    "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x05",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by demand",

+    "PublicDescription": "Clean L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x06",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by demand",

+    "PublicDescription": "Dirty L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xA0",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect calls",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 0",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 1",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 2",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 3",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 4",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 5",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 6",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 7",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 7",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",

+    "PublicDescription": "number of near branch instructions retired that were mispredicted and taken.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x0e",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x60",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x42",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "RFO requests that hit L2 cache",

+    "PublicDescription": "RFO requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x22",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "RFO requests that miss L2 cache",

+    "PublicDescription": "RFO requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x44",

+    "EventName": "L2_RQSTS.CODE_RD_HIT",

+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",

+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x24",

+    "EventName": "L2_RQSTS.CODE_RD_MISS",

+    "BriefDescription": "L2 cache misses when fetching instructions",

+    "PublicDescription": "L2 cache misses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x27",

+    "EventName": "L2_RQSTS.ALL_DEMAND_MISS",

+    "BriefDescription": "Demand requests that miss L2 cache",

+    "PublicDescription": "Demand requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xe7",

+    "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",

+    "BriefDescription": "Demand requests to L2 cache",

+    "PublicDescription": "Demand requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3F",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All requests that miss L2 cache",

+    "PublicDescription": "All requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "PublicDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x0e",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x60",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",

+    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x0e",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Misses in all ITLB levels that cause completed page walks",

+    "PublicDescription": "Misses in all ITLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x60",

+    "EventName": "ITLB_MISSES.STLB_HIT",

+    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",

+    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",

+    "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",

+    "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",

+    "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 4 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xe6",

+    "UMask": "0x1f",

+    "EventName": "BACLEARS.ANY",

+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE",

+    "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.COUNT",

+    "BriefDescription": "Number of machine clears (nukes) of any type. ",

+    "PublicDescription": "Number of machine clears (nukes) of any type. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_ACTIVE",

+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_4_UOPS",

+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_END",

+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_SWITCHES",

+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are executed in port 0",

+    "PublicDescription": "Cycles per thread when uops are executed in port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are executed in port 1",

+    "PublicDescription": "Cycles per thread when uops are executed in port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when uops are executed in port 2",

+    "PublicDescription": "Cycles per thread when uops are executed in port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when uops are executed in port 3",

+    "PublicDescription": "Cycles per thread when uops are executed in port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are executed in port 4",

+    "PublicDescription": "Cycles per thread when uops are executed in port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are executed in port 5",

+    "PublicDescription": "Cycles per thread when uops are executed in port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_6",

+    "BriefDescription": "Cycles per thread when uops are executed in port 6",

+    "PublicDescription": "Cycles per thread when uops are executed in port 6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_7",

+    "BriefDescription": "Cycles per thread when uops are executed in port 7",

+    "PublicDescription": "Cycles per thread when uops are executed in port 7",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",

+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",

+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",

+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",

+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",

+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",

+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",

+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",

+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.FB_FULL",

+    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x07",

+    "EventName": "AVX_INSTS.ALL",

+    "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",

+    "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x04",

+    "EventName": "ICACHE.IFDATA_STALL",

+    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all requests that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc08fff",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all requests that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c8fff",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01004007f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc007f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c07f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c07f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts demand data reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/HSW/Haswell_core_V20.tsv b/x86data/perfmon_data/HSW/Haswell_core_V20.tsv
new file mode 100644
index 0000000..7091fe3
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_core_V20.tsv
@@ -0,0 +1,329 @@
+# Performance Monitoring Events for the Fourth Generation Intel Core Processors Based on the Haswell Microarchitecture - V20
+# 8/3/2015 11:45:18 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state.	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	loads blocked by overlapping with store buffer that cannot be forwarded	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x03	0x08	LD_BLOCKS.NO_SR	The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare on address.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x01	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Load misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x04	DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x10	DTLB_LOAD_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x20	DTLB_LOAD_MISSES.STLB_HIT_4K	Load misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x40	DTLB_LOAD_MISSES.STLB_HIT_2M	Load misses that miss the  DTLB and hit the STLB (2M)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x80	DTLB_LOAD_MISSES.PDE_CACHE_MISS	DTLB demand load misses with low part of linear-to-physical address translation missed	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x10	UOPS_ISSUED.FLAGS_MERGE	Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x20	UOPS_ISSUED.SLOW_LEA	Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x40	UOPS_ISSUED.SINGLE_MUL	Number of Multiply packed/scalar single precision uops allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	0	null
+0x14	0x02	ARITH.DIVIDER_UOPS	Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x21	L2_RQSTS.DEMAND_DATA_RD_MISS	Demand Data Read miss L2, no rejects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x41	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x30	L2_RQSTS.L2_PF_MISS	L2 prefetch requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x50	L2_RQSTS.L2_PF_HIT	L2 prefetch requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE1	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE2	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE4	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xF8	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x27	0x50	L2_DEMAND_RQSTS.WB_HIT	Not rejected writebacks that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x2e	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x2e	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x3c	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x3c	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other thread is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	2	2	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x48	0x02	L1D_PEND_MISS.REQUEST_FB_FULL	Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding.	2	2	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Store miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x04	DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M	Store misses in all DTLB levels that cause completed page walks (2M/4M)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x10	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x20	DTLB_STORE_MISSES.STLB_HIT_4K	Store misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x40	DTLB_STORE_MISSES.STLB_HIT_2M	Store misses that miss the  DTLB and hit the STLB (2M)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x80	DTLB_STORE_MISSES.PDE_CACHE_MISS	DTLB store misses with low part of linear-to-physical address translation missed	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x4c	0x01	LOAD_HIT_PRE.SW_PF	Not software-prefetch load dispatches that hit FB allocated for software prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x4c	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x4f	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x01	TX_MEM.ABORT_CONFLICT	Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x02	TX_MEM.ABORT_CAPACITY_WRITE	Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x04	TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK	Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x08	TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY	Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x10	TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH	Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x20	TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT	Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x40	TX_MEM.HLE_ELISION_BUFFER_FULL	Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x58	0x01	MOVE_ELIMINATION.INT_ELIMINATED	Number of integer Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null
+0x58	0x02	MOVE_ELIMINATION.SIMD_ELIMINATED	Number of SIMD Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null
+0x58	0x04	MOVE_ELIMINATION.INT_NOT_ELIMINATED	Number of integer Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null
+0x58	0x08	MOVE_ELIMINATION.SIMD_NOT_ELIMINATED	Number of SIMD Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0	null
+0x5d	0x01	TX_EXEC.MISC1	Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x02	TX_EXEC.MISC2	Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x04	TX_EXEC.MISC3	Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x08	TX_EXEC.MISC4	Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x10	TX_EXEC.MISC5	Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x80	0x02	ICACHE.MISSES	Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x80	0x04	ICACHE.IFETCH_STALL	Cycles where a code fetch is stalled due to L1 instruction-cache miss.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x02	ITLB_MISSES.WALK_COMPLETED_4K	Code miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x04	ITLB_MISSES.WALK_COMPLETED_2M_4M	Code miss in all TLB levels causes a page walk that completes. (2M/4M)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x10	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x20	ITLB_MISSES.STLB_HIT_4K	Core misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x40	ITLB_MISSES.STLB_HIT_2M	Code misses that miss the  DTLB and hit the STLB (2M)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x87	0x04	ILD_STALL.IQ_FULL	Stall cycles because IQ is full	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0x88	BR_MISP_EXEC.TAKEN_RETURN_NEAR	Taken speculative and retired mispredicted indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x9c	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xA1	0x01	UOPS_EXECUTED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_EXECUTED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x04	UOPS_EXECUTED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x08	UOPS_EXECUTED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x10	UOPS_EXECUTED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x20	UOPS_EXECUTED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_EXECUTED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_EXECUTED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Cycles with pending L2 cache miss loads.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Cycles with pending L1 cache miss loads.	2	2	2000003	0	0	0	8	0	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_LDM_PENDING	Cycles with pending memory loads.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_EXECUTE	Total execution stalls	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Execution stalls due to L2 cache misses.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_LDM_PENDING	Execution stalls due to memory subsystem.	0,1,2,3	0,1,2,3	2000003	0	0	0	6	0	0	0	0	0	0	null
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Execution stalls due to L1 data cache misses	2	2	2000003	0	0	0	12	0	0	0	0	0	0	null
+0xa8	0x01	LSD.UOPS	Number of Uops delivered by the LSD.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xae	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE	Number of uops executed on the core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	HSM31
+0xB1	0x01	UOPS_EXECUTED.STALL_CYCLES	Counts number of cycles no uops were dispatched to be executed on this thread.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xb2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Offcore requests buffer cannot take more entries for this thread core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x11	PAGE_WALKER_LOADS.DTLB_L1	Number of DTLB page walker hits in the L1+FB	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x21	PAGE_WALKER_LOADS.ITLB_L1	Number of ITLB page walker hits in the L1+FB	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x41	PAGE_WALKER_LOADS.EPT_DTLB_L1	Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x81	PAGE_WALKER_LOADS.EPT_ITLB_L1	Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x12	PAGE_WALKER_LOADS.DTLB_L2	Number of DTLB page walker hits in the L2	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x22	PAGE_WALKER_LOADS.ITLB_L2	Number of ITLB page walker hits in the L2	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x42	PAGE_WALKER_LOADS.EPT_DTLB_L2	Counts the number of Extended Page Table walks from the DTLB that hit in the L2.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x82	PAGE_WALKER_LOADS.EPT_ITLB_L2	Counts the number of Extended Page Table walks from the ITLB that hit in the L2.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x14	PAGE_WALKER_LOADS.DTLB_L3	Number of DTLB page walker hits in the L3 + XSNP	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x24	PAGE_WALKER_LOADS.ITLB_L3	Number of ITLB page walker hits in the L3 + XSNP	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x44	PAGE_WALKER_LOADS.EPT_DTLB_L3	Counts the number of Extended Page Table walks from the DTLB that hit in the L3.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x84	PAGE_WALKER_LOADS.EPT_ITLB_L3	Counts the number of Extended Page Table walks from the ITLB that hit in the L2.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x18	PAGE_WALKER_LOADS.DTLB_MEMORY	Number of DTLB page walker hits in Memory	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x28	PAGE_WALKER_LOADS.ITLB_MEMORY	Number of ITLB page walker hits in Memory	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x48	PAGE_WALKER_LOADS.EPT_DTLB_MEMORY	Counts the number of Extended Page Table walks from the DTLB that hit in memory.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBC	0x88	PAGE_WALKER_LOADS.EPT_ITLB_MEMORY	Counts the number of Extended Page Table walks from the ITLB that hit in memory.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xBD	0x01	TLB_FLUSH.DTLB_THREAD	DTLB flush attempts of the thread-specific entries	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xBD	0x20	TLB_FLUSH.STLB_ANY	STLB flush attempts	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC0	0x01	INST_RETIRED.PREC_DIST	Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution	1	1	2000003	0	0	0	0	0	0	0	2	0	0	null
+0xC1	0x08	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	HSM57
+0xC1	0x10	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	HSM57
+0xC1	0x40	OTHER_ASSISTS.ANY_WB_ASSIST	Number of times any microcode assist is invoked by HW upon uop writeback.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	1	0	null
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.CORE_STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	0	null
+0xC3	0x01	MACHINE_CLEARS.CYCLES	Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3).	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	1	0	0	null
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null
+0xc8	0x01	HLE_RETIRED.START	Number of times an HLE execution started.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x02	HLE_RETIRED.COMMIT	Number of times an HLE execution successfully committed	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x04	HLE_RETIRED.ABORTED	Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xc8	0x08	HLE_RETIRED.ABORTED_MISC1	Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x10	HLE_RETIRED.ABORTED_MISC2	Number of times an HLE execution aborted due to uncommon conditions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x20	HLE_RETIRED.ABORTED_MISC3	Number of times an HLE execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x40	HLE_RETIRED.ABORTED_MISC4	Number of times an HLE execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc8	0x80	HLE_RETIRED.ABORTED_MISC5	Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x01	RTM_RETIRED.START	Number of times an RTM execution started.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x02	RTM_RETIRED.COMMIT	Number of times an RTM execution successfully committed	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x04	RTM_RETIRED.ABORTED	Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xc9	0x08	RTM_RETIRED.ABORTED_MISC1	Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x10	RTM_RETIRED.ABORTED_MISC2	Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x20	RTM_RETIRED.ABORTED_MISC3	Number of times an RTM execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x40	RTM_RETIRED.ABORTED_MISC4	Number of times an RTM execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xc9	0x80	RTM_RETIRED.ABORTED_MISC5	Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	0	null
+0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	0	HSM26
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	0	HSM26
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	0	HSM26
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32	3	3	100003	0x3F6	0x20	1	0	0	0	0	2	0	0	HSM26
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	0	HSM26
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	0	HSM26
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	0	HSM26
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	0	HSM26
+0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	HSM30
+0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	HSM30
+0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	1	HSM30
+0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD1	0x04	MEM_LOAD_UOPS_RETIRED.L3_HIT	Retired load uops which data sources were data hits in L3 without snoops required.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30
+0xD1	0x08	MEM_LOAD_UOPS_RETIRED.L1_MISS	Retired load uops misses in L1 cache as data sources.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD1	0x10	MEM_LOAD_UOPS_RETIRED.L2_MISS	Miss in mid-level (L2) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD1	0x20	MEM_LOAD_UOPS_RETIRED.L3_MISS	Miss in last-level (L3) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30
+0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30
+0xD2	0x01	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30
+0xD2	0x02	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30
+0xD2	0x04	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared L3.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30
+0xD2	0x08	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in L3 without snoops required.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30
+0xD3	0x01	MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM	Data from local DRAM either Snoop not needed or Snoop Miss (RspI)	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30
+0x3c	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x08	L2_TRANS.ALL_PF	L2 or L3 HW prefetches that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xf1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xf1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xf1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xF2	0x05	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xF2	0x06	L2_LINES_OUT.DEMAND_DIRTY	Dirty L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x01	UOPS_EXECUTED_PORT.PORT_0_CORE	Cycles per core when uops are exectuted in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x02	UOPS_EXECUTED_PORT.PORT_1_CORE	Cycles per core when uops are exectuted in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x04	UOPS_EXECUTED_PORT.PORT_2_CORE	Cycles per core when uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x08	UOPS_EXECUTED_PORT.PORT_3_CORE	Cycles per core when uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x10	UOPS_EXECUTED_PORT.PORT_4_CORE	Cycles per core when uops are exectuted in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x20	UOPS_EXECUTED_PORT.PORT_5_CORE	Cycles per core when uops are exectuted in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x40	UOPS_EXECUTED_PORT.PORT_6_CORE	Cycles per core when uops are exectuted in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xA1	0x80	UOPS_EXECUTED_PORT.PORT_7_CORE	Cycles per core when uops are dispatched to port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xC5	0x20	BR_MISP_RETIRED.NEAR_TAKEN	number of near branch instructions retired that were mispredicted and taken.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0x08	0x0e	DTLB_LOAD_MISSES.WALK_COMPLETED	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x60	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x42	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x22	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x44	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x24	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x27	L2_RQSTS.ALL_DEMAND_MISS	Demand requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xe7	L2_RQSTS.ALL_DEMAND_REFERENCES	Demand requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x3F	L2_RQSTS.MISS	All requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x0e	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x60	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x0e	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x60	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC	Cycles where at least 1 uop was executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0	HSM31
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC	Cycles where at least 2 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	HSM31
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC	Cycles where at least 3 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0	HSM31
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC	Cycles where at least 4 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	HSM31
+0xe6	0x1f	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE	Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0	null
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	1	1	0	1	0	0	0	null
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x04	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x08	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x10	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x20	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	1	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	2	2	2000003	0	0	0	1	0	1	0	0	0	0	null
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xC6	0x07	AVX_INSTS.ALL	Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x80	0x04	ICACHE.IFDATA_STALL	Cycles where a code fetch is stalled due to L1 instruction-cache miss.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/HSW/Haswell_matrix_V20.json b/x86data/perfmon_data/HSW/Haswell_matrix_V20.json
new file mode 100644
index 0000000..afb643f
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_matrix_V20.json
@@ -0,0 +1,177 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand data reads"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand data writes (RFOs)"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000010",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to L2) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000020",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to L2) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000040",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L3_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L3_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L3_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000200",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "OTHER",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any other requests"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000090",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000120",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000240",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000091",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000122",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000244",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_READS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x00000007f7",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all data/code/rfo reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_REQUESTS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008fff",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all requests"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3f803c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.NO_SNOOP_NEEDED",
+    "MATRIX_VALUE": "0x01003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_MISS",
+    "MATRIX_VALUE": "0x02003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoops sent to sibling cores return clean response"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.HIT_OTHER_CORE_NO_FWD",
+    "MATRIX_VALUE": "0x04003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.HITM_OTHER_CORE",
+    "MATRIX_VALUE": "0x10003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3fffc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss in the L3"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.LOCAL_DRAM",
+    "MATRIX_VALUE": "0x0100400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the L3 and the data is returned from local dram"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/HSW/Haswell_matrix_V20.tsv b/x86data/perfmon_data/HSW/Haswell_matrix_V20.tsv
new file mode 100644
index 0000000..0ae9fd7
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_matrix_V20.tsv
@@ -0,0 +1,29 @@
+# Performance Monitoring Events for the Fourth Generation Intel Core Processors Based on the Haswell Microarchitecture - V20
+# 8/3/2015 11:45:18 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand data reads
+DEMAND_RFO	Null	0x0002	0,1	Counts all demand data writes (RFOs)
+DEMAND_CODE_RD	Null	0x0004	0,1	Counts all demand code reads
+PF_L2_DATA_RD	Null	0x0010	0,1	Counts prefetch (that bring data to L2) data reads
+PF_L2_RFO	Null	0x0020	0,1	Counts all prefetch (that bring data to L2) RFOs
+PF_L2_CODE_RD	Null	0x0040	0,1	Counts all prefetch (that bring data to LLC only) code reads
+PF_L3_DATA_RD	Null	0x0080	0,1	Counts all prefetch (that bring data to LLC only) data reads
+PF_L3_RFO	Null	0x0100	0,1	Counts all prefetch (that bring data to LLC only) RFOs
+PF_L3_CODE_RD	Null	0x0200	0,1	Counts prefetch (that bring data to LLC only) code reads
+OTHER	Null	0x8000	0,1	Counts any other requests
+ALL_PF_DATA_RD	Null	0x0090	0,1	Counts all prefetch data reads
+ALL_PF_RFO	Null	0x0120	0,1	Counts prefetch RFOs
+ALL_PF_CODE_RD	Null	0x0240	0,1	Counts all prefetch code reads
+ALL_DATA_RD	Null	0x0091	0,1	Counts all demand & prefetch data reads
+ALL_RFO	Null	0x0122	0,1	Counts all demand & prefetch RFOs
+ALL_CODE_RD	Null	0x0244	0,1	Counts all demand & prefetch code reads
+ALL_READS	Null	0x07f7	0,1	Counts all data/code/rfo reads (demand & prefetch)
+ALL_REQUESTS	Null	0x8fff	0,1	Counts all requests
+Null	L3_HIT.ANY_RESPONSE	0x3f803c	0,1	hit in the L3
+Null	L3_HIT.NO_SNOOP_NEEDED	0x01003c	0,1	hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
+Null	L3_HIT.SNOOP_MISS	0x02003c	0,1	hit in the L3 and the snoops sent to sibling cores return clean response
+Null	L3_HIT.HIT_OTHER_CORE_NO_FWD	0x04003c	0,1	hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
+Null	L3_HIT.HITM_OTHER_CORE	0x10003c	0,1	hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
+Null	L3_MISS.ANY_RESPONSE	0x3fffc0	0,1	miss in the L3
+Null	L3_MISS.LOCAL_DRAM	0x010040	0,1	miss the L3 and the data is returned from local dram
diff --git a/x86data/perfmon_data/HSW/Haswell_matrix_bit_definitions_V20.json b/x86data/perfmon_data/HSW/Haswell_matrix_bit_definitions_V20.json
new file mode 100644
index 0000000..4526635
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_matrix_bit_definitions_V20.json
@@ -0,0 +1,254 @@
+[
+  {
+    "BitName": "DEMAND_DATA_RD",
+    "BitIndex": "0",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_RFO",
+    "BitIndex": "1",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_CODE_RD",
+    "BitIndex": "2",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "COREWB",
+    "BitIndex": "3",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_DATA_RD",
+    "BitIndex": "4",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_RFO",
+    "BitIndex": "5",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_CODE_RD",
+    "BitIndex": "6",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_DATA_RD",
+    "BitIndex": "7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_RFO",
+    "BitIndex": "8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_CODE_RD",
+    "BitIndex": "9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SPLIT_LOCK_UC_LOCK",
+    "BitIndex": "10",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "STREAMING_STORES",
+    "BitIndex": "11",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "OTHER",
+    "BitIndex": "15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_DATA_RD",
+    "BitIndex": "4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_RFO",
+    "BitIndex": "5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_CODE_RD",
+    "BitIndex": "6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_DATA_RD",
+    "BitIndex": "0,4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_RFO",
+    "BitIndex": "1,5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_CODE_RD",
+    "BitIndex": "2,6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_READS",
+    "BitIndex": "0,1,2,4,5,6,7,8,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_REQUESTS",
+    "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_RESPONSE",
+    "BitIndex": "16",
+    "Type": "2",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SUPPLIER_NONE",
+    "BitIndex": "17",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_M",
+    "BitIndex": "18",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_E",
+    "BitIndex": "19",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_S",
+    "BitIndex": "20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT",
+    "BitIndex": "18,19,20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_LOCAL_DRAM",
+    "BitIndex": "22",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NONE",
+    "BitIndex": "31",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NOT_NEEDED",
+    "BitIndex": "32",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_MISS",
+    "BitIndex": "33",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_NO_FWD",
+    "BitIndex": "34",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_WITH_FWD",
+    "BitIndex": "35",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "18,19,20,21"
+  },
+  {
+    "BitName": "SNOOP_HITM",
+    "BitIndex": "36",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NON_DRAM",
+    "BitIndex": "37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_SNOOP",
+    "BitIndex": "31,32,33,34,35,36,37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/HSW/Haswell_matrix_bit_definitions_V20.tsv b/x86data/perfmon_data/HSW/Haswell_matrix_bit_definitions_V20.tsv
new file mode 100644
index 0000000..6abf129
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_matrix_bit_definitions_V20.tsv
@@ -0,0 +1,40 @@
+# Performance Monitoring Events for the Fourth Generation Intel Core Processors Based on the Haswell Microarchitecture - V20
+# 8/3/2015 11:45:18 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	Type	MATRIX_REG	BitsNotCombinedWith
+DEMAND_DATA_RD	0	1	0,1	Null
+DEMAND_RFO	1	1	0,1	Null
+DEMAND_CODE_RD	2	1	0,1	Null
+COREWB	3	1	0,1	Null
+PF_L2_DATA_RD	4	1	0,1	Null
+PF_L2_RFO	5	1	0,1	Null
+PF_L2_CODE_RD	6	1	0,1	Null
+PF_L3_DATA_RD	7	1	0,1	Null
+PF_L3_RFO	8	1	0,1	Null
+PF_L3_CODE_RD	9	1	0,1	Null
+SPLIT_LOCK_UC_LOCK	10	1	0,1	Null
+STREAMING_STORES	11	1	0,1	Null
+OTHER	15	1	0,1	Null
+ALL_PF_DATA_RD	4,7	1	0,1	Null
+ALL_PF_RFO	5,8	1	0,1	Null
+ALL_PF_CODE_RD	6,9	1	0,1	Null
+ALL_DATA_RD	0,4,7	1	0,1	Null
+ALL_RFO	1,5,8	1	0,1	Null
+ALL_CODE_RD	2,6,9	1	0,1	Null
+ALL_READS	0,1,2,4,5,6,7,8,9	1	0,1	Null
+ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	0,1	Null
+ANY_RESPONSE	16	2	0,1	Null
+SUPPLIER_NONE	17	3	0,1	Null
+L3_HIT_M	18	3	0,1	Null
+L3_HIT_E	19	3	0,1	Null
+L3_HIT_S	20	3	0,1	Null
+L3_HIT	18,19,20	3	0,1	Null
+L3_MISS_LOCAL_DRAM	22	3	0,1	Null
+SNOOP_NONE	31	4	0,1	Null
+SNOOP_NOT_NEEDED	32	4	0,1	Null
+SNOOP_MISS	33	4	0,1	Null
+SNOOP_HIT_NO_FWD	34	4	0,1	Null
+SNOOP_HIT_WITH_FWD	35	4	0,1	18,19,20,21
+SNOOP_HITM	36	4	0,1	Null
+SNOOP_NON_DRAM	37	4	0,1	Null
+ANY_SNOOP	31,32,33,34,35,36,37	4	0,1	Null
diff --git a/x86data/perfmon_data/HSW/Haswell_offcore_V20.tsv b/x86data/perfmon_data/HSW/Haswell_offcore_V20.tsv
new file mode 100644
index 0000000..8df8f05
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_offcore_V20.tsv
@@ -0,0 +1,45 @@
+# Performance Monitoring Events for the Fourth Generation Intel Core Processors Based on the Haswell Microarchitecture - V20
+# 8/3/2015 11:45:18 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE	Counts all requests that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc08fff	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE	Counts all requests that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c8fff	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM	Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01004007f7	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE	Counts all data/code/rfo reads (demand & prefetch) that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc007f7	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE	Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c07f7	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD	Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c07f7	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM	Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400244	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE	Counts all demand & prefetch code reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00244	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0244	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM	Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400122	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE	Counts all demand & prefetch RFOs that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00122	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE	Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0122	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0122	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM	Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400091	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE	Counts all demand & prefetch data reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00091	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE	Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0091	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0091	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE	Counts prefetch (that bring data to LLC only) code reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00200	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE	Counts prefetch (that bring data to LLC only) code reads that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0200	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) RFOs  that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00100	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) RFOs  that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0100	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) data reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00080	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0080	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) code reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00040	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) code reads that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0040	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE	Counts all prefetch (that bring data to L2) RFOs that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00020	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE	Counts all prefetch (that bring data to L2) RFOs that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0020	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE	Counts prefetch (that bring data to L2) data reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00010	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE	Counts prefetch (that bring data to L2) data reads that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0010	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM	Counts all demand code reads that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400004	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE	Counts all demand code reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00004	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE	Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0004	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0004	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM	Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400002	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE	Counts all demand data writes (RFOs) that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00002	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE	Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0002	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0002	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM	Counts demand data reads that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400001	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE	Counts demand data reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00001	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE	Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0001	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD	Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0001	0	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/HSW/Haswell_uncore_V20.json b/x86data/perfmon_data/HSW/Haswell_uncore_V20.json
new file mode 100644
index 0000000..17593e7
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_uncore_V20.json
@@ -0,0 +1,374 @@
+[
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x21",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
+    "BriefDescription": "An external snoop misses in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x41",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
+    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x81",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
+    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x24",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
+    "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x44",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
+    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x84",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
+    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x28",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
+    "BriefDescription": "An external snoop hits a modified line in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x48",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
+    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x88",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
+    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x11",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
+    "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x21",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
+    "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x41",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
+    "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x81",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
+    "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x18",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
+    "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x28",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
+    "BriefDescription": "L3 Lookup write request that access cache and found line in I-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x48",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
+    "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x88",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
+    "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x1f",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
+    "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x2f",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
+    "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x4f",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
+    "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x8f",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
+    "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x86",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
+    "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x46",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
+    "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x16",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
+    "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x26",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
+    "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+    "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
+    "PublicDescription": "tbd",
+    "Counter": "0,",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x81",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+    "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x81",
+    "UMask": "0x20",
+    "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
+    "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x83",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
+    "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)",
+    "PublicDescription": "tbd",
+    "Counter": "0,",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "iMPH-U",
+    "EventCode": "0x84",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+    "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "NCU",
+    "EventCode": "0x0",
+    "UMask": "0x01",
+    "EventName": "UNC_CLOCK.SOCKET",
+    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
+    "PublicDescription": "tbd",
+    "Counter": "FIXED",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/HSW/Haswell_uncore_V20.tsv b/x86data/perfmon_data/HSW/Haswell_uncore_V20.tsv
new file mode 100644
index 0000000..62d6603
--- /dev/null
+++ b/x86data/perfmon_data/HSW/Haswell_uncore_V20.tsv
@@ -0,0 +1,35 @@
+# Performance Monitoring Events for the Fourth Generation Intel Core Processors Based on the Haswell Microarchitecture - V20
+# 8/16/2015 11:29:42 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+Unit	EventCode	UMask	EventName	Description	Counter	CounterMask	Invert	EdgeDetect
+CBO	0x22	0x21	UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL	An external snoop misses in some processor core.	0,1	0	0	0
+CBO	0x22	0x41	UNC_CBO_XSNP_RESPONSE.MISS_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.	0,1	0	0	0
+CBO	0x22	0x81	UNC_CBO_XSNP_RESPONSE.MISS_EVICTION	A cross-core snoop resulted from L3 Eviction which misses in some processor core.	0,1	0	0	0
+CBO	0x22	0x24	UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL	An external snoop hits a non-modified line in some processor core.	0,1	0	0	0
+CBO	0x22	0x44	UNC_CBO_XSNP_RESPONSE.HIT_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.	0,1	0	0	0
+CBO	0x22	0x84	UNC_CBO_XSNP_RESPONSE.HIT_EVICTION	A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.	0,1	0	0	0
+CBO	0x22	0x28	UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL	An external snoop hits a modified line in some processor core.	0,1	0	0	0
+CBO	0x22	0x48	UNC_CBO_XSNP_RESPONSE.HITM_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.	0,1	0	0	0
+CBO	0x22	0x88	UNC_CBO_XSNP_RESPONSE.HITM_EVICTION	A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.	0,1	0	0	0
+CBO	0x34	0x11	UNC_CBO_CACHE_LOOKUP.READ_M	L3 Lookup read request that access cache and found line in M-state	0,1	0	0	0
+CBO	0x34	0x21	UNC_CBO_CACHE_LOOKUP.WRITE_M	L3 Lookup write request that access cache and found line in M-state	0,1	0	0	0
+CBO	0x34	0x41	UNC_CBO_CACHE_LOOKUP.EXTSNP_M	L3 Lookup external snoop request that access cache and found line in M-state	0,1	0	0	0
+CBO	0x34	0x81	UNC_CBO_CACHE_LOOKUP.ANY_M	L3 Lookup any request that access cache and found line in M-state	0,1	0	0	0
+CBO	0x34	0x18	UNC_CBO_CACHE_LOOKUP.READ_I	L3 Lookup read request that access cache and found line in I-state	0,1	0	0	0
+CBO	0x34	0x28	UNC_CBO_CACHE_LOOKUP.WRITE_I	L3 Lookup write request that access cache and found line in I-state	0,1	0	0	0
+CBO	0x34	0x48	UNC_CBO_CACHE_LOOKUP.EXTSNP_I	L3 Lookup external snoop request that access cache and found line in I-state	0,1	0	0	0
+CBO	0x34	0x88	UNC_CBO_CACHE_LOOKUP.ANY_I	L3 Lookup any request that access cache and found line in I-state	0,1	0	0	0
+CBO	0x34	0x1f	UNC_CBO_CACHE_LOOKUP.READ_MESI	L3 Lookup read request that access cache and found line in any MESI-state	0,1	0	0	0
+CBO	0x34	0x2f	UNC_CBO_CACHE_LOOKUP.WRITE_MESI	L3 Lookup write request that access cache and found line in MESI-state	0,1	0	0	0
+CBO	0x34	0x4f	UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI	L3 Lookup external snoop request that access cache and found line in MESI-state	0,1	0	0	0
+CBO	0x34	0x8f	UNC_CBO_CACHE_LOOKUP.ANY_MESI	L3 Lookup any request that access cache and found line in MESI-state	0,1	0	0	0
+CBO	0x34	0x86	UNC_CBO_CACHE_LOOKUP.ANY_ES	L3 Lookup any request that access cache and found line in E or S-state	0,1	0	0	0
+CBO	0x34	0x46	UNC_CBO_CACHE_LOOKUP.EXTSNP_ES	L3 Lookup external snoop request that access cache and found line in E or S-state	0,1	0	0	0
+CBO	0x34	0x16	UNC_CBO_CACHE_LOOKUP.READ_ES	L3 Lookup read request that access cache and found line in E or S-state	0,1	0	0	0
+CBO	0x34	0x26	UNC_CBO_CACHE_LOOKUP.WRITE_ES	L3 Lookup write request that access cache and found line in E or S-state	0,1	0	0	0
+iMPH-U	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.ALL	Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.	0,	0	0	0
+iMPH-U	0x81	0x01	UNC_ARB_TRK_REQUESTS.ALL	Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.	0,1	0	0	0
+iMPH-U	0x81	0x20	UNC_ARB_TRK_REQUESTS.WRITES	Number of Writes allocated - any write transactions: full/partials writes and evictions.	0,1	0	0	0
+iMPH-U	0x83	0x01	UNC_ARB_COH_TRK_OCCUPANCY.All	Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)	0,	0	0	0
+iMPH-U	0x84	0x01	UNC_ARB_COH_TRK_REQUESTS.ALL	Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.	0,1	0	0	0
+NCU	0x0	0x01	UNC_CLOCK.SOCKET	This 48-bit fixed counter counts the UCLK cycles	FIXED	0	0	0
diff --git a/x86data/perfmon_data/HSX/HaswellX_core_V14.json b/x86data/perfmon_data/HSX/HaswellX_core_V14.json
new file mode 100644
index 0000000..499d334
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_core_V14.json
@@ -0,0 +1,8604 @@
+[

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired from execution.",

+    "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.\n",

+    "Counter": "Fixed counter 1",

+    "CounterHTOff": "Fixed counter 1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Core cycles when the thread is not in halt state.",

+    "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. \n",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Reference cycles when the core is not in halt state.",

+    "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.",

+    "Counter": "Fixed counter 3",

+    "CounterHTOff": "Fixed counter 3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "LD_BLOCKS.STORE_FORWARD",

+    "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded",

+    "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS.NO_SR",

+    "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",

+    "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "MISALIGN_MEM_REF.LOADS",

+    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "MISALIGN_MEM_REF.STORES",

+    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies in MOB due to partial compare on address.",

+    "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x01",

+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Load misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Load misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x02",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x04",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x40",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",

+    "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M)",

+    "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x80",

+    "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",

+    "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",

+    "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES",

+    "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.... ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x10",

+    "EventName": "UOPS_ISSUED.FLAGS_MERGE",

+    "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",

+    "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x20",

+    "EventName": "UOPS_ISSUED.SLOW_LEA",

+    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x40",

+    "EventName": "UOPS_ISSUED.SINGLE_MUL",

+    "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "PublicDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x02",

+    "EventName": "ARITH.DIVIDER_UOPS",

+    "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",

+    "PublicDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x21",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",

+    "BriefDescription": "Demand Data Read miss L2, no rejects",

+    "PublicDescription": "Demand Data Read miss L2, no rejects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x41",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",

+    "BriefDescription": "Demand Data Read requests that hit L2 cache",

+    "PublicDescription": "Demand Data Read requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.L2_PF_MISS",

+    "BriefDescription": "L2 prefetch requests that miss L2 cache",

+    "PublicDescription": "L2 prefetch requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x50",

+    "EventName": "L2_RQSTS.L2_PF_HIT",

+    "BriefDescription": "L2 prefetch requests that hit L2 cache",

+    "PublicDescription": "L2 prefetch requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE1",

+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests",

+    "PublicDescription": "Demand Data Read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE2",

+    "EventName": "L2_RQSTS.ALL_RFO",

+    "BriefDescription": "RFO requests to L2 cache",

+    "PublicDescription": "RFO requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE4",

+    "EventName": "L2_RQSTS.ALL_CODE_RD",

+    "BriefDescription": "L2 code requests",

+    "PublicDescription": "L2 code requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xF8",

+    "EventName": "L2_RQSTS.ALL_PF",

+    "BriefDescription": "Requests from L2 hardware prefetchers",

+    "PublicDescription": "Requests from L2 hardware prefetchers",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x50",

+    "EventName": "L2_DEMAND_RQSTS.WB_HIT",

+    "BriefDescription": "Not rejected writebacks that hit L2 cache",

+    "PublicDescription": "Not rejected writebacks that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2e",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Core-originated cacheable demand requests missed L3",

+    "PublicDescription": "Core-originated cacheable demand requests missed L3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2e",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Core-originated cacheable demand requests that refer to L3",

+    "PublicDescription": "Core-originated cacheable demand requests that refer to L3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",

+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",

+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",

+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING",

+    "BriefDescription": "L1D miss oustandings duration in cycles",

+    "PublicDescription": "L1D miss oustandings duration in cycles",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",

+    "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e",

+    "PublicDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",

+    "BriefDescription": "Cycles with L1D load Misses outstanding.",

+    "PublicDescription": "Cycles with L1D load Misses outstanding.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x01",

+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x02",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",

+    "PublicDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x04",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x20",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x40",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",

+    "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M)",

+    "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x80",

+    "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",

+    "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",

+    "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4c",

+    "UMask": "0x01",

+    "EventName": "LOAD_HIT_PRE.SW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4c",

+    "UMask": "0x02",

+    "EventName": "LOAD_HIT_PRE.HW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4f",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Cycle count for an Extended Page table walk.",

+    "PublicDescription": "Cycle count for an Extended Page table walk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x01",

+    "EventName": "L1D.REPLACEMENT",

+    "BriefDescription": "L1D data line replacements",

+    "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x01",

+    "EventName": "TX_MEM.ABORT_CONFLICT",

+    "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",

+    "PublicDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x02",

+    "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",

+    "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",

+    "PublicDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x04",

+    "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",

+    "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",

+    "PublicDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x08",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x10",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x20",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x40",

+    "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",

+    "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",

+    "PublicDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x01",

+    "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x02",

+    "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x04",

+    "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x08",

+    "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0",

+    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

+    "PublicDescription": "Unhalted core cycles when the thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x02",

+    "EventName": "CPL_CYCLES.RING123",

+    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "PublicDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0_TRANS",

+    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "PublicDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x01",

+    "EventName": "TX_EXEC.MISC1",

+    "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",

+    "PublicDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x02",

+    "EventName": "TX_EXEC.MISC2",

+    "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",

+    "PublicDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x04",

+    "EventName": "TX_EXEC.MISC3",

+    "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",

+    "PublicDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x08",

+    "EventName": "TX_EXEC.MISC4",

+    "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",

+    "PublicDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x10",

+    "EventName": "TX_EXEC.MISC5",

+    "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",

+    "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_CYCLES",

+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",

+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "PublicDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",

+    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x01",

+    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "PublicDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x02",

+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1D is locked",

+    "PublicDescription": "Cycles when L1D is locked",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x02",

+    "EventName": "IDQ.EMPTY",

+    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "PublicDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_UOPS",

+    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x20",

+    "EventName": "IDQ.MS_MITE_UOPS",

+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_CYCLES",

+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_OCCUR",

+    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles MITE is delivering 4 Uops",

+    "PublicDescription": "Cycles MITE is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles MITE is delivering any Uop",

+    "PublicDescription": "Cycles MITE is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x3c",

+    "EventName": "IDQ.MITE_ALL_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x01",

+    "EventName": "ICACHE.HIT",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x02",

+    "EventName": "ICACHE.MISSES",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",

+    "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x04",

+    "EventName": "ICACHE.IFETCH_STALL",

+    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x01",

+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Misses at all ITLB levels that cause page walks",

+    "PublicDescription": "Misses at all ITLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x02",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",

+    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",

+    "PublicDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x04",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",

+    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",

+    "PublicDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x10",

+    "EventName": "ITLB_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISSES.STLB_HIT_4K",

+    "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",

+    "PublicDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x40",

+    "EventName": "ITLB_MISSES.STLB_HIT_2M",

+    "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M)",

+    "PublicDescription": "Code misses that miss the  DTLB and hit the STLB (2M)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x01",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

+    "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x04",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Stall cycles because IQ is full",

+    "PublicDescription": "Stall cycles because IQ is full",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x41",

+    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken macro-conditional branches",

+    "PublicDescription": "Not taken macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x81",

+    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired macro-conditional branches",

+    "PublicDescription": "Taken speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x82",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",

+    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x84",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x88",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x90",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired direct near calls",

+    "PublicDescription": "Taken speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xA0",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired indirect calls",

+    "PublicDescription": "Taken speculative and retired indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC1",

+    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired macro-conditional branches",

+    "PublicDescription": "Speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC2",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",

+    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC4",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC8",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Speculative and retired indirect return branches.",

+    "PublicDescription": "Speculative and retired indirect return branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xD0",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired direct near calls",

+    "PublicDescription": "Speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xFF",

+    "EventName": "BR_INST_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired  branches",

+    "PublicDescription": "Speculative and retired  branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x41",

+    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x81",

+    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x84",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x88",

+    "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC1",

+    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC4",

+    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xFF",

+    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9c",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",

+    "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled.  This event is counted on a per-core basis.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "PublicDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are executed in port 0",

+    "PublicDescription": "Cycles per thread when uops are executed in port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are executed in port 1",

+    "PublicDescription": "Cycles per thread when uops are executed in port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when uops are executed in port 2",

+    "PublicDescription": "Cycles per thread when uops are executed in port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when uops are executed in port 3",

+    "PublicDescription": "Cycles per thread when uops are executed in port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are executed in port 4",

+    "PublicDescription": "Cycles per thread when uops are executed in port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are executed in port 5",

+    "PublicDescription": "Cycles per thread when uops are executed in port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_6",

+    "BriefDescription": "Cycles per thread when uops are executed in port 6",

+    "PublicDescription": "Cycles per thread when uops are executed in port 6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_7",

+    "BriefDescription": "Cycles per thread when uops are executed in port 7",

+    "PublicDescription": "Cycles per thread when uops are executed in port 7",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x01",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource-related stall cycles",

+    "PublicDescription": "Resource-related stall cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x04",

+    "EventName": "RESOURCE_STALLS.RS",

+    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",

+    "PublicDescription": "Cycles stalled due to no eligible RS entry available.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x08",

+    "EventName": "RESOURCE_STALLS.SB",

+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB",

+    "BriefDescription": "Cycles stalled due to re-order buffer full.",

+    "PublicDescription": "Cycles stalled due to re-order buffer full.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",

+    "BriefDescription": "Cycles with pending L2 cache miss loads.",

+    "PublicDescription": "Cycles with pending L2 cache miss loads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",

+    "BriefDescription": "Cycles with pending L1 cache miss loads.",

+    "PublicDescription": "Cycles with pending L1 cache miss loads.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",

+    "BriefDescription": "Cycles with pending memory loads.",

+    "PublicDescription": "Cycles with pending memory loads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",

+    "BriefDescription": "Total execution stalls",

+    "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",

+    "BriefDescription": "Execution stalls due to L2 cache misses.",

+    "PublicDescription": "Execution stalls due to L2 cache misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",

+    "BriefDescription": "Execution stalls due to memory subsystem.",

+    "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",

+    "BriefDescription": "Execution stalls due to L1 data cache misses",

+    "PublicDescription": "Execution stalls due to L1 data cache misses",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xa8",

+    "UMask": "0x01",

+    "EventName": "LSD.UOPS",

+    "BriefDescription": "Number of Uops delivered by the LSD.",

+    "PublicDescription": "Number of Uops delivered by the LSD.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x02",

+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xae",

+    "UMask": "0x01",

+    "EventName": "ITLB.ITLB_FLUSH",

+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "PublicDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests sent to uncore",

+    "PublicDescription": "Demand Data Read requests sent to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

+    "BriefDescription": "Cacheable and noncachaeble code read requests",

+    "PublicDescription": "Cacheable and noncachaeble code read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",

+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "PublicDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb0",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",

+    "BriefDescription": "Demand and prefetch data reads",

+    "PublicDescription": "Demand and prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE",

+    "BriefDescription": "Number of uops executed on the core.",

+    "PublicDescription": "Number of uops executed on the core.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.STALL_CYCLES",

+    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "PublicDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb2",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",

+    "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",

+    "PublicDescription": "Offcore requests buffer cannot take more entries for this thread core.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x11",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L1",

+    "BriefDescription": "Number of DTLB page walker hits in the L1+FB",

+    "PublicDescription": "Number of DTLB page walker hits in the L1+FB",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x21",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L1",

+    "BriefDescription": "Number of ITLB page walker hits in the L1+FB",

+    "PublicDescription": "Number of ITLB page walker hits in the L1+FB",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x41",

+    "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x81",

+    "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x12",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L2",

+    "BriefDescription": "Number of DTLB page walker hits in the L2",

+    "PublicDescription": "Number of DTLB page walker hits in the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x22",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L2",

+    "BriefDescription": "Number of ITLB page walker hits in the L2",

+    "PublicDescription": "Number of ITLB page walker hits in the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x42",

+    "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x82",

+    "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x14",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_L3",

+    "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",

+    "PublicDescription": "Number of DTLB page walker hits in the L3 + XSNP",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x24",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_L3",

+    "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",

+    "PublicDescription": "Number of ITLB page walker hits in the L3 + XSNP",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x44",

+    "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x84",

+    "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x18",

+    "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",

+    "BriefDescription": "Number of DTLB page walker hits in Memory",

+    "PublicDescription": "Number of DTLB page walker hits in Memory",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x28",

+    "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",

+    "BriefDescription": "Number of ITLB page walker hits in Memory",

+    "PublicDescription": "Number of ITLB page walker hits in Memory",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x48",

+    "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBC",

+    "UMask": "0x88",

+    "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",

+    "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",

+    "PublicDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x01",

+    "EventName": "TLB_FLUSH.DTLB_THREAD",

+    "BriefDescription": "DTLB flush attempts of the thread-specific entries",

+    "PublicDescription": "DTLB flush attempts of the thread-specific entries",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x20",

+    "EventName": "TLB_FLUSH.STLB_ANY",

+    "BriefDescription": "STLB flush attempts",

+    "PublicDescription": "STLB flush attempts",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",

+    "PublicDescription": "Number of instructions retired. General Counter   - architectural event",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.PREC_DIST",

+    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "Counter": "1",

+    "CounterHTOff": "1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x08",

+    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

+    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "PublicDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM57",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x10",

+    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

+    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "PublicDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM57",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x40",

+    "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",

+    "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "PublicDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.ALL",

+    "BriefDescription": "Actually retired uops.",

+    "PublicDescription": "Actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x02",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used.",

+    "PublicDescription": "This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops.",

+    "PublicDescription": "Cycles without actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Cycles with less than 10 actually retired uops.",

+    "PublicDescription": "Cycles with less than 10 actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "10",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops.",

+    "PublicDescription": "Cycles without actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.CYCLES",

+    "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",

+    "PublicDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-modifying code (SMC) detected.",

+    "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x20",

+    "EventName": "MACHINE_CLEARS.MASKMOV",

+    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",

+    "PublicDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x01",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Conditional branch instructions retired.",

+    "PublicDescription": "Conditional branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x02",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect near call instructions retired.",

+    "PublicDescription": "Direct and indirect near call instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All (macro) branch instructions retired.",

+    "PublicDescription": "All (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x08",

+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",

+    "BriefDescription": "Return instructions retired.",

+    "PublicDescription": "Return instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x10",

+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Not taken branch instructions retired.",

+    "PublicDescription": "Not taken branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x20",

+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "Taken branch instructions retired.",

+    "PublicDescription": "Taken branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x40",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Far branch instructions retired.",

+    "PublicDescription": "Far branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x04",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "All (macro) branch instructions retired. ",

+    "PublicDescription": "All (macro) branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x01",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional branch instructions retired.",

+    "PublicDescription": "Mispredicted conditional branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All mispredicted macro branch instructions retired.",

+    "PublicDescription": "All mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x04",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "Mispredicted macro branch instructions retired. ",

+    "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x01",

+    "EventName": "HLE_RETIRED.START",

+    "BriefDescription": "Number of times an HLE execution started.",

+    "PublicDescription": "Number of times an HLE execution started.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x02",

+    "EventName": "HLE_RETIRED.COMMIT",

+    "BriefDescription": "Number of times an HLE execution successfully committed",

+    "PublicDescription": "Number of times an HLE execution successfully committed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x04",

+    "EventName": "HLE_RETIRED.ABORTED",

+    "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",

+    "PublicDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x08",

+    "EventName": "HLE_RETIRED.ABORTED_MISC1",

+    "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "PublicDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x10",

+    "EventName": "HLE_RETIRED.ABORTED_MISC2",

+    "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",

+    "PublicDescription": "Number of times an HLE execution aborted due to uncommon conditions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x20",

+    "EventName": "HLE_RETIRED.ABORTED_MISC3",

+    "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",

+    "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x40",

+    "EventName": "HLE_RETIRED.ABORTED_MISC4",

+    "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",

+    "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc8",

+    "UMask": "0x80",

+    "EventName": "HLE_RETIRED.ABORTED_MISC5",

+    "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",

+    "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x01",

+    "EventName": "RTM_RETIRED.START",

+    "BriefDescription": "Number of times an RTM execution started.",

+    "PublicDescription": "Number of times an RTM execution started.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x02",

+    "EventName": "RTM_RETIRED.COMMIT",

+    "BriefDescription": "Number of times an RTM execution successfully committed",

+    "PublicDescription": "Number of times an RTM execution successfully committed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x04",

+    "EventName": "RTM_RETIRED.ABORTED",

+    "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",

+    "PublicDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x08",

+    "EventName": "RTM_RETIRED.ABORTED_MISC1",

+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",

+    "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x10",

+    "EventName": "RTM_RETIRED.ABORTED_MISC2",

+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x20",

+    "EventName": "RTM_RETIRED.ABORTED_MISC3",

+    "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",

+    "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x40",

+    "EventName": "RTM_RETIRED.ABORTED_MISC4",

+    "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",

+    "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc9",

+    "UMask": "0x80",

+    "EventName": "RTM_RETIRED.ABORTED_MISC5",

+    "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",

+    "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x02",

+    "EventName": "FP_ASSIST.X87_OUTPUT",

+    "BriefDescription": "Number of X87 assists due to output value.",

+    "PublicDescription": "Number of X87 assists due to output value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x04",

+    "EventName": "FP_ASSIST.X87_INPUT",

+    "BriefDescription": "Number of X87 assists due to input value.",

+    "PublicDescription": "Number of X87 assists due to input value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x08",

+    "EventName": "FP_ASSIST.SIMD_OUTPUT",

+    "BriefDescription": "Number of SIMD FP assists due to Output values",

+    "PublicDescription": "Number of SIMD FP assists due to Output values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x10",

+    "EventName": "FP_ASSIST.SIMD_INPUT",

+    "BriefDescription": "Number of SIMD FP assists due to input values",

+    "PublicDescription": "Number of SIMD FP assists due to input values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x1E",

+    "EventName": "FP_ASSIST.ANY",

+    "BriefDescription": "Cycles with any input/output SSE or FP assist",

+    "PublicDescription": "Cycles with any input/output SSE or FP assist",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x20",

+    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",

+    "BriefDescription": "Count cases of saving new LBR",

+    "PublicDescription": "Count cases of saving new LBR",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

+    "BriefDescription": "Loads with latency value being above 4",

+    "PublicDescription": "Loads with latency value being above 4",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

+    "BriefDescription": "Loads with latency value being above 8",

+    "PublicDescription": "Loads with latency value being above 8",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

+    "BriefDescription": "Loads with latency value being above 16",

+    "PublicDescription": "Loads with latency value being above 16",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

+    "BriefDescription": "Loads with latency value being above 32",

+    "PublicDescription": "Loads with latency value being above 32",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

+    "BriefDescription": "Loads with latency value being above 64",

+    "PublicDescription": "Loads with latency value being above 64",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

+    "BriefDescription": "Loads with latency value being above 128",

+    "PublicDescription": "Loads with latency value being above 128",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "1009",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

+    "BriefDescription": "Loads with latency value being above 256",

+    "PublicDescription": "Loads with latency value being above 256",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "503",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

+    "BriefDescription": "Loads with latency value being above 512",

+    "PublicDescription": "Loads with latency value being above 512",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "101",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x11",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",

+    "BriefDescription": "Retired load uops that miss the STLB.",

+    "PublicDescription": "Retired load uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x12",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",

+    "BriefDescription": "Retired store uops that miss the STLB.",

+    "PublicDescription": "Retired store uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x21",

+    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",

+    "BriefDescription": "Retired load uops with locked access.",

+    "PublicDescription": "Retired load uops with locked access.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x41",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",

+    "BriefDescription": "Retired load uops that split across a cacheline boundary.",

+    "PublicDescription": "Retired load uops that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x42",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",

+    "BriefDescription": "Retired store uops that split across a cacheline boundary.",

+    "PublicDescription": "Retired store uops that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x81",

+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

+    "BriefDescription": "All retired load uops.",

+    "PublicDescription": "All retired load uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x82",

+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

+    "BriefDescription": "All retired store uops.",

+    "PublicDescription": "All retired store uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",

+    "BriefDescription": "Retired load uops with L1 cache hits as data sources.",

+    "PublicDescription": "Retired load uops with L1 cache hits as data sources.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

+    "BriefDescription": "Retired load uops with L2 cache hits as data sources.",

+    "PublicDescription": "Retired load uops with L2 cache hits as data sources.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",

+    "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",

+    "PublicDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",

+    "BriefDescription": "Retired load uops misses in L1 cache as data sources.",

+    "PublicDescription": "Retired load uops misses in L1 cache as data sources.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",

+    "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",

+    "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",

+    "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",

+    "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",

+    "PublicDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",

+    "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",

+    "PublicDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",

+    "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",

+    "PublicDescription": "Retired load uops which data sources were HitM responses from shared L3.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",

+    "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",

+    "PublicDescription": "Retired load uops which data sources were hits in L3 without snoops required.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM26, HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM",

+    "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "PublicDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM",

+    "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",

+    "PublicDescription": "Retired load uop whose Data Source was: Remote cache HITM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD",

+    "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",

+    "PublicDescription": "Retired load uop whose Data Source was: forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM30",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3c",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Thread cycles when thread is not in halt state",

+    "PublicDescription": "Thread cycles when thread is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x01",

+    "EventName": "L2_TRANS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests that access L2 cache",

+    "PublicDescription": "Demand Data Read requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x02",

+    "EventName": "L2_TRANS.RFO",

+    "BriefDescription": "RFO requests that access L2 cache",

+    "PublicDescription": "RFO requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x04",

+    "EventName": "L2_TRANS.CODE_RD",

+    "BriefDescription": "L2 cache accesses when fetching instructions",

+    "PublicDescription": "L2 cache accesses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x08",

+    "EventName": "L2_TRANS.ALL_PF",

+    "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",

+    "PublicDescription": "L2 or L3 HW prefetches that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANS.L1D_WB",

+    "BriefDescription": "L1D writebacks that access L2 cache",

+    "PublicDescription": "L1D writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANS.L2_FILL",

+    "BriefDescription": "L2 fill requests that access L2 cache",

+    "PublicDescription": "L2 fill requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANS.L2_WB",

+    "BriefDescription": "L2 writebacks that access L2 cache",

+    "PublicDescription": "L2 writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANS.ALL_REQUESTS",

+    "BriefDescription": "Transactions accessing L2 pipe",

+    "PublicDescription": "Transactions accessing L2 pipe",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_IN.I",

+    "BriefDescription": "L2 cache lines in I state filling L2",

+    "PublicDescription": "L2 cache lines in I state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_IN.S",

+    "BriefDescription": "L2 cache lines in S state filling L2",

+    "PublicDescription": "L2 cache lines in S state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xf1",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_IN.E",

+    "BriefDescription": "L2 cache lines in E state filling L2",

+    "PublicDescription": "L2 cache lines in E state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x07",

+    "EventName": "L2_LINES_IN.ALL",

+    "BriefDescription": "L2 cache lines filling L2",

+    "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x05",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by demand",

+    "PublicDescription": "Clean L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x06",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by demand",

+    "PublicDescription": "Dirty L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xA0",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect calls",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 0",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 1",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 2",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 3",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 4",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 5",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",

+    "BriefDescription": "Cycles per core when uops are exectuted in port 6",

+    "PublicDescription": "Cycles per core when uops are exectuted in port 6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 7",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 7",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",

+    "PublicDescription": "number of near branch instructions retired that were mispredicted and taken.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x0e",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x60",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x42",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "RFO requests that hit L2 cache",

+    "PublicDescription": "RFO requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x22",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "RFO requests that miss L2 cache",

+    "PublicDescription": "RFO requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x44",

+    "EventName": "L2_RQSTS.CODE_RD_HIT",

+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",

+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x24",

+    "EventName": "L2_RQSTS.CODE_RD_MISS",

+    "BriefDescription": "L2 cache misses when fetching instructions",

+    "PublicDescription": "L2 cache misses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x27",

+    "EventName": "L2_RQSTS.ALL_DEMAND_MISS",

+    "BriefDescription": "Demand requests that miss L2 cache",

+    "PublicDescription": "Demand requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xe7",

+    "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",

+    "BriefDescription": "Demand requests to L2 cache",

+    "PublicDescription": "Demand requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3F",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All requests that miss L2 cache",

+    "PublicDescription": "All requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "PublicDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x0e",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x60",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",

+    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x0e",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Misses in all ITLB levels that cause completed page walks",

+    "PublicDescription": "Misses in all ITLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x60",

+    "EventName": "ITLB_MISSES.STLB_HIT",

+    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",

+    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",

+    "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",

+    "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",

+    "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 4 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "HSM31",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xe6",

+    "UMask": "0x1f",

+    "EventName": "BACLEARS.ANY",

+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE",

+    "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.COUNT",

+    "BriefDescription": "Number of machine clears (nukes) of any type. ",

+    "PublicDescription": "Number of machine clears (nukes) of any type. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_ACTIVE",

+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_4_UOPS",

+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_END",

+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_SWITCHES",

+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are executed in port 0",

+    "PublicDescription": "Cycles per thread when uops are executed in port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are executed in port 1",

+    "PublicDescription": "Cycles per thread when uops are executed in port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when uops are executed in port 2",

+    "PublicDescription": "Cycles per thread when uops are executed in port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when uops are executed in port 3",

+    "PublicDescription": "Cycles per thread when uops are executed in port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are executed in port 4",

+    "PublicDescription": "Cycles per thread when uops are executed in port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are executed in port 5",

+    "PublicDescription": "Cycles per thread when uops are executed in port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_6",

+    "BriefDescription": "Cycles per thread when uops are executed in port 6",

+    "PublicDescription": "Cycles per thread when uops are executed in port 6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_7",

+    "BriefDescription": "Cycles per thread when uops are executed in port 7",

+    "PublicDescription": "Cycles per thread when uops are executed in port 7",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",

+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",

+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",

+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",

+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",

+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xb1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",

+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",

+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",

+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.FB_FULL",

+    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x07",

+    "EventName": "AVX_INSTS.ALL",

+    "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",

+    "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x04",

+    "EventName": "ICACHE.IFDATA_STALL",

+    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts demand data reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0600400001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0600400002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0600400004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0600400091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x067f800091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc00091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x087fc00091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0600400122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c0244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0600400244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04003c07f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c07f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc007f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x06004007f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x067f8007f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc007f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x087fc007f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all requests that hit in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c8fff",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all requests that miss in the L3",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc08fff",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "ELLC": "0",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/HSX/HaswellX_core_V14.tsv b/x86data/perfmon_data/HSX/HaswellX_core_V14.tsv
new file mode 100644
index 0000000..98fe789
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_core_V14.tsv
@@ -0,0 +1,332 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 v3 family based on the Haswell-E microarchitecture - V14
+# 8/3/2015 11:49:51 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata	ELLC
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state.	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	loads blocked by overlapping with store buffer that cannot be forwarded	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x03	0x08	LD_BLOCKS.NO_SR	The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare on address.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x01	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Load misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x04	DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x10	DTLB_LOAD_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x20	DTLB_LOAD_MISSES.STLB_HIT_4K	Load misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x40	DTLB_LOAD_MISSES.STLB_HIT_2M	Load misses that miss the  DTLB and hit the STLB (2M)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x80	DTLB_LOAD_MISSES.PDE_CACHE_MISS	DTLB demand load misses with low part of linear-to-physical address translation missed	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0E	0x10	UOPS_ISSUED.FLAGS_MERGE	Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0E	0x20	UOPS_ISSUED.SLOW_LEA	Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0E	0x40	UOPS_ISSUED.SINGLE_MUL	Number of Multiply packed/scalar single precision uops allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null	0
+0x0E	0x01	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	0	null	0
+0x14	0x02	ARITH.DIVIDER_UOPS	Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x21	L2_RQSTS.DEMAND_DATA_RD_MISS	Demand Data Read miss L2, no rejects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x41	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x30	L2_RQSTS.L2_PF_MISS	L2 prefetch requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x50	L2_RQSTS.L2_PF_HIT	L2 prefetch requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xE1	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xE2	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xE4	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xF8	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x27	0x50	L2_DEMAND_RQSTS.WB_HIT	Not rejected writebacks that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x2e	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x2e	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x3c	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x3c	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other thread is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	2	2	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x48	0x02	L1D_PEND_MISS.REQUEST_FB_FULL	Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding.	2	2	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Store miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x04	DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M	Store misses in all DTLB levels that cause completed page walks (2M/4M)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x10	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x20	DTLB_STORE_MISSES.STLB_HIT_4K	Store misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x40	DTLB_STORE_MISSES.STLB_HIT_2M	Store misses that miss the  DTLB and hit the STLB (2M)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x80	DTLB_STORE_MISSES.PDE_CACHE_MISS	DTLB store misses with low part of linear-to-physical address translation missed	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x4c	0x01	LOAD_HIT_PRE.SW_PF	Not software-prefetch load dispatches that hit FB allocated for software prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x4c	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x4f	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x01	TX_MEM.ABORT_CONFLICT	Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x02	TX_MEM.ABORT_CAPACITY_WRITE	Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x04	TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK	Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x08	TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY	Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x10	TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH	Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x20	TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT	Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x54	0x40	TX_MEM.HLE_ELISION_BUFFER_FULL	Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x58	0x01	MOVE_ELIMINATION.INT_ELIMINATED	Number of integer Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x58	0x02	MOVE_ELIMINATION.SIMD_ELIMINATED	Number of SIMD Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x58	0x04	MOVE_ELIMINATION.INT_NOT_ELIMINATED	Number of integer Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x58	0x08	MOVE_ELIMINATION.SIMD_NOT_ELIMINATED	Number of SIMD Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0	null	0
+0x5d	0x01	TX_EXEC.MISC1	Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5d	0x02	TX_EXEC.MISC2	Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5d	0x04	TX_EXEC.MISC3	Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5d	0x08	TX_EXEC.MISC4	Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5d	0x10	TX_EXEC.MISC5	Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null	0
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x80	0x02	ICACHE.MISSES	Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x80	0x04	ICACHE.IFETCH_STALL	Cycles where a code fetch is stalled due to L1 instruction-cache miss.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x02	ITLB_MISSES.WALK_COMPLETED_4K	Code miss in all TLB levels causes a page walk that completes. (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x04	ITLB_MISSES.WALK_COMPLETED_2M_4M	Code miss in all TLB levels causes a page walk that completes. (2M/4M)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x10	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x20	ITLB_MISSES.STLB_HIT_4K	Core misses that miss the  DTLB and hit the STLB (4K)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x40	ITLB_MISSES.STLB_HIT_2M	Code misses that miss the  DTLB and hit the STLB (2M)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x87	0x04	ILD_STALL.IQ_FULL	Stall cycles because IQ is full	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0x88	BR_MISP_EXEC.TAKEN_RETURN_NEAR	Taken speculative and retired mispredicted indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x9c	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null	0
+0xA1	0x01	UOPS_EXECUTED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x02	UOPS_EXECUTED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x04	UOPS_EXECUTED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x08	UOPS_EXECUTED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x10	UOPS_EXECUTED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x20	UOPS_EXECUTED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x40	UOPS_EXECUTED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x80	UOPS_EXECUTED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Cycles with pending L2 cache miss loads.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Cycles with pending L1 cache miss loads.	2	2	2000003	0	0	0	8	0	0	0	0	0	0	null	0
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_LDM_PENDING	Cycles with pending memory loads.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	null	0
+0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_EXECUTE	Total execution stalls	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Execution stalls due to L2 cache misses.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	0	null	0
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_LDM_PENDING	Execution stalls due to memory subsystem.	0,1,2,3	0,1,2,3	2000003	0	0	0	6	0	0	0	0	0	0	null	0
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Execution stalls due to L1 data cache misses	2	2	2000003	0	0	0	12	0	0	0	0	0	0	null	0
+0xa8	0x01	LSD.UOPS	Number of Uops delivered by the LSD.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xae	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE	Number of uops executed on the core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	HSM31	0
+0xB1	0x01	UOPS_EXECUTED.STALL_CYCLES	Counts number of cycles no uops were dispatched to be executed on this thread.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null	0
+0xb2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Offcore requests buffer cannot take more entries for this thread core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x11	PAGE_WALKER_LOADS.DTLB_L1	Number of DTLB page walker hits in the L1+FB	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x21	PAGE_WALKER_LOADS.ITLB_L1	Number of ITLB page walker hits in the L1+FB	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x41	PAGE_WALKER_LOADS.EPT_DTLB_L1	Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x81	PAGE_WALKER_LOADS.EPT_ITLB_L1	Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x12	PAGE_WALKER_LOADS.DTLB_L2	Number of DTLB page walker hits in the L2	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x22	PAGE_WALKER_LOADS.ITLB_L2	Number of ITLB page walker hits in the L2	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x42	PAGE_WALKER_LOADS.EPT_DTLB_L2	Counts the number of Extended Page Table walks from the DTLB that hit in the L2.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x82	PAGE_WALKER_LOADS.EPT_ITLB_L2	Counts the number of Extended Page Table walks from the ITLB that hit in the L2.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x14	PAGE_WALKER_LOADS.DTLB_L3	Number of DTLB page walker hits in the L3 + XSNP	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x24	PAGE_WALKER_LOADS.ITLB_L3	Number of ITLB page walker hits in the L3 + XSNP	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x44	PAGE_WALKER_LOADS.EPT_DTLB_L3	Counts the number of Extended Page Table walks from the DTLB that hit in the L3.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x84	PAGE_WALKER_LOADS.EPT_ITLB_L3	Counts the number of Extended Page Table walks from the ITLB that hit in the L2.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x18	PAGE_WALKER_LOADS.DTLB_MEMORY	Number of DTLB page walker hits in Memory	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x28	PAGE_WALKER_LOADS.ITLB_MEMORY	Number of ITLB page walker hits in Memory	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x48	PAGE_WALKER_LOADS.EPT_DTLB_MEMORY	Counts the number of Extended Page Table walks from the DTLB that hit in memory.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBC	0x88	PAGE_WALKER_LOADS.EPT_ITLB_MEMORY	Counts the number of Extended Page Table walks from the ITLB that hit in memory.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBD	0x01	TLB_FLUSH.DTLB_THREAD	DTLB flush attempts of the thread-specific entries	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xBD	0x20	TLB_FLUSH.STLB_ANY	STLB flush attempts	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC0	0x01	INST_RETIRED.PREC_DIST	Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution	1	1	2000003	0	0	0	0	0	0	0	2	0	0	null	0
+0xC1	0x08	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	HSM57	0
+0xC1	0x10	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	HSM57	0
+0xC1	0x40	OTHER_ASSISTS.ANY_WB_ASSIST	Number of times any microcode assist is invoked by HW upon uop writeback.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	1	0	null	0
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0	null	0
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	0	null	0
+0xC2	0x01	UOPS_RETIRED.CORE_STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	0	null	0
+0xC3	0x01	MACHINE_CLEARS.CYCLES	Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null	0
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null	0
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null	0
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null	0
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null	0
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3).	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	1	0	0	null	0
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null	0
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null	0
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null	0
+0xc8	0x01	HLE_RETIRED.START	Number of times an HLE execution started.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x02	HLE_RETIRED.COMMIT	Number of times an HLE execution successfully committed	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x04	HLE_RETIRED.ABORTED	Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xc8	0x08	HLE_RETIRED.ABORTED_MISC1	Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x10	HLE_RETIRED.ABORTED_MISC2	Number of times an HLE execution aborted due to uncommon conditions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x20	HLE_RETIRED.ABORTED_MISC3	Number of times an HLE execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x40	HLE_RETIRED.ABORTED_MISC4	Number of times an HLE execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc8	0x80	HLE_RETIRED.ABORTED_MISC5	Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x01	RTM_RETIRED.START	Number of times an RTM execution started.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x02	RTM_RETIRED.COMMIT	Number of times an RTM execution successfully committed	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x04	RTM_RETIRED.ABORTED	Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0	null	0
+0xc9	0x08	RTM_RETIRED.ABORTED_MISC1	Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x10	RTM_RETIRED.ABORTED_MISC2	Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x20	RTM_RETIRED.ABORTED_MISC3	Number of times an RTM execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x40	RTM_RETIRED.ABORTED_MISC4	Number of times an RTM execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xc9	0x80	RTM_RETIRED.ABORTED_MISC5	Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	0	null	0
+0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	0	HSM26	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	0	HSM26	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	0	HSM26	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32	3	3	100003	0x3F6	0x20	1	0	0	0	0	2	0	0	HSM26	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	0	HSM26	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	0	HSM26	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	0	HSM26	0
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	0	HSM26	0
+0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	HSM30	0
+0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	HSM30	0
+0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	1	HSM30	0
+0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD1	0x04	MEM_LOAD_UOPS_RETIRED.L3_HIT	Retired load uops which data sources were data hits in L3 without snoops required.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30	0
+0xD1	0x08	MEM_LOAD_UOPS_RETIRED.L1_MISS	Retired load uops misses in L1 cache as data sources.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD1	0x10	MEM_LOAD_UOPS_RETIRED.L2_MISS	Miss in mid-level (L2) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD1	0x20	MEM_LOAD_UOPS_RETIRED.L3_MISS	Miss in last-level (L3) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30	0
+0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD2	0x01	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30	0
+0xD2	0x02	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30	0
+0xD2	0x04	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared L3.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30	0
+0xD2	0x08	MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in L3 without snoops required.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM26, HSM30	0
+0xD3	0x01	MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM	Data from local DRAM either Snoop not needed or Snoop Miss (RspI)	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD3	0x04	MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM	Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD3	0x10	MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM	Retired load uop whose Data Source was: Remote cache HITM	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0xD3	0x20	MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD	Retired load uop whose Data Source was: forwarded from remote cache	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	HSM30	0
+0x3c	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x08	L2_TRANS.ALL_PF	L2 or L3 HW prefetches that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xf1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xF2	0x05	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xF2	0x06	L2_LINES_OUT.DEMAND_DIRTY	Dirty L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x01	UOPS_EXECUTED_PORT.PORT_0_CORE	Cycles per core when uops are exectuted in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x02	UOPS_EXECUTED_PORT.PORT_1_CORE	Cycles per core when uops are exectuted in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x04	UOPS_EXECUTED_PORT.PORT_2_CORE	Cycles per core when uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x08	UOPS_EXECUTED_PORT.PORT_3_CORE	Cycles per core when uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x10	UOPS_EXECUTED_PORT.PORT_4_CORE	Cycles per core when uops are exectuted in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x20	UOPS_EXECUTED_PORT.PORT_5_CORE	Cycles per core when uops are exectuted in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x40	UOPS_EXECUTED_PORT.PORT_6_CORE	Cycles per core when uops are exectuted in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xA1	0x80	UOPS_EXECUTED_PORT.PORT_7_CORE	Cycles per core when uops are dispatched to port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0xC5	0x20	BR_MISP_RETIRED.NEAR_TAKEN	number of near branch instructions retired that were mispredicted and taken.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null	0
+0x08	0x0e	DTLB_LOAD_MISSES.WALK_COMPLETED	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x08	0x60	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x42	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x22	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x44	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x24	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x27	L2_RQSTS.ALL_DEMAND_MISS	Demand requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xe7	L2_RQSTS.ALL_DEMAND_REFERENCES	Demand requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0x3F	L2_RQSTS.MISS	All requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x0e	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x49	0x60	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x0e	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0x85	0x60	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC	Cycles where at least 1 uop was executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0	HSM31	0
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC	Cycles where at least 2 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0	HSM31	0
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC	Cycles where at least 3 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0	HSM31	0
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC	Cycles where at least 4 uops were executed per-thread	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0	HSM31	0
+0xe6	0x1f	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE	Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	0	0	0	null	0
+0xC3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0	null	0
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	1	1	0	1	0	0	0	null	0
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null	0
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x04	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x08	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x10	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x20	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null	0
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null	0
+0xb1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	1	0	0	0	0	0	null	0
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null	0
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	2	2	2000003	0	0	0	1	0	1	0	0	0	0	null	0
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null	0
+0xC6	0x07	AVX_INSTS.ALL	Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
+0x80	0x04	ICACHE.IFDATA_STALL	Cycles where a code fetch is stalled due to L1 instruction-cache miss.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null	0
diff --git a/x86data/perfmon_data/HSX/HaswellX_matrix_V14.json b/x86data/perfmon_data/HSX/HaswellX_matrix_V14.json
new file mode 100644
index 0000000..b721937
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_matrix_V14.json
@@ -0,0 +1,212 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand data reads"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand data writes (RFOs)"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand code reads"
+  },
+  {
+    "MATRIX_REQUEST": "COREWB",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000008",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts writebacks (modified to exclusive)"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000010",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to L2) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000020",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to L2) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000040",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000200",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "OTHER",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any other requests"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000090",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000120",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000240",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000091",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000122",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000244",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_READS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x00000007f7",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all data/code/rfo reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_REQUESTS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008fff",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all requests"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3f803c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.NO_SNOOP_NEEDED",
+    "MATRIX_VALUE": "0x01003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.SNOOP_MISS",
+    "MATRIX_VALUE": "0x02003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoops sent to sibling cores return clean response"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+    "MATRIX_VALUE": "0x04003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.HITM_OTHER_CORE",
+    "MATRIX_VALUE": "0x10003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3fffc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss in the L3"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.LOCAL_DRAM",
+    "MATRIX_VALUE": "0x0600400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the L3 and the data is returned from local dram"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.REMOTE_DRAM",
+    "MATRIX_VALUE": "0x067f800000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the L3 and the data is returned from remote dram"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_DRAM",
+    "MATRIX_VALUE": "0x067fc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the L3 and the data is returned from local or remote dram"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.REMOTE_HITM",
+    "MATRIX_VALUE": "0x107fc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the L3 and the modified data is transferred from remote cache"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.REMOTE_HIT_FORWARD",
+    "MATRIX_VALUE": "0x087fc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the L3 and clean or shared data is transferred from remote cache"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/HSX/HaswellX_matrix_V14.tsv b/x86data/perfmon_data/HSX/HaswellX_matrix_V14.tsv
new file mode 100644
index 0000000..84c0adc
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_matrix_V14.tsv
@@ -0,0 +1,34 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 v3 family based on the Haswell-E microarchitecture - V14
+# 8/3/2015 11:49:52 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand data reads
+DEMAND_RFO	Null	0x0002	0,1	Counts all demand data writes (RFOs)
+DEMAND_CODE_RD	Null	0x0004	0,1	Counts all demand code reads
+COREWB	Null	0x0008	0,1	Counts writebacks (modified to exclusive)
+PF_L2_DATA_RD	Null	0x0010	0,1	Counts prefetch (that bring data to L2) data reads
+PF_L2_RFO	Null	0x0020	0,1	Counts all prefetch (that bring data to L2) RFOs
+PF_L2_CODE_RD	Null	0x0040	0,1	Counts all prefetch (that bring data to LLC only) code reads
+PF_LLC_DATA_RD	Null	0x0080	0,1	Counts all prefetch (that bring data to LLC only) data reads
+PF_LLC_RFO	Null	0x0100	0,1	Counts all prefetch (that bring data to LLC only) RFOs
+PF_LLC_CODE_RD	Null	0x0200	0,1	Counts prefetch (that bring data to LLC only) code reads
+OTHER	Null	0x8000	0,1	Counts any other requests
+ALL_PF_DATA_RD	Null	0x0090	0,1	Counts all prefetch data reads
+ALL_PF_RFO	Null	0x0120	0,1	Counts prefetch RFOs
+ALL_PF_CODE_RD	Null	0x0240	0,1	Counts all prefetch code reads
+ALL_DATA_RD	Null	0x0091	0,1	Counts all demand & prefetch data reads
+ALL_RFO	Null	0x0122	0,1	Counts all demand & prefetch RFOs
+ALL_CODE_RD	Null	0x0244	0,1	Counts all demand & prefetch code reads
+ALL_READS	Null	0x07f7	0,1	Counts all data/code/rfo reads (demand & prefetch)
+ALL_REQUESTS	Null	0x8fff	0,1	Counts all requests
+Null	LLC_HIT.ANY_RESPONSE	0x3f803c	0,1	hit in the L3
+Null	LLC_HIT.NO_SNOOP_NEEDED	0x01003c	0,1	hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
+Null	LLC_HIT.SNOOP_MISS	0x02003c	0,1	hit in the L3 and the snoops sent to sibling cores return clean response
+Null	LLC_HIT.HIT_OTHER_CORE_NO_FWD	0x04003c	0,1	hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
+Null	LLC_HIT.HITM_OTHER_CORE	0x10003c	0,1	hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
+Null	LLC_MISS.ANY_RESPONSE	0x3fffc0	0,1	miss in the L3
+Null	LLC_MISS.LOCAL_DRAM	0x060040	0,1	miss the L3 and the data is returned from local dram
+Null	LLC_MISS.REMOTE_DRAM	0x067f80	0,1	miss the L3 and the data is returned from remote dram
+Null	LLC_MISS.ANY_DRAM	0x067fc0	0,1	miss the L3 and the data is returned from local or remote dram
+Null	LLC_MISS.REMOTE_HITM	0x107fc0	0,1	miss the L3 and the modified data is transferred from remote cache
+Null	LLC_MISS.REMOTE_HIT_FORWARD	0x087fc0	0,1	miss the L3 and clean or shared data is transferred from remote cache
diff --git a/x86data/perfmon_data/HSX/HaswellX_matrix_bit_definitions_V14.json b/x86data/perfmon_data/HSX/HaswellX_matrix_bit_definitions_V14.json
new file mode 100644
index 0000000..a6041ec
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_matrix_bit_definitions_V14.json
@@ -0,0 +1,296 @@
+[
+  {
+    "BitName": "DEMAND_DATA_RD",
+    "BitIndex": "0",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_RFO",
+    "BitIndex": "1",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_CODE_RD",
+    "BitIndex": "2",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "COREWB",
+    "BitIndex": "3",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_DATA_RD",
+    "BitIndex": "4",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_RFO",
+    "BitIndex": "5",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_CODE_RD",
+    "BitIndex": "6",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_DATA_RD",
+    "BitIndex": "7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_RFO",
+    "BitIndex": "8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_CODE_RD",
+    "BitIndex": "9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SPLIT_LOCK_UC_LOCK",
+    "BitIndex": "10",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "STREAMING_STORES",
+    "BitIndex": "11",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "OTHER",
+    "BitIndex": "15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_DATA_RD",
+    "BitIndex": "4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_RFO",
+    "BitIndex": "5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_CODE_RD",
+    "BitIndex": "6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_DATA_RD",
+    "BitIndex": "0,4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_RFO",
+    "BitIndex": "1,5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_CODE_RD",
+    "BitIndex": "2,6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_READS",
+    "BitIndex": "0,1,2,4,5,6,7,8,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_REQUESTS",
+    "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_RESPONSE",
+    "BitIndex": "16",
+    "Type": "2",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SUPPLIER_NONE",
+    "BitIndex": "17",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_M",
+    "BitIndex": "18",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_E",
+    "BitIndex": "19",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_S",
+    "BitIndex": "20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_F",
+    "BitIndex": "21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT",
+    "BitIndex": "18,19,20,21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_LOCAL_DRAM",
+    "BitIndex": "22",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_REMOTE_HOP0",
+    "BitIndex": "27",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_REMOTE_HOP1",
+    "BitIndex": "28",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_REMOTE_HOP2P",
+    "BitIndex": "29",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS",
+    "BitIndex": "22,27,28,29",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SPL_HIT",
+    "BitIndex": "30",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NONE",
+    "BitIndex": "31",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NOT_NEEDED",
+    "BitIndex": "32",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_MISS",
+    "BitIndex": "33",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_NO_FWD",
+    "BitIndex": "34",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_WITH_FWD",
+    "BitIndex": "35",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "18,19,20,21"
+  },
+  {
+    "BitName": "SNOOP_HITM",
+    "BitIndex": "36",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NON_DRAM",
+    "BitIndex": "37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_SNOOP",
+    "BitIndex": "31,32,33,34,35,36,37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/HSX/HaswellX_matrix_bit_definitions_V14.tsv b/x86data/perfmon_data/HSX/HaswellX_matrix_bit_definitions_V14.tsv
new file mode 100644
index 0000000..aae33db
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_matrix_bit_definitions_V14.tsv
@@ -0,0 +1,46 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 v3 family based on the Haswell-E microarchitecture - V14
+# 8/3/2015 11:49:53 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	Type	MATRIX_REG	BitsNotCombinedWith
+DEMAND_DATA_RD	0	1	0,1	Null
+DEMAND_RFO	1	1	0,1	Null
+DEMAND_CODE_RD	2	1	0,1	Null
+COREWB	3	1	0,1	Null
+PF_L2_DATA_RD	4	1	0,1	Null
+PF_L2_RFO	5	1	0,1	Null
+PF_L2_CODE_RD	6	1	0,1	Null
+PF_L3_DATA_RD	7	1	0,1	Null
+PF_L3_RFO	8	1	0,1	Null
+PF_L3_CODE_RD	9	1	0,1	Null
+SPLIT_LOCK_UC_LOCK	10	1	0,1	Null
+STREAMING_STORES	11	1	0,1	Null
+OTHER	15	1	0,1	Null
+ALL_PF_DATA_RD	4,7	1	0,1	Null
+ALL_PF_RFO	5,8	1	0,1	Null
+ALL_PF_CODE_RD	6,9	1	0,1	Null
+ALL_DATA_RD	0,4,7	1	0,1	Null
+ALL_RFO	1,5,8	1	0,1	Null
+ALL_CODE_RD	2,6,9	1	0,1	Null
+ALL_READS	0,1,2,4,5,6,7,8,9	1	0,1	Null
+ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	0,1	Null
+ANY_RESPONSE	16	2	0,1	Null
+SUPPLIER_NONE	17	3	0,1	Null
+L3_HIT_M	18	3	0,1	Null
+L3_HIT_E	19	3	0,1	Null
+L3_HIT_S	20	3	0,1	Null
+L3_HIT_F	21	3	0,1	Null
+L3_HIT	18,19,20,21	3	0,1	Null
+L3_MISS_LOCAL_DRAM	22	3	0,1	Null
+L3_MISS_REMOTE_HOP0	27	3	0,1	Null
+L3_MISS_REMOTE_HOP1	28	3	0,1	Null
+L3_MISS_REMOTE_HOP2P	29	3	0,1	Null
+L3_MISS	22,27,28,29	3	0,1	Null
+SPL_HIT	30	4	0,1	Null
+SNOOP_NONE	31	4	0,1	Null
+SNOOP_NOT_NEEDED	32	4	0,1	Null
+SNOOP_MISS	33	4	0,1	Null
+SNOOP_HIT_NO_FWD	34	4	0,1	Null
+SNOOP_HIT_WITH_FWD	35	4	0,1	18,19,20,21
+SNOOP_HITM	36	4	0,1	Null
+SNOOP_NON_DRAM	37	4	0,1	Null
+ANY_SNOOP	31,32,33,34,35,36,37	4	0,1	Null
diff --git a/x86data/perfmon_data/HSX/HaswellX_offcore_V14.tsv b/x86data/perfmon_data/HSX/HaswellX_offcore_V14.tsv
new file mode 100644
index 0000000..1fe984a
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_offcore_V14.tsv
@@ -0,0 +1,51 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 v3 family based on the Haswell-E microarchitecture - V14
+# 8/3/2015 11:49:53 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata	ELLC
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD	Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0001	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE	Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0001	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE	Counts demand data reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00001	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM	Counts demand data reads that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0600400001	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0002	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE	Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0002	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE	Counts all demand data writes (RFOs) that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00002	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM	Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0600400002	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0004	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE	Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0004	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE	Counts all demand code reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00004	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM	Counts all demand code reads that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0600400004	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE	Counts prefetch (that bring data to L2) data reads that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0010	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE	Counts prefetch (that bring data to L2) data reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00010	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE	Counts all prefetch (that bring data to L2) RFOs that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0020	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE	Counts all prefetch (that bring data to L2) RFOs that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00020	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) code reads that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0040	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) code reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00040	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0080	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) data reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00080	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0100	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00100	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE	Counts prefetch (that bring data to LLC only) code reads that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c0200	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE	Counts prefetch (that bring data to LLC only) code reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00200	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0091	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE	Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0091	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE	Counts all demand & prefetch data reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00091	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM	Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0600400091	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM	Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x067f800091	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM	Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x107fc00091	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD	Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x087fc00091	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0122	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE	Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c0122	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE	Counts all demand & prefetch RFOs that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00122	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM	Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0600400122	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD	Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c0244	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE	Counts all demand & prefetch code reads that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc00244	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM	Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0600400244	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD	Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04003c07f7	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE	Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10003c07f7	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE	Counts all data/code/rfo reads (demand & prefetch) that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc007f7	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM	Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x06004007f7	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM	Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x067f8007f7	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM	Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x107fc007f7	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD	Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x087fc007f7	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE	Counts all requests that hit in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3f803c8fff	0	0	0	0	0	0	0	0	null	0
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE	Counts all requests that miss in the L3	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fffc08fff	0	0	0	0	0	0	0	0	null	0
diff --git a/x86data/perfmon_data/HSX/HaswellX_uncore_V14.json b/x86data/perfmon_data/HSX/HaswellX_uncore_V14.json
new file mode 100644
index 0000000..a14608d
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_uncore_V14.json
@@ -0,0 +1,15362 @@
+[
+  {
+    "Unit": "CBO",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_C_BOUNCE_CONTROL",
+    "BriefDescription": "Bounce Control",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_C_CLOCKTICKS",
+    "BriefDescription": "Uncore Clocks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1F",
+    "UMask": "0x0",
+    "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+    "BriefDescription": "Counter 0 Occupancy",
+    "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_C_FAST_ASSERTED",
+    "BriefDescription": "FaST wire asserted",
+    "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted.  Incoming distress includes both up and dn.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x3",
+    "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+    "BriefDescription": "Cache Lookups; Data Read Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x5",
+    "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+    "BriefDescription": "Cache Lookups; Write Requests",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x9",
+    "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+    "BriefDescription": "Cache Lookups; External Snoop Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x11",
+    "EventName": "UNC_C_LLC_LOOKUP.ANY",
+    "BriefDescription": "Cache Lookups; Any Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x41",
+    "EventName": "UNC_C_LLC_LOOKUP.NID",
+    "BriefDescription": "Cache Lookups; Lookups that Match NID",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x21",
+    "EventName": "UNC_C_LLC_LOOKUP.READ",
+    "BriefDescription": "Cache Lookups; Any Read Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter0[22:18]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x1",
+    "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+    "BriefDescription": "Lines Victimized; Lines in M state",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x2",
+    "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+    "BriefDescription": "Lines Victimized; Lines in E state",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x4",
+    "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+    "BriefDescription": "Lines in S State",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x8",
+    "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
+    "BriefDescription": "Lines Victimized",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x40",
+    "EventName": "UNC_C_LLC_VICTIMS.NID",
+    "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x10",
+    "EventName": "UNC_C_LLC_VICTIMS.MISS",
+    "BriefDescription": "Lines Victimized",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x1",
+    "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+    "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x2",
+    "EventName": "UNC_C_MISC.WC_ALIASING",
+    "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x4",
+    "EventName": "UNC_C_MISC.STARTED",
+    "BriefDescription": "Cbo Misc",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x8",
+    "EventName": "UNC_C_MISC.RFO_HIT_S",
+    "BriefDescription": "Cbo Misc; RFO HitS",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state.  This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x10",
+    "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+    "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x20",
+    "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+    "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x1",
+    "EventName": "UNC_C_QLRU.AGE0",
+    "BriefDescription": "LRU Queue; LRU Age 0",
+    "PublicDescription": "How often age was set to 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x2",
+    "EventName": "UNC_C_QLRU.AGE1",
+    "BriefDescription": "LRU Queue; LRU Age 1",
+    "PublicDescription": "How often age was set to 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x4",
+    "EventName": "UNC_C_QLRU.AGE2",
+    "BriefDescription": "LRU Queue; LRU Age 2",
+    "PublicDescription": "How often age was set to 2",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x8",
+    "EventName": "UNC_C_QLRU.AGE3",
+    "BriefDescription": "LRU Queue; LRU Age 3",
+    "PublicDescription": "How often age was set to 3",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x10",
+    "EventName": "UNC_C_QLRU.LRU_DECREMENT",
+    "BriefDescription": "LRU Queue; LRU Bits Decremented",
+    "PublicDescription": "How often all LRU bits were decremented by 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3C",
+    "UMask": "0x20",
+    "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
+    "BriefDescription": "LRU Queue; Non-0 Aged Victim",
+    "PublicDescription": "How often we picked a victim that had a non-zero age",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+    "BriefDescription": "AD Ring In Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_AD_USED.UP_ODD",
+    "BriefDescription": "AD Ring In Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
+    "BriefDescription": "AD Ring In Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
+    "BriefDescription": "AD Ring In Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_AD_USED.UP",
+    "BriefDescription": "AD Ring In Use; Up",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_AD_USED.DOWN",
+    "BriefDescription": "AD Ring In Use; Down",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_AD_USED.ALL",
+    "BriefDescription": "AD Ring In Use; All",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
+    "BriefDescription": "AK Ring In Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_AK_USED.UP_ODD",
+    "BriefDescription": "AK Ring In Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
+    "BriefDescription": "AK Ring In Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
+    "BriefDescription": "AK Ring In Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_AK_USED.UP",
+    "BriefDescription": "AK Ring In Use; Up",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_AK_USED.DOWN",
+    "BriefDescription": "AK Ring In Use; Down",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_AK_USED.ALL",
+    "BriefDescription": "AK Ring In Use; All",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
+    "BriefDescription": "BL Ring in Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BL_USED.UP_ODD",
+    "BriefDescription": "BL Ring in Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
+    "BriefDescription": "BL Ring in Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
+    "BriefDescription": "BL Ring in Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_BL_USED.UP",
+    "BriefDescription": "BL Ring in Use; Up",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_BL_USED.DOWN",
+    "BriefDescription": "BL Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_BL_USED.ALL",
+    "BriefDescription": "BL Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_BOUNCES.AD",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BOUNCES.AK",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BOUNCES.BL",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RING_BOUNCES.IV",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1E",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_IV_USED.ANY",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1E",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_IV_USED.UP",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1E",
+    "UMask": "0xCC",
+    "EventName": "UNC_C_RING_IV_USED.DOWN",
+    "BriefDescription": "BL Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1E",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_IV_USED.DN",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_SINK_STARVED.AD",
+    "BriefDescription": "AD",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_SINK_STARVED.AK",
+    "BriefDescription": "AK",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_SINK_STARVED.IV",
+    "BriefDescription": "IV",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_SINK_STARVED.BL",
+    "BriefDescription": "BL",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_C_RING_SRC_THRTL",
+    "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ",
+    "BriefDescription": "Ingress Allocations; IRQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
+    "BriefDescription": "Ingress Allocations; IRQ Rejected",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_INSERTS.IPQ",
+    "BriefDescription": "Ingress Allocations; IPQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_INSERTS.PRQ",
+    "BriefDescription": "Ingress Allocations; PRQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
+    "BriefDescription": "Ingress Allocations; PRQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
+    "BriefDescription": "Probe Queue Retries; Any Reject",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject.  TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
+    "BriefDescription": "Probe Queue Retries; No Egress Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full.  IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
+    "BriefDescription": "Probe Queue Retries; Address Conflict",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts.  Address conflicts out of the IPQ should be rare.  They will generally only occur if two different sockets are sending requests to the same address at the same time.  This is a true 'conflict' case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "Probe Queue Retries; No QPI Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
+    "BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x28",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
+    "BriefDescription": "Probe Queue Retries; Target Node Filter",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
+    "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
+    "PublicDescription": "Counts the number of IRQ retries that occur.  Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons.  Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
+    "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
+    "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress.  The egress is the buffer that queues up for allocating onto the ring.  IRQ requests can make use of all four rings and all four Egresses.  If any of the queues that a given request needs to make use of are full, the request will be retried.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+    "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+    "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR.  In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo.  Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete.  This comes up most commonly with prefetches.  Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC.  Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+    "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
+    "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available.  RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory.  If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available.  Note that there are multiple RTID pools for the different sockets.  There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available.  This event does not provide any filtering for this case.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
+    "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits.  These credits are required in order to send transactions to the QPI agent.  Please see the QPI_IGR_CREDITS events for more information.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
+    "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
+    "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
+    "BriefDescription": "Ingress Request Queue Rejects",
+    "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
+    "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
+    "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
+    "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
+    "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x29",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
+    "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
+    "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
+    "BriefDescription": "ISMQ Retries; Any Reject",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject.  ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries).  ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID.  Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
+    "BriefDescription": "ISMQ Retries; No Egress Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring.  If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+    "BriefDescription": "ISMQ Retries; No RTIDs",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs.  M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory.  If no RTIDs are available, they will be retried.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "ISMQ Retries; No QPI Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+    "BriefDescription": "ISMQ Retries; No IIO Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x80",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
+    "BriefDescription": "ISMQ Retries",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
+    "BriefDescription": "ISMQ Retries",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2A",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
+    "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
+    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2A",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
+    "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
+    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2A",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
+    "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
+    "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
+    "BriefDescription": "Ingress Occupancy; IRQ",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJECTED",
+    "BriefDescription": "IRQ Rejected",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.;RTLSignal: PmonIrqQualRejAllocU119H[0];Additional Notes: IRQ_REJECTED should not be Ored with the other umasks.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+    "BriefDescription": "Ingress Occupancy; IPQ",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ",
+    "BriefDescription": "Ingress Occupancy; PRQ Rejects",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3D",
+    "UMask": "0x1",
+    "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3D",
+    "UMask": "0x2",
+    "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3E",
+    "UMask": "0x1",
+    "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3E",
+    "UMask": "0x2",
+    "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TOR_INSERTS.OPCODE",
+    "BriefDescription": "TOR Inserts; Opcode Match",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TOR_INSERTS.EVICTION",
+    "BriefDescription": "TOR Inserts; Evictions",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Eviction transactions inserted into the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TOR_INSERTS.ALL",
+    "BriefDescription": "TOR Inserts; All",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR.    This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TOR_INSERTS.WB",
+    "BriefDescription": "TOR Inserts; Writebacks",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Write transactions inserted into the TOR.   This does not include 'RFO', but actual operations that contain data being sent from the core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x3",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
+    "BriefDescription": "TOR Inserts; Miss Opcode Match",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x41",
+    "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
+    "BriefDescription": "TOR Inserts; NID and Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x44",
+    "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
+    "BriefDescription": "TOR Inserts; NID Matched Evictions",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x48",
+    "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
+    "BriefDescription": "TOR Inserts; NID Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.  In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x50",
+    "EventName": "UNC_C_TOR_INSERTS.NID_WB",
+    "BriefDescription": "TOR Inserts; NID Matched Writebacks",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched write transactions inserted into the TOR.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x43",
+    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+    "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x4A",
+    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+    "BriefDescription": "TOR Inserts; NID Matched Miss All",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x2A",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
+    "BriefDescription": "TOR Inserts; Misses to Local Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x8A",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
+    "BriefDescription": "TOR Inserts; Misses to Remote Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x28",
+    "EventName": "UNC_C_TOR_INSERTS.LOCAL",
+    "BriefDescription": "TOR Inserts; Local Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x88",
+    "EventName": "UNC_C_TOR_INSERTS.REMOTE",
+    "BriefDescription": "TOR Inserts; Remote Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x23",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
+    "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x83",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
+    "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x21",
+    "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
+    "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x81",
+    "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
+    "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+    "BriefDescription": "TOR Occupancy; Opcode Match",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
+    "BriefDescription": "TOR Occupancy; Evictions",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+    "BriefDescription": "TOR Occupancy; Any",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries.  This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x3",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
+    "BriefDescription": "TOR Occupancy; Miss Opcode Match",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0xA",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
+    "BriefDescription": "TOR Occupancy; Miss All",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x41",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+    "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x44",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
+    "BriefDescription": "TOR Occupancy; NID Matched Evictions",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x48",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+    "BriefDescription": "TOR Occupancy; NID Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x43",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
+    "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x4A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
+    "BriefDescription": "TOR Occupancy; NID Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x2A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x8A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x28",
+    "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x88",
+    "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x23",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
+    "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x83",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+    "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x21",
+    "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
+    "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x81",
+    "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
+    "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TOR_OCCUPANCY.WB",
+    "BriefDescription": "TOR Occupancy; Writebacks",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR.   This does not include 'RFO', but actual operations that contain data being sent from the core.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x50",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
+    "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TxR_ADS_USED.AD",
+    "BriefDescription": "Onto AD Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_ADS_USED.AK",
+    "BriefDescription": "Onto AK Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_ADS_USED.BL",
+    "BriefDescription": "Onto BL Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
+    "BriefDescription": "Egress Allocations; AD - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
+    "BriefDescription": "Egress Allocations; AK - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
+    "BriefDescription": "Egress Allocations; BL - Cacheno",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
+    "BriefDescription": "Egress Allocations; IV - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring.  This is commonly used for snoops to the cores.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
+    "BriefDescription": "Egress Allocations; AD - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring.  This is commonly used for outbound requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x20",
+    "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
+    "BriefDescription": "Egress Allocations; AK - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring.  This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x40",
+    "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
+    "BriefDescription": "Egress Allocations; BL - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring.  This is commonly used for transfering writeback data to the cache.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
+    "BriefDescription": "Injection Starvation; Onto AK Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
+    "BriefDescription": "Injection Starvation; Onto BL Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TxR_STARVED.IV",
+    "BriefDescription": "Injection Starvation; Onto IV Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TxR_STARVED.AD_CORE",
+    "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x3",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
+    "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x1",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
+    "BriefDescription": "QPI Address/Opcode Match; Address",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x2",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
+    "BriefDescription": "QPI Address/Opcode Match; Opcode",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x4",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
+    "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x8",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
+    "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x10",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
+    "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_H_BT_CYCLES_NE",
+    "BriefDescription": "BT Cycles Not Empty",
+    "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x4",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x8",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x10",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_H_BYPASS_IMC.TAKEN",
+    "BriefDescription": "HA to iMC Bypass; Taken",
+    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
+    "BriefDescription": "HA to iMC Bypass; Not Taken",
+    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_H_CLOCKTICKS",
+    "BriefDescription": "uclks",
+    "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x11",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_COUNT",
+    "BriefDescription": "Direct2Core Messages Sent",
+    "PublicDescription": "Number of Direct2Core messages sent",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
+    "BriefDescription": "Cycles when Direct2Core was Disabled",
+    "PublicDescription": "Number of cycles in which Direct2Core was disabled",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x13",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
+    "BriefDescription": "Number of Reads that had Direct2Core Overridden",
+    "PublicDescription": "Number of Reads where Direct2Core overridden",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x41",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECTORY_LAT_OPT",
+    "BriefDescription": "Directory Lat Opt Return",
+    "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xC",
+    "UMask": "0x1",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
+    "BriefDescription": "Directory Lookups; Snoop Needed",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xC",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
+    "BriefDescription": "Directory Lookups; Snoop Not Needed",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xD",
+    "UMask": "0x1",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
+    "BriefDescription": "Directory Updates; Directory Set",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory sets.  This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xD",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
+    "BriefDescription": "Directory Updates; Directory Clear",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory clears.  This occurs when snoops were sent and all returned with RspI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xD",
+    "UMask": "0x3",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
+    "BriefDescription": "Directory Updates; Any Directory Update",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x1",
+    "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x2",
+    "EventName": "UNC_H_HITME_HIT.WBMTOI",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x4",
+    "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x8",
+    "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x10",
+    "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x20",
+    "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x40",
+    "EventName": "UNC_H_HITME_HIT.RSPFWDS",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x80",
+    "EventName": "UNC_H_HITME_HIT.RSP",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x70",
+    "EventName": "UNC_H_HITME_HIT.ALLOCS",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x42",
+    "EventName": "UNC_H_HITME_HIT.EVICTS",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0x26",
+    "EventName": "UNC_H_HITME_HIT.INVALS",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0xFF",
+    "EventName": "UNC_H_HITME_HIT.ALL",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x71",
+    "UMask": "0xF",
+    "EventName": "UNC_H_HITME_HIT.HOM",
+    "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x1",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x2",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x4",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x8",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x10",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x20",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x40",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0x80",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0xFF",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x72",
+    "UMask": "0xF",
+    "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
+    "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x1",
+    "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x2",
+    "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x4",
+    "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x8",
+    "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x10",
+    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x20",
+    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x40",
+    "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x80",
+    "EventName": "UNC_H_HITME_LOOKUP.RSP",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x70",
+    "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0x26",
+    "EventName": "UNC_H_HITME_LOOKUP.INVALS",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0xFF",
+    "EventName": "UNC_H_HITME_LOOKUP.ALL",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x70",
+    "UMask": "0xF",
+    "EventName": "UNC_H_HITME_LOOKUP.HOM",
+    "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
+    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
+    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x8",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x10",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x20",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IMC_READS.NORMAL",
+    "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
+    "PublicDescription": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1E",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IMC_RETRY",
+    "BriefDescription": "Retry Events",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IMC_WRITES.FULL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0x8",
+    "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1A",
+    "UMask": "0xF",
+    "EventName": "UNC_H_IMC_WRITES.ALL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x61",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
+    "BriefDescription": "IOT Backpressure",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x61",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
+    "BriefDescription": "IOT Backpressure",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x64",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x64",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x65",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IOT_CTS_HI.CTS2",
+    "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x65",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IOT_CTS_HI.CTS3",
+    "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x62",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x62",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x2",
+    "EventName": "UNC_H_OSB.READS_LOCAL",
+    "BriefDescription": "OSB Snoop Broadcast; Local Reads",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x4",
+    "EventName": "UNC_H_OSB.INVITOE_LOCAL",
+    "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x8",
+    "EventName": "UNC_H_OSB.REMOTE",
+    "BriefDescription": "OSB Snoop Broadcast; Remote",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x10",
+    "EventName": "UNC_H_OSB.CANCELLED",
+    "BriefDescription": "OSB Snoop Broadcast; Cancelled",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x20",
+    "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
+    "BriefDescription": "OSB Snoop Broadcast; Reads Local -  Useful",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x40",
+    "EventName": "UNC_H_OSB.REMOTE_USEFUL",
+    "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x1",
+    "EventName": "UNC_H_OSB_EDR.ALL",
+    "BriefDescription": "OSB Early Data Return; All",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x2",
+    "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
+    "BriefDescription": "OSB Early Data Return; Reads to Local  I",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x4",
+    "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
+    "BriefDescription": "OSB Early Data Return; Reads to Remote I",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x8",
+    "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
+    "BriefDescription": "OSB Early Data Return; Reads to Local S",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x10",
+    "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
+    "BriefDescription": "OSB Early Data Return; Reads to Remote S",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x3",
+    "EventName": "UNC_H_REQUESTS.READS",
+    "BriefDescription": "Read and Write Requests; Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests.  This is a good proxy for LLC Read Misses (including RFOs).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0xC",
+    "EventName": "UNC_H_REQUESTS.WRITES",
+    "BriefDescription": "Read and Write Requests; Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket.  This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_H_REQUESTS.READS_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket.  This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x10",
+    "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local InvItoEs",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x20",
+    "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote InvItoEs",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_AD_USED.CW_ODD",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x3",
+    "EventName": "UNC_H_RING_AD_USED.CW",
+    "BriefDescription": "HA AD Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0xC",
+    "EventName": "UNC_H_RING_AD_USED.CCW",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_AK_USED.CW_ODD",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x3",
+    "EventName": "UNC_H_RING_AK_USED.CW",
+    "BriefDescription": "HA AK Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0xC",
+    "EventName": "UNC_H_RING_AK_USED.CCW",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_BL_USED.CW_ODD",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x3",
+    "EventName": "UNC_H_RING_BL_USED.CW",
+    "BriefDescription": "HA BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0xC",
+    "EventName": "UNC_H_RING_BL_USED.CCW",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x68",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x68",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6A",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6A",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x69",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x69",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6B",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6B",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xA",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
+    "BriefDescription": "Data beat the Snoop Responses; Local Requests",
+    "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xA",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
+    "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
+    "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
+    "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
+    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
+    "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
+    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x8",
+    "UMask": "0x3",
+    "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
+    "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
+    "PublicDescription": "Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
+    "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
+    "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
+    "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
+    "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOP_RESP.RSPI",
+    "BriefDescription": "Snoop Responses Received; RspI",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOP_RESP.RSPS",
+    "BriefDescription": "Snoop Responses Received; RspS",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x4",
+    "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+    "BriefDescription": "Snoop Responses Received; RspIFwd",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x8",
+    "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+    "BriefDescription": "Snoop Responses Received; RspSFwd",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x10",
+    "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+    "BriefDescription": "Snoop Responses Received; Rsp*WB",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x20",
+    "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+    "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x40",
+    "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+    "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
+    "BriefDescription": "Snoop Responses Received Local; RspI",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
+    "BriefDescription": "Snoop Responses Received Local; RspS",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x4",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
+    "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x8",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
+    "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x10",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
+    "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x20",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
+    "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x40",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
+    "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x80",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
+    "BriefDescription": "Snoop Responses Received Local; Other",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for all other snoop responses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6C",
+    "UMask": "0x1",
+    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6C",
+    "UMask": "0x2",
+    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6C",
+    "UMask": "0x4",
+    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6C",
+    "UMask": "0x8",
+    "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x10",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x20",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x40",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1B",
+    "UMask": "0x80",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1C",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1C",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1C",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1C",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
+    "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used.  It will not return valid count when BT is disabled.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
+    "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries.  It will not return valid count when BT is disabled.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
+    "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
+    "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x10",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
+    "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x20",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
+    "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x40",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+    "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x4",
+    "UMask": "0x80",
+    "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
+    "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
+    "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x5",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
+    "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
+    "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
+    "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
+    "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xF",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TxR_AD.HOM",
+    "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
+    "PublicDescription": "Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring.  NDR stands for 'non-data response' and is generally used for completions that do not include data.  AD NDR is used for transactions to remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2A",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
+    "BriefDescription": "AD Egress Full; Scheduler 0",
+    "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2A",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
+    "BriefDescription": "AD Egress Full; Scheduler 1",
+    "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2A",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+    "BriefDescription": "AD Egress Full; All",
+    "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
+    "BriefDescription": "AD Egress Not Empty; Scheduler 0",
+    "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
+    "BriefDescription": "AD Egress Not Empty; Scheduler 1",
+    "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+    "BriefDescription": "AD Egress Not Empty; All",
+    "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
+    "BriefDescription": "AD Egress Allocations; Scheduler 0",
+    "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
+    "BriefDescription": "AD Egress Allocations; Scheduler 1",
+    "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+    "BriefDescription": "AD Egress Allocations; All",
+    "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
+    "BriefDescription": "AK Egress Full; Scheduler 0",
+    "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
+    "BriefDescription": "AK Egress Full; Scheduler 1",
+    "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+    "BriefDescription": "AK Egress Full; All",
+    "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
+    "BriefDescription": "AK Egress Not Empty; Scheduler 0",
+    "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
+    "BriefDescription": "AK Egress Not Empty; Scheduler 1",
+    "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+    "BriefDescription": "AK Egress Not Empty; All",
+    "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2F",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
+    "BriefDescription": "AK Egress Allocations; Scheduler 0",
+    "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2F",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
+    "BriefDescription": "AK Egress Allocations; Scheduler 1",
+    "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2F",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
+    "BriefDescription": "AK Egress Allocations; All",
+    "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL.DRS_CACHE",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to the cache.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL.DRS_CORE",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TxR_BL.DRS_QPI",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
+    "BriefDescription": "BL Egress Full; Scheduler 0",
+    "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
+    "BriefDescription": "BL Egress Full; Scheduler 1",
+    "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+    "BriefDescription": "BL Egress Full; All",
+    "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
+    "BriefDescription": "BL Egress Not Empty; Scheduler 0",
+    "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
+    "BriefDescription": "BL Egress Not Empty; Scheduler 1",
+    "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+    "BriefDescription": "BL Egress Not Empty; All",
+    "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
+    "BriefDescription": "BL Egress Allocations; Scheduler 0",
+    "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
+    "BriefDescription": "BL Egress Allocations; Scheduler 1",
+    "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
+    "BriefDescription": "BL Egress Allocations; All",
+    "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6D",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_STARVED.AK",
+    "BriefDescription": "Injection Starvation; For AK Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6D",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_STARVED.BL",
+    "BriefDescription": "Injection Starvation; For BL Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x1",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x2",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x4",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x8",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x1",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x2",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x4",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x8",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+    "BriefDescription": "Total Write Cache Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
+    "BriefDescription": "Total Write Cache Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_I_CLOCKTICKS",
+    "BriefDescription": "Clocks in the IRP",
+    "PublicDescription": "Number of clocks in the IRP.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+    "BriefDescription": "Coherent Ops; PCIRdCur",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_I_COHERENT_OPS.CRD",
+    "BriefDescription": "Coherent Ops; CRd",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_I_COHERENT_OPS.DRD",
+    "BriefDescription": "Coherent Ops; DRd",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_I_COHERENT_OPS.RFO",
+    "BriefDescription": "Coherent Ops; RFO",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+    "BriefDescription": "Coherent Ops; PCIItoM",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+    "BriefDescription": "Coherent Ops; PCIDCAHin5t",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x40",
+    "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+    "BriefDescription": "Coherent Ops; WbMtoI",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x80",
+    "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+    "BriefDescription": "Coherent Ops; CLFlush",
+    "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_I_MISC0.FAST_REQ",
+    "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_I_MISC0.FAST_REJ",
+    "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x4",
+    "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x8",
+    "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x10",
+    "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+    "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x20",
+    "EventName": "UNC_I_MISC0.FAST_XFER",
+    "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x40",
+    "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+    "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x80",
+    "EventName": "UNC_I_MISC0.UNKNOWN",
+    "BriefDescription": "Misc Events - Set 0",
+    "PublicDescription": "RTLSignal: iirpc2irppm_misc0_events0[7] + iirpc2irppm_misc0_events1[7];RTLSignal2: .iirpc2irppm_misc0_events0[6]+.iirpc2irppm_misc0_events1[6]",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_I_MISC1.SLOW_I",
+    "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
+    "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_I_MISC1.SLOW_S",
+    "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
+    "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_I_MISC1.SLOW_E",
+    "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
+    "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_I_MISC1.SLOW_M",
+    "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
+    "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x10",
+    "EventName": "UNC_I_MISC1.LOST_FWD",
+    "BriefDescription": "Misc Events - Set 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x20",
+    "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+    "BriefDescription": "Misc Events - Set 1; Received Invalid",
+    "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x40",
+    "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+    "BriefDescription": "Misc Events - Set 1; Received Valid",
+    "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x80",
+    "EventName": "UNC_I_MISC1.DATA_THROTTLE",
+    "BriefDescription": "Misc Events - Set 1; Data Throttled",
+    "PublicDescription": "IRP throttled switch data",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_AK_INSERTS",
+    "BriefDescription": "AK Ingress Occupancy",
+    "PublicDescription": "Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - DRS",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x2",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - NCB",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x8",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x3",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - NCS",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_I_SNOOP_RESP.MISS",
+    "BriefDescription": "Snoop Responses; Miss",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x2",
+    "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+    "BriefDescription": "Snoop Responses; Hit I",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x4",
+    "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+    "BriefDescription": "Snoop Responses; Hit E or S",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x8",
+    "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+    "BriefDescription": "Snoop Responses; Hit M",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x10",
+    "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+    "BriefDescription": "Snoop Responses; SnpCode",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x20",
+    "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+    "BriefDescription": "Snoop Responses; SnpData",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x40",
+    "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+    "BriefDescription": "Snoop Responses; SnpInv",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_I_TRANSACTIONS.READS",
+    "BriefDescription": "Inbound Transaction Count; Reads",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_I_TRANSACTIONS.WRITES",
+    "BriefDescription": "Inbound Transaction Count; Writes",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x4",
+    "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
+    "BriefDescription": "Inbound Transaction Count; Read Prefetches",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x8",
+    "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+    "BriefDescription": "Inbound Transaction Count; Write Prefetches",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x10",
+    "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+    "BriefDescription": "Inbound Transaction Count; Atomic",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x20",
+    "EventName": "UNC_I_TRANSACTIONS.OTHER",
+    "BriefDescription": "Inbound Transaction Count; Other",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x40",
+    "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+    "BriefDescription": "Inbound Transaction Count; Select Source",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.  If this bit is not set, then requests from all sources will be counted.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "IRPFilter[4:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x18",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
+    "BriefDescription": "No AD Egress Credit Stalls",
+    "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x19",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
+    "BriefDescription": "No BL Egress Credit Stalls",
+    "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xE",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
+    "BriefDescription": "Outbound Read Requests",
+    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xF",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
+    "BriefDescription": "Outbound Read Requests",
+    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xD",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
+    "BriefDescription": "Outbound Request Queue Occupancy",
+    "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CLOCKTICKS",
+    "BriefDescription": "pclk Cycles",
+    "PublicDescription": "The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x60",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6A",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6B",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6C",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6D",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6E",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6F",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x70",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x71",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x61",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x62",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x63",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x64",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x65",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x66",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x67",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x68",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x69",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x30",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE0",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x31",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE1",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3A",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE10",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3B",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE11",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3C",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE12",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3D",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE13",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3E",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE14",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3F",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE15",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x40",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE16",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x41",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE17",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x32",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE2",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x33",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE3",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x34",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE4",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x35",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE5",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x36",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE6",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x37",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE7",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE8",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x39",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE9",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xB",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND0_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xC",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND1_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[15:8]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xD",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND2_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[23:16]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xE",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND3_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[31:24]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
+    "BriefDescription": "Thermal Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
+    "BriefDescription": "OS Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
+    "BriefDescription": "Power Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x73",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
+    "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x74",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_TRANS_CYCLES",
+    "BriefDescription": "Cycles spent changing Frequency",
+    "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2F",
+    "UMask": "0x0",
+    "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
+    "BriefDescription": "Memory Phase Shedding Cycles",
+    "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2A",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
+    "BriefDescription": "Package C State Residency - C0",
+    "PublicDescription": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2B",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
+    "BriefDescription": "Package C State Residency - C2E",
+    "PublicDescription": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2C",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
+    "BriefDescription": "Package C State Residency - C3",
+    "PublicDescription": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2D",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
+    "BriefDescription": "Package C State Residency - C6",
+    "PublicDescription": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2E",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
+    "BriefDescription": "Package C7 State Residency",
+    "PublicDescription": "Counts the number of cycles when the package was in C7.  This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0x40",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+    "BriefDescription": "Number of cores in C-State; C0 and C1",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0x80",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+    "BriefDescription": "Number of cores in C-State; C3",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0xC0",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+    "BriefDescription": "Number of cores in C-State; C6 and C7",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+    "BriefDescription": "External Prochot",
+    "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+    "BriefDescription": "Internal Prochot",
+    "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x72",
+    "UMask": "0x0",
+    "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+    "BriefDescription": "Total Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x79",
+    "UMask": "0x0",
+    "EventName": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Ring GV with same final and initial frequency",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VR_HOT_CYCLES",
+    "BriefDescription": "VR Hot",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x14",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_CLOCKTICKS",
+    "BriefDescription": "Number of qfclks",
+    "PublicDescription": "Counts the number of clocks in the QPI LL.  This clock runs at 1/4th the 'GT/s' speed of the QPI link.  For example, a 4GT/s link will have qfclk or 1GHz.  HSX does not support dynamic link speeds, so this frequency is fixed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_CTO_COUNT",
+    "BriefDescription": "Count of CTO Events",
+    "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "QPIMask0[17:0],QPIMatch0[17:0],QPIMask1[19:16],QPIMatch1[19:16]",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful.  There were sufficient credits, the RBT valid bit was set and there was an RBT tag match.  The message was marked to spawn direct2core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits.  Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction.  This is common for IO transactions.  There were enough Egress credits and the RBT tag matched but the valid bit was not set.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits.   The valid bit was set.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x40",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x80",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_L1_POWER_CYCLES",
+    "BriefDescription": "Cycles in L1",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x10",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL0P_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0p",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xF",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL0_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_BYPASSED",
+    "BriefDescription": "Rx Flit Buffer Bypassed",
+    "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
+    "BriefDescription": "CRC Errors Detected; LinkInit",
+    "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
+    "BriefDescription": "CRC Errors Detected; Normal Operations",
+    "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1E",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
+    "BriefDescription": "VN0 Credit Consumed; DRS",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1E",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
+    "BriefDescription": "VN0 Credit Consumed; NCB",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1E",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
+    "BriefDescription": "VN0 Credit Consumed; NCS",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1E",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
+    "BriefDescription": "VN0 Credit Consumed; HOM",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1E",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
+    "BriefDescription": "VN0 Credit Consumed; SNP",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1E",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
+    "BriefDescription": "VN0 Credit Consumed; NDR",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
+    "BriefDescription": "VN1 Credit Consumed; DRS",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
+    "BriefDescription": "VN1 Credit Consumed; NCB",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
+    "BriefDescription": "VN1 Credit Consumed; NCS",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
+    "BriefDescription": "VN1 Credit Consumed; HOM",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
+    "BriefDescription": "VN1 Credit Consumed; SNP",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
+    "BriefDescription": "VN1 Credit Consumed; NDR",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1D",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
+    "BriefDescription": "VNA Credit Consumed",
+    "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_CYCLES_NE",
+    "BriefDescription": "RxQ Cycles Not Empty",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xF",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xF",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
+    "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload.  When QPI is not in a power saving state, it continuously transmits flits across the link.  When there are no protocol flits to send, it will send IDLE and NULL flits  across.  These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
+    "BriefDescription": "Flits Received - Group 1; SNP Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are received on the home channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
+    "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel.  This basically counts the number of remote memory requests received over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
+    "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x6",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
+    "BriefDescription": "Flits Received - Group 1; HOM Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
+    "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
+    "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x18",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
+    "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
+    "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
+    "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0xC",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI.    This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x8",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS",
+    "BriefDescription": "Rx Flit Buffer Allocations",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xC",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xC",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xA",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xA",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xB",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xB",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xE",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xE",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xD",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xD",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xB",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY",
+    "BriefDescription": "RxQ Occupancy - All Packets",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
+    "BriefDescription": "RxQ Occupancy - DRS; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
+    "BriefDescription": "RxQ Occupancy - DRS; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x18",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
+    "BriefDescription": "RxQ Occupancy - HOM; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x18",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
+    "BriefDescription": "RxQ Occupancy - HOM; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
+    "BriefDescription": "RxQ Occupancy - NCB; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
+    "BriefDescription": "RxQ Occupancy - NCB; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
+    "BriefDescription": "RxQ Occupancy - NCS; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x17",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
+    "BriefDescription": "RxQ Occupancy - NCS; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1A",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
+    "BriefDescription": "RxQ Occupancy - NDR; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1A",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
+    "BriefDescription": "RxQ Occupancy - NDR; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x19",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
+    "BriefDescription": "RxQ Occupancy - SNP; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x19",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
+    "BriefDescription": "RxQ Occupancy - SNP; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x40",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits.  For details on a message class granularity, use the Egress Credit Occupancy events.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x80",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.GV",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3A",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3A",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3A",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3A",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3A",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3A",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xD",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0p",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xC",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL0_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_BYPASSED",
+    "BriefDescription": "Tx Flit Buffer Bypassed",
+    "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
+    "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
+    "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
+    "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
+    "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_CYCLES_NE",
+    "BriefDescription": "Tx Flit Buffer Cycles not Empty",
+    "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
+    "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
+    "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
+    "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
+    "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
+    "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are transmitted on the home channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel.  This basically counts the number of remote memory requests transmitted over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x6",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x18",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not te NCB headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0xC",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI.    This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_INSERTS",
+    "BriefDescription": "Tx Flit Buffer Allocations",
+    "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_OCCUPANCY",
+    "BriefDescription": "Tx Flit Buffer Occupancy",
+    "PublicDescription": "Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x26",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x26",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x22",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x22",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x24",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x24",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x27",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x27",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x23",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x23",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x29",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x25",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2A",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2A",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2A",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1F",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1F",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1F",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2B",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2B",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x20",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x20",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2C",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2C",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x21",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x21",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1C",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_VNA_CREDIT_RETURNS",
+    "BriefDescription": "VNA Credits Returned",
+    "PublicDescription": "Number of VNA credits returned.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1B",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
+    "BriefDescription": "VNA Credits Pending Return - Occupancy",
+    "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_R2_CLOCKTICKS",
+    "BriefDescription": "Number of uclks in domain",
+    "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2D",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2D",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2D",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2D",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
+    "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
+    "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
+    "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x3",
+    "EventName": "UNC_R2_RING_AD_USED.CW",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0xC",
+    "EventName": "UNC_R2_RING_AD_USED.CCW",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
+    "BriefDescription": "AK Ingress Bounced; Up",
+    "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AK_BOUNCES.DN",
+    "BriefDescription": "AK Ingress Bounced; Dn",
+    "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x3",
+    "EventName": "UNC_R2_RING_AK_USED.CW",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0xC",
+    "EventName": "UNC_R2_RING_AK_USED.CCW",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x3",
+    "EventName": "UNC_R2_RING_BL_USED.CW",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0xC",
+    "EventName": "UNC_R2_RING_BL_USED.CCW",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xA",
+    "UMask": "0x3",
+    "EventName": "UNC_R2_RING_IV_USED.CW",
+    "BriefDescription": "R2 IV Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xA",
+    "UMask": "0xC",
+    "EventName": "UNC_R2_RING_IV_USED.CCW",
+    "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xA",
+    "UMask": "0xF",
+    "EventName": "UNC_R2_RING_IV_USED.ANY",
+    "BriefDescription": "R2 IV Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
+    "BriefDescription": "Ingress Cycles Not Empty; NCB",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
+    "BriefDescription": "Ingress Cycles Not Empty; NCS",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RxR_INSERTS.NCB",
+    "BriefDescription": "Ingress Allocations; NCB",
+    "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RxR_INSERTS.NCS",
+    "BriefDescription": "Ingress Allocations; NCS",
+    "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
+    "BriefDescription": "Ingress Occupancy Accumulator; DRS",
+    "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2A",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2A",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2C",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2C",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2C",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x2C",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
+    "BriefDescription": "Egress Cycles Full; AD",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
+    "BriefDescription": "Egress Cycles Full; AK",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
+    "BriefDescription": "Egress Cycles Full; BL",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.AD",
+    "BriefDescription": "Egress Cycles Not Empty; AD",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AD Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.AK",
+    "BriefDescription": "Egress Cycles Not Empty; AK",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AK Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.BL",
+    "BriefDescription": "Egress Cycles Not Empty; BL",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; BL Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
+    "BriefDescription": "Egress CCW NACK; AD CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
+    "BriefDescription": "Egress CCW NACK; BL CCW",
+    "PublicDescription": "BL CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
+    "BriefDescription": "Egress CCW NACK; AK CCW",
+    "PublicDescription": "AK CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
+    "BriefDescription": "Egress CCW NACK; AK CCW",
+    "PublicDescription": "BL CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
+    "BriefDescription": "Egress CCW NACK; BL CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
+    "BriefDescription": "Egress CCW NACK; BL CW",
+    "PublicDescription": "AD Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_CLOCKTICKS",
+    "BriefDescription": "Number of uclks in domain",
+    "PublicDescription": "Counts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1F",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1F",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1F",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1F",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1F",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1F",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1F",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1F",
+    "UMask": "0x80",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x80",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2D",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
+    "BriefDescription": "HA/R2 AD Credits Empty",
+    "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2D",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
+    "BriefDescription": "HA/R2 AD Credits Empty",
+    "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2D",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
+    "BriefDescription": "HA/R2 AD Credits Empty",
+    "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2D",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
+    "BriefDescription": "HA/R2 AD Credits Empty",
+    "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xB",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
+    "BriefDescription": "IOT Backpressure",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xB",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
+    "BriefDescription": "IOT Backpressure",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xD",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_IOT_CTS_HI.CTS2",
+    "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xD",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_IOT_CTS_HI.CTS3",
+    "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xC",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_IOT_CTS_LO.CTS0",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xC",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_IOT_CTS_LO.CTS1",
+    "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+    "PublicDescription": "Debug Mask/Match Tie-Ins",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x21",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x21",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x21",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x21",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2E",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2E",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2E",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2E",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2F",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2F",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2F",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2F",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2F",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2F",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2F",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
+    "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+    "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
+    "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
+    "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x3",
+    "EventName": "UNC_R3_RING_AD_USED.CW",
+    "BriefDescription": "R3 AD Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0xC",
+    "EventName": "UNC_R3_RING_AD_USED.CCW",
+    "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
+    "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+    "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
+    "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
+    "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x3",
+    "EventName": "UNC_R3_RING_AK_USED.CW",
+    "BriefDescription": "R3 AK Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0xC",
+    "EventName": "UNC_R3_RING_AK_USED.CCW",
+    "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
+    "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
+    "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
+    "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
+    "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x3",
+    "EventName": "UNC_R3_RING_BL_USED.CW",
+    "BriefDescription": "R3 BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0xC",
+    "EventName": "UNC_R3_RING_BL_USED.CCW",
+    "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xA",
+    "UMask": "0x3",
+    "EventName": "UNC_R3_RING_IV_USED.CW",
+    "BriefDescription": "R3 IV Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xA",
+    "UMask": "0xF",
+    "EventName": "UNC_R3_RING_IV_USED.ANY",
+    "BriefDescription": "R3 IV Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xE",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_SINK_STARVED.AK",
+    "BriefDescription": "Ring Stop Starved; AK",
+    "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
+    "BriefDescription": "Ingress Cycles Not Empty; HOM",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
+    "BriefDescription": "Ingress Cycles Not Empty; SNP",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+    "BriefDescription": "Ingress Cycles Not Empty; NDR",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
+    "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
+    "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
+    "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
+    "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x14",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
+    "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
+    "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x14",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
+    "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
+    "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x14",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
+    "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
+    "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x14",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
+    "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
+    "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_INSERTS.HOM",
+    "BriefDescription": "Ingress Allocations; HOM",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_INSERTS.SNP",
+    "BriefDescription": "Ingress Allocations; SNP",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_INSERTS.NDR",
+    "BriefDescription": "Ingress Allocations; NDR",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_INSERTS.DRS",
+    "BriefDescription": "Ingress Allocations; DRS",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_INSERTS.NCB",
+    "BriefDescription": "Ingress Allocations; NCB",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_INSERTS.NCS",
+    "BriefDescription": "Ingress Allocations; NCS",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
+    "BriefDescription": "VN1 Ingress Allocations; HOM",
+    "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
+    "BriefDescription": "VN1 Ingress Allocations; SNP",
+    "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
+    "BriefDescription": "VN1 Ingress Allocations; NDR",
+    "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
+    "BriefDescription": "VN1 Ingress Allocations; DRS",
+    "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x15",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
+    "BriefDescription": "VN1 Ingress Allocations; NCB",
+    "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x15",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS",
+    "BriefDescription": "VN1 Ingress Allocations; NCS",
+    "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
+    "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
+    "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+    "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
+    "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+    "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+    "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
+    "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
+    "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB",
+    "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB",
+    "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS",
+    "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS",
+    "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2A",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2A",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
+    "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
+    "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2B",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
+    "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
+    "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2B",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
+    "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
+    "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2C",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2C",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2C",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2C",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
+    "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
+    "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_TxR_NACK.DN_AD",
+    "BriefDescription": "Egress CCW NACK; AD CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_TxR_NACK.DN_BL",
+    "BriefDescription": "Egress CCW NACK; BL CCW",
+    "PublicDescription": "BL CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_TxR_NACK.DN_AK",
+    "BriefDescription": "Egress CCW NACK; AK CCW",
+    "PublicDescription": "AK CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_TxR_NACK.UP_AD",
+    "BriefDescription": "Egress CCW NACK; AK CCW",
+    "PublicDescription": "BL CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_TxR_NACK.UP_BL",
+    "BriefDescription": "Egress CCW NACK; BL CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_TxR_NACK.UP_AK",
+    "BriefDescription": "Egress CCW NACK; BL CW",
+    "PublicDescription": "AD Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
+    "BriefDescription": "VN0 Credit Used; HOM Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
+    "BriefDescription": "VN0 Credit Used; SNP Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
+    "BriefDescription": "VN0 Credit Used; NDR Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
+    "BriefDescription": "VN0 Credit Used; DRS Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
+    "BriefDescription": "VN0 Credit Used; NCB Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
+    "BriefDescription": "VN0 Credit Used; NCS Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
+    "BriefDescription": "VN1 Credit Used; HOM Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+    "BriefDescription": "VN1 Credit Used; SNP Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+    "BriefDescription": "VN1 Credit Used; NDR Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
+    "BriefDescription": "VN1 Credit Used; DRS Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
+    "BriefDescription": "VN1 Credit Used; NCB Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
+    "BriefDescription": "VN1 Credit Used; NCS Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
+    "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x33",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
+    "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
+    "BriefDescription": "VNA Credit Reject; HOM Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
+    "BriefDescription": "VNA Credit Reject; SNP Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
+    "BriefDescription": "VNA Credit Reject; NDR Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
+    "BriefDescription": "VNA Credit Reject; DRS Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
+    "BriefDescription": "VNA Credit Reject; NCB Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
+    "BriefDescription": "VNA Credit Reject; NCS Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_S_BOUNCE_CONTROL",
+    "BriefDescription": "Bounce Control",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_S_CLOCKTICKS",
+    "BriefDescription": "Uncore Clocks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_S_FAST_ASSERTED",
+    "BriefDescription": "FaST wire asserted",
+    "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1B",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
+    "BriefDescription": "AD Ring In Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1B",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RING_AD_USED.UP_ODD",
+    "BriefDescription": "AD Ring In Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1B",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN",
+    "BriefDescription": "AD Ring In Use; Down and Event",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1B",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RING_AD_USED.DOWN_ODD",
+    "BriefDescription": "AD Ring In Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1B",
+    "UMask": "0x3",
+    "EventName": "UNC_S_RING_AD_USED.UP",
+    "BriefDescription": "AD Ring In Use; Up",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1B",
+    "UMask": "0xC",
+    "EventName": "UNC_S_RING_AD_USED.DOWN",
+    "BriefDescription": "AD Ring In Use; Down",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1C",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
+    "BriefDescription": "AK Ring In Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1C",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RING_AK_USED.UP_ODD",
+    "BriefDescription": "AK Ring In Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1C",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN",
+    "BriefDescription": "AK Ring In Use; Down and Event",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1C",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RING_AK_USED.DOWN_ODD",
+    "BriefDescription": "AK Ring In Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1C",
+    "UMask": "0x3",
+    "EventName": "UNC_S_RING_AK_USED.UP",
+    "BriefDescription": "AK Ring In Use; Up",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1C",
+    "UMask": "0xC",
+    "EventName": "UNC_S_RING_AK_USED.DOWN",
+    "BriefDescription": "AK Ring In Use; Down",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1D",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
+    "BriefDescription": "BL Ring in Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1D",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RING_BL_USED.UP_ODD",
+    "BriefDescription": "BL Ring in Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1D",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN",
+    "BriefDescription": "BL Ring in Use; Down and Event",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1D",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RING_BL_USED.DOWN_ODD",
+    "BriefDescription": "BL Ring in Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1D",
+    "UMask": "0x3",
+    "EventName": "UNC_S_RING_BL_USED.UP",
+    "BriefDescription": "BL Ring in Use; Up",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1D",
+    "UMask": "0xC",
+    "EventName": "UNC_S_RING_BL_USED.DOWN",
+    "BriefDescription": "BL Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x5",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RING_BOUNCES.AD_CACHE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RING_BOUNCES.AK_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RING_BOUNCES.BL_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x5",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RING_BOUNCES.IV_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1E",
+    "UMask": "0x3",
+    "EventName": "UNC_S_RING_IV_USED.UP",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in HSX.  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1E",
+    "UMask": "0xC",
+    "EventName": "UNC_S_RING_IV_USED.DN",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in HSX.  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x6",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x6",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x6",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x6",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
+    "BriefDescription": "Injection Starvation; AD - Credits",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
+    "BriefDescription": "Injection Starvation; AD - Bounces",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
+    "BriefDescription": "Injection Starvation; BL - Credits",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
+    "BriefDescription": "Injection Starvation; BL - Bounces",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
+    "BriefDescription": "Bypass; AD - Credits",
+    "PublicDescription": "Bypass the Sbo Ingress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RxR_BYPASS.AD_BNC",
+    "BriefDescription": "Bypass; AD - Bounces",
+    "PublicDescription": "Bypass the Sbo Ingress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x12",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
+    "BriefDescription": "Bypass; BL - Credits",
+    "PublicDescription": "Bypass the Sbo Ingress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x12",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RxR_BYPASS.BL_BNC",
+    "BriefDescription": "Bypass; BL - Bounces",
+    "PublicDescription": "Bypass the Sbo Ingress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x12",
+    "UMask": "0x10",
+    "EventName": "UNC_S_RxR_BYPASS.AK",
+    "BriefDescription": "Bypass; AK",
+    "PublicDescription": "Bypass the Sbo Ingress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x12",
+    "UMask": "0x20",
+    "EventName": "UNC_S_RxR_BYPASS.IV",
+    "BriefDescription": "Bypass; IV",
+    "PublicDescription": "Bypass the Sbo Ingress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
+    "BriefDescription": "Injection Starvation; AD - Credits",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
+    "BriefDescription": "Injection Starvation; AD - Bounces",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x14",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
+    "BriefDescription": "Injection Starvation; BL - Credits",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x14",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
+    "BriefDescription": "Injection Starvation; BL - Bounces",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x14",
+    "UMask": "0x10",
+    "EventName": "UNC_S_RxR_CRD_STARVED.AK",
+    "BriefDescription": "Injection Starvation; AK",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x14",
+    "UMask": "0x20",
+    "EventName": "UNC_S_RxR_CRD_STARVED.IV",
+    "BriefDescription": "Injection Starvation; IV",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x14",
+    "UMask": "0x40",
+    "EventName": "UNC_S_RxR_CRD_STARVED.IFV",
+    "BriefDescription": "Injection Starvation; IVF Credit",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
+    "BriefDescription": "Ingress Allocations; AD - Credits",
+    "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RxR_INSERTS.AD_BNC",
+    "BriefDescription": "Ingress Allocations; AD - Bounces",
+    "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
+    "BriefDescription": "Ingress Allocations; BL - Credits",
+    "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RxR_INSERTS.BL_BNC",
+    "BriefDescription": "Ingress Allocations; BL - Bounces",
+    "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_S_RxR_INSERTS.AK",
+    "BriefDescription": "Ingress Allocations; AK",
+    "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_S_RxR_INSERTS.IV",
+    "BriefDescription": "Ingress Allocations; IV",
+    "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
+    "BriefDescription": "Ingress Occupancy; AD - Credits",
+    "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
+    "BriefDescription": "Ingress Occupancy; AD - Bounces",
+    "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x11",
+    "UMask": "0x4",
+    "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
+    "BriefDescription": "Ingress Occupancy; BL - Credits",
+    "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x11",
+    "UMask": "0x8",
+    "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
+    "BriefDescription": "Ingress Occupancy; BL - Bounces",
+    "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_S_RxR_OCCUPANCY.AK",
+    "BriefDescription": "Ingress Occupancy; AK",
+    "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_S_RxR_OCCUPANCY.IV",
+    "BriefDescription": "Ingress Occupancy; IV",
+    "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x4",
+    "UMask": "0x1",
+    "EventName": "UNC_S_TxR_ADS_USED.AD",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x4",
+    "UMask": "0x2",
+    "EventName": "UNC_S_TxR_ADS_USED.AK",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_S_TxR_ADS_USED.BL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
+    "BriefDescription": "Egress Allocations; AD - Credits",
+    "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
+    "BriefDescription": "Egress Allocations; AD - Bounces",
+    "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
+    "BriefDescription": "Egress Allocations; BL - Credits",
+    "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_S_TxR_INSERTS.BL_BNC",
+    "BriefDescription": "Egress Allocations; BL - Bounces",
+    "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_S_TxR_INSERTS.AK",
+    "BriefDescription": "Egress Allocations; AK",
+    "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x2",
+    "UMask": "0x20",
+    "EventName": "UNC_S_TxR_INSERTS.IV",
+    "BriefDescription": "Egress Allocations; IV",
+    "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
+    "BriefDescription": "Egress Occupancy; AD - Credits",
+    "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
+    "BriefDescription": "Egress Occupancy; AD - Bounces",
+    "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
+    "BriefDescription": "Egress Occupancy; BL - Credits",
+    "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
+    "BriefDescription": "Egress Occupancy; BL - Bounces",
+    "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1",
+    "UMask": "0x10",
+    "EventName": "UNC_S_TxR_OCCUPANCY.AK",
+    "BriefDescription": "Egress Occupancy; AK",
+    "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x1",
+    "UMask": "0x20",
+    "EventName": "UNC_S_TxR_OCCUPANCY.IV",
+    "BriefDescription": "Egress Occupancy; IV",
+    "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_S_TxR_STARVED.AD",
+    "BriefDescription": "Injection Starvation; Onto AD Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_S_TxR_STARVED.AK",
+    "BriefDescription": "Injection Starvation; Onto AK Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x3",
+    "UMask": "0x4",
+    "EventName": "UNC_S_TxR_STARVED.BL",
+    "BriefDescription": "Injection Starvation; Onto BL Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "SBO",
+    "EventCode": "0x3",
+    "UMask": "0x8",
+    "EventName": "UNC_S_TxR_STARVED.IV",
+    "BriefDescription": "Injection Starvation; Onto IV Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x8",
+    "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x1",
+    "EventName": "UNC_U_FILTER_MATCH.ENABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "UBoxFilter[3:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x2",
+    "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x4",
+    "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "UBoxFilter[3:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x8",
+    "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x45",
+    "UMask": "0x1",
+    "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+    "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+    "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x46",
+    "UMask": "0x0",
+    "EventName": "UNC_U_RACU_REQUESTS",
+    "BriefDescription": "RACU Request",
+    "PublicDescription": "Number outstanding register requests within message channel tracker",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x1",
+    "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
+    "BriefDescription": "Monitor Sent to T0; Monitor T0",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x2",
+    "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+    "BriefDescription": "Monitor Sent to T0; Monitor T1",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x4",
+    "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
+    "BriefDescription": "Monitor Sent to T0; Livelock",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x8",
+    "EventName": "UNC_U_U2C_EVENTS.LTERROR",
+    "BriefDescription": "Monitor Sent to T0; LTError",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x10",
+    "EventName": "UNC_U_U2C_EVENTS.CMC",
+    "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x20",
+    "EventName": "UNC_U_U2C_EVENTS.UMC",
+    "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x40",
+    "EventName": "UNC_U_U2C_EVENTS.TRAP",
+    "BriefDescription": "Monitor Sent to T0; Trap",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x80",
+    "EventName": "UNC_U_U2C_EVENTS.OTHER",
+    "BriefDescription": "Monitor Sent to T0; Other",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_M_ACT_COUNT.RD",
+    "BriefDescription": "DRAM Activate Count; Activate due to Read",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_M_ACT_COUNT.WR",
+    "BriefDescription": "DRAM Activate Count; Activate due to Write",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_M_ACT_COUNT.BYP",
+    "BriefDescription": "DRAM Activate Count; Activate due to Write",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA1",
+    "UMask": "0x1",
+    "EventName": "UNC_M_BYP_CMDS.ACT",
+    "BriefDescription": "ACT command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA1",
+    "UMask": "0x2",
+    "EventName": "UNC_M_BYP_CMDS.CAS",
+    "BriefDescription": "CAS command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA1",
+    "UMask": "0x4",
+    "EventName": "UNC_M_BYP_CMDS.PRE",
+    "BriefDescription": "PRE command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x1",
+    "EventName": "UNC_M_CAS_COUNT.RD_REG",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x2",
+    "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller.  This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ.  While it is possible for underfills to be issed in both WMM and RMM, this event counts both.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x3",
+    "EventName": "UNC_M_CAS_COUNT.RD",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x8",
+    "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic' DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0xC",
+    "EventName": "UNC_M_CAS_COUNT.WR",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0xF",
+    "EventName": "UNC_M_CAS_COUNT.ALL",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x10",
+    "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x20",
+    "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_M_CLOCKTICKS",
+    "BriefDescription": "DRAM Clockticks",
+    "PublicDescription": "RTLSignal: 1'b1;RTLSignal2: ONE",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_M_DRAM_PRE_ALL",
+    "BriefDescription": "DRAM Precharge All Commands",
+    "PublicDescription": "Counts the number of times that the precharge all command was sent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+    "BriefDescription": "Number of DRAM Refreshes Issued",
+    "PublicDescription": "Counts the number of refreshes issued.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+    "BriefDescription": "Number of DRAM Refreshes Issued",
+    "PublicDescription": "Counts the number of refreshes issued.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
+    "BriefDescription": "ECC Correctable Errors",
+    "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_M_MAJOR_MODES.READ",
+    "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_M_MAJOR_MODES.WRITE",
+    "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+    "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+    "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x84",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
+    "BriefDescription": "Channel DLLOFF Cycles",
+    "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x85",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CHANNEL_PPD",
+    "BriefDescription": "Channel PPD Cycles",
+    "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x1",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x2",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x4",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x8",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x10",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x20",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x40",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x80",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x86",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
+    "BriefDescription": "Critical Throttle Cycles",
+    "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_PCU_THROTTLING",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x43",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_SELF_REFRESH",
+    "BriefDescription": "Clock-Enabled Self-Refresh",
+    "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x1",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x2",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x4",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x8",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x10",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x20",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x40",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x80",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
+    "BriefDescription": "Read Preemption Count; Read over Read Preemption",
+    "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
+    "BriefDescription": "Read Preemption Count; Read over Write Preemption",
+    "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+    "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses.  This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode.  This does not include PRE commands sent as a result of the page close counter expiration.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_M_PRE_COUNT.RD",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to read",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_M_PRE_COUNT.WR",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to write",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_M_PRE_COUNT.BYP",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_RD_CAS_PRIO.LOW",
+    "BriefDescription": "Read CAS issued with LOW priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_RD_CAS_PRIO.MED",
+    "BriefDescription": "Read CAS issued with MEDIUM priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
+    "BriefDescription": "Read CAS issued with HIGH priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xA0",
+    "UMask": "0x8",
+    "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
+    "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x8",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x10",
+    "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+    "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x3",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x5",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x6",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x7",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x9",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0xA",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0xB",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0xC",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0xD",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0xE",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0xF",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x11",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x12",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x13",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB0",
+    "UMask": "0x14",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB1",
+    "UMask": "0x1",
+    "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
+    "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB1",
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+    "EventName": "UNC_M_RPQ_CYCLES_NE",
+    "BriefDescription": "Read Pending Queue Not Empty",
+    "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x10",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_INSERTS",
+    "BriefDescription": "Read Pending Queue Allocations",
+    "PublicDescription": "Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x91",
+    "UMask": "0x0",
+    "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
+    "BriefDescription": "VMSE MXB write buffer occupancy",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x90",
+    "UMask": "0x1",
+    "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
+    "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x90",
+    "UMask": "0x2",
+    "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
+    "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xC0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xC0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WMM_TO_RMM.STARVE",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xC0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x22",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_CYCLES_FULL",
+    "BriefDescription": "Write Pending Queue Full Cycles",
+    "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x21",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_CYCLES_NE",
+    "BriefDescription": "Write Pending Queue Not Empty",
+    "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x23",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_READ_HIT",
+    "BriefDescription": "Write Pending Queue CAM Match",
+    "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x24",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_WRITE_HIT",
+    "BriefDescription": "Write Pending Queue CAM Match",
+    "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xC1",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WRONG_MM",
+    "BriefDescription": "Not getting the requested Major Mode",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x8",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x10",
+    "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+    "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x3",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x5",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x6",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x7",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x9",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xA",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xB",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xC",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xD",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xE",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0xF",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x11",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x12",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x13",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB8",
+    "UMask": "0x14",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x8",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x10",
+    "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
+    "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x3",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x5",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x6",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x7",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0x9",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0xA",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0xB",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0xC",
+    "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
+    "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB9",
+    "UMask": "0xD",
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+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x10",
+    "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+    "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x3",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x5",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x6",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x7",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x9",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xA",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xB",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xC",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xD",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xE",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0xF",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x11",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x12",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x13",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBE",
+    "UMask": "0x14",
+    "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
+    "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x8",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x10",
+    "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
+    "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x3",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x5",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x6",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x7",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x9",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xA",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xB",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xC",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xD",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xE",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0xF",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x11",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x12",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x13",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x14",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_U_CLOCKTICKS",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
+    "BriefDescription": "Ingress Occupancy; IRQ Rejected",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
+    "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
+    "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
+    "BriefDescription": "Tracker Cycles Not Empty; All Requests",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x80",
+    "EventName": "UNC_I_MISC0.PF_TIMEOUT",
+    "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
+    "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch.   This happens in the case of a prefetch TimeOut",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_M_DCLOCKTICKS",
+    "BriefDescription": "DRAM Clockticks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x4",
+    "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
+    "BriefDescription": "Lines Victimized; Lines in S State",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x4E",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+    "BriefDescription": "Package C State Residency - C1E",
+    "PublicDescription": "Counts the number of cycles when the package was in C1E.  This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert).  Residency events do not include transition times.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x79",
+    "UMask": "0x0",
+    "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Ring GV with same final and initial frequency",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/HSX/HaswellX_uncore_V14.tsv b/x86data/perfmon_data/HSX/HaswellX_uncore_V14.tsv
new file mode 100644
index 0000000..c4acb87
--- /dev/null
+++ b/x86data/perfmon_data/HSX/HaswellX_uncore_V14.tsv
@@ -0,0 +1,1284 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 v3 family based on the Haswell-E microarchitecture - V14
+# 8/17/2015 12:07:16 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+Unit	EventCode	UMask	EventName	Description	Counter	MSRValue	Filter	Internal
+CBO	0xA	0x0	UNC_C_BOUNCE_CONTROL	Bounce Control	0,1,2,3	0	null	0
+CBO	0x0	0x0	UNC_C_CLOCKTICKS	Uncore Clocks	0,1,2,3	0	null	0
+CBO	0x1F	0x0	UNC_C_COUNTER0_OCCUPANCY	Counter 0 Occupancy	0,1,2,3	0	null	0
+CBO	0x9	0x0	UNC_C_FAST_ASSERTED	FaST wire asserted	0,1	0	null	0
+CBO	0x34	0x3	UNC_C_LLC_LOOKUP.DATA_READ	Cache Lookups; Data Read Request	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x5	UNC_C_LLC_LOOKUP.WRITE	Cache Lookups; Write Requests	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x9	UNC_C_LLC_LOOKUP.REMOTE_SNOOP	Cache Lookups; External Snoop Request	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x11	UNC_C_LLC_LOOKUP.ANY	Cache Lookups; Any Request	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x41	UNC_C_LLC_LOOKUP.NID	Cache Lookups; Lookups that Match NID	0,1,2,3	0	CBoFilter0[23:17]	0
+CBO	0x34	0x21	UNC_C_LLC_LOOKUP.READ	Cache Lookups; Any Read Request	0,1,2,3	0	CBoFilter0[22:18]	0
+CBO	0x37	0x1	UNC_C_LLC_VICTIMS.M_STATE	Lines Victimized; Lines in M state	0,1,2,3	0	null	0
+CBO	0x37	0x2	UNC_C_LLC_VICTIMS.E_STATE	Lines Victimized; Lines in E state	0,1,2,3	0	null	0
+CBO	0x37	0x4	UNC_C_LLC_VICTIMS.S_STATE	Lines in S State	0,1,2,3	0	null	0
+CBO	0x37	0x8	UNC_C_LLC_VICTIMS.F_STATE	Lines Victimized	0,1,2,3	0	null	0
+CBO	0x37	0x40	UNC_C_LLC_VICTIMS.NID	Lines Victimized; Victimized Lines that Match NID	0,1,2,3	0	CBoFilter1[17:10]	0
+CBO	0x37	0x10	UNC_C_LLC_VICTIMS.MISS	Lines Victimized	0,1,2,3	0	null	0
+CBO	0x39	0x1	UNC_C_MISC.RSPI_WAS_FSE	Cbo Misc; Silent Snoop Eviction	0,1,2,3	0	null	0
+CBO	0x39	0x2	UNC_C_MISC.WC_ALIASING	Cbo Misc; Write Combining Aliasing	0,1,2,3	0	null	0
+CBO	0x39	0x4	UNC_C_MISC.STARTED	Cbo Misc	0,1,2,3	0	null	0
+CBO	0x39	0x8	UNC_C_MISC.RFO_HIT_S	Cbo Misc; RFO HitS	0,1,2,3	0	null	0
+CBO	0x39	0x10	UNC_C_MISC.CVZERO_PREFETCH_VICTIM	Cbo Misc; Clean Victim with raw CV=0	0,1,2,3	0	null	0
+CBO	0x39	0x20	UNC_C_MISC.CVZERO_PREFETCH_MISS	Cbo Misc; DRd hitting non-M with raw CV=0	0,1,2,3	0	null	0
+CBO	0x3C	0x1	UNC_C_QLRU.AGE0	LRU Queue; LRU Age 0	0,1,2,3	0	null	0
+CBO	0x3C	0x2	UNC_C_QLRU.AGE1	LRU Queue; LRU Age 1	0,1,2,3	0	null	0
+CBO	0x3C	0x4	UNC_C_QLRU.AGE2	LRU Queue; LRU Age 2	0,1,2,3	0	null	0
+CBO	0x3C	0x8	UNC_C_QLRU.AGE3	LRU Queue; LRU Age 3	0,1,2,3	0	null	0
+CBO	0x3C	0x10	UNC_C_QLRU.LRU_DECREMENT	LRU Queue; LRU Bits Decremented	0,1,2,3	0	null	0
+CBO	0x3C	0x20	UNC_C_QLRU.VICTIM_NON_ZERO	LRU Queue; Non-0 Aged Victim	0,1,2,3	0	null	0
+CBO	0x1B	0x1	UNC_C_RING_AD_USED.UP_EVEN	AD Ring In Use; Up and Even	0,1,2,3	0	null	0
+CBO	0x1B	0x2	UNC_C_RING_AD_USED.UP_ODD	AD Ring In Use; Up and Odd	0,1,2,3	0	null	0
+CBO	0x1B	0x4	UNC_C_RING_AD_USED.DOWN_EVEN	AD Ring In Use; Down and Even	0,1,2,3	0	null	0
+CBO	0x1B	0x8	UNC_C_RING_AD_USED.DOWN_ODD	AD Ring In Use; Down and Odd	0,1,2,3	0	null	0
+CBO	0x1B	0x3	UNC_C_RING_AD_USED.UP	AD Ring In Use; Up	0,1,2,3	0	null	0
+CBO	0x1B	0xC	UNC_C_RING_AD_USED.DOWN	AD Ring In Use; Down	0,1,2,3	0	null	0
+CBO	0x1B	0xF	UNC_C_RING_AD_USED.ALL	AD Ring In Use; All	0,1,2,3	0	null	0
+CBO	0x1C	0x1	UNC_C_RING_AK_USED.UP_EVEN	AK Ring In Use; Up and Even	0,1,2,3	0	null	0
+CBO	0x1C	0x2	UNC_C_RING_AK_USED.UP_ODD	AK Ring In Use; Up and Odd	0,1,2,3	0	null	0
+CBO	0x1C	0x4	UNC_C_RING_AK_USED.DOWN_EVEN	AK Ring In Use; Down and Even	0,1,2,3	0	null	0
+CBO	0x1C	0x8	UNC_C_RING_AK_USED.DOWN_ODD	AK Ring In Use; Down and Odd	0,1,2,3	0	null	0
+CBO	0x1C	0x3	UNC_C_RING_AK_USED.UP	AK Ring In Use; Up	0,1,2,3	0	null	0
+CBO	0x1C	0xC	UNC_C_RING_AK_USED.DOWN	AK Ring In Use; Down	0,1,2,3	0	null	0
+CBO	0x1C	0xF	UNC_C_RING_AK_USED.ALL	AK Ring In Use; All	0,1,2,3	0	null	0
+CBO	0x1D	0x1	UNC_C_RING_BL_USED.UP_EVEN	BL Ring in Use; Up and Even	0,1,2,3	0	null	0
+CBO	0x1D	0x2	UNC_C_RING_BL_USED.UP_ODD	BL Ring in Use; Up and Odd	0,1,2,3	0	null	0
+CBO	0x1D	0x4	UNC_C_RING_BL_USED.DOWN_EVEN	BL Ring in Use; Down and Even	0,1,2,3	0	null	0
+CBO	0x1D	0x8	UNC_C_RING_BL_USED.DOWN_ODD	BL Ring in Use; Down and Odd	0,1,2,3	0	null	0
+CBO	0x1D	0x3	UNC_C_RING_BL_USED.UP	BL Ring in Use; Up	0,1,2,3	0	null	0
+CBO	0x1D	0xC	UNC_C_RING_BL_USED.DOWN	BL Ring in Use; Down	0,1,2,3	0	null	0
+CBO	0x1D	0xF	UNC_C_RING_BL_USED.ALL	BL Ring in Use; Down	0,1,2,3	0	null	0
+CBO	0x5	0x1	UNC_C_RING_BOUNCES.AD	Number of LLC responses that bounced on the Ring.; AD	0,1,2,3	0	null	0
+CBO	0x5	0x2	UNC_C_RING_BOUNCES.AK	Number of LLC responses that bounced on the Ring.; AK	0,1,2,3	0	null	0
+CBO	0x5	0x4	UNC_C_RING_BOUNCES.BL	Number of LLC responses that bounced on the Ring.; BL	0,1,2,3	0	null	0
+CBO	0x5	0x10	UNC_C_RING_BOUNCES.IV	Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.	0,1,2,3	0	null	0
+CBO	0x1E	0xF	UNC_C_RING_IV_USED.ANY	BL Ring in Use; Any	0,1,2,3	0	null	0
+CBO	0x1E	0x3	UNC_C_RING_IV_USED.UP	BL Ring in Use; Any	0,1,2,3	0	null	0
+CBO	0x1E	0xCC	UNC_C_RING_IV_USED.DOWN	BL Ring in Use; Down	0,1,2,3	0	null	0
+CBO	0x1E	0xC	UNC_C_RING_IV_USED.DN	BL Ring in Use; Any	0,1,2,3	0	null	0
+CBO	0x6	0x1	UNC_C_RING_SINK_STARVED.AD	AD	0,1,2,3	0	null	0
+CBO	0x6	0x2	UNC_C_RING_SINK_STARVED.AK	AK	0,1,2,3	0	null	0
+CBO	0x6	0x8	UNC_C_RING_SINK_STARVED.IV	IV	0,1,2,3	0	null	0
+CBO	0x6	0x4	UNC_C_RING_SINK_STARVED.BL	BL	0,1,2,3	0	null	0
+CBO	0x7	0x0	UNC_C_RING_SRC_THRTL	Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.	0,1,2,3	0	null	0
+CBO	0x12	0x1	UNC_C_RxR_EXT_STARVED.IRQ	Ingress Arbiter Blocking Cycles; IPQ	0,1,2,3	0	null	0
+CBO	0x12	0x2	UNC_C_RxR_EXT_STARVED.IPQ	Ingress Arbiter Blocking Cycles; IRQ	0,1,2,3	0	null	0
+CBO	0x12	0x4	UNC_C_RxR_EXT_STARVED.PRQ	Ingress Arbiter Blocking Cycles; PRQ	0,1,2,3	0	null	0
+CBO	0x12	0x8	UNC_C_RxR_EXT_STARVED.ISMQ_BIDS	Ingress Arbiter Blocking Cycles; ISMQ_BID	0,1,2,3	0	null	0
+CBO	0x13	0x1	UNC_C_RxR_INSERTS.IRQ	Ingress Allocations; IRQ	0,1,2,3	0	null	0
+CBO	0x13	0x2	UNC_C_RxR_INSERTS.IRQ_REJ	Ingress Allocations; IRQ Rejected	0,1,2,3	0	null	0
+CBO	0x13	0x4	UNC_C_RxR_INSERTS.IPQ	Ingress Allocations; IPQ	0,1,2,3	0	null	0
+CBO	0x13	0x10	UNC_C_RxR_INSERTS.PRQ	Ingress Allocations; PRQ	0,1,2,3	0	null	0
+CBO	0x13	0x20	UNC_C_RxR_INSERTS.PRQ_REJ	Ingress Allocations; PRQ	0,1,2,3	0	null	0
+CBO	0x14	0x1	UNC_C_RxR_INT_STARVED.IRQ	Ingress Internal Starvation Cycles; IRQ	0,1,2,3	0	null	0
+CBO	0x14	0x4	UNC_C_RxR_INT_STARVED.IPQ	Ingress Internal Starvation Cycles; IPQ	0,1,2,3	0	null	0
+CBO	0x14	0x8	UNC_C_RxR_INT_STARVED.ISMQ	Ingress Internal Starvation Cycles; ISMQ	0,1,2,3	0	null	0
+CBO	0x14	0x10	UNC_C_RxR_INT_STARVED.PRQ	Ingress Internal Starvation Cycles; PRQ	0,1,2,3	0	null	0
+CBO	0x31	0x1	UNC_C_RxR_IPQ_RETRY.ANY	Probe Queue Retries; Any Reject	0,1,2,3	0	null	0
+CBO	0x31	0x2	UNC_C_RxR_IPQ_RETRY.FULL	Probe Queue Retries; No Egress Credits	0,1,2,3	0	null	0
+CBO	0x31	0x4	UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT	Probe Queue Retries; Address Conflict	0,1,2,3	0	null	0
+CBO	0x31	0x10	UNC_C_RxR_IPQ_RETRY.QPI_CREDITS	Probe Queue Retries; No QPI Credits	0,1,2,3	0	null	0
+CBO	0x28	0x1	UNC_C_RxR_IPQ_RETRY2.AD_SBO	Probe Queue Retries; No AD Sbo Credits	0,1,2,3	0	null	0
+CBO	0x28	0x40	UNC_C_RxR_IPQ_RETRY2.TARGET	Probe Queue Retries; Target Node Filter	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x32	0x1	UNC_C_RxR_IRQ_RETRY.ANY	Ingress Request Queue Rejects; Any Reject	0,1,2,3	0	null	0
+CBO	0x32	0x2	UNC_C_RxR_IRQ_RETRY.FULL	Ingress Request Queue Rejects; No Egress Credits	0,1,2,3	0	null	0
+CBO	0x32	0x4	UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT	Ingress Request Queue Rejects; Address Conflict	0,1,2,3	0	null	0
+CBO	0x32	0x8	UNC_C_RxR_IRQ_RETRY.RTID	Ingress Request Queue Rejects; No RTIDs	0,1,2,3	0	null	0
+CBO	0x32	0x10	UNC_C_RxR_IRQ_RETRY.QPI_CREDITS	Ingress Request Queue Rejects; No QPI Credits	0,1,2,3	0	null	0
+CBO	0x32	0x20	UNC_C_RxR_IRQ_RETRY.IIO_CREDITS	Ingress Request Queue Rejects; No IIO Credits	0,1,2,3	0	null	0
+CBO	0x32	0x40	UNC_C_RxR_IRQ_RETRY.NID	Ingress Request Queue Rejects	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x29	0x1	UNC_C_RxR_IRQ_RETRY2.AD_SBO	Ingress Request Queue Rejects; No AD Sbo Credits	0,1,2,3	0	null	0
+CBO	0x29	0x2	UNC_C_RxR_IRQ_RETRY2.BL_SBO	Ingress Request Queue Rejects; No BL Sbo Credits	0,1,2,3	0	null	0
+CBO	0x29	0x40	UNC_C_RxR_IRQ_RETRY2.TARGET	Ingress Request Queue Rejects; Target Node Filter	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x33	0x1	UNC_C_RxR_ISMQ_RETRY.ANY	ISMQ Retries; Any Reject	0,1,2,3	0	null	0
+CBO	0x33	0x2	UNC_C_RxR_ISMQ_RETRY.FULL	ISMQ Retries; No Egress Credits	0,1,2,3	0	null	0
+CBO	0x33	0x8	UNC_C_RxR_ISMQ_RETRY.RTID	ISMQ Retries; No RTIDs	0,1,2,3	0	null	0
+CBO	0x33	0x10	UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS	ISMQ Retries; No QPI Credits	0,1,2,3	0	null	0
+CBO	0x33	0x20	UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS	ISMQ Retries; No IIO Credits	0,1,2,3	0	null	0
+CBO	0x33	0x80	UNC_C_RxR_ISMQ_RETRY.WB_CREDITS	ISMQ Retries	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x33	0x40	UNC_C_RxR_ISMQ_RETRY.NID	ISMQ Retries	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x2A	0x1	UNC_C_RxR_ISMQ_RETRY2.AD_SBO	ISMQ Request Queue Rejects; No AD Sbo Credits	0,1,2,3	0	null	0
+CBO	0x2A	0x2	UNC_C_RxR_ISMQ_RETRY2.BL_SBO	ISMQ Request Queue Rejects; No BL Sbo Credits	0,1,2,3	0	null	0
+CBO	0x2A	0x40	UNC_C_RxR_ISMQ_RETRY2.TARGET	ISMQ Request Queue Rejects; Target Node Filter	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x11	0x1	UNC_C_RxR_OCCUPANCY.IRQ	Ingress Occupancy; IRQ	0	0	null	0
+CBO	0x11	0x2	UNC_C_RxR_OCCUPANCY.IRQ_REJECTED	IRQ Rejected	0	0	null	0
+CBO	0x11	0x4	UNC_C_RxR_OCCUPANCY.IPQ	Ingress Occupancy; IPQ	0	0	null	0
+CBO	0x11	0x20	UNC_C_RxR_OCCUPANCY.PRQ_REJ	Ingress Occupancy; PRQ Rejects	0	0	null	0
+CBO	0x3D	0x1	UNC_C_SBO_CREDITS_ACQUIRED.AD	SBo Credits Acquired; For AD Ring	0,1,2,3	0	null	0
+CBO	0x3D	0x2	UNC_C_SBO_CREDITS_ACQUIRED.BL	SBo Credits Acquired; For BL Ring	0,1,2,3	0	null	0
+CBO	0x3E	0x1	UNC_C_SBO_CREDIT_OCCUPANCY.AD	SBo Credits Occupancy; For AD Ring	0	0	null	0
+CBO	0x3E	0x2	UNC_C_SBO_CREDIT_OCCUPANCY.BL	SBo Credits Occupancy; For BL Ring	0	0	null	0
+CBO	0x35	0x1	UNC_C_TOR_INSERTS.OPCODE	TOR Inserts; Opcode Match	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x4	UNC_C_TOR_INSERTS.EVICTION	TOR Inserts; Evictions	0,1,2,3	0	null	0
+CBO	0x35	0x8	UNC_C_TOR_INSERTS.ALL	TOR Inserts; All	0,1,2,3	0	null	0
+CBO	0x35	0x10	UNC_C_TOR_INSERTS.WB	TOR Inserts; Writebacks	0,1,2,3	0	null	0
+CBO	0x35	0x3	UNC_C_TOR_INSERTS.MISS_OPCODE	TOR Inserts; Miss Opcode Match	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x41	UNC_C_TOR_INSERTS.NID_OPCODE	TOR Inserts; NID and Opcode Matched	0,1,2,3	0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x35	0x44	UNC_C_TOR_INSERTS.NID_EVICTION	TOR Inserts; NID Matched Evictions	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x35	0x48	UNC_C_TOR_INSERTS.NID_ALL	TOR Inserts; NID Matched	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x35	0x50	UNC_C_TOR_INSERTS.NID_WB	TOR Inserts; NID Matched Writebacks	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x35	0x43	UNC_C_TOR_INSERTS.NID_MISS_OPCODE	TOR Inserts; NID and Opcode Matched Miss	0,1,2,3	0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x35	0x4A	UNC_C_TOR_INSERTS.NID_MISS_ALL	TOR Inserts; NID Matched Miss All	0,1,2,3	0	CBoFilter1[15:0]	0
+CBO	0x35	0x2A	UNC_C_TOR_INSERTS.MISS_LOCAL	TOR Inserts; Misses to Local Memory	0,1,2,3	0	null	0
+CBO	0x35	0x8A	UNC_C_TOR_INSERTS.MISS_REMOTE	TOR Inserts; Misses to Remote Memory	0,1,2,3	0	null	0
+CBO	0x35	0x28	UNC_C_TOR_INSERTS.LOCAL	TOR Inserts; Local Memory	0,1,2,3	0	null	0
+CBO	0x35	0x88	UNC_C_TOR_INSERTS.REMOTE	TOR Inserts; Remote Memory	0,1,2,3	0	null	0
+CBO	0x35	0x23	UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE	TOR Inserts; Misses to Local Memory - Opcode Matched	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x83	UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE	TOR Inserts; Misses to Remote Memory - Opcode Matched	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x21	UNC_C_TOR_INSERTS.LOCAL_OPCODE	TOR Inserts; Local Memory - Opcode Matched	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x35	0x81	UNC_C_TOR_INSERTS.REMOTE_OPCODE	TOR Inserts; Remote Memory - Opcode Matched	0,1,2,3	0	CBoFilter1[28:20]	0
+CBO	0x36	0x1	UNC_C_TOR_OCCUPANCY.OPCODE	TOR Occupancy; Opcode Match	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x4	UNC_C_TOR_OCCUPANCY.EVICTION	TOR Occupancy; Evictions	0	0	null	0
+CBO	0x36	0x8	UNC_C_TOR_OCCUPANCY.ALL	TOR Occupancy; Any	0	0	null	0
+CBO	0x36	0x3	UNC_C_TOR_OCCUPANCY.MISS_OPCODE	TOR Occupancy; Miss Opcode Match	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0xA	UNC_C_TOR_OCCUPANCY.MISS_ALL	TOR Occupancy; Miss All	0	0	null	0
+CBO	0x36	0x41	UNC_C_TOR_OCCUPANCY.NID_OPCODE	TOR Occupancy; NID and Opcode Matched	0	0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x36	0x44	UNC_C_TOR_OCCUPANCY.NID_EVICTION	TOR Occupancy; NID Matched Evictions	0	0	CBoFilter1[15:0]	0
+CBO	0x36	0x48	UNC_C_TOR_OCCUPANCY.NID_ALL	TOR Occupancy; NID Matched	0	0	CBoFilter1[15:0]	0
+CBO	0x36	0x43	UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE	TOR Occupancy; NID and Opcode Matched Miss	0	0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x36	0x4A	UNC_C_TOR_OCCUPANCY.NID_MISS_ALL	TOR Occupancy; NID Matched	0	0	CBoFilter1[15:0]	0
+CBO	0x36	0x2A	UNC_C_TOR_OCCUPANCY.MISS_LOCAL	TOR Occupancy	0	0	null	0
+CBO	0x36	0x8A	UNC_C_TOR_OCCUPANCY.MISS_REMOTE	TOR Occupancy	0	0	null	0
+CBO	0x36	0x28	UNC_C_TOR_OCCUPANCY.LOCAL	TOR Occupancy	0	0	null	0
+CBO	0x36	0x88	UNC_C_TOR_OCCUPANCY.REMOTE	TOR Occupancy	0	0	null	0
+CBO	0x36	0x23	UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE	TOR Occupancy; Misses to Local Memory - Opcode Matched	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x83	UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE	TOR Occupancy; Misses to Remote Memory - Opcode Matched	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x21	UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE	TOR Occupancy; Local Memory - Opcode Matched	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x81	UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE	TOR Occupancy; Remote Memory - Opcode Matched	0	0	CBoFilter1[28:20]	0
+CBO	0x36	0x10	UNC_C_TOR_OCCUPANCY.WB	TOR Occupancy; Writebacks	0	0	null	0
+CBO	0x36	0x50	UNC_C_TOR_OCCUPANCY.NID_WB	TOR Occupancy; NID Matched Writebacks	0	0	CBoFilter1[15:0]	0
+CBO	0x4	0x1	UNC_C_TxR_ADS_USED.AD	Onto AD Ring	0,1,2,3	0	null	0
+CBO	0x4	0x2	UNC_C_TxR_ADS_USED.AK	Onto AK Ring	0,1,2,3	0	null	0
+CBO	0x4	0x4	UNC_C_TxR_ADS_USED.BL	Onto BL Ring	0,1,2,3	0	null	0
+CBO	0x2	0x1	UNC_C_TxR_INSERTS.AD_CACHE	Egress Allocations; AD - Cachebo	0,1,2,3	0	null	0
+CBO	0x2	0x2	UNC_C_TxR_INSERTS.AK_CACHE	Egress Allocations; AK - Cachebo	0,1,2,3	0	null	0
+CBO	0x2	0x4	UNC_C_TxR_INSERTS.BL_CACHE	Egress Allocations; BL - Cacheno	0,1,2,3	0	null	0
+CBO	0x2	0x8	UNC_C_TxR_INSERTS.IV_CACHE	Egress Allocations; IV - Cachebo	0,1,2,3	0	null	0
+CBO	0x2	0x10	UNC_C_TxR_INSERTS.AD_CORE	Egress Allocations; AD - Corebo	0,1,2,3	0	null	0
+CBO	0x2	0x20	UNC_C_TxR_INSERTS.AK_CORE	Egress Allocations; AK - Corebo	0,1,2,3	0	null	0
+CBO	0x2	0x40	UNC_C_TxR_INSERTS.BL_CORE	Egress Allocations; BL - Corebo	0,1,2,3	0	null	0
+CBO	0x3	0x2	UNC_C_TxR_STARVED.AK_BOTH	Injection Starvation; Onto AK Ring	0,1,2,3	0	null	0
+CBO	0x3	0x4	UNC_C_TxR_STARVED.BL_BOTH	Injection Starvation; Onto BL Ring	0,1,2,3	0	null	0
+CBO	0x3	0x8	UNC_C_TxR_STARVED.IV	Injection Starvation; Onto IV Ring	0,1,2,3	0	null	0
+CBO	0x3	0x10	UNC_C_TxR_STARVED.AD_CORE	Injection Starvation; Onto AD Ring (to core)	0,1,2,3	0	null	0
+HA	0x20	0x3	UNC_H_ADDR_OPC_MATCH.FILT	QPI Address/Opcode Match; Address & Opcode Match	0,1,2,3	0	HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]	0
+HA	0x20	0x1	UNC_H_ADDR_OPC_MATCH.ADDR	QPI Address/Opcode Match; Address	0,1,2,3	0	HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]	0
+HA	0x20	0x2	UNC_H_ADDR_OPC_MATCH.OPC	QPI Address/Opcode Match; Opcode	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x4	UNC_H_ADDR_OPC_MATCH.AD	QPI Address/Opcode Match; AD Opcodes	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x8	UNC_H_ADDR_OPC_MATCH.BL	QPI Address/Opcode Match; BL Opcodes	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x10	UNC_H_ADDR_OPC_MATCH.AK	QPI Address/Opcode Match; AK Opcodes	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x42	0x0	UNC_H_BT_CYCLES_NE	BT Cycles Not Empty	0,1,2,3	0	null	0
+HA	0x51	0x2	UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD	BT to HT Not Issued; Incoming Snoop Hazard	0,1,2,3	0	null	0
+HA	0x51	0x4	UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD	BT to HT Not Issued; Incoming Data Hazard	0,1,2,3	0	null	0
+HA	0x51	0x8	UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD	BT to HT Not Issued; Incoming Data Hazard	0,1,2,3	0	null	0
+HA	0x51	0x10	UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD	BT to HT Not Issued; Incoming Data Hazard	0,1,2,3	0	null	0
+HA	0x14	0x1	UNC_H_BYPASS_IMC.TAKEN	HA to iMC Bypass; Taken	0,1,2,3	0	null	0
+HA	0x14	0x2	UNC_H_BYPASS_IMC.NOT_TAKEN	HA to iMC Bypass; Not Taken	0,1,2,3	0	null	0
+HA	0x0	0x0	UNC_H_CLOCKTICKS	uclks	0,1,2,3	0	null	0
+HA	0x11	0x0	UNC_H_DIRECT2CORE_COUNT	Direct2Core Messages Sent	0,1,2,3	0	null	0
+HA	0x12	0x0	UNC_H_DIRECT2CORE_CYCLES_DISABLED	Cycles when Direct2Core was Disabled	0,1,2,3	0	null	0
+HA	0x13	0x0	UNC_H_DIRECT2CORE_TXN_OVERRIDE	Number of Reads that had Direct2Core Overridden	0,1,2,3	0	null	0
+HA	0x41	0x0	UNC_H_DIRECTORY_LAT_OPT	Directory Lat Opt Return	0,1,2,3	0	null	0
+HA	0xC	0x1	UNC_H_DIRECTORY_LOOKUP.SNP	Directory Lookups; Snoop Needed	0,1,2,3	0	null	0
+HA	0xC	0x2	UNC_H_DIRECTORY_LOOKUP.NO_SNP	Directory Lookups; Snoop Not Needed	0,1,2,3	0	null	0
+HA	0xD	0x1	UNC_H_DIRECTORY_UPDATE.SET	Directory Updates; Directory Set	0,1,2,3	0	null	0
+HA	0xD	0x2	UNC_H_DIRECTORY_UPDATE.CLEAR	Directory Updates; Directory Clear	0,1,2,3	0	null	0
+HA	0xD	0x3	UNC_H_DIRECTORY_UPDATE.ANY	Directory Updates; Any Directory Update	0,1,2,3	0	null	0
+HA	0x71	0x1	UNC_H_HITME_HIT.READ_OR_INVITOE	Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE	0,1,2,3	0	null	0
+HA	0x71	0x2	UNC_H_HITME_HIT.WBMTOI	Counts Number of Hits in HitMe Cache; op is WbMtoI	0,1,2,3	0	null	0
+HA	0x71	0x4	UNC_H_HITME_HIT.ACKCNFLTWBI	Counts Number of Hits in HitMe Cache; op is AckCnfltWbI	0,1,2,3	0	null	0
+HA	0x71	0x8	UNC_H_HITME_HIT.WBMTOE_OR_S	Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS	0,1,2,3	0	null	0
+HA	0x71	0x10	UNC_H_HITME_HIT.RSPFWDI_REMOTE	Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request	0,1,2,3	0	null	0
+HA	0x71	0x20	UNC_H_HITME_HIT.RSPFWDI_LOCAL	Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request	0,1,2,3	0	null	0
+HA	0x71	0x40	UNC_H_HITME_HIT.RSPFWDS	Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb	0,1,2,3	0	null	0
+HA	0x71	0x80	UNC_H_HITME_HIT.RSP	Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI	0,1,2,3	0	null	0
+HA	0x71	0x70	UNC_H_HITME_HIT.ALLOCS	Counts Number of Hits in HitMe Cache; Allocations	0,1,2,3	0	null	0
+HA	0x71	0x42	UNC_H_HITME_HIT.EVICTS	Counts Number of Hits in HitMe Cache; Allocations	0,1,2,3	0	null	0
+HA	0x71	0x26	UNC_H_HITME_HIT.INVALS	Counts Number of Hits in HitMe Cache; Invalidations	0,1,2,3	0	null	0
+HA	0x71	0xFF	UNC_H_HITME_HIT.ALL	Counts Number of Hits in HitMe Cache; All Requests	0,1,2,3	0	null	0
+HA	0x71	0xF	UNC_H_HITME_HIT.HOM	Counts Number of Hits in HitMe Cache; HOM Requests	0,1,2,3	0	null	0
+HA	0x72	0x1	UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE	Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE	0,1,2,3	0	null	0
+HA	0x72	0x2	UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI	Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI	0,1,2,3	0	null	0
+HA	0x72	0x4	UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI	Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI	0,1,2,3	0	null	0
+HA	0x72	0x8	UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S	Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS	0,1,2,3	0	null	0
+HA	0x72	0x10	UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE	Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request	0,1,2,3	0	null	0
+HA	0x72	0x20	UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL	Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request	0,1,2,3	0	null	0
+HA	0x72	0x40	UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS	Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb	0,1,2,3	0	null	0
+HA	0x72	0x80	UNC_H_HITME_HIT_PV_BITS_SET.RSP	Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI	0,1,2,3	0	null	0
+HA	0x72	0xFF	UNC_H_HITME_HIT_PV_BITS_SET.ALL	Accumulates Number of PV bits set on HitMe Cache Hits; All Requests	0,1,2,3	0	null	0
+HA	0x72	0xF	UNC_H_HITME_HIT_PV_BITS_SET.HOM	Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests	0,1,2,3	0	null	0
+HA	0x70	0x1	UNC_H_HITME_LOOKUP.READ_OR_INVITOE	Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE	0,1,2,3	0	null	0
+HA	0x70	0x2	UNC_H_HITME_LOOKUP.WBMTOI	Counts Number of times HitMe Cache is accessed; op is WbMtoI	0,1,2,3	0	null	0
+HA	0x70	0x4	UNC_H_HITME_LOOKUP.ACKCNFLTWBI	Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI	0,1,2,3	0	null	0
+HA	0x70	0x8	UNC_H_HITME_LOOKUP.WBMTOE_OR_S	Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS	0,1,2,3	0	null	0
+HA	0x70	0x10	UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE	Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request	0,1,2,3	0	null	0
+HA	0x70	0x20	UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL	Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request	0,1,2,3	0	null	0
+HA	0x70	0x40	UNC_H_HITME_LOOKUP.RSPFWDS	Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb	0,1,2,3	0	null	0
+HA	0x70	0x80	UNC_H_HITME_LOOKUP.RSP	Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI	0,1,2,3	0	null	0
+HA	0x70	0x70	UNC_H_HITME_LOOKUP.ALLOCS	Counts Number of times HitMe Cache is accessed; Allocations	0,1,2,3	0	null	0
+HA	0x70	0x26	UNC_H_HITME_LOOKUP.INVALS	Counts Number of times HitMe Cache is accessed; Invalidations	0,1,2,3	0	null	0
+HA	0x70	0xFF	UNC_H_HITME_LOOKUP.ALL	Counts Number of times HitMe Cache is accessed; All Requests	0,1,2,3	0	null	0
+HA	0x70	0xF	UNC_H_HITME_LOOKUP.HOM	Counts Number of times HitMe Cache is accessed; HOM Requests	0,1,2,3	0	null	0
+HA	0x22	0x1	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0	Cycles without QPI Ingress Credits; AD to QPI Link 0	0,1,2,3	0	null	0
+HA	0x22	0x2	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1	Cycles without QPI Ingress Credits; AD to QPI Link 1	0,1,2,3	0	null	0
+HA	0x22	0x4	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0	Cycles without QPI Ingress Credits; BL to QPI Link 0	0,1,2,3	0	null	0
+HA	0x22	0x8	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1	Cycles without QPI Ingress Credits; BL to QPI Link 1	0,1,2,3	0	null	0
+HA	0x22	0x10	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2	Cycles without QPI Ingress Credits; BL to QPI Link 0	0,1,2,3	0	null	0
+HA	0x22	0x20	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2	Cycles without QPI Ingress Credits; BL to QPI Link 1	0,1,2,3	0	null	0
+HA	0x17	0x1	UNC_H_IMC_READS.NORMAL	HA to iMC Normal Priority Reads Issued; Normal Priority	0,1,2,3	0	null	0
+HA	0x1E	0x0	UNC_H_IMC_RETRY	Retry Events	0,1,2,3	0	null	0
+HA	0x1A	0x1	UNC_H_IMC_WRITES.FULL	HA to iMC Full Line Writes Issued; Full Line Non-ISOCH	0,1,2,3	0	null	0
+HA	0x1A	0x2	UNC_H_IMC_WRITES.PARTIAL	HA to iMC Full Line Writes Issued; Partial Non-ISOCH	0,1,2,3	0	null	0
+HA	0x1A	0x4	UNC_H_IMC_WRITES.FULL_ISOCH	HA to iMC Full Line Writes Issued; ISOCH Full Line	0,1,2,3	0	null	0
+HA	0x1A	0x8	UNC_H_IMC_WRITES.PARTIAL_ISOCH	HA to iMC Full Line Writes Issued; ISOCH Partial	0,1,2,3	0	null	0
+HA	0x1A	0xF	UNC_H_IMC_WRITES.ALL	HA to iMC Full Line Writes Issued; All Writes	0,1,2,3	0	null	0
+HA	0x61	0x1	UNC_H_IOT_BACKPRESSURE.SAT	IOT Backpressure	0,1,2	0	null	0
+HA	0x61	0x2	UNC_H_IOT_BACKPRESSURE.HUB	IOT Backpressure	0,1,2	0	null	0
+HA	0x64	0x1	UNC_H_IOT_CTS_EAST_LO.CTS0	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+HA	0x64	0x2	UNC_H_IOT_CTS_EAST_LO.CTS1	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+HA	0x65	0x1	UNC_H_IOT_CTS_HI.CTS2	IOT Common Trigger Sequencer - Hi	0,1,2	0	null	0
+HA	0x65	0x2	UNC_H_IOT_CTS_HI.CTS3	IOT Common Trigger Sequencer - Hi	0,1,2	0	null	0
+HA	0x62	0x1	UNC_H_IOT_CTS_WEST_LO.CTS0	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+HA	0x62	0x2	UNC_H_IOT_CTS_WEST_LO.CTS1	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+HA	0x53	0x2	UNC_H_OSB.READS_LOCAL	OSB Snoop Broadcast; Local Reads	0,1,2,3	0	null	0
+HA	0x53	0x4	UNC_H_OSB.INVITOE_LOCAL	OSB Snoop Broadcast; Local InvItoE	0,1,2,3	0	null	0
+HA	0x53	0x8	UNC_H_OSB.REMOTE	OSB Snoop Broadcast; Remote	0,1,2,3	0	null	0
+HA	0x53	0x10	UNC_H_OSB.CANCELLED	OSB Snoop Broadcast; Cancelled	0,1,2,3	0	null	0
+HA	0x53	0x20	UNC_H_OSB.READS_LOCAL_USEFUL	OSB Snoop Broadcast; Reads Local -  Useful	0,1,2,3	0	null	0
+HA	0x53	0x40	UNC_H_OSB.REMOTE_USEFUL	OSB Snoop Broadcast; Remote - Useful	0,1,2,3	0	null	0
+HA	0x54	0x1	UNC_H_OSB_EDR.ALL	OSB Early Data Return; All	0,1,2,3	0	null	0
+HA	0x54	0x2	UNC_H_OSB_EDR.READS_LOCAL_I	OSB Early Data Return; Reads to Local  I	0,1,2,3	0	null	0
+HA	0x54	0x4	UNC_H_OSB_EDR.READS_REMOTE_I	OSB Early Data Return; Reads to Remote I	0,1,2,3	0	null	0
+HA	0x54	0x8	UNC_H_OSB_EDR.READS_LOCAL_S	OSB Early Data Return; Reads to Local S	0,1,2,3	0	null	0
+HA	0x54	0x10	UNC_H_OSB_EDR.READS_REMOTE_S	OSB Early Data Return; Reads to Remote S	0,1,2,3	0	null	0
+HA	0x1	0x3	UNC_H_REQUESTS.READS	Read and Write Requests; Reads	0,1,2,3	0	null	0
+HA	0x1	0xC	UNC_H_REQUESTS.WRITES	Read and Write Requests; Writes	0,1,2,3	0	null	0
+HA	0x1	0x1	UNC_H_REQUESTS.READS_LOCAL	Read and Write Requests; Local Reads	0,1,2,3	0	null	0
+HA	0x1	0x2	UNC_H_REQUESTS.READS_REMOTE	Read and Write Requests; Remote Reads	0,1,2,3	0	null	0
+HA	0x1	0x4	UNC_H_REQUESTS.WRITES_LOCAL	Read and Write Requests; Local Writes	0,1,2,3	0	null	0
+HA	0x1	0x8	UNC_H_REQUESTS.WRITES_REMOTE	Read and Write Requests; Remote Writes	0,1,2,3	0	null	0
+HA	0x1	0x10	UNC_H_REQUESTS.INVITOE_LOCAL	Read and Write Requests; Local InvItoEs	0,1,2,3	0	null	0
+HA	0x1	0x20	UNC_H_REQUESTS.INVITOE_REMOTE	Read and Write Requests; Remote InvItoEs	0,1,2,3	0	null	0
+HA	0x3E	0x1	UNC_H_RING_AD_USED.CW_EVEN	HA AD Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+HA	0x3E	0x2	UNC_H_RING_AD_USED.CW_ODD	HA AD Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+HA	0x3E	0x4	UNC_H_RING_AD_USED.CCW_EVEN	HA AD Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+HA	0x3E	0x8	UNC_H_RING_AD_USED.CCW_ODD	HA AD Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+HA	0x3E	0x3	UNC_H_RING_AD_USED.CW	HA AD Ring in Use; Clockwise	0,1,2,3	0	null	0
+HA	0x3E	0xC	UNC_H_RING_AD_USED.CCW	HA AD Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+HA	0x3F	0x1	UNC_H_RING_AK_USED.CW_EVEN	HA AK Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+HA	0x3F	0x2	UNC_H_RING_AK_USED.CW_ODD	HA AK Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+HA	0x3F	0x4	UNC_H_RING_AK_USED.CCW_EVEN	HA AK Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+HA	0x3F	0x8	UNC_H_RING_AK_USED.CCW_ODD	HA AK Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+HA	0x3F	0x3	UNC_H_RING_AK_USED.CW	HA AK Ring in Use; Clockwise	0,1,2,3	0	null	0
+HA	0x3F	0xC	UNC_H_RING_AK_USED.CCW	HA AK Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+HA	0x40	0x1	UNC_H_RING_BL_USED.CW_EVEN	HA BL Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+HA	0x40	0x2	UNC_H_RING_BL_USED.CW_ODD	HA BL Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+HA	0x40	0x4	UNC_H_RING_BL_USED.CCW_EVEN	HA BL Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+HA	0x40	0x8	UNC_H_RING_BL_USED.CCW_ODD	HA BL Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+HA	0x40	0x3	UNC_H_RING_BL_USED.CW	HA BL Ring in Use; Clockwise	0,1,2,3	0	null	0
+HA	0x40	0xC	UNC_H_RING_BL_USED.CCW	HA BL Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+HA	0x15	0x1	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0	iMC RPQ Credits Empty - Regular; Channel 0	0,1,2,3	0	null	0
+HA	0x15	0x2	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1	iMC RPQ Credits Empty - Regular; Channel 1	0,1,2,3	0	null	0
+HA	0x15	0x4	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2	iMC RPQ Credits Empty - Regular; Channel 2	0,1,2,3	0	null	0
+HA	0x15	0x8	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3	iMC RPQ Credits Empty - Regular; Channel 3	0,1,2,3	0	null	0
+HA	0x16	0x1	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0	iMC RPQ Credits Empty - Special; Channel 0	0,1,2,3	0	null	0
+HA	0x16	0x2	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1	iMC RPQ Credits Empty - Special; Channel 1	0,1,2,3	0	null	0
+HA	0x16	0x4	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2	iMC RPQ Credits Empty - Special; Channel 2	0,1,2,3	0	null	0
+HA	0x16	0x8	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3	iMC RPQ Credits Empty - Special; Channel 3	0,1,2,3	0	null	0
+HA	0x68	0x1	UNC_H_SBO0_CREDITS_ACQUIRED.AD	SBo0 Credits Acquired; For AD Ring	0,1,2,3	0	null	0
+HA	0x68	0x2	UNC_H_SBO0_CREDITS_ACQUIRED.BL	SBo0 Credits Acquired; For BL Ring	0,1,2,3	0	null	0
+HA	0x6A	0x1	UNC_H_SBO0_CREDIT_OCCUPANCY.AD	SBo0 Credits Occupancy; For AD Ring	0,1,2,3	0	null	0
+HA	0x6A	0x2	UNC_H_SBO0_CREDIT_OCCUPANCY.BL	SBo0 Credits Occupancy; For BL Ring	0,1,2,3	0	null	0
+HA	0x69	0x1	UNC_H_SBO1_CREDITS_ACQUIRED.AD	SBo1 Credits Acquired; For AD Ring	0,1,2,3	0	null	0
+HA	0x69	0x2	UNC_H_SBO1_CREDITS_ACQUIRED.BL	SBo1 Credits Acquired; For BL Ring	0,1,2,3	0	null	0
+HA	0x6B	0x1	UNC_H_SBO1_CREDIT_OCCUPANCY.AD	SBo1 Credits Occupancy; For AD Ring	0,1,2,3	0	null	0
+HA	0x6B	0x2	UNC_H_SBO1_CREDIT_OCCUPANCY.BL	SBo1 Credits Occupancy; For BL Ring	0,1,2,3	0	null	0
+HA	0xA	0x1	UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL	Data beat the Snoop Responses; Local Requests	0,1,2,3	0	null	0
+HA	0xA	0x2	UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE	Data beat the Snoop Responses; Remote Requests	0,1,2,3	0	null	0
+HA	0x8	0x1	UNC_H_SNOOP_CYCLES_NE.LOCAL	Cycles with Snoops Outstanding; Local Requests	0,1,2,3	0	null	0
+HA	0x8	0x2	UNC_H_SNOOP_CYCLES_NE.REMOTE	Cycles with Snoops Outstanding; Remote Requests	0,1,2,3	0	null	0
+HA	0x8	0x3	UNC_H_SNOOP_CYCLES_NE.ALL	Cycles with Snoops Outstanding; All Requests	0,1,2,3	0	null	0
+HA	0x9	0x1	UNC_H_SNOOP_OCCUPANCY.LOCAL	Tracker Snoops Outstanding Accumulator; Local Requests	0,1,2,3	0	null	0
+HA	0x9	0x2	UNC_H_SNOOP_OCCUPANCY.REMOTE	Tracker Snoops Outstanding Accumulator; Remote Requests	0,1,2,3	0	null	0
+HA	0x21	0x1	UNC_H_SNOOP_RESP.RSPI	Snoop Responses Received; RspI	0,1,2,3	0	null	0
+HA	0x21	0x2	UNC_H_SNOOP_RESP.RSPS	Snoop Responses Received; RspS	0,1,2,3	0	null	0
+HA	0x21	0x4	UNC_H_SNOOP_RESP.RSPIFWD	Snoop Responses Received; RspIFwd	0,1,2,3	0	null	0
+HA	0x21	0x8	UNC_H_SNOOP_RESP.RSPSFWD	Snoop Responses Received; RspSFwd	0,1,2,3	0	null	0
+HA	0x21	0x10	UNC_H_SNOOP_RESP.RSP_WB	Snoop Responses Received; Rsp*WB	0,1,2,3	0	null	0
+HA	0x21	0x20	UNC_H_SNOOP_RESP.RSP_FWD_WB	Snoop Responses Received; Rsp*Fwd*WB	0,1,2,3	0	null	0
+HA	0x21	0x40	UNC_H_SNOOP_RESP.RSPCNFLCT	Snoop Responses Received; RSPCNFLCT*	0,1,2,3	0	null	0
+HA	0x60	0x1	UNC_H_SNP_RESP_RECV_LOCAL.RSPI	Snoop Responses Received Local; RspI	0,1,2,3	0	null	0
+HA	0x60	0x2	UNC_H_SNP_RESP_RECV_LOCAL.RSPS	Snoop Responses Received Local; RspS	0,1,2,3	0	null	0
+HA	0x60	0x4	UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD	Snoop Responses Received Local; RspIFwd	0,1,2,3	0	null	0
+HA	0x60	0x8	UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD	Snoop Responses Received Local; RspSFwd	0,1,2,3	0	null	0
+HA	0x60	0x10	UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB	Snoop Responses Received Local; Rsp*WB	0,1,2,3	0	null	0
+HA	0x60	0x20	UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB	Snoop Responses Received Local; Rsp*FWD*WB	0,1,2,3	0	null	0
+HA	0x60	0x40	UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT	Snoop Responses Received Local; RspCnflct	0,1,2,3	0	null	0
+HA	0x60	0x80	UNC_H_SNP_RESP_RECV_LOCAL.OTHER	Snoop Responses Received Local; Other	0,1,2,3	0	null	0
+HA	0x6C	0x1	UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD	Stall on No Sbo Credits; For SBo0, AD Ring	0,1,2,3	0	null	0
+HA	0x6C	0x2	UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD	Stall on No Sbo Credits; For SBo1, AD Ring	0,1,2,3	0	null	0
+HA	0x6C	0x4	UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL	Stall on No Sbo Credits; For SBo0, BL Ring	0,1,2,3	0	null	0
+HA	0x6C	0x8	UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL	Stall on No Sbo Credits; For SBo1, BL Ring	0,1,2,3	0	null	0
+HA	0x1B	0x1	UNC_H_TAD_REQUESTS_G0.REGION0	HA Requests to a TAD Region - Group 0; TAD Region 0	0,1,2,3	0	null	0
+HA	0x1B	0x2	UNC_H_TAD_REQUESTS_G0.REGION1	HA Requests to a TAD Region - Group 0; TAD Region 1	0,1,2,3	0	null	0
+HA	0x1B	0x4	UNC_H_TAD_REQUESTS_G0.REGION2	HA Requests to a TAD Region - Group 0; TAD Region 2	0,1,2,3	0	null	0
+HA	0x1B	0x8	UNC_H_TAD_REQUESTS_G0.REGION3	HA Requests to a TAD Region - Group 0; TAD Region 3	0,1,2,3	0	null	0
+HA	0x1B	0x10	UNC_H_TAD_REQUESTS_G0.REGION4	HA Requests to a TAD Region - Group 0; TAD Region 4	0,1,2,3	0	null	0
+HA	0x1B	0x20	UNC_H_TAD_REQUESTS_G0.REGION5	HA Requests to a TAD Region - Group 0; TAD Region 5	0,1,2,3	0	null	0
+HA	0x1B	0x40	UNC_H_TAD_REQUESTS_G0.REGION6	HA Requests to a TAD Region - Group 0; TAD Region 6	0,1,2,3	0	null	0
+HA	0x1B	0x80	UNC_H_TAD_REQUESTS_G0.REGION7	HA Requests to a TAD Region - Group 0; TAD Region 7	0,1,2,3	0	null	0
+HA	0x1C	0x1	UNC_H_TAD_REQUESTS_G1.REGION8	HA Requests to a TAD Region - Group 1; TAD Region 8	0,1,2,3	0	null	0
+HA	0x1C	0x2	UNC_H_TAD_REQUESTS_G1.REGION9	HA Requests to a TAD Region - Group 1; TAD Region 9	0,1,2,3	0	null	0
+HA	0x1C	0x4	UNC_H_TAD_REQUESTS_G1.REGION10	HA Requests to a TAD Region - Group 1; TAD Region 10	0,1,2,3	0	null	0
+HA	0x1C	0x8	UNC_H_TAD_REQUESTS_G1.REGION11	HA Requests to a TAD Region - Group 1; TAD Region 11	0,1,2,3	0	null	0
+HA	0x2	0x1	UNC_H_TRACKER_CYCLES_FULL.GP	Tracker Cycles Full; Cycles GP Completely Used	0,1,2,3	0	null	0
+HA	0x2	0x2	UNC_H_TRACKER_CYCLES_FULL.ALL	Tracker Cycles Full; Cycles Completely Used	0,1,2,3	0	null	0
+HA	0x4	0x4	UNC_H_TRACKER_OCCUPANCY.READS_LOCAL	Tracker Occupancy Accumultor; Local Read Requests	0,1,2,3	0	null	0
+HA	0x4	0x8	UNC_H_TRACKER_OCCUPANCY.READS_REMOTE	Tracker Occupancy Accumultor; Remote Read Requests	0,1,2,3	0	null	0
+HA	0x4	0x10	UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL	Tracker Occupancy Accumultor; Local Write Requests	0,1,2,3	0	null	0
+HA	0x4	0x20	UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE	Tracker Occupancy Accumultor; Remote Write Requests	0,1,2,3	0	null	0
+HA	0x4	0x40	UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL	Tracker Occupancy Accumultor; Local InvItoE Requests	0,1,2,3	0	null	0
+HA	0x4	0x80	UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE	Tracker Occupancy Accumultor; Remote InvItoE Requests	0,1,2,3	0	null	0
+HA	0x5	0x1	UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL	Data Pending Occupancy Accumultor; Local Requests	0,1,2,3	0	null	0
+HA	0x5	0x2	UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE	Data Pending Occupancy Accumultor; Remote Requests	0,1,2,3	0	null	0
+HA	0xF	0x4	UNC_H_TxR_AD.HOM	Outbound NDR Ring Transactions; Non-data Responses	0,1,2,3	0	null	0
+HA	0x2A	0x1	UNC_H_TxR_AD_CYCLES_FULL.SCHED0	AD Egress Full; Scheduler 0	0,1,2,3	0	null	0
+HA	0x2A	0x2	UNC_H_TxR_AD_CYCLES_FULL.SCHED1	AD Egress Full; Scheduler 1	0,1,2,3	0	null	0
+HA	0x2A	0x3	UNC_H_TxR_AD_CYCLES_FULL.ALL	AD Egress Full; All	0,1,2,3	0	null	0
+HA	0x29	0x1	UNC_H_TxR_AD_CYCLES_NE.SCHED0	AD Egress Not Empty; Scheduler 0	0,1,2,3	0	null	0
+HA	0x29	0x2	UNC_H_TxR_AD_CYCLES_NE.SCHED1	AD Egress Not Empty; Scheduler 1	0,1,2,3	0	null	0
+HA	0x29	0x3	UNC_H_TxR_AD_CYCLES_NE.ALL	AD Egress Not Empty; All	0,1,2,3	0	null	0
+HA	0x27	0x1	UNC_H_TxR_AD_INSERTS.SCHED0	AD Egress Allocations; Scheduler 0	0,1,2,3	0	null	0
+HA	0x27	0x2	UNC_H_TxR_AD_INSERTS.SCHED1	AD Egress Allocations; Scheduler 1	0,1,2,3	0	null	0
+HA	0x27	0x3	UNC_H_TxR_AD_INSERTS.ALL	AD Egress Allocations; All	0,1,2,3	0	null	0
+HA	0x32	0x1	UNC_H_TxR_AK_CYCLES_FULL.SCHED0	AK Egress Full; Scheduler 0	0,1,2,3	0	null	0
+HA	0x32	0x2	UNC_H_TxR_AK_CYCLES_FULL.SCHED1	AK Egress Full; Scheduler 1	0,1,2,3	0	null	0
+HA	0x32	0x3	UNC_H_TxR_AK_CYCLES_FULL.ALL	AK Egress Full; All	0,1,2,3	0	null	0
+HA	0x31	0x1	UNC_H_TxR_AK_CYCLES_NE.SCHED0	AK Egress Not Empty; Scheduler 0	0,1,2,3	0	null	0
+HA	0x31	0x2	UNC_H_TxR_AK_CYCLES_NE.SCHED1	AK Egress Not Empty; Scheduler 1	0,1,2,3	0	null	0
+HA	0x31	0x3	UNC_H_TxR_AK_CYCLES_NE.ALL	AK Egress Not Empty; All	0,1,2,3	0	null	0
+HA	0x2F	0x1	UNC_H_TxR_AK_INSERTS.SCHED0	AK Egress Allocations; Scheduler 0	0,1,2,3	0	null	0
+HA	0x2F	0x2	UNC_H_TxR_AK_INSERTS.SCHED1	AK Egress Allocations; Scheduler 1	0,1,2,3	0	null	0
+HA	0x2F	0x3	UNC_H_TxR_AK_INSERTS.ALL	AK Egress Allocations; All	0,1,2,3	0	null	0
+HA	0x10	0x1	UNC_H_TxR_BL.DRS_CACHE	Outbound DRS Ring Transactions to Cache; Data to Cache	0,1,2,3	0	null	0
+HA	0x10	0x2	UNC_H_TxR_BL.DRS_CORE	Outbound DRS Ring Transactions to Cache; Data to Core	0,1,2,3	0	null	0
+HA	0x10	0x4	UNC_H_TxR_BL.DRS_QPI	Outbound DRS Ring Transactions to Cache; Data to QPI	0,1,2,3	0	null	0
+HA	0x36	0x1	UNC_H_TxR_BL_CYCLES_FULL.SCHED0	BL Egress Full; Scheduler 0	0,1,2,3	0	null	0
+HA	0x36	0x2	UNC_H_TxR_BL_CYCLES_FULL.SCHED1	BL Egress Full; Scheduler 1	0,1,2,3	0	null	0
+HA	0x36	0x3	UNC_H_TxR_BL_CYCLES_FULL.ALL	BL Egress Full; All	0,1,2,3	0	null	0
+HA	0x35	0x1	UNC_H_TxR_BL_CYCLES_NE.SCHED0	BL Egress Not Empty; Scheduler 0	0,1,2,3	0	null	0
+HA	0x35	0x2	UNC_H_TxR_BL_CYCLES_NE.SCHED1	BL Egress Not Empty; Scheduler 1	0,1,2,3	0	null	0
+HA	0x35	0x3	UNC_H_TxR_BL_CYCLES_NE.ALL	BL Egress Not Empty; All	0,1,2,3	0	null	0
+HA	0x33	0x1	UNC_H_TxR_BL_INSERTS.SCHED0	BL Egress Allocations; Scheduler 0	0,1,2,3	0	null	0
+HA	0x33	0x2	UNC_H_TxR_BL_INSERTS.SCHED1	BL Egress Allocations; Scheduler 1	0,1,2,3	0	null	0
+HA	0x33	0x3	UNC_H_TxR_BL_INSERTS.ALL	BL Egress Allocations; All	0,1,2,3	0	null	0
+HA	0x6D	0x1	UNC_H_TxR_STARVED.AK	Injection Starvation; For AK Ring	0,1,2,3	0	null	0
+HA	0x6D	0x2	UNC_H_TxR_STARVED.BL	Injection Starvation; For BL Ring	0,1,2,3	0	null	0
+HA	0x18	0x1	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0	HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0	0,1,2,3	0	null	0
+HA	0x18	0x2	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1	HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1	0,1,2,3	0	null	0
+HA	0x18	0x4	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2	HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2	0,1,2,3	0	null	0
+HA	0x18	0x8	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3	HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3	0,1,2,3	0	null	0
+HA	0x19	0x1	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0	HA iMC CHN0 WPQ Credits Empty - Special; Channel 0	0,1,2,3	0	null	0
+HA	0x19	0x2	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1	HA iMC CHN0 WPQ Credits Empty - Special; Channel 1	0,1,2,3	0	null	0
+HA	0x19	0x4	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2	HA iMC CHN0 WPQ Credits Empty - Special; Channel 2	0,1,2,3	0	null	0
+HA	0x19	0x8	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3	HA iMC CHN0 WPQ Credits Empty - Special; Channel 3	0,1,2,3	0	null	0
+IRP	0x12	0x1	UNC_I_CACHE_TOTAL_OCCUPANCY.ANY	Total Write Cache Occupancy; Any Source	0,1	0	null	0
+IRP	0x12	0x2	UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE	Total Write Cache Occupancy; Select Source	0,1	0	null	0
+IRP	0x0	0x0	UNC_I_CLOCKTICKS	Clocks in the IRP	0,1	0	null	0
+IRP	0x13	0x1	UNC_I_COHERENT_OPS.PCIRDCUR	Coherent Ops; PCIRdCur	0,1	0	null	0
+IRP	0x13	0x2	UNC_I_COHERENT_OPS.CRD	Coherent Ops; CRd	0,1	0	null	0
+IRP	0x13	0x4	UNC_I_COHERENT_OPS.DRD	Coherent Ops; DRd	0,1	0	null	0
+IRP	0x13	0x8	UNC_I_COHERENT_OPS.RFO	Coherent Ops; RFO	0,1	0	null	0
+IRP	0x13	0x10	UNC_I_COHERENT_OPS.PCITOM	Coherent Ops; PCIItoM	0,1	0	null	0
+IRP	0x13	0x20	UNC_I_COHERENT_OPS.PCIDCAHINT	Coherent Ops; PCIDCAHin5t	0,1	0	null	0
+IRP	0x13	0x40	UNC_I_COHERENT_OPS.WBMTOI	Coherent Ops; WbMtoI	0,1	0	null	0
+IRP	0x13	0x80	UNC_I_COHERENT_OPS.CLFLUSH	Coherent Ops; CLFlush	0,1	0	null	0
+IRP	0x14	0x1	UNC_I_MISC0.FAST_REQ	Misc Events - Set 0; Fastpath Requests	0,1	0	null	0
+IRP	0x14	0x2	UNC_I_MISC0.FAST_REJ	Misc Events - Set 0; Fastpath Rejects	0,1	0	null	0
+IRP	0x14	0x4	UNC_I_MISC0.2ND_RD_INSERT	Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary	0,1	0	null	0
+IRP	0x14	0x8	UNC_I_MISC0.2ND_WR_INSERT	Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary	0,1	0	null	0
+IRP	0x14	0x10	UNC_I_MISC0.2ND_ATOMIC_INSERT	Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary	0,1	0	null	0
+IRP	0x14	0x20	UNC_I_MISC0.FAST_XFER	Misc Events - Set 0; Fastpath Transfers From Primary to Secondary	0,1	0	null	0
+IRP	0x14	0x40	UNC_I_MISC0.PF_ACK_HINT	Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary	0,1	0	null	0
+IRP	0x14	0x80	UNC_I_MISC0.UNKNOWN	Misc Events - Set 0	0,1	0	null	0
+IRP	0x15	0x1	UNC_I_MISC1.SLOW_I	Misc Events - Set 1; Slow Transfer of I Line	0,1	0	null	0
+IRP	0x15	0x2	UNC_I_MISC1.SLOW_S	Misc Events - Set 1; Slow Transfer of S Line	0,1	0	null	0
+IRP	0x15	0x4	UNC_I_MISC1.SLOW_E	Misc Events - Set 1; Slow Transfer of E Line	0,1	0	null	0
+IRP	0x15	0x8	UNC_I_MISC1.SLOW_M	Misc Events - Set 1; Slow Transfer of M Line	0,1	0	null	0
+IRP	0x15	0x10	UNC_I_MISC1.LOST_FWD	Misc Events - Set 1	0,1	0	null	0
+IRP	0x15	0x20	UNC_I_MISC1.SEC_RCVD_INVLD	Misc Events - Set 1; Received Invalid	0,1	0	null	0
+IRP	0x15	0x40	UNC_I_MISC1.SEC_RCVD_VLD	Misc Events - Set 1; Received Valid	0,1	0	null	0
+IRP	0x15	0x80	UNC_I_MISC1.DATA_THROTTLE	Misc Events - Set 1; Data Throttled	0,1	0	null	0
+IRP	0xA	0x0	UNC_I_RxR_AK_INSERTS	AK Ingress Occupancy	0,1	0	null	0
+IRP	0x4	0x0	UNC_I_RxR_BL_DRS_CYCLES_FULL	tbd	0,1	0	null	0
+IRP	0x1	0x0	UNC_I_RxR_BL_DRS_INSERTS	BL Ingress Occupancy - DRS	0,1	0	null	0
+IRP	0x7	0x0	UNC_I_RxR_BL_DRS_OCCUPANCY	tbd	0,1	0	null	0
+IRP	0x5	0x0	UNC_I_RxR_BL_NCB_CYCLES_FULL	tbd	0,1	0	null	0
+IRP	0x2	0x0	UNC_I_RxR_BL_NCB_INSERTS	BL Ingress Occupancy - NCB	0,1	0	null	0
+IRP	0x8	0x0	UNC_I_RxR_BL_NCB_OCCUPANCY	tbd	0,1	0	null	0
+IRP	0x6	0x0	UNC_I_RxR_BL_NCS_CYCLES_FULL	tbd	0,1	0	null	0
+IRP	0x3	0x0	UNC_I_RxR_BL_NCS_INSERTS	BL Ingress Occupancy - NCS	0,1	0	null	0
+IRP	0x9	0x0	UNC_I_RxR_BL_NCS_OCCUPANCY	tbd	0,1	0	null	0
+IRP	0x17	0x1	UNC_I_SNOOP_RESP.MISS	Snoop Responses; Miss	0,1	0	null	0
+IRP	0x17	0x2	UNC_I_SNOOP_RESP.HIT_I	Snoop Responses; Hit I	0,1	0	null	0
+IRP	0x17	0x4	UNC_I_SNOOP_RESP.HIT_ES	Snoop Responses; Hit E or S	0,1	0	null	0
+IRP	0x17	0x8	UNC_I_SNOOP_RESP.HIT_M	Snoop Responses; Hit M	0,1	0	null	0
+IRP	0x17	0x10	UNC_I_SNOOP_RESP.SNPCODE	Snoop Responses; SnpCode	0,1	0	null	0
+IRP	0x17	0x20	UNC_I_SNOOP_RESP.SNPDATA	Snoop Responses; SnpData	0,1	0	null	0
+IRP	0x17	0x40	UNC_I_SNOOP_RESP.SNPINV	Snoop Responses; SnpInv	0,1	0	null	0
+IRP	0x16	0x1	UNC_I_TRANSACTIONS.READS	Inbound Transaction Count; Reads	0,1	0	null	0
+IRP	0x16	0x2	UNC_I_TRANSACTIONS.WRITES	Inbound Transaction Count; Writes	0,1	0	null	0
+IRP	0x16	0x4	UNC_I_TRANSACTIONS.RD_PREF	Inbound Transaction Count; Read Prefetches	0,1	0	null	0
+IRP	0x16	0x8	UNC_I_TRANSACTIONS.WR_PREF	Inbound Transaction Count; Write Prefetches	0,1	0	null	0
+IRP	0x16	0x10	UNC_I_TRANSACTIONS.ATOMIC	Inbound Transaction Count; Atomic	0,1	0	null	0
+IRP	0x16	0x20	UNC_I_TRANSACTIONS.OTHER	Inbound Transaction Count; Other	0,1	0	null	0
+IRP	0x16	0x40	UNC_I_TRANSACTIONS.ORDERINGQ	Inbound Transaction Count; Select Source	0,1	0	IRPFilter[4:0]	0
+IRP	0x18	0x0	UNC_I_TxR_AD_STALL_CREDIT_CYCLES	No AD Egress Credit Stalls	0,1	0	null	0
+IRP	0x19	0x0	UNC_I_TxR_BL_STALL_CREDIT_CYCLES	No BL Egress Credit Stalls	0,1	0	null	0
+IRP	0xE	0x0	UNC_I_TxR_DATA_INSERTS_NCB	Outbound Read Requests	0,1	0	null	0
+IRP	0xF	0x0	UNC_I_TxR_DATA_INSERTS_NCS	Outbound Read Requests	0,1	0	null	0
+IRP	0xD	0x0	UNC_I_TxR_REQUEST_OCCUPANCY	Outbound Request Queue Occupancy	0,1	0	null	0
+PCU	0x0	0x0	UNC_P_CLOCKTICKS	pclk Cycles	0,1,2,3	0	null	0
+PCU	0x60	0x0	UNC_P_CORE0_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6A	0x0	UNC_P_CORE10_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6B	0x0	UNC_P_CORE11_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6C	0x0	UNC_P_CORE12_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6D	0x0	UNC_P_CORE13_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6E	0x0	UNC_P_CORE14_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x6F	0x0	UNC_P_CORE15_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x70	0x0	UNC_P_CORE16_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x71	0x0	UNC_P_CORE17_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x61	0x0	UNC_P_CORE1_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x62	0x0	UNC_P_CORE2_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x63	0x0	UNC_P_CORE3_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x64	0x0	UNC_P_CORE4_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x65	0x0	UNC_P_CORE5_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x66	0x0	UNC_P_CORE6_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x67	0x0	UNC_P_CORE7_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x68	0x0	UNC_P_CORE8_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x69	0x0	UNC_P_CORE9_TRANSITION_CYCLES	Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x30	0x0	UNC_P_DEMOTIONS_CORE0	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x31	0x0	UNC_P_DEMOTIONS_CORE1	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3A	0x0	UNC_P_DEMOTIONS_CORE10	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3B	0x0	UNC_P_DEMOTIONS_CORE11	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3C	0x0	UNC_P_DEMOTIONS_CORE12	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3D	0x0	UNC_P_DEMOTIONS_CORE13	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3E	0x0	UNC_P_DEMOTIONS_CORE14	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x3F	0x0	UNC_P_DEMOTIONS_CORE15	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x40	0x0	UNC_P_DEMOTIONS_CORE16	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x41	0x0	UNC_P_DEMOTIONS_CORE17	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x32	0x0	UNC_P_DEMOTIONS_CORE2	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x33	0x0	UNC_P_DEMOTIONS_CORE3	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x34	0x0	UNC_P_DEMOTIONS_CORE4	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x35	0x0	UNC_P_DEMOTIONS_CORE5	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x36	0x0	UNC_P_DEMOTIONS_CORE6	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x37	0x0	UNC_P_DEMOTIONS_CORE7	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x38	0x0	UNC_P_DEMOTIONS_CORE8	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0x39	0x0	UNC_P_DEMOTIONS_CORE9	Core C State Demotions	0,1,2,3	0	null	0
+PCU	0xB	0x0	UNC_P_FREQ_BAND0_CYCLES	Frequency Residency	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0xC	0x0	UNC_P_FREQ_BAND1_CYCLES	Frequency Residency	0,1,2,3	0	PCUFilter[15:8]	0
+PCU	0xD	0x0	UNC_P_FREQ_BAND2_CYCLES	Frequency Residency	0,1,2,3	0	PCUFilter[23:16]	0
+PCU	0xE	0x0	UNC_P_FREQ_BAND3_CYCLES	Frequency Residency	0,1,2,3	0	PCUFilter[31:24]	0
+PCU	0x4	0x0	UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES	Thermal Strongest Upper Limit Cycles	0,1,2,3	0	null	0
+PCU	0x6	0x0	UNC_P_FREQ_MAX_OS_CYCLES	OS Strongest Upper Limit Cycles	0,1,2,3	0	null	0
+PCU	0x5	0x0	UNC_P_FREQ_MAX_POWER_CYCLES	Power Strongest Upper Limit Cycles	0,1,2,3	0	null	0
+PCU	0x73	0x0	UNC_P_FREQ_MIN_IO_P_CYCLES	IO P Limit Strongest Lower Limit Cycles	0,1,2,3	0	null	0
+PCU	0x74	0x0	UNC_P_FREQ_TRANS_CYCLES	Cycles spent changing Frequency	0,1,2,3	0	null	0
+PCU	0x2F	0x0	UNC_P_MEMORY_PHASE_SHEDDING_CYCLES	Memory Phase Shedding Cycles	0,1,2,3	0	null	0
+PCU	0x2A	0x0	UNC_P_PKG_RESIDENCY_C0_CYCLES	Package C State Residency - C0	0,1,2,3	0	null	0
+PCU	0x2B	0x0	UNC_P_PKG_RESIDENCY_C2E_CYCLES	Package C State Residency - C2E	0,1,2,3	0	null	0
+PCU	0x2C	0x0	UNC_P_PKG_RESIDENCY_C3_CYCLES	Package C State Residency - C3	0,1,2,3	0	null	0
+PCU	0x2D	0x0	UNC_P_PKG_RESIDENCY_C6_CYCLES	Package C State Residency - C6	0,1,2,3	0	null	0
+PCU	0x2E	0x0	UNC_P_PKG_RESIDENCY_C7_CYCLES	Package C7 State Residency	0,1,2,3	0	null	0
+PCU	0x80	0x40	UNC_P_POWER_STATE_OCCUPANCY.CORES_C0	Number of cores in C-State; C0 and C1	0,1,2,3	0	null	0
+PCU	0x80	0x80	UNC_P_POWER_STATE_OCCUPANCY.CORES_C3	Number of cores in C-State; C3	0,1,2,3	0	null	0
+PCU	0x80	0xC0	UNC_P_POWER_STATE_OCCUPANCY.CORES_C6	Number of cores in C-State; C6 and C7	0,1,2,3	0	null	0
+PCU	0xA	0x0	UNC_P_PROCHOT_EXTERNAL_CYCLES	External Prochot	0,1,2,3	0	null	0
+PCU	0x9	0x0	UNC_P_PROCHOT_INTERNAL_CYCLES	Internal Prochot	0,1,2,3	0	null	0
+PCU	0x72	0x0	UNC_P_TOTAL_TRANSITION_CYCLES	Total Core C State Transition Cycles	0,1,2,3	0	null	0
+PCU	0x79	0x0	UNC_P_UFS_TRANSITIONS_NO_CHANGE	tbd	0,1,2,3	0	null	0
+PCU	0x42	0x0	UNC_P_VR_HOT_CYCLES	VR Hot	0,1,2,3	0	null	0
+QPI LL	0x14	0x0	UNC_Q_CLOCKTICKS	Number of qfclks	0,1,2,3	0	null	0
+QPI LL	0x38	0x0	UNC_Q_CTO_COUNT	Count of CTO Events	0,1,2,3	0	QPIMask0[17:0],QPIMatch0[17:0],QPIMask1[19:16],QPIMatch1[19:16]	1
+QPI LL	0x13	0x1	UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT	Direct 2 Core Spawning; Spawn Success	0,1,2,3	0	null	0
+QPI LL	0x13	0x2	UNC_Q_DIRECT2CORE.FAILURE_CREDITS	Direct 2 Core Spawning; Spawn Failure - Egress Credits	0,1,2,3	0	null	0
+QPI LL	0x13	0x4	UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT	Direct 2 Core Spawning; Spawn Failure - RBT Invalid	0,1,2,3	0	null	0
+QPI LL	0x13	0x8	UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT	Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid	0,1,2,3	0	null	0
+QPI LL	0x13	0x10	UNC_Q_DIRECT2CORE.FAILURE_MISS	Direct 2 Core Spawning; Spawn Failure - RBT Miss	0,1,2,3	0	null	0
+QPI LL	0x13	0x20	UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS	Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss	0,1,2,3	0	null	0
+QPI LL	0x13	0x40	UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS	Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid	0,1,2,3	0	null	0
+QPI LL	0x13	0x80	UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS	Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid	0,1,2,3	0	null	0
+QPI LL	0x12	0x0	UNC_Q_L1_POWER_CYCLES	Cycles in L1	0,1,2,3	0	null	0
+QPI LL	0x10	0x0	UNC_Q_RxL0P_POWER_CYCLES	Cycles in L0p	0,1,2,3	0	null	0
+QPI LL	0xF	0x0	UNC_Q_RxL0_POWER_CYCLES	Cycles in L0	0,1,2,3	0	null	0
+QPI LL	0x9	0x0	UNC_Q_RxL_BYPASSED	Rx Flit Buffer Bypassed	0,1,2,3	0	null	0
+QPI LL	0x3	0x1	UNC_Q_RxL_CRC_ERRORS.LINK_INIT	CRC Errors Detected; LinkInit	0,1,2,3	0	null	0
+QPI LL	0x3	0x2	UNC_Q_RxL_CRC_ERRORS.NORMAL_OP	CRC Errors Detected; Normal Operations	0,1,2,3	0	null	0
+QPI LL	0x1E	0x1	UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS	VN0 Credit Consumed; DRS	0,1,2,3	0	null	1
+QPI LL	0x1E	0x2	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB	VN0 Credit Consumed; NCB	0,1,2,3	0	null	1
+QPI LL	0x1E	0x4	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS	VN0 Credit Consumed; NCS	0,1,2,3	0	null	1
+QPI LL	0x1E	0x8	UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM	VN0 Credit Consumed; HOM	0,1,2,3	0	null	1
+QPI LL	0x1E	0x10	UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP	VN0 Credit Consumed; SNP	0,1,2,3	0	null	1
+QPI LL	0x1E	0x20	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR	VN0 Credit Consumed; NDR	0,1,2,3	0	null	1
+QPI LL	0x39	0x1	UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS	VN1 Credit Consumed; DRS	0,1,2,3	0	null	1
+QPI LL	0x39	0x2	UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB	VN1 Credit Consumed; NCB	0,1,2,3	0	null	1
+QPI LL	0x39	0x4	UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS	VN1 Credit Consumed; NCS	0,1,2,3	0	null	1
+QPI LL	0x39	0x8	UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM	VN1 Credit Consumed; HOM	0,1,2,3	0	null	1
+QPI LL	0x39	0x10	UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP	VN1 Credit Consumed; SNP	0,1,2,3	0	null	1
+QPI LL	0x39	0x20	UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR	VN1 Credit Consumed; NDR	0,1,2,3	0	null	1
+QPI LL	0x1D	0x0	UNC_Q_RxL_CREDITS_CONSUMED_VNA	VNA Credit Consumed	0,1,2,3	0	null	1
+QPI LL	0xA	0x0	UNC_Q_RxL_CYCLES_NE	RxQ Cycles Not Empty	0,1,2,3	0	null	0
+QPI LL	0xF	0x1	UNC_Q_RxL_CYCLES_NE_DRS.VN0	RxQ Cycles Not Empty - DRS; for VN0	0,1,2,3	0	null	1
+QPI LL	0xF	0x2	UNC_Q_RxL_CYCLES_NE_DRS.VN1	RxQ Cycles Not Empty - DRS; for VN1	0,1,2,3	0	null	1
+QPI LL	0x12	0x1	UNC_Q_RxL_CYCLES_NE_HOM.VN0	RxQ Cycles Not Empty - HOM; for VN0	0,1,2,3	0	null	1
+QPI LL	0x12	0x2	UNC_Q_RxL_CYCLES_NE_HOM.VN1	RxQ Cycles Not Empty - HOM; for VN1	0,1,2,3	0	null	1
+QPI LL	0x10	0x1	UNC_Q_RxL_CYCLES_NE_NCB.VN0	RxQ Cycles Not Empty - NCB; for VN0	0,1,2,3	0	null	1
+QPI LL	0x10	0x2	UNC_Q_RxL_CYCLES_NE_NCB.VN1	RxQ Cycles Not Empty - NCB; for VN1	0,1,2,3	0	null	1
+QPI LL	0x11	0x1	UNC_Q_RxL_CYCLES_NE_NCS.VN0	RxQ Cycles Not Empty - NCS; for VN0	0,1,2,3	0	null	1
+QPI LL	0x11	0x2	UNC_Q_RxL_CYCLES_NE_NCS.VN1	RxQ Cycles Not Empty - NCS; for VN1	0,1,2,3	0	null	1
+QPI LL	0x14	0x1	UNC_Q_RxL_CYCLES_NE_NDR.VN0	RxQ Cycles Not Empty - NDR; for VN0	0,1,2,3	0	null	1
+QPI LL	0x14	0x2	UNC_Q_RxL_CYCLES_NE_NDR.VN1	RxQ Cycles Not Empty - NDR; for VN1	0,1,2,3	0	null	1
+QPI LL	0x13	0x1	UNC_Q_RxL_CYCLES_NE_SNP.VN0	RxQ Cycles Not Empty - SNP; for VN0	0,1,2,3	0	null	1
+QPI LL	0x13	0x2	UNC_Q_RxL_CYCLES_NE_SNP.VN1	RxQ Cycles Not Empty - SNP; for VN1	0,1,2,3	0	null	1
+QPI LL	0x1	0x1	UNC_Q_RxL_FLITS_G0.IDLE	Flits Received - Group 0; Idle and Null Flits	0,1,2,3	0	null	0
+QPI LL	0x2	0x1	UNC_Q_RxL_FLITS_G1.SNP	Flits Received - Group 1; SNP Flits	0,1,2,3	0	null	1
+QPI LL	0x2	0x2	UNC_Q_RxL_FLITS_G1.HOM_REQ	Flits Received - Group 1; HOM Request Flits	0,1,2,3	0	null	1
+QPI LL	0x2	0x4	UNC_Q_RxL_FLITS_G1.HOM_NONREQ	Flits Received - Group 1; HOM Non-Request Flits	0,1,2,3	0	null	1
+QPI LL	0x2	0x6	UNC_Q_RxL_FLITS_G1.HOM	Flits Received - Group 1; HOM Flits	0,1,2,3	0	null	1
+QPI LL	0x2	0x8	UNC_Q_RxL_FLITS_G1.DRS_DATA	Flits Received - Group 1; DRS Data Flits	0,1,2,3	0	null	1
+QPI LL	0x2	0x10	UNC_Q_RxL_FLITS_G1.DRS_NONDATA	Flits Received - Group 1; DRS Header Flits	0,1,2,3	0	null	1
+QPI LL	0x2	0x18	UNC_Q_RxL_FLITS_G1.DRS	Flits Received - Group 1; DRS Flits (both Header and Data)	0,1,2,3	0	null	1
+QPI LL	0x3	0x1	UNC_Q_RxL_FLITS_G2.NDR_AD	Flits Received - Group 2; Non-Data Response Rx Flits - AD	0,1,2,3	0	null	1
+QPI LL	0x3	0x2	UNC_Q_RxL_FLITS_G2.NDR_AK	Flits Received - Group 2; Non-Data Response Rx Flits - AK	0,1,2,3	0	null	1
+QPI LL	0x3	0x4	UNC_Q_RxL_FLITS_G2.NCB_DATA	Flits Received - Group 2; Non-Coherent data Rx Flits	0,1,2,3	0	null	1
+QPI LL	0x3	0x8	UNC_Q_RxL_FLITS_G2.NCB_NONDATA	Flits Received - Group 2; Non-Coherent non-data Rx Flits	0,1,2,3	0	null	1
+QPI LL	0x3	0xC	UNC_Q_RxL_FLITS_G2.NCB	Flits Received - Group 2; Non-Coherent Rx Flits	0,1,2,3	0	null	1
+QPI LL	0x3	0x10	UNC_Q_RxL_FLITS_G2.NCS	Flits Received - Group 2; Non-Coherent standard Rx Flits	0,1,2,3	0	null	1
+QPI LL	0x8	0x0	UNC_Q_RxL_INSERTS	Rx Flit Buffer Allocations	0,1,2,3	0	null	0
+QPI LL	0x9	0x1	UNC_Q_RxL_INSERTS_DRS.VN0	Rx Flit Buffer Allocations - DRS; for VN0	0,1,2,3	0	null	1
+QPI LL	0x9	0x2	UNC_Q_RxL_INSERTS_DRS.VN1	Rx Flit Buffer Allocations - DRS; for VN1	0,1,2,3	0	null	1
+QPI LL	0xC	0x1	UNC_Q_RxL_INSERTS_HOM.VN0	Rx Flit Buffer Allocations - HOM; for VN0	0,1,2,3	0	null	1
+QPI LL	0xC	0x2	UNC_Q_RxL_INSERTS_HOM.VN1	Rx Flit Buffer Allocations - HOM; for VN1	0,1,2,3	0	null	1
+QPI LL	0xA	0x1	UNC_Q_RxL_INSERTS_NCB.VN0	Rx Flit Buffer Allocations - NCB; for VN0	0,1,2,3	0	null	1
+QPI LL	0xA	0x2	UNC_Q_RxL_INSERTS_NCB.VN1	Rx Flit Buffer Allocations - NCB; for VN1	0,1,2,3	0	null	1
+QPI LL	0xB	0x1	UNC_Q_RxL_INSERTS_NCS.VN0	Rx Flit Buffer Allocations - NCS; for VN0	0,1,2,3	0	null	1
+QPI LL	0xB	0x2	UNC_Q_RxL_INSERTS_NCS.VN1	Rx Flit Buffer Allocations - NCS; for VN1	0,1,2,3	0	null	1
+QPI LL	0xE	0x1	UNC_Q_RxL_INSERTS_NDR.VN0	Rx Flit Buffer Allocations - NDR; for VN0	0,1,2,3	0	null	1
+QPI LL	0xE	0x2	UNC_Q_RxL_INSERTS_NDR.VN1	Rx Flit Buffer Allocations - NDR; for VN1	0,1,2,3	0	null	1
+QPI LL	0xD	0x1	UNC_Q_RxL_INSERTS_SNP.VN0	Rx Flit Buffer Allocations - SNP; for VN0	0,1,2,3	0	null	1
+QPI LL	0xD	0x2	UNC_Q_RxL_INSERTS_SNP.VN1	Rx Flit Buffer Allocations - SNP; for VN1	0,1,2,3	0	null	1
+QPI LL	0xB	0x0	UNC_Q_RxL_OCCUPANCY	RxQ Occupancy - All Packets	0,1,2,3	0	null	0
+QPI LL	0x15	0x1	UNC_Q_RxL_OCCUPANCY_DRS.VN0	RxQ Occupancy - DRS; for VN0	0,1,2,3	0	null	1
+QPI LL	0x15	0x2	UNC_Q_RxL_OCCUPANCY_DRS.VN1	RxQ Occupancy - DRS; for VN1	0,1,2,3	0	null	1
+QPI LL	0x18	0x1	UNC_Q_RxL_OCCUPANCY_HOM.VN0	RxQ Occupancy - HOM; for VN0	0,1,2,3	0	null	1
+QPI LL	0x18	0x2	UNC_Q_RxL_OCCUPANCY_HOM.VN1	RxQ Occupancy - HOM; for VN1	0,1,2,3	0	null	1
+QPI LL	0x16	0x1	UNC_Q_RxL_OCCUPANCY_NCB.VN0	RxQ Occupancy - NCB; for VN0	0,1,2,3	0	null	1
+QPI LL	0x16	0x2	UNC_Q_RxL_OCCUPANCY_NCB.VN1	RxQ Occupancy - NCB; for VN1	0,1,2,3	0	null	1
+QPI LL	0x17	0x1	UNC_Q_RxL_OCCUPANCY_NCS.VN0	RxQ Occupancy - NCS; for VN0	0,1,2,3	0	null	1
+QPI LL	0x17	0x2	UNC_Q_RxL_OCCUPANCY_NCS.VN1	RxQ Occupancy - NCS; for VN1	0,1,2,3	0	null	1
+QPI LL	0x1A	0x1	UNC_Q_RxL_OCCUPANCY_NDR.VN0	RxQ Occupancy - NDR; for VN0	0,1,2,3	0	null	1
+QPI LL	0x1A	0x2	UNC_Q_RxL_OCCUPANCY_NDR.VN1	RxQ Occupancy - NDR; for VN1	0,1,2,3	0	null	1
+QPI LL	0x19	0x1	UNC_Q_RxL_OCCUPANCY_SNP.VN0	RxQ Occupancy - SNP; for VN0	0,1,2,3	0	null	1
+QPI LL	0x19	0x2	UNC_Q_RxL_OCCUPANCY_SNP.VN1	RxQ Occupancy - SNP; for VN1	0,1,2,3	0	null	1
+QPI LL	0x35	0x1	UNC_Q_RxL_STALLS_VN0.BGF_DRS	Stalls Sending to R3QPI on VN0; BGF Stall - HOM	0,1,2,3	0	null	1
+QPI LL	0x35	0x2	UNC_Q_RxL_STALLS_VN0.BGF_NCB	Stalls Sending to R3QPI on VN0; BGF Stall - SNP	0,1,2,3	0	null	1
+QPI LL	0x35	0x4	UNC_Q_RxL_STALLS_VN0.BGF_NCS	Stalls Sending to R3QPI on VN0; BGF Stall - NDR	0,1,2,3	0	null	1
+QPI LL	0x35	0x8	UNC_Q_RxL_STALLS_VN0.BGF_HOM	Stalls Sending to R3QPI on VN0; BGF Stall - DRS	0,1,2,3	0	null	1
+QPI LL	0x35	0x10	UNC_Q_RxL_STALLS_VN0.BGF_SNP	Stalls Sending to R3QPI on VN0; BGF Stall - NCB	0,1,2,3	0	null	1
+QPI LL	0x35	0x20	UNC_Q_RxL_STALLS_VN0.BGF_NDR	Stalls Sending to R3QPI on VN0; BGF Stall - NCS	0,1,2,3	0	null	1
+QPI LL	0x35	0x40	UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS	Stalls Sending to R3QPI on VN0; Egress Credits	0,1,2,3	0	null	1
+QPI LL	0x35	0x80	UNC_Q_RxL_STALLS_VN0.GV	Stalls Sending to R3QPI on VN0; GV	0,1,2,3	0	null	1
+QPI LL	0x3A	0x1	UNC_Q_RxL_STALLS_VN1.BGF_DRS	Stalls Sending to R3QPI on VN1; BGF Stall - HOM	0,1,2,3	0	null	1
+QPI LL	0x3A	0x2	UNC_Q_RxL_STALLS_VN1.BGF_NCB	Stalls Sending to R3QPI on VN1; BGF Stall - SNP	0,1,2,3	0	null	1
+QPI LL	0x3A	0x4	UNC_Q_RxL_STALLS_VN1.BGF_NCS	Stalls Sending to R3QPI on VN1; BGF Stall - NDR	0,1,2,3	0	null	1
+QPI LL	0x3A	0x8	UNC_Q_RxL_STALLS_VN1.BGF_HOM	Stalls Sending to R3QPI on VN1; BGF Stall - DRS	0,1,2,3	0	null	1
+QPI LL	0x3A	0x10	UNC_Q_RxL_STALLS_VN1.BGF_SNP	Stalls Sending to R3QPI on VN1; BGF Stall - NCB	0,1,2,3	0	null	1
+QPI LL	0x3A	0x20	UNC_Q_RxL_STALLS_VN1.BGF_NDR	Stalls Sending to R3QPI on VN1; BGF Stall - NCS	0,1,2,3	0	null	1
+QPI LL	0xD	0x0	UNC_Q_TxL0P_POWER_CYCLES	Cycles in L0p	0,1,2,3	0	null	0
+QPI LL	0xC	0x0	UNC_Q_TxL0_POWER_CYCLES	Cycles in L0	0,1,2,3	0	null	0
+QPI LL	0x5	0x0	UNC_Q_TxL_BYPASSED	Tx Flit Buffer Bypassed	0,1,2,3	0	null	0
+QPI LL	0x2	0x1	UNC_Q_TxL_CRC_NO_CREDITS.FULL	Cycles Stalled with no LLR Credits; LLR is full	0,1,2,3	0	null	0
+QPI LL	0x2	0x2	UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL	Cycles Stalled with no LLR Credits; LLR is almost full	0,1,2,3	0	null	0
+QPI LL	0x6	0x0	UNC_Q_TxL_CYCLES_NE	Tx Flit Buffer Cycles not Empty	0,1,2,3	0	null	0
+QPI LL	0x0	0x2	UNC_Q_TxL_FLITS_G0.DATA	Flits Transferred - Group 0; Data Tx Flits	0,1,2,3	0	null	0
+QPI LL	0x0	0x4	UNC_Q_TxL_FLITS_G0.NON_DATA	Flits Transferred - Group 0; Non-Data protocol Tx Flits	0,1,2,3	0	null	0
+QPI LL	0x0	0x1	UNC_Q_TxL_FLITS_G1.SNP	Flits Transferred - Group 1; SNP Flits	0,1,2,3	0	null	1
+QPI LL	0x0	0x2	UNC_Q_TxL_FLITS_G1.HOM_REQ	Flits Transferred - Group 1; HOM Request Flits	0,1,2,3	0	null	1
+QPI LL	0x0	0x4	UNC_Q_TxL_FLITS_G1.HOM_NONREQ	Flits Transferred - Group 1; HOM Non-Request Flits	0,1,2,3	0	null	1
+QPI LL	0x0	0x6	UNC_Q_TxL_FLITS_G1.HOM	Flits Transferred - Group 1; HOM Flits	0,1,2,3	0	null	1
+QPI LL	0x0	0x8	UNC_Q_TxL_FLITS_G1.DRS_DATA	Flits Transferred - Group 1; DRS Data Flits	0,1,2,3	0	null	1
+QPI LL	0x0	0x10	UNC_Q_TxL_FLITS_G1.DRS_NONDATA	Flits Transferred - Group 1; DRS Header Flits	0,1,2,3	0	null	1
+QPI LL	0x0	0x18	UNC_Q_TxL_FLITS_G1.DRS	Flits Transferred - Group 1; DRS Flits (both Header and Data)	0,1,2,3	0	null	1
+QPI LL	0x1	0x1	UNC_Q_TxL_FLITS_G2.NDR_AD	Flits Transferred - Group 2; Non-Data Response Tx Flits - AD	0,1,2,3	0	null	1
+QPI LL	0x1	0x2	UNC_Q_TxL_FLITS_G2.NDR_AK	Flits Transferred - Group 2; Non-Data Response Tx Flits - AK	0,1,2,3	0	null	1
+QPI LL	0x1	0x4	UNC_Q_TxL_FLITS_G2.NCB_DATA	Flits Transferred - Group 2; Non-Coherent data Tx Flits	0,1,2,3	0	null	1
+QPI LL	0x1	0x8	UNC_Q_TxL_FLITS_G2.NCB_NONDATA	Flits Transferred - Group 2; Non-Coherent non-data Tx Flits	0,1,2,3	0	null	1
+QPI LL	0x1	0xC	UNC_Q_TxL_FLITS_G2.NCB	Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits	0,1,2,3	0	null	1
+QPI LL	0x1	0x10	UNC_Q_TxL_FLITS_G2.NCS	Flits Transferred - Group 2; Non-Coherent standard Tx Flits	0,1,2,3	0	null	1
+QPI LL	0x4	0x0	UNC_Q_TxL_INSERTS	Tx Flit Buffer Allocations	0,1,2,3	0	null	0
+QPI LL	0x7	0x0	UNC_Q_TxL_OCCUPANCY	Tx Flit Buffer Occupancy	0,1,2,3	0	null	0
+QPI LL	0x26	0x1	UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0	R3QPI Egress Credit Occupancy - HOM; for VN0	0,1,2,3	0	null	1
+QPI LL	0x26	0x2	UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1	R3QPI Egress Credit Occupancy - HOM; for VN1	0,1,2,3	0	null	1
+QPI LL	0x22	0x1	UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0	R3QPI Egress Credit Occupancy - AD HOM; for VN0	0,1,2,3	0	null	1
+QPI LL	0x22	0x2	UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1	R3QPI Egress Credit Occupancy - AD HOM; for VN1	0,1,2,3	0	null	1
+QPI LL	0x28	0x1	UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0	R3QPI Egress Credit Occupancy - AD NDR; for VN0	0,1,2,3	0	null	1
+QPI LL	0x28	0x2	UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1	R3QPI Egress Credit Occupancy - AD NDR; for VN1	0,1,2,3	0	null	1
+QPI LL	0x24	0x1	UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0	R3QPI Egress Credit Occupancy - AD NDR; for VN0	0,1,2,3	0	null	1
+QPI LL	0x24	0x2	UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1	R3QPI Egress Credit Occupancy - AD NDR; for VN1	0,1,2,3	0	null	1
+QPI LL	0x27	0x1	UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0	R3QPI Egress Credit Occupancy - SNP; for VN0	0,1,2,3	0	null	1
+QPI LL	0x27	0x2	UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1	R3QPI Egress Credit Occupancy - SNP; for VN1	0,1,2,3	0	null	1
+QPI LL	0x23	0x1	UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0	R3QPI Egress Credit Occupancy - AD SNP; for VN0	0,1,2,3	0	null	1
+QPI LL	0x23	0x2	UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1	R3QPI Egress Credit Occupancy - AD SNP; for VN1	0,1,2,3	0	null	1
+QPI LL	0x29	0x0	UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED	R3QPI Egress Credit Occupancy - AK NDR	0,1,2,3	0	null	1
+QPI LL	0x25	0x0	UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY	R3QPI Egress Credit Occupancy - AK NDR	0,1,2,3	0	null	1
+QPI LL	0x2A	0x1	UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0	R3QPI Egress Credit Occupancy - DRS; for VN0	0,1,2,3	0	null	1
+QPI LL	0x2A	0x2	UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1	R3QPI Egress Credit Occupancy - DRS; for VN1	0,1,2,3	0	null	1
+QPI LL	0x2A	0x4	UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR	R3QPI Egress Credit Occupancy - DRS; for Shared VN	0,1,2,3	0	null	1
+QPI LL	0x1F	0x1	UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0	R3QPI Egress Credit Occupancy - BL DRS; for VN0	0,1,2,3	0	null	1
+QPI LL	0x1F	0x2	UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1	R3QPI Egress Credit Occupancy - BL DRS; for VN1	0,1,2,3	0	null	1
+QPI LL	0x1F	0x4	UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR	R3QPI Egress Credit Occupancy - BL DRS; for Shared VN	0,1,2,3	0	null	1
+QPI LL	0x2B	0x1	UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0	R3QPI Egress Credit Occupancy - NCB; for VN0	0,1,2,3	0	null	1
+QPI LL	0x2B	0x2	UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1	R3QPI Egress Credit Occupancy - NCB; for VN1	0,1,2,3	0	null	1
+QPI LL	0x20	0x1	UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0	R3QPI Egress Credit Occupancy - BL NCB; for VN0	0,1,2,3	0	null	1
+QPI LL	0x20	0x2	UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1	R3QPI Egress Credit Occupancy - BL NCB; for VN1	0,1,2,3	0	null	1
+QPI LL	0x2C	0x1	UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0	R3QPI Egress Credit Occupancy - NCS; for VN0	0,1,2,3	0	null	1
+QPI LL	0x2C	0x2	UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1	R3QPI Egress Credit Occupancy - NCS; for VN1	0,1,2,3	0	null	1
+QPI LL	0x21	0x1	UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0	R3QPI Egress Credit Occupancy - BL NCS; for VN0	0,1,2,3	0	null	1
+QPI LL	0x21	0x2	UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1	R3QPI Egress Credit Occupancy - BL NCS; for VN1	0,1,2,3	0	null	1
+QPI LL	0x1C	0x0	UNC_Q_VNA_CREDIT_RETURNS	VNA Credits Returned	0,1,2,3	0	null	1
+QPI LL	0x1B	0x0	UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY	VNA Credits Pending Return - Occupancy	0,1,2,3	0	null	1
+R2PCIe	0x1	0x0	UNC_R2_CLOCKTICKS	Number of uclks in domain	0,1,2,3	0	null	0
+R2PCIe	0x2D	0x1	UNC_R2_IIO_CREDIT.PRQ_QPI0	tbd	0,1	0	null	0
+R2PCIe	0x2D	0x2	UNC_R2_IIO_CREDIT.PRQ_QPI1	tbd	0,1	0	null	0
+R2PCIe	0x2D	0x4	UNC_R2_IIO_CREDIT.ISOCH_QPI0	tbd	0,1	0	null	0
+R2PCIe	0x2D	0x8	UNC_R2_IIO_CREDIT.ISOCH_QPI1	tbd	0,1	0	null	0
+R2PCIe	0x33	0x8	UNC_R2_IIO_CREDITS_ACQUIRED.DRS	R2PCIe IIO Credit Acquired; DRS	0,1	0	null	0
+R2PCIe	0x33	0x10	UNC_R2_IIO_CREDITS_ACQUIRED.NCB	R2PCIe IIO Credit Acquired; NCB	0,1	0	null	0
+R2PCIe	0x33	0x20	UNC_R2_IIO_CREDITS_ACQUIRED.NCS	R2PCIe IIO Credit Acquired; NCS	0,1	0	null	0
+R2PCIe	0x32	0x8	UNC_R2_IIO_CREDITS_USED.DRS	R2PCIe IIO Credits in Use; DRS	0,1	0	null	0
+R2PCIe	0x32	0x10	UNC_R2_IIO_CREDITS_USED.NCB	R2PCIe IIO Credits in Use; NCB	0,1	0	null	0
+R2PCIe	0x32	0x20	UNC_R2_IIO_CREDITS_USED.NCS	R2PCIe IIO Credits in Use; NCS	0,1	0	null	0
+R2PCIe	0x7	0x1	UNC_R2_RING_AD_USED.CW_EVEN	R2 AD Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x7	0x2	UNC_R2_RING_AD_USED.CW_ODD	R2 AD Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x7	0x4	UNC_R2_RING_AD_USED.CCW_EVEN	R2 AD Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x7	0x8	UNC_R2_RING_AD_USED.CCW_ODD	R2 AD Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x7	0x3	UNC_R2_RING_AD_USED.CW	R2 AD Ring in Use; Clockwise	0,1,2,3	0	null	0
+R2PCIe	0x7	0xC	UNC_R2_RING_AD_USED.CCW	R2 AD Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+R2PCIe	0x12	0x1	UNC_R2_RING_AK_BOUNCES.UP	AK Ingress Bounced; Up	0,1,2,3	0	null	0
+R2PCIe	0x12	0x2	UNC_R2_RING_AK_BOUNCES.DN	AK Ingress Bounced; Dn	0,1,2,3	0	null	0
+R2PCIe	0x8	0x1	UNC_R2_RING_AK_USED.CW_EVEN	R2 AK Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x8	0x2	UNC_R2_RING_AK_USED.CW_ODD	R2 AK Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x8	0x4	UNC_R2_RING_AK_USED.CCW_EVEN	R2 AK Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x8	0x8	UNC_R2_RING_AK_USED.CCW_ODD	R2 AK Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x8	0x3	UNC_R2_RING_AK_USED.CW	R2 AK Ring in Use; Clockwise	0,1,2,3	0	null	0
+R2PCIe	0x8	0xC	UNC_R2_RING_AK_USED.CCW	R2 AK Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+R2PCIe	0x9	0x1	UNC_R2_RING_BL_USED.CW_EVEN	R2 BL Ring in Use; Clockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x9	0x2	UNC_R2_RING_BL_USED.CW_ODD	R2 BL Ring in Use; Clockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x9	0x4	UNC_R2_RING_BL_USED.CCW_EVEN	R2 BL Ring in Use; Counterclockwise and Even	0,1,2,3	0	null	0
+R2PCIe	0x9	0x8	UNC_R2_RING_BL_USED.CCW_ODD	R2 BL Ring in Use; Counterclockwise and Odd	0,1,2,3	0	null	0
+R2PCIe	0x9	0x3	UNC_R2_RING_BL_USED.CW	R2 BL Ring in Use; Clockwise	0,1,2,3	0	null	0
+R2PCIe	0x9	0xC	UNC_R2_RING_BL_USED.CCW	R2 BL Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+R2PCIe	0xA	0x3	UNC_R2_RING_IV_USED.CW	R2 IV Ring in Use; Clockwise	0,1,2,3	0	null	0
+R2PCIe	0xA	0xC	UNC_R2_RING_IV_USED.CCW	R2 IV Ring in Use; Counterclockwise	0,1,2,3	0	null	0
+R2PCIe	0xA	0xF	UNC_R2_RING_IV_USED.ANY	R2 IV Ring in Use; Any	0,1,2,3	0	null	0
+R2PCIe	0x10	0x10	UNC_R2_RxR_CYCLES_NE.NCB	Ingress Cycles Not Empty; NCB	0,1	0	null	0
+R2PCIe	0x10	0x20	UNC_R2_RxR_CYCLES_NE.NCS	Ingress Cycles Not Empty; NCS	0,1	0	null	0
+R2PCIe	0x11	0x10	UNC_R2_RxR_INSERTS.NCB	Ingress Allocations; NCB	0,1	0	null	0
+R2PCIe	0x11	0x20	UNC_R2_RxR_INSERTS.NCS	Ingress Allocations; NCS	0,1	0	null	0
+R2PCIe	0x13	0x8	UNC_R2_RxR_OCCUPANCY.DRS	Ingress Occupancy Accumulator; DRS	0	0	null	0
+R2PCIe	0x28	0x1	UNC_R2_SBO0_CREDITS_ACQUIRED.AD	SBo0 Credits Acquired; For AD Ring	0,1	0	null	0
+R2PCIe	0x28	0x2	UNC_R2_SBO0_CREDITS_ACQUIRED.BL	SBo0 Credits Acquired; For BL Ring	0,1	0	null	0
+R2PCIe	0x2A	0x1	UNC_R2_SBO0_CREDIT_OCCUPANCY.AD	SBo0 Credits Occupancy; For AD Ring	0	0	null	0
+R2PCIe	0x2A	0x2	UNC_R2_SBO0_CREDIT_OCCUPANCY.BL	SBo0 Credits Occupancy; For BL Ring	0	0	null	0
+R2PCIe	0x2C	0x1	UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD	Stall on No Sbo Credits; For SBo0, AD Ring	0,1	0	null	0
+R2PCIe	0x2C	0x2	UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD	Stall on No Sbo Credits; For SBo1, AD Ring	0,1	0	null	0
+R2PCIe	0x2C	0x4	UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL	Stall on No Sbo Credits; For SBo0, BL Ring	0,1	0	null	0
+R2PCIe	0x2C	0x8	UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL	Stall on No Sbo Credits; For SBo1, BL Ring	0,1	0	null	0
+R2PCIe	0x25	0x1	UNC_R2_TxR_CYCLES_FULL.AD	Egress Cycles Full; AD	0	0	null	0
+R2PCIe	0x25	0x2	UNC_R2_TxR_CYCLES_FULL.AK	Egress Cycles Full; AK	0	0	null	0
+R2PCIe	0x25	0x4	UNC_R2_TxR_CYCLES_FULL.BL	Egress Cycles Full; BL	0	0	null	0
+R2PCIe	0x23	0x1	UNC_R2_TxR_CYCLES_NE.AD	Egress Cycles Not Empty; AD	0	0	null	0
+R2PCIe	0x23	0x2	UNC_R2_TxR_CYCLES_NE.AK	Egress Cycles Not Empty; AK	0	0	null	0
+R2PCIe	0x23	0x4	UNC_R2_TxR_CYCLES_NE.BL	Egress Cycles Not Empty; BL	0	0	null	0
+R2PCIe	0x26	0x1	UNC_R2_TxR_NACK_CW.DN_AD	Egress CCW NACK; AD CCW	0,1	0	null	0
+R2PCIe	0x26	0x2	UNC_R2_TxR_NACK_CW.DN_BL	Egress CCW NACK; BL CCW	0,1	0	null	0
+R2PCIe	0x26	0x4	UNC_R2_TxR_NACK_CW.DN_AK	Egress CCW NACK; AK CCW	0,1	0	null	0
+R2PCIe	0x26	0x8	UNC_R2_TxR_NACK_CW.UP_AD	Egress CCW NACK; AK CCW	0,1	0	null	0
+R2PCIe	0x26	0x10	UNC_R2_TxR_NACK_CW.UP_BL	Egress CCW NACK; BL CCW	0,1	0	null	0
+R2PCIe	0x26	0x20	UNC_R2_TxR_NACK_CW.UP_AK	Egress CCW NACK; BL CW	0,1	0	null	0
+R3QPI	0x1	0x0	UNC_R3_CLOCKTICKS	Number of uclks in domain	0,1,2	0	null	0
+R3QPI	0x1F	0x1	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x1F	0x2	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x1F	0x4	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x1F	0x8	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x1F	0x10	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x1F	0x20	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x1F	0x40	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x1F	0x80	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x22	0x1	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x22	0x2	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x22	0x4	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x22	0x8	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x22	0x10	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x22	0x20	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x22	0x40	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x22	0x80	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7	CBox AD Credits Empty	0,1	0	null	0
+R3QPI	0x2D	0x1	UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0	HA/R2 AD Credits Empty	0,1	0	null	0
+R3QPI	0x2D	0x2	UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1	HA/R2 AD Credits Empty	0,1	0	null	0
+R3QPI	0x2D	0x4	UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB	HA/R2 AD Credits Empty	0,1	0	null	0
+R3QPI	0x2D	0x8	UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS	HA/R2 AD Credits Empty	0,1	0	null	0
+R3QPI	0xB	0x1	UNC_R3_IOT_BACKPRESSURE.SAT	IOT Backpressure	0,1,2	0	null	0
+R3QPI	0xB	0x2	UNC_R3_IOT_BACKPRESSURE.HUB	IOT Backpressure	0,1,2	0	null	0
+R3QPI	0xD	0x1	UNC_R3_IOT_CTS_HI.CTS2	IOT Common Trigger Sequencer - Hi	0,1,2	0	null	0
+R3QPI	0xD	0x2	UNC_R3_IOT_CTS_HI.CTS3	IOT Common Trigger Sequencer - Hi	0,1,2	0	null	0
+R3QPI	0xC	0x1	UNC_R3_IOT_CTS_LO.CTS0	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+R3QPI	0xC	0x2	UNC_R3_IOT_CTS_LO.CTS1	IOT Common Trigger Sequencer - Lo	0,1,2	0	null	0
+R3QPI	0x20	0x1	UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA	QPI0 AD Credits Empty	0,1	0	null	0
+R3QPI	0x20	0x2	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM	QPI0 AD Credits Empty	0,1	0	null	0
+R3QPI	0x20	0x4	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP	QPI0 AD Credits Empty	0,1	0	null	0
+R3QPI	0x20	0x8	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR	QPI0 AD Credits Empty	0,1	0	null	0
+R3QPI	0x20	0x10	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM	QPI0 AD Credits Empty	0,1	0	null	0
+R3QPI	0x20	0x20	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP	QPI0 AD Credits Empty	0,1	0	null	0
+R3QPI	0x20	0x40	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR	QPI0 AD Credits Empty	0,1	0	null	0
+R3QPI	0x21	0x1	UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA	QPI0 BL Credits Empty	0,1	0	null	0
+R3QPI	0x21	0x10	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM	QPI0 BL Credits Empty	0,1	0	null	0
+R3QPI	0x21	0x20	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP	QPI0 BL Credits Empty	0,1	0	null	0
+R3QPI	0x21	0x40	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR	QPI0 BL Credits Empty	0,1	0	null	0
+R3QPI	0x2E	0x1	UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA	QPI1 AD Credits Empty	0,1	0	null	0
+R3QPI	0x2E	0x10	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM	QPI1 AD Credits Empty	0,1	0	null	0
+R3QPI	0x2E	0x20	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP	QPI1 AD Credits Empty	0,1	0	null	0
+R3QPI	0x2E	0x40	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR	QPI1 AD Credits Empty	0,1	0	null	0
+R3QPI	0x2F	0x1	UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA	QPI1 BL Credits Empty	0,1	0	null	0
+R3QPI	0x2F	0x2	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM	QPI1 BL Credits Empty	0,1	0	null	0
+R3QPI	0x2F	0x4	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP	QPI1 BL Credits Empty	0,1	0	null	0
+R3QPI	0x2F	0x8	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR	QPI1 BL Credits Empty	0,1	0	null	0
+R3QPI	0x2F	0x10	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM	QPI1 BL Credits Empty	0,1	0	null	0
+R3QPI	0x2F	0x20	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP	QPI1 BL Credits Empty	0,1	0	null	0
+R3QPI	0x2F	0x40	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR	QPI1 BL Credits Empty	0,1	0	null	0
+R3QPI	0x7	0x1	UNC_R3_RING_AD_USED.CW_EVEN	R3 AD Ring in Use; Clockwise and Even	0,1,2	0	null	0
+R3QPI	0x7	0x2	UNC_R3_RING_AD_USED.CW_ODD	R3 AD Ring in Use; Clockwise and Odd	0,1,2	0	null	0
+R3QPI	0x7	0x4	UNC_R3_RING_AD_USED.CCW_EVEN	R3 AD Ring in Use; Counterclockwise and Even	0,1,2	0	null	0
+R3QPI	0x7	0x8	UNC_R3_RING_AD_USED.CCW_ODD	R3 AD Ring in Use; Counterclockwise and Odd	0,1,2	0	null	0
+R3QPI	0x7	0x3	UNC_R3_RING_AD_USED.CW	R3 AD Ring in Use; Clockwise	0,1,2	0	null	0
+R3QPI	0x7	0xC	UNC_R3_RING_AD_USED.CCW	R3 AD Ring in Use; Counterclockwise	0,1,2	0	null	0
+R3QPI	0x8	0x1	UNC_R3_RING_AK_USED.CW_EVEN	R3 AK Ring in Use; Clockwise and Even	0,1,2	0	null	0
+R3QPI	0x8	0x2	UNC_R3_RING_AK_USED.CW_ODD	R3 AK Ring in Use; Clockwise and Odd	0,1,2	0	null	0
+R3QPI	0x8	0x4	UNC_R3_RING_AK_USED.CCW_EVEN	R3 AK Ring in Use; Counterclockwise and Even	0,1,2	0	null	0
+R3QPI	0x8	0x8	UNC_R3_RING_AK_USED.CCW_ODD	R3 AK Ring in Use; Counterclockwise and Odd	0,1,2	0	null	0
+R3QPI	0x8	0x3	UNC_R3_RING_AK_USED.CW	R3 AK Ring in Use; Clockwise	0,1,2	0	null	0
+R3QPI	0x8	0xC	UNC_R3_RING_AK_USED.CCW	R3 AK Ring in Use; Counterclockwise	0,1,2	0	null	0
+R3QPI	0x9	0x1	UNC_R3_RING_BL_USED.CW_EVEN	R3 BL Ring in Use; Clockwise and Even	0,1,2	0	null	0
+R3QPI	0x9	0x2	UNC_R3_RING_BL_USED.CW_ODD	R3 BL Ring in Use; Clockwise and Odd	0,1,2	0	null	0
+R3QPI	0x9	0x4	UNC_R3_RING_BL_USED.CCW_EVEN	R3 BL Ring in Use; Counterclockwise and Even	0,1,2	0	null	0
+R3QPI	0x9	0x8	UNC_R3_RING_BL_USED.CCW_ODD	R3 BL Ring in Use; Counterclockwise and Odd	0,1,2	0	null	0
+R3QPI	0x9	0x3	UNC_R3_RING_BL_USED.CW	R3 BL Ring in Use; Clockwise	0,1,2	0	null	0
+R3QPI	0x9	0xC	UNC_R3_RING_BL_USED.CCW	R3 BL Ring in Use; Counterclockwise	0,1,2	0	null	0
+R3QPI	0xA	0x3	UNC_R3_RING_IV_USED.CW	R3 IV Ring in Use; Clockwise	0,1,2	0	null	0
+R3QPI	0xA	0xF	UNC_R3_RING_IV_USED.ANY	R3 IV Ring in Use; Any	0,1,2	0	null	0
+R3QPI	0xE	0x2	UNC_R3_RING_SINK_STARVED.AK	Ring Stop Starved; AK	0,1,2	0	null	0
+R3QPI	0x10	0x1	UNC_R3_RxR_CYCLES_NE.HOM	Ingress Cycles Not Empty; HOM	0,1	0	null	0
+R3QPI	0x10	0x2	UNC_R3_RxR_CYCLES_NE.SNP	Ingress Cycles Not Empty; SNP	0,1	0	null	0
+R3QPI	0x10	0x4	UNC_R3_RxR_CYCLES_NE.NDR	Ingress Cycles Not Empty; NDR	0,1	0	null	0
+R3QPI	0x14	0x1	UNC_R3_RxR_CYCLES_NE_VN1.HOM	VN1 Ingress Cycles Not Empty; HOM	0,1	0	null	0
+R3QPI	0x14	0x2	UNC_R3_RxR_CYCLES_NE_VN1.SNP	VN1 Ingress Cycles Not Empty; SNP	0,1	0	null	0
+R3QPI	0x14	0x4	UNC_R3_RxR_CYCLES_NE_VN1.NDR	VN1 Ingress Cycles Not Empty; NDR	0,1	0	null	0
+R3QPI	0x14	0x8	UNC_R3_RxR_CYCLES_NE_VN1.DRS	VN1 Ingress Cycles Not Empty; DRS	0,1	0	null	0
+R3QPI	0x14	0x10	UNC_R3_RxR_CYCLES_NE_VN1.NCB	VN1 Ingress Cycles Not Empty; NCB	0,1	0	null	0
+R3QPI	0x14	0x20	UNC_R3_RxR_CYCLES_NE_VN1.NCS	VN1 Ingress Cycles Not Empty; NCS	0,1	0	null	0
+R3QPI	0x11	0x1	UNC_R3_RxR_INSERTS.HOM	Ingress Allocations; HOM	0,1	0	null	0
+R3QPI	0x11	0x2	UNC_R3_RxR_INSERTS.SNP	Ingress Allocations; SNP	0,1	0	null	0
+R3QPI	0x11	0x4	UNC_R3_RxR_INSERTS.NDR	Ingress Allocations; NDR	0,1	0	null	0
+R3QPI	0x11	0x8	UNC_R3_RxR_INSERTS.DRS	Ingress Allocations; DRS	0,1	0	null	0
+R3QPI	0x11	0x10	UNC_R3_RxR_INSERTS.NCB	Ingress Allocations; NCB	0,1	0	null	0
+R3QPI	0x11	0x20	UNC_R3_RxR_INSERTS.NCS	Ingress Allocations; NCS	0,1	0	null	0
+R3QPI	0x15	0x1	UNC_R3_RxR_INSERTS_VN1.HOM	VN1 Ingress Allocations; HOM	0,1	0	null	0
+R3QPI	0x15	0x2	UNC_R3_RxR_INSERTS_VN1.SNP	VN1 Ingress Allocations; SNP	0,1	0	null	0
+R3QPI	0x15	0x4	UNC_R3_RxR_INSERTS_VN1.NDR	VN1 Ingress Allocations; NDR	0,1	0	null	0
+R3QPI	0x15	0x8	UNC_R3_RxR_INSERTS_VN1.DRS	VN1 Ingress Allocations; DRS	0,1	0	null	0
+R3QPI	0x15	0x10	UNC_R3_RxR_INSERTS_VN1.NCB	VN1 Ingress Allocations; NCB	0,1	0	null	0
+R3QPI	0x15	0x20	UNC_R3_RxR_INSERTS_VN1.NCS	VN1 Ingress Allocations; NCS	0,1	0	null	0
+R3QPI	0x13	0x1	UNC_R3_RxR_OCCUPANCY_VN1.HOM	VN1 Ingress Occupancy Accumulator; HOM	0	0	null	0
+R3QPI	0x13	0x2	UNC_R3_RxR_OCCUPANCY_VN1.SNP	VN1 Ingress Occupancy Accumulator; SNP	0	0	null	0
+R3QPI	0x13	0x4	UNC_R3_RxR_OCCUPANCY_VN1.NDR	VN1 Ingress Occupancy Accumulator; NDR	0	0	null	0
+R3QPI	0x13	0x8	UNC_R3_RxR_OCCUPANCY_VN1.DRS	VN1 Ingress Occupancy Accumulator; DRS	0	0	null	0
+R3QPI	0x13	0x10	UNC_R3_RxR_OCCUPANCY_VN1.NCB	VN1 Ingress Occupancy Accumulator; NCB	0	0	null	0
+R3QPI	0x13	0x20	UNC_R3_RxR_OCCUPANCY_VN1.NCS	VN1 Ingress Occupancy Accumulator; NCS	0	0	null	0
+R3QPI	0x28	0x1	UNC_R3_SBO0_CREDITS_ACQUIRED.AD	SBo0 Credits Acquired; For AD Ring	0,1	0	null	0
+R3QPI	0x28	0x2	UNC_R3_SBO0_CREDITS_ACQUIRED.BL	SBo0 Credits Acquired; For BL Ring	0,1	0	null	0
+R3QPI	0x2A	0x1	UNC_R3_SBO0_CREDIT_OCCUPANCY.AD	SBo0 Credits Occupancy; For AD Ring	0	0	null	0
+R3QPI	0x2A	0x2	UNC_R3_SBO0_CREDIT_OCCUPANCY.BL	SBo0 Credits Occupancy; For BL Ring	0	0	null	0
+R3QPI	0x29	0x1	UNC_R3_SBO1_CREDITS_ACQUIRED.AD	SBo1 Credits Acquired; For AD Ring	0,1	0	null	0
+R3QPI	0x29	0x2	UNC_R3_SBO1_CREDITS_ACQUIRED.BL	SBo1 Credits Acquired; For BL Ring	0,1	0	null	0
+R3QPI	0x2B	0x1	UNC_R3_SBO1_CREDIT_OCCUPANCY.AD	SBo1 Credits Occupancy; For AD Ring	0	0	null	0
+R3QPI	0x2B	0x2	UNC_R3_SBO1_CREDIT_OCCUPANCY.BL	SBo1 Credits Occupancy; For BL Ring	0	0	null	0
+R3QPI	0x2C	0x1	UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD	Stall on No Sbo Credits; For SBo0, AD Ring	0,1	0	null	0
+R3QPI	0x2C	0x2	UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD	Stall on No Sbo Credits; For SBo1, AD Ring	0,1	0	null	0
+R3QPI	0x2C	0x4	UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL	Stall on No Sbo Credits; For SBo0, BL Ring	0,1	0	null	0
+R3QPI	0x2C	0x8	UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL	Stall on No Sbo Credits; For SBo1, BL Ring	0,1	0	null	0
+R3QPI	0x26	0x1	UNC_R3_TxR_NACK.DN_AD	Egress CCW NACK; AD CCW	0,1	0	null	0
+R3QPI	0x26	0x2	UNC_R3_TxR_NACK.DN_BL	Egress CCW NACK; BL CCW	0,1	0	null	0
+R3QPI	0x26	0x4	UNC_R3_TxR_NACK.DN_AK	Egress CCW NACK; AK CCW	0,1	0	null	0
+R3QPI	0x26	0x8	UNC_R3_TxR_NACK.UP_AD	Egress CCW NACK; AK CCW	0,1	0	null	0
+R3QPI	0x26	0x10	UNC_R3_TxR_NACK.UP_BL	Egress CCW NACK; BL CCW	0,1	0	null	0
+R3QPI	0x26	0x20	UNC_R3_TxR_NACK.UP_AK	Egress CCW NACK; BL CW	0,1	0	null	0
+R3QPI	0x37	0x1	UNC_R3_VN0_CREDITS_REJECT.HOM	VN0 Credit Acquisition Failed on DRS; HOM Message Class	0,1	0	null	0
+R3QPI	0x37	0x2	UNC_R3_VN0_CREDITS_REJECT.SNP	VN0 Credit Acquisition Failed on DRS; SNP Message Class	0,1	0	null	0
+R3QPI	0x37	0x4	UNC_R3_VN0_CREDITS_REJECT.NDR	VN0 Credit Acquisition Failed on DRS; NDR Message Class	0,1	0	null	0
+R3QPI	0x37	0x8	UNC_R3_VN0_CREDITS_REJECT.DRS	VN0 Credit Acquisition Failed on DRS; DRS Message Class	0,1	0	null	0
+R3QPI	0x37	0x10	UNC_R3_VN0_CREDITS_REJECT.NCB	VN0 Credit Acquisition Failed on DRS; NCB Message Class	0,1	0	null	0
+R3QPI	0x37	0x20	UNC_R3_VN0_CREDITS_REJECT.NCS	VN0 Credit Acquisition Failed on DRS; NCS Message Class	0,1	0	null	0
+R3QPI	0x36	0x1	UNC_R3_VN0_CREDITS_USED.HOM	VN0 Credit Used; HOM Message Class	0,1	0	null	0
+R3QPI	0x36	0x2	UNC_R3_VN0_CREDITS_USED.SNP	VN0 Credit Used; SNP Message Class	0,1	0	null	0
+R3QPI	0x36	0x4	UNC_R3_VN0_CREDITS_USED.NDR	VN0 Credit Used; NDR Message Class	0,1	0	null	0
+R3QPI	0x36	0x8	UNC_R3_VN0_CREDITS_USED.DRS	VN0 Credit Used; DRS Message Class	0,1	0	null	0
+R3QPI	0x36	0x10	UNC_R3_VN0_CREDITS_USED.NCB	VN0 Credit Used; NCB Message Class	0,1	0	null	0
+R3QPI	0x36	0x20	UNC_R3_VN0_CREDITS_USED.NCS	VN0 Credit Used; NCS Message Class	0,1	0	null	0
+R3QPI	0x39	0x1	UNC_R3_VN1_CREDITS_REJECT.HOM	VN1 Credit Acquisition Failed on DRS; HOM Message Class	0,1	0	null	0
+R3QPI	0x39	0x2	UNC_R3_VN1_CREDITS_REJECT.SNP	VN1 Credit Acquisition Failed on DRS; SNP Message Class	0,1	0	null	0
+R3QPI	0x39	0x4	UNC_R3_VN1_CREDITS_REJECT.NDR	VN1 Credit Acquisition Failed on DRS; NDR Message Class	0,1	0	null	0
+R3QPI	0x39	0x8	UNC_R3_VN1_CREDITS_REJECT.DRS	VN1 Credit Acquisition Failed on DRS; DRS Message Class	0,1	0	null	0
+R3QPI	0x39	0x10	UNC_R3_VN1_CREDITS_REJECT.NCB	VN1 Credit Acquisition Failed on DRS; NCB Message Class	0,1	0	null	0
+R3QPI	0x39	0x20	UNC_R3_VN1_CREDITS_REJECT.NCS	VN1 Credit Acquisition Failed on DRS; NCS Message Class	0,1	0	null	0
+R3QPI	0x38	0x1	UNC_R3_VN1_CREDITS_USED.HOM	VN1 Credit Used; HOM Message Class	0,1	0	null	0
+R3QPI	0x38	0x2	UNC_R3_VN1_CREDITS_USED.SNP	VN1 Credit Used; SNP Message Class	0,1	0	null	0
+R3QPI	0x38	0x4	UNC_R3_VN1_CREDITS_USED.NDR	VN1 Credit Used; NDR Message Class	0,1	0	null	0
+R3QPI	0x38	0x8	UNC_R3_VN1_CREDITS_USED.DRS	VN1 Credit Used; DRS Message Class	0,1	0	null	0
+R3QPI	0x38	0x10	UNC_R3_VN1_CREDITS_USED.NCB	VN1 Credit Used; NCB Message Class	0,1	0	null	0
+R3QPI	0x38	0x20	UNC_R3_VN1_CREDITS_USED.NCS	VN1 Credit Used; NCS Message Class	0,1	0	null	0
+R3QPI	0x33	0x1	UNC_R3_VNA_CREDITS_ACQUIRED.AD	VNA credit Acquisitions; HOM Message Class	0,1	0	null	0
+R3QPI	0x33	0x4	UNC_R3_VNA_CREDITS_ACQUIRED.BL	VNA credit Acquisitions; HOM Message Class	0,1	0	null	0
+R3QPI	0x34	0x1	UNC_R3_VNA_CREDITS_REJECT.HOM	VNA Credit Reject; HOM Message Class	0,1	0	null	0
+R3QPI	0x34	0x2	UNC_R3_VNA_CREDITS_REJECT.SNP	VNA Credit Reject; SNP Message Class	0,1	0	null	0
+R3QPI	0x34	0x4	UNC_R3_VNA_CREDITS_REJECT.NDR	VNA Credit Reject; NDR Message Class	0,1	0	null	0
+R3QPI	0x34	0x8	UNC_R3_VNA_CREDITS_REJECT.DRS	VNA Credit Reject; DRS Message Class	0,1	0	null	0
+R3QPI	0x34	0x10	UNC_R3_VNA_CREDITS_REJECT.NCB	VNA Credit Reject; NCB Message Class	0,1	0	null	0
+R3QPI	0x34	0x20	UNC_R3_VNA_CREDITS_REJECT.NCS	VNA Credit Reject; NCS Message Class	0,1	0	null	0
+SBO	0xA	0x0	UNC_S_BOUNCE_CONTROL	Bounce Control	0,1,2,3	0	null	0
+SBO	0x0	0x0	UNC_S_CLOCKTICKS	Uncore Clocks	0,1,2,3	0	null	0
+SBO	0x9	0x0	UNC_S_FAST_ASSERTED	FaST wire asserted	0,1,2,3	0	null	0
+SBO	0x1B	0x1	UNC_S_RING_AD_USED.UP_EVEN	AD Ring In Use; Up and Even	0,1,2,3	0	null	0
+SBO	0x1B	0x2	UNC_S_RING_AD_USED.UP_ODD	AD Ring In Use; Up and Odd	0,1,2,3	0	null	0
+SBO	0x1B	0x4	UNC_S_RING_AD_USED.DOWN_EVEN	AD Ring In Use; Down and Event	0,1,2,3	0	null	0
+SBO	0x1B	0x8	UNC_S_RING_AD_USED.DOWN_ODD	AD Ring In Use; Down and Odd	0,1,2,3	0	null	0
+SBO	0x1B	0x3	UNC_S_RING_AD_USED.UP	AD Ring In Use; Up	0,1,2,3	0	null	0
+SBO	0x1B	0xC	UNC_S_RING_AD_USED.DOWN	AD Ring In Use; Down	0,1,2,3	0	null	0
+SBO	0x1C	0x1	UNC_S_RING_AK_USED.UP_EVEN	AK Ring In Use; Up and Even	0,1,2,3	0	null	0
+SBO	0x1C	0x2	UNC_S_RING_AK_USED.UP_ODD	AK Ring In Use; Up and Odd	0,1,2,3	0	null	0
+SBO	0x1C	0x4	UNC_S_RING_AK_USED.DOWN_EVEN	AK Ring In Use; Down and Event	0,1,2,3	0	null	0
+SBO	0x1C	0x8	UNC_S_RING_AK_USED.DOWN_ODD	AK Ring In Use; Down and Odd	0,1,2,3	0	null	0
+SBO	0x1C	0x3	UNC_S_RING_AK_USED.UP	AK Ring In Use; Up	0,1,2,3	0	null	0
+SBO	0x1C	0xC	UNC_S_RING_AK_USED.DOWN	AK Ring In Use; Down	0,1,2,3	0	null	0
+SBO	0x1D	0x1	UNC_S_RING_BL_USED.UP_EVEN	BL Ring in Use; Up and Even	0,1,2,3	0	null	0
+SBO	0x1D	0x2	UNC_S_RING_BL_USED.UP_ODD	BL Ring in Use; Up and Odd	0,1,2,3	0	null	0
+SBO	0x1D	0x4	UNC_S_RING_BL_USED.DOWN_EVEN	BL Ring in Use; Down and Event	0,1,2,3	0	null	0
+SBO	0x1D	0x8	UNC_S_RING_BL_USED.DOWN_ODD	BL Ring in Use; Down and Odd	0,1,2,3	0	null	0
+SBO	0x1D	0x3	UNC_S_RING_BL_USED.UP	BL Ring in Use; Up	0,1,2,3	0	null	0
+SBO	0x1D	0xC	UNC_S_RING_BL_USED.DOWN	BL Ring in Use; Down	0,1,2,3	0	null	0
+SBO	0x5	0x1	UNC_S_RING_BOUNCES.AD_CACHE	Number of LLC responses that bounced on the Ring.	0,1,2,3	0	null	0
+SBO	0x5	0x2	UNC_S_RING_BOUNCES.AK_CORE	Number of LLC responses that bounced on the Ring.; Acknowledgements to core	0,1,2,3	0	null	0
+SBO	0x5	0x4	UNC_S_RING_BOUNCES.BL_CORE	Number of LLC responses that bounced on the Ring.; Data Responses to core	0,1,2,3	0	null	0
+SBO	0x5	0x8	UNC_S_RING_BOUNCES.IV_CORE	Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.	0,1,2,3	0	null	0
+SBO	0x1E	0x3	UNC_S_RING_IV_USED.UP	BL Ring in Use; Any	0,1,2,3	0	null	0
+SBO	0x1E	0xC	UNC_S_RING_IV_USED.DN	BL Ring in Use; Any	0,1,2,3	0	null	0
+SBO	0x6	0x1	UNC_S_RING_SINK_STARVED.AD_CACHE	tbd	0,1,2,3	0	null	0
+SBO	0x6	0x2	UNC_S_RING_SINK_STARVED.AK_CORE	tbd	0,1,2,3	0	null	0
+SBO	0x6	0x4	UNC_S_RING_SINK_STARVED.BL_CORE	tbd	0,1,2,3	0	null	0
+SBO	0x6	0x8	UNC_S_RING_SINK_STARVED.IV_CORE	tbd	0,1,2,3	0	null	0
+SBO	0x15	0x1	UNC_S_RxR_BUSY_STARVED.AD_CRD	Injection Starvation; AD - Credits	0,1,2,3	0	null	0
+SBO	0x15	0x2	UNC_S_RxR_BUSY_STARVED.AD_BNC	Injection Starvation; AD - Bounces	0,1,2,3	0	null	0
+SBO	0x15	0x4	UNC_S_RxR_BUSY_STARVED.BL_CRD	Injection Starvation; BL - Credits	0,1,2,3	0	null	0
+SBO	0x15	0x8	UNC_S_RxR_BUSY_STARVED.BL_BNC	Injection Starvation; BL - Bounces	0,1,2,3	0	null	0
+SBO	0x12	0x1	UNC_S_RxR_BYPASS.AD_CRD	Bypass; AD - Credits	0,1,2,3	0	null	0
+SBO	0x12	0x2	UNC_S_RxR_BYPASS.AD_BNC	Bypass; AD - Bounces	0,1,2,3	0	null	0
+SBO	0x12	0x4	UNC_S_RxR_BYPASS.BL_CRD	Bypass; BL - Credits	0,1,2,3	0	null	0
+SBO	0x12	0x8	UNC_S_RxR_BYPASS.BL_BNC	Bypass; BL - Bounces	0,1,2,3	0	null	0
+SBO	0x12	0x10	UNC_S_RxR_BYPASS.AK	Bypass; AK	0,1,2,3	0	null	0
+SBO	0x12	0x20	UNC_S_RxR_BYPASS.IV	Bypass; IV	0,1,2,3	0	null	0
+SBO	0x14	0x1	UNC_S_RxR_CRD_STARVED.AD_CRD	Injection Starvation; AD - Credits	0,1,2,3	0	null	0
+SBO	0x14	0x2	UNC_S_RxR_CRD_STARVED.AD_BNC	Injection Starvation; AD - Bounces	0,1,2,3	0	null	0
+SBO	0x14	0x4	UNC_S_RxR_CRD_STARVED.BL_CRD	Injection Starvation; BL - Credits	0,1,2,3	0	null	0
+SBO	0x14	0x8	UNC_S_RxR_CRD_STARVED.BL_BNC	Injection Starvation; BL - Bounces	0,1,2,3	0	null	0
+SBO	0x14	0x10	UNC_S_RxR_CRD_STARVED.AK	Injection Starvation; AK	0,1,2,3	0	null	0
+SBO	0x14	0x20	UNC_S_RxR_CRD_STARVED.IV	Injection Starvation; IV	0,1,2,3	0	null	0
+SBO	0x14	0x40	UNC_S_RxR_CRD_STARVED.IFV	Injection Starvation; IVF Credit	0,1,2,3	0	null	0
+SBO	0x13	0x1	UNC_S_RxR_INSERTS.AD_CRD	Ingress Allocations; AD - Credits	0,1,2,3	0	null	0
+SBO	0x13	0x2	UNC_S_RxR_INSERTS.AD_BNC	Ingress Allocations; AD - Bounces	0,1,2,3	0	null	0
+SBO	0x13	0x4	UNC_S_RxR_INSERTS.BL_CRD	Ingress Allocations; BL - Credits	0,1,2,3	0	null	0
+SBO	0x13	0x8	UNC_S_RxR_INSERTS.BL_BNC	Ingress Allocations; BL - Bounces	0,1,2,3	0	null	0
+SBO	0x13	0x10	UNC_S_RxR_INSERTS.AK	Ingress Allocations; AK	0,1,2,3	0	null	0
+SBO	0x13	0x20	UNC_S_RxR_INSERTS.IV	Ingress Allocations; IV	0,1,2,3	0	null	0
+SBO	0x11	0x1	UNC_S_RxR_OCCUPANCY.AD_CRD	Ingress Occupancy; AD - Credits	0,1,2,3	0	null	0
+SBO	0x11	0x2	UNC_S_RxR_OCCUPANCY.AD_BNC	Ingress Occupancy; AD - Bounces	0,1,2,3	0	null	0
+SBO	0x11	0x4	UNC_S_RxR_OCCUPANCY.BL_CRD	Ingress Occupancy; BL - Credits	0,1,2,3	0	null	0
+SBO	0x11	0x8	UNC_S_RxR_OCCUPANCY.BL_BNC	Ingress Occupancy; BL - Bounces	0,1,2,3	0	null	0
+SBO	0x11	0x10	UNC_S_RxR_OCCUPANCY.AK	Ingress Occupancy; AK	0,1,2,3	0	null	0
+SBO	0x11	0x20	UNC_S_RxR_OCCUPANCY.IV	Ingress Occupancy; IV	0,1,2,3	0	null	0
+SBO	0x4	0x1	UNC_S_TxR_ADS_USED.AD	tbd	0,1,2,3	0	null	0
+SBO	0x4	0x2	UNC_S_TxR_ADS_USED.AK	tbd	0,1,2,3	0	null	0
+SBO	0x4	0x4	UNC_S_TxR_ADS_USED.BL	tbd	0,1,2,3	0	null	0
+SBO	0x2	0x1	UNC_S_TxR_INSERTS.AD_CRD	Egress Allocations; AD - Credits	0,1,2,3	0	null	0
+SBO	0x2	0x2	UNC_S_TxR_INSERTS.AD_BNC	Egress Allocations; AD - Bounces	0,1,2,3	0	null	0
+SBO	0x2	0x4	UNC_S_TxR_INSERTS.BL_CRD	Egress Allocations; BL - Credits	0,1,2,3	0	null	0
+SBO	0x2	0x8	UNC_S_TxR_INSERTS.BL_BNC	Egress Allocations; BL - Bounces	0,1,2,3	0	null	0
+SBO	0x2	0x10	UNC_S_TxR_INSERTS.AK	Egress Allocations; AK	0,1,2,3	0	null	0
+SBO	0x2	0x20	UNC_S_TxR_INSERTS.IV	Egress Allocations; IV	0,1,2,3	0	null	0
+SBO	0x1	0x1	UNC_S_TxR_OCCUPANCY.AD_CRD	Egress Occupancy; AD - Credits	0,1,2,3	0	null	0
+SBO	0x1	0x2	UNC_S_TxR_OCCUPANCY.AD_BNC	Egress Occupancy; AD - Bounces	0,1,2,3	0	null	0
+SBO	0x1	0x4	UNC_S_TxR_OCCUPANCY.BL_CRD	Egress Occupancy; BL - Credits	0,1,2,3	0	null	0
+SBO	0x1	0x8	UNC_S_TxR_OCCUPANCY.BL_BNC	Egress Occupancy; BL - Bounces	0,1,2,3	0	null	0
+SBO	0x1	0x10	UNC_S_TxR_OCCUPANCY.AK	Egress Occupancy; AK	0,1,2,3	0	null	0
+SBO	0x1	0x20	UNC_S_TxR_OCCUPANCY.IV	Egress Occupancy; IV	0,1,2,3	0	null	0
+SBO	0x3	0x1	UNC_S_TxR_STARVED.AD	Injection Starvation; Onto AD Ring	0,1,2,3	0	null	0
+SBO	0x3	0x2	UNC_S_TxR_STARVED.AK	Injection Starvation; Onto AK Ring	0,1,2,3	0	null	0
+SBO	0x3	0x4	UNC_S_TxR_STARVED.BL	Injection Starvation; Onto BL Ring	0,1,2,3	0	null	0
+SBO	0x3	0x8	UNC_S_TxR_STARVED.IV	Injection Starvation; Onto IV Ring	0,1,2,3	0	null	0
+UBOX	0x42	0x8	UNC_U_EVENT_MSG.DOORBELL_RCVD	VLW Received	0,1	0	null	0
+UBOX	0x41	0x1	UNC_U_FILTER_MATCH.ENABLE	Filter Match	0,1	0	UBoxFilter[3:0]	0
+UBOX	0x41	0x2	UNC_U_FILTER_MATCH.DISABLE	Filter Match	0,1	0	null	0
+UBOX	0x41	0x4	UNC_U_FILTER_MATCH.U2C_ENABLE	Filter Match	0,1	0	UBoxFilter[3:0]	0
+UBOX	0x41	0x8	UNC_U_FILTER_MATCH.U2C_DISABLE	Filter Match	0,1	0	null	0
+UBOX	0x45	0x1	UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK	Cycles PHOLD Assert to Ack; Assert to ACK	0,1	0	null	0
+UBOX	0x46	0x0	UNC_U_RACU_REQUESTS	RACU Request	0,1	0	null	0
+UBOX	0x43	0x1	UNC_U_U2C_EVENTS.MONITOR_T0	Monitor Sent to T0; Monitor T0	0,1	0	null	0
+UBOX	0x43	0x2	UNC_U_U2C_EVENTS.MONITOR_T1	Monitor Sent to T0; Monitor T1	0,1	0	null	0
+UBOX	0x43	0x4	UNC_U_U2C_EVENTS.LIVELOCK	Monitor Sent to T0; Livelock	0,1	0	null	0
+UBOX	0x43	0x8	UNC_U_U2C_EVENTS.LTERROR	Monitor Sent to T0; LTError	0,1	0	null	0
+UBOX	0x43	0x10	UNC_U_U2C_EVENTS.CMC	Monitor Sent to T0; Correctable Machine Check	0,1	0	null	0
+UBOX	0x43	0x20	UNC_U_U2C_EVENTS.UMC	Monitor Sent to T0; Uncorrectable Machine Check	0,1	0	null	0
+UBOX	0x43	0x40	UNC_U_U2C_EVENTS.TRAP	Monitor Sent to T0; Trap	0,1	0	null	0
+UBOX	0x43	0x80	UNC_U_U2C_EVENTS.OTHER	Monitor Sent to T0; Other	0,1	0	null	0
+iMC	0x1	0x1	UNC_M_ACT_COUNT.RD	DRAM Activate Count; Activate due to Read	0,1,2,3	0	null	0
+iMC	0x1	0x2	UNC_M_ACT_COUNT.WR	DRAM Activate Count; Activate due to Write	0,1,2,3	0	null	0
+iMC	0x1	0x8	UNC_M_ACT_COUNT.BYP	DRAM Activate Count; Activate due to Write	0,1,2,3	0	null	0
+iMC	0xA1	0x1	UNC_M_BYP_CMDS.ACT	ACT command issued by 2 cycle bypass	0,1,2,3	0	null	0
+iMC	0xA1	0x2	UNC_M_BYP_CMDS.CAS	CAS command issued by 2 cycle bypass	0,1,2,3	0	null	0
+iMC	0xA1	0x4	UNC_M_BYP_CMDS.PRE	PRE command issued by 2 cycle bypass	0,1,2,3	0	null	0
+iMC	0x4	0x1	UNC_M_CAS_COUNT.RD_REG	DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)	0,1,2,3	0	null	0
+iMC	0x4	0x2	UNC_M_CAS_COUNT.RD_UNDERFILL	DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued	0,1,2,3	0	null	0
+iMC	0x4	0x3	UNC_M_CAS_COUNT.RD	DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)	0,1,2,3	0	null	0
+iMC	0x4	0x4	UNC_M_CAS_COUNT.WR_WMM	DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode	0,1,2,3	0	null	0
+iMC	0x4	0x8	UNC_M_CAS_COUNT.WR_RMM	DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode	0,1,2,3	0	null	0
+iMC	0x4	0xC	UNC_M_CAS_COUNT.WR	DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)	0,1,2,3	0	null	0
+iMC	0x4	0xF	UNC_M_CAS_COUNT.ALL	DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)	0,1,2,3	0	null	0
+iMC	0x4	0x10	UNC_M_CAS_COUNT.RD_WMM	DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM	0,1,2,3	0	null	0
+iMC	0x4	0x20	UNC_M_CAS_COUNT.RD_RMM	DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM	0,1,2,3	0	null	0
+iMC	0x0	0x0	UNC_M_CLOCKTICKS	DRAM Clockticks	0,1,2,3	0	null	0
+iMC	0x6	0x0	UNC_M_DRAM_PRE_ALL	DRAM Precharge All Commands	0,1,2,3	0	null	0
+iMC	0x5	0x2	UNC_M_DRAM_REFRESH.PANIC	Number of DRAM Refreshes Issued	0,1,2,3	0	null	0
+iMC	0x5	0x4	UNC_M_DRAM_REFRESH.HIGH	Number of DRAM Refreshes Issued	0,1,2,3	0	null	0
+iMC	0x9	0x0	UNC_M_ECC_CORRECTABLE_ERRORS	ECC Correctable Errors	0,1,2,3	0	null	0
+iMC	0x7	0x1	UNC_M_MAJOR_MODES.READ	Cycles in a Major Mode; Read Major Mode	0,1,2,3	0	null	0
+iMC	0x7	0x2	UNC_M_MAJOR_MODES.WRITE	Cycles in a Major Mode; Write Major Mode	0,1,2,3	0	null	0
+iMC	0x7	0x4	UNC_M_MAJOR_MODES.PARTIAL	Cycles in a Major Mode; Partial Major Mode	0,1,2,3	0	null	0
+iMC	0x7	0x8	UNC_M_MAJOR_MODES.ISOCH	Cycles in a Major Mode; Isoch Major Mode	0,1,2,3	0	null	0
+iMC	0x84	0x0	UNC_M_POWER_CHANNEL_DLLOFF	Channel DLLOFF Cycles	0,1,2,3	0	null	0
+iMC	0x85	0x0	UNC_M_POWER_CHANNEL_PPD	Channel PPD Cycles	0,1,2,3	0	null	0
+iMC	0x83	0x1	UNC_M_POWER_CKE_CYCLES.RANK0	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x2	UNC_M_POWER_CKE_CYCLES.RANK1	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x4	UNC_M_POWER_CKE_CYCLES.RANK2	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x8	UNC_M_POWER_CKE_CYCLES.RANK3	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x10	UNC_M_POWER_CKE_CYCLES.RANK4	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x20	UNC_M_POWER_CKE_CYCLES.RANK5	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x40	UNC_M_POWER_CKE_CYCLES.RANK6	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x83	0x80	UNC_M_POWER_CKE_CYCLES.RANK7	CKE_ON_CYCLES by Rank; DIMM ID	0,1,2,3	0	null	0
+iMC	0x86	0x0	UNC_M_POWER_CRITICAL_THROTTLE_CYCLES	Critical Throttle Cycles	0,1,2,3	0	null	0
+iMC	0x42	0x0	UNC_M_POWER_PCU_THROTTLING	tbd	0,1,2,3	0	null	0
+iMC	0x43	0x0	UNC_M_POWER_SELF_REFRESH	Clock-Enabled Self-Refresh	0,1,2,3	0	null	0
+iMC	0x41	0x1	UNC_M_POWER_THROTTLE_CYCLES.RANK0	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x2	UNC_M_POWER_THROTTLE_CYCLES.RANK1	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x4	UNC_M_POWER_THROTTLE_CYCLES.RANK2	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x8	UNC_M_POWER_THROTTLE_CYCLES.RANK3	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x10	UNC_M_POWER_THROTTLE_CYCLES.RANK4	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x20	UNC_M_POWER_THROTTLE_CYCLES.RANK5	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x40	UNC_M_POWER_THROTTLE_CYCLES.RANK6	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x41	0x80	UNC_M_POWER_THROTTLE_CYCLES.RANK7	Throttle Cycles for Rank 0; DIMM ID	0,1,2,3	0	null	0
+iMC	0x8	0x1	UNC_M_PREEMPTION.RD_PREEMPT_RD	Read Preemption Count; Read over Read Preemption	0,1,2,3	0	null	0
+iMC	0x8	0x2	UNC_M_PREEMPTION.RD_PREEMPT_WR	Read Preemption Count; Read over Write Preemption	0,1,2,3	0	null	0
+iMC	0x2	0x1	UNC_M_PRE_COUNT.PAGE_MISS	DRAM Precharge commands.; Precharges due to page miss	0,1,2,3	0	null	0
+iMC	0x2	0x2	UNC_M_PRE_COUNT.PAGE_CLOSE	DRAM Precharge commands.; Precharge due to timer expiration	0,1,2,3	0	null	0
+iMC	0x2	0x4	UNC_M_PRE_COUNT.RD	DRAM Precharge commands.; Precharge due to read	0,1,2,3	0	null	0
+iMC	0x2	0x8	UNC_M_PRE_COUNT.WR	DRAM Precharge commands.; Precharge due to write	0,1,2,3	0	null	0
+iMC	0x2	0x10	UNC_M_PRE_COUNT.BYP	DRAM Precharge commands.; Precharge due to bypass	0,1,2,3	0	null	0
+iMC	0xA0	0x1	UNC_M_RD_CAS_PRIO.LOW	Read CAS issued with LOW priority	0,1,2,3	0	null	0
+iMC	0xA0	0x2	UNC_M_RD_CAS_PRIO.MED	Read CAS issued with MEDIUM priority	0,1,2,3	0	null	0
+iMC	0xA0	0x4	UNC_M_RD_CAS_PRIO.HIGH	Read CAS issued with HIGH priority	0,1,2,3	0	null	0
+iMC	0xA0	0x8	UNC_M_RD_CAS_PRIO.PANIC	Read CAS issued with PANIC NON ISOCH priority (starved)	0,1,2,3	0	null	0
+iMC	0xB0	0x1	UNC_M_RD_CAS_RANK0.BANK1	RD_CAS Access to Rank 0; Bank 1	0,1,2,3	0	null	0
+iMC	0xB0	0x2	UNC_M_RD_CAS_RANK0.BANK2	RD_CAS Access to Rank 0; Bank 2	0,1,2,3	0	null	0
+iMC	0xB0	0x4	UNC_M_RD_CAS_RANK0.BANK4	RD_CAS Access to Rank 0; Bank 4	0,1,2,3	0	null	0
+iMC	0xB0	0x8	UNC_M_RD_CAS_RANK0.BANK8	RD_CAS Access to Rank 0; Bank 8	0,1,2,3	0	null	0
+iMC	0xB0	0x10	UNC_M_RD_CAS_RANK0.ALLBANKS	RD_CAS Access to Rank 0; All Banks	0,1,2,3	0	null	0
+iMC	0xB0	0x0	UNC_M_RD_CAS_RANK0.BANK0	RD_CAS Access to Rank 0; Bank 0	0,1,2,3	0	null	0
+iMC	0xB0	0x3	UNC_M_RD_CAS_RANK0.BANK3	RD_CAS Access to Rank 0; Bank 3	0,1,2,3	0	null	0
+iMC	0xB0	0x5	UNC_M_RD_CAS_RANK0.BANK5	RD_CAS Access to Rank 0; Bank 5	0,1,2,3	0	null	0
+iMC	0xB0	0x6	UNC_M_RD_CAS_RANK0.BANK6	RD_CAS Access to Rank 0; Bank 6	0,1,2,3	0	null	0
+iMC	0xB0	0x7	UNC_M_RD_CAS_RANK0.BANK7	RD_CAS Access to Rank 0; Bank 7	0,1,2,3	0	null	0
+iMC	0xB0	0x9	UNC_M_RD_CAS_RANK0.BANK9	RD_CAS Access to Rank 0; Bank 9	0,1,2,3	0	null	0
+iMC	0xB0	0xA	UNC_M_RD_CAS_RANK0.BANK10	RD_CAS Access to Rank 0; Bank 10	0,1,2,3	0	null	0
+iMC	0xB0	0xB	UNC_M_RD_CAS_RANK0.BANK11	RD_CAS Access to Rank 0; Bank 11	0,1,2,3	0	null	0
+iMC	0xB0	0xC	UNC_M_RD_CAS_RANK0.BANK12	RD_CAS Access to Rank 0; Bank 12	0,1,2,3	0	null	0
+iMC	0xB0	0xD	UNC_M_RD_CAS_RANK0.BANK13	RD_CAS Access to Rank 0; Bank 13	0,1,2,3	0	null	0
+iMC	0xB0	0xE	UNC_M_RD_CAS_RANK0.BANK14	RD_CAS Access to Rank 0; Bank 14	0,1,2,3	0	null	0
+iMC	0xB0	0xF	UNC_M_RD_CAS_RANK0.BANK15	RD_CAS Access to Rank 0; Bank 15	0,1,2,3	0	null	0
+iMC	0xB0	0x11	UNC_M_RD_CAS_RANK0.BANKG0	RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB0	0x12	UNC_M_RD_CAS_RANK0.BANKG1	RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB0	0x13	UNC_M_RD_CAS_RANK0.BANKG2	RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB0	0x14	UNC_M_RD_CAS_RANK0.BANKG3	RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB1	0x1	UNC_M_RD_CAS_RANK1.BANK1	RD_CAS Access to Rank 1; Bank 1	0,1,2,3	0	null	0
+iMC	0xB1	0x2	UNC_M_RD_CAS_RANK1.BANK2	RD_CAS Access to Rank 1; Bank 2	0,1,2,3	0	null	0
+iMC	0xB1	0x4	UNC_M_RD_CAS_RANK1.BANK4	RD_CAS Access to Rank 1; Bank 4	0,1,2,3	0	null	0
+iMC	0xB1	0x8	UNC_M_RD_CAS_RANK1.BANK8	RD_CAS Access to Rank 1; Bank 8	0,1,2,3	0	null	0
+iMC	0xB1	0x10	UNC_M_RD_CAS_RANK1.ALLBANKS	RD_CAS Access to Rank 1; All Banks	0,1,2,3	0	null	0
+iMC	0xB1	0x0	UNC_M_RD_CAS_RANK1.BANK0	RD_CAS Access to Rank 1; Bank 0	0,1,2,3	0	null	0
+iMC	0xB1	0x3	UNC_M_RD_CAS_RANK1.BANK3	RD_CAS Access to Rank 1; Bank 3	0,1,2,3	0	null	0
+iMC	0xB1	0x5	UNC_M_RD_CAS_RANK1.BANK5	RD_CAS Access to Rank 1; Bank 5	0,1,2,3	0	null	0
+iMC	0xB1	0x6	UNC_M_RD_CAS_RANK1.BANK6	RD_CAS Access to Rank 1; Bank 6	0,1,2,3	0	null	0
+iMC	0xB1	0x7	UNC_M_RD_CAS_RANK1.BANK7	RD_CAS Access to Rank 1; Bank 7	0,1,2,3	0	null	0
+iMC	0xB1	0x9	UNC_M_RD_CAS_RANK1.BANK9	RD_CAS Access to Rank 1; Bank 9	0,1,2,3	0	null	0
+iMC	0xB1	0xA	UNC_M_RD_CAS_RANK1.BANK10	RD_CAS Access to Rank 1; Bank 10	0,1,2,3	0	null	0
+iMC	0xB1	0xB	UNC_M_RD_CAS_RANK1.BANK11	RD_CAS Access to Rank 1; Bank 11	0,1,2,3	0	null	0
+iMC	0xB1	0xC	UNC_M_RD_CAS_RANK1.BANK12	RD_CAS Access to Rank 1; Bank 12	0,1,2,3	0	null	0
+iMC	0xB1	0xD	UNC_M_RD_CAS_RANK1.BANK13	RD_CAS Access to Rank 1; Bank 13	0,1,2,3	0	null	0
+iMC	0xB1	0xE	UNC_M_RD_CAS_RANK1.BANK14	RD_CAS Access to Rank 1; Bank 14	0,1,2,3	0	null	0
+iMC	0xB1	0xF	UNC_M_RD_CAS_RANK1.BANK15	RD_CAS Access to Rank 1; Bank 15	0,1,2,3	0	null	0
+iMC	0xB1	0x11	UNC_M_RD_CAS_RANK1.BANKG0	RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB1	0x12	UNC_M_RD_CAS_RANK1.BANKG1	RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB1	0x13	UNC_M_RD_CAS_RANK1.BANKG2	RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB1	0x14	UNC_M_RD_CAS_RANK1.BANKG3	RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB2	0x0	UNC_M_RD_CAS_RANK2.BANK0	RD_CAS Access to Rank 2; Bank 0	0,1,2,3	0	null	0
+iMC	0xB4	0x1	UNC_M_RD_CAS_RANK4.BANK1	RD_CAS Access to Rank 4; Bank 1	0,1,2,3	0	null	0
+iMC	0xB4	0x2	UNC_M_RD_CAS_RANK4.BANK2	RD_CAS Access to Rank 4; Bank 2	0,1,2,3	0	null	0
+iMC	0xB4	0x4	UNC_M_RD_CAS_RANK4.BANK4	RD_CAS Access to Rank 4; Bank 4	0,1,2,3	0	null	0
+iMC	0xB4	0x8	UNC_M_RD_CAS_RANK4.BANK8	RD_CAS Access to Rank 4; Bank 8	0,1,2,3	0	null	0
+iMC	0xB4	0x10	UNC_M_RD_CAS_RANK4.ALLBANKS	RD_CAS Access to Rank 4; All Banks	0,1,2,3	0	null	0
+iMC	0xB4	0x0	UNC_M_RD_CAS_RANK4.BANK0	RD_CAS Access to Rank 4; Bank 0	0,1,2,3	0	null	0
+iMC	0xB4	0x3	UNC_M_RD_CAS_RANK4.BANK3	RD_CAS Access to Rank 4; Bank 3	0,1,2,3	0	null	0
+iMC	0xB4	0x5	UNC_M_RD_CAS_RANK4.BANK5	RD_CAS Access to Rank 4; Bank 5	0,1,2,3	0	null	0
+iMC	0xB4	0x6	UNC_M_RD_CAS_RANK4.BANK6	RD_CAS Access to Rank 4; Bank 6	0,1,2,3	0	null	0
+iMC	0xB4	0x7	UNC_M_RD_CAS_RANK4.BANK7	RD_CAS Access to Rank 4; Bank 7	0,1,2,3	0	null	0
+iMC	0xB4	0x9	UNC_M_RD_CAS_RANK4.BANK9	RD_CAS Access to Rank 4; Bank 9	0,1,2,3	0	null	0
+iMC	0xB4	0xA	UNC_M_RD_CAS_RANK4.BANK10	RD_CAS Access to Rank 4; Bank 10	0,1,2,3	0	null	0
+iMC	0xB4	0xB	UNC_M_RD_CAS_RANK4.BANK11	RD_CAS Access to Rank 4; Bank 11	0,1,2,3	0	null	0
+iMC	0xB4	0xC	UNC_M_RD_CAS_RANK4.BANK12	RD_CAS Access to Rank 4; Bank 12	0,1,2,3	0	null	0
+iMC	0xB4	0xD	UNC_M_RD_CAS_RANK4.BANK13	RD_CAS Access to Rank 4; Bank 13	0,1,2,3	0	null	0
+iMC	0xB4	0xE	UNC_M_RD_CAS_RANK4.BANK14	RD_CAS Access to Rank 4; Bank 14	0,1,2,3	0	null	0
+iMC	0xB4	0xF	UNC_M_RD_CAS_RANK4.BANK15	RD_CAS Access to Rank 4; Bank 15	0,1,2,3	0	null	0
+iMC	0xB4	0x11	UNC_M_RD_CAS_RANK4.BANKG0	RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB4	0x12	UNC_M_RD_CAS_RANK4.BANKG1	RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB4	0x13	UNC_M_RD_CAS_RANK4.BANKG2	RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB4	0x14	UNC_M_RD_CAS_RANK4.BANKG3	RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB5	0x1	UNC_M_RD_CAS_RANK5.BANK1	RD_CAS Access to Rank 5; Bank 1	0,1,2,3	0	null	0
+iMC	0xB5	0x2	UNC_M_RD_CAS_RANK5.BANK2	RD_CAS Access to Rank 5; Bank 2	0,1,2,3	0	null	0
+iMC	0xB5	0x4	UNC_M_RD_CAS_RANK5.BANK4	RD_CAS Access to Rank 5; Bank 4	0,1,2,3	0	null	0
+iMC	0xB5	0x8	UNC_M_RD_CAS_RANK5.BANK8	RD_CAS Access to Rank 5; Bank 8	0,1,2,3	0	null	0
+iMC	0xB5	0x10	UNC_M_RD_CAS_RANK5.ALLBANKS	RD_CAS Access to Rank 5; All Banks	0,1,2,3	0	null	0
+iMC	0xB5	0x0	UNC_M_RD_CAS_RANK5.BANK0	RD_CAS Access to Rank 5; Bank 0	0,1,2,3	0	null	0
+iMC	0xB5	0x3	UNC_M_RD_CAS_RANK5.BANK3	RD_CAS Access to Rank 5; Bank 3	0,1,2,3	0	null	0
+iMC	0xB5	0x5	UNC_M_RD_CAS_RANK5.BANK5	RD_CAS Access to Rank 5; Bank 5	0,1,2,3	0	null	0
+iMC	0xB5	0x6	UNC_M_RD_CAS_RANK5.BANK6	RD_CAS Access to Rank 5; Bank 6	0,1,2,3	0	null	0
+iMC	0xB5	0x7	UNC_M_RD_CAS_RANK5.BANK7	RD_CAS Access to Rank 5; Bank 7	0,1,2,3	0	null	0
+iMC	0xB5	0x9	UNC_M_RD_CAS_RANK5.BANK9	RD_CAS Access to Rank 5; Bank 9	0,1,2,3	0	null	0
+iMC	0xB5	0xA	UNC_M_RD_CAS_RANK5.BANK10	RD_CAS Access to Rank 5; Bank 10	0,1,2,3	0	null	0
+iMC	0xB5	0xB	UNC_M_RD_CAS_RANK5.BANK11	RD_CAS Access to Rank 5; Bank 11	0,1,2,3	0	null	0
+iMC	0xB5	0xC	UNC_M_RD_CAS_RANK5.BANK12	RD_CAS Access to Rank 5; Bank 12	0,1,2,3	0	null	0
+iMC	0xB5	0xD	UNC_M_RD_CAS_RANK5.BANK13	RD_CAS Access to Rank 5; Bank 13	0,1,2,3	0	null	0
+iMC	0xB5	0xE	UNC_M_RD_CAS_RANK5.BANK14	RD_CAS Access to Rank 5; Bank 14	0,1,2,3	0	null	0
+iMC	0xB5	0xF	UNC_M_RD_CAS_RANK5.BANK15	RD_CAS Access to Rank 5; Bank 15	0,1,2,3	0	null	0
+iMC	0xB5	0x11	UNC_M_RD_CAS_RANK5.BANKG0	RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB5	0x12	UNC_M_RD_CAS_RANK5.BANKG1	RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB5	0x13	UNC_M_RD_CAS_RANK5.BANKG2	RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB5	0x14	UNC_M_RD_CAS_RANK5.BANKG3	RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB6	0x1	UNC_M_RD_CAS_RANK6.BANK1	RD_CAS Access to Rank 6; Bank 1	0,1,2,3	0	null	0
+iMC	0xB6	0x2	UNC_M_RD_CAS_RANK6.BANK2	RD_CAS Access to Rank 6; Bank 2	0,1,2,3	0	null	0
+iMC	0xB6	0x4	UNC_M_RD_CAS_RANK6.BANK4	RD_CAS Access to Rank 6; Bank 4	0,1,2,3	0	null	0
+iMC	0xB6	0x8	UNC_M_RD_CAS_RANK6.BANK8	RD_CAS Access to Rank 6; Bank 8	0,1,2,3	0	null	0
+iMC	0xB6	0x10	UNC_M_RD_CAS_RANK6.ALLBANKS	RD_CAS Access to Rank 6; All Banks	0,1,2,3	0	null	0
+iMC	0xB6	0x0	UNC_M_RD_CAS_RANK6.BANK0	RD_CAS Access to Rank 6; Bank 0	0,1,2,3	0	null	0
+iMC	0xB6	0x3	UNC_M_RD_CAS_RANK6.BANK3	RD_CAS Access to Rank 6; Bank 3	0,1,2,3	0	null	0
+iMC	0xB6	0x5	UNC_M_RD_CAS_RANK6.BANK5	RD_CAS Access to Rank 6; Bank 5	0,1,2,3	0	null	0
+iMC	0xB6	0x6	UNC_M_RD_CAS_RANK6.BANK6	RD_CAS Access to Rank 6; Bank 6	0,1,2,3	0	null	0
+iMC	0xB6	0x7	UNC_M_RD_CAS_RANK6.BANK7	RD_CAS Access to Rank 6; Bank 7	0,1,2,3	0	null	0
+iMC	0xB6	0x9	UNC_M_RD_CAS_RANK6.BANK9	RD_CAS Access to Rank 6; Bank 9	0,1,2,3	0	null	0
+iMC	0xB6	0xA	UNC_M_RD_CAS_RANK6.BANK10	RD_CAS Access to Rank 6; Bank 10	0,1,2,3	0	null	0
+iMC	0xB6	0xB	UNC_M_RD_CAS_RANK6.BANK11	RD_CAS Access to Rank 6; Bank 11	0,1,2,3	0	null	0
+iMC	0xB6	0xC	UNC_M_RD_CAS_RANK6.BANK12	RD_CAS Access to Rank 6; Bank 12	0,1,2,3	0	null	0
+iMC	0xB6	0xD	UNC_M_RD_CAS_RANK6.BANK13	RD_CAS Access to Rank 6; Bank 13	0,1,2,3	0	null	0
+iMC	0xB6	0xE	UNC_M_RD_CAS_RANK6.BANK14	RD_CAS Access to Rank 6; Bank 14	0,1,2,3	0	null	0
+iMC	0xB6	0xF	UNC_M_RD_CAS_RANK6.BANK15	RD_CAS Access to Rank 6; Bank 15	0,1,2,3	0	null	0
+iMC	0xB6	0x11	UNC_M_RD_CAS_RANK6.BANKG0	RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB6	0x12	UNC_M_RD_CAS_RANK6.BANKG1	RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB6	0x13	UNC_M_RD_CAS_RANK6.BANKG2	RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB6	0x14	UNC_M_RD_CAS_RANK6.BANKG3	RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB7	0x1	UNC_M_RD_CAS_RANK7.BANK1	RD_CAS Access to Rank 7; Bank 1	0,1,2,3	0	null	0
+iMC	0xB7	0x2	UNC_M_RD_CAS_RANK7.BANK2	RD_CAS Access to Rank 7; Bank 2	0,1,2,3	0	null	0
+iMC	0xB7	0x4	UNC_M_RD_CAS_RANK7.BANK4	RD_CAS Access to Rank 7; Bank 4	0,1,2,3	0	null	0
+iMC	0xB7	0x8	UNC_M_RD_CAS_RANK7.BANK8	RD_CAS Access to Rank 7; Bank 8	0,1,2,3	0	null	0
+iMC	0xB7	0x10	UNC_M_RD_CAS_RANK7.ALLBANKS	RD_CAS Access to Rank 7; All Banks	0,1,2,3	0	null	0
+iMC	0xB7	0x0	UNC_M_RD_CAS_RANK7.BANK0	RD_CAS Access to Rank 7; Bank 0	0,1,2,3	0	null	0
+iMC	0xB7	0x3	UNC_M_RD_CAS_RANK7.BANK3	RD_CAS Access to Rank 7; Bank 3	0,1,2,3	0	null	0
+iMC	0xB7	0x5	UNC_M_RD_CAS_RANK7.BANK5	RD_CAS Access to Rank 7; Bank 5	0,1,2,3	0	null	0
+iMC	0xB7	0x6	UNC_M_RD_CAS_RANK7.BANK6	RD_CAS Access to Rank 7; Bank 6	0,1,2,3	0	null	0
+iMC	0xB7	0x7	UNC_M_RD_CAS_RANK7.BANK7	RD_CAS Access to Rank 7; Bank 7	0,1,2,3	0	null	0
+iMC	0xB7	0x9	UNC_M_RD_CAS_RANK7.BANK9	RD_CAS Access to Rank 7; Bank 9	0,1,2,3	0	null	0
+iMC	0xB7	0xA	UNC_M_RD_CAS_RANK7.BANK10	RD_CAS Access to Rank 7; Bank 10	0,1,2,3	0	null	0
+iMC	0xB7	0xB	UNC_M_RD_CAS_RANK7.BANK11	RD_CAS Access to Rank 7; Bank 11	0,1,2,3	0	null	0
+iMC	0xB7	0xC	UNC_M_RD_CAS_RANK7.BANK12	RD_CAS Access to Rank 7; Bank 12	0,1,2,3	0	null	0
+iMC	0xB7	0xD	UNC_M_RD_CAS_RANK7.BANK13	RD_CAS Access to Rank 7; Bank 13	0,1,2,3	0	null	0
+iMC	0xB7	0xE	UNC_M_RD_CAS_RANK7.BANK14	RD_CAS Access to Rank 7; Bank 14	0,1,2,3	0	null	0
+iMC	0xB7	0xF	UNC_M_RD_CAS_RANK7.BANK15	RD_CAS Access to Rank 7; Bank 15	0,1,2,3	0	null	0
+iMC	0xB7	0x11	UNC_M_RD_CAS_RANK7.BANKG0	RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB7	0x12	UNC_M_RD_CAS_RANK7.BANKG1	RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB7	0x13	UNC_M_RD_CAS_RANK7.BANKG2	RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB7	0x14	UNC_M_RD_CAS_RANK7.BANKG3	RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0x11	0x0	UNC_M_RPQ_CYCLES_NE	Read Pending Queue Not Empty	0,1,2,3	0	null	0
+iMC	0x10	0x0	UNC_M_RPQ_INSERTS	Read Pending Queue Allocations	0,1,2,3	0	null	0
+iMC	0x91	0x0	UNC_M_VMSE_MXB_WR_OCCUPANCY	VMSE MXB write buffer occupancy	0,1,2,3	0	null	0
+iMC	0x90	0x1	UNC_M_VMSE_WR_PUSH.WMM	VMSE WR PUSH issued; VMSE write PUSH issued in WMM	0,1,2,3	0	null	0
+iMC	0x90	0x2	UNC_M_VMSE_WR_PUSH.RMM	VMSE WR PUSH issued; VMSE write PUSH issued in RMM	0,1,2,3	0	null	0
+iMC	0xC0	0x1	UNC_M_WMM_TO_RMM.LOW_THRESH	Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter	0,1,2,3	0	null	0
+iMC	0xC0	0x2	UNC_M_WMM_TO_RMM.STARVE	Transition from WMM to RMM because of low threshold	0,1,2,3	0	null	0
+iMC	0xC0	0x4	UNC_M_WMM_TO_RMM.VMSE_RETRY	Transition from WMM to RMM because of low threshold	0,1,2,3	0	null	0
+iMC	0x22	0x0	UNC_M_WPQ_CYCLES_FULL	Write Pending Queue Full Cycles	0,1,2,3	0	null	0
+iMC	0x21	0x0	UNC_M_WPQ_CYCLES_NE	Write Pending Queue Not Empty	0,1,2,3	0	null	0
+iMC	0x23	0x0	UNC_M_WPQ_READ_HIT	Write Pending Queue CAM Match	0,1,2,3	0	null	0
+iMC	0x24	0x0	UNC_M_WPQ_WRITE_HIT	Write Pending Queue CAM Match	0,1,2,3	0	null	0
+iMC	0xC1	0x0	UNC_M_WRONG_MM	Not getting the requested Major Mode	0,1,2,3	0	null	0
+iMC	0xB8	0x1	UNC_M_WR_CAS_RANK0.BANK1	WR_CAS Access to Rank 0; Bank 1	0,1,2,3	0	null	0
+iMC	0xB8	0x2	UNC_M_WR_CAS_RANK0.BANK2	WR_CAS Access to Rank 0; Bank 2	0,1,2,3	0	null	0
+iMC	0xB8	0x4	UNC_M_WR_CAS_RANK0.BANK4	WR_CAS Access to Rank 0; Bank 4	0,1,2,3	0	null	0
+iMC	0xB8	0x8	UNC_M_WR_CAS_RANK0.BANK8	WR_CAS Access to Rank 0; Bank 8	0,1,2,3	0	null	0
+iMC	0xB8	0x10	UNC_M_WR_CAS_RANK0.ALLBANKS	WR_CAS Access to Rank 0; All Banks	0,1,2,3	0	null	0
+iMC	0xB8	0x0	UNC_M_WR_CAS_RANK0.BANK0	WR_CAS Access to Rank 0; Bank 0	0,1,2,3	0	null	0
+iMC	0xB8	0x3	UNC_M_WR_CAS_RANK0.BANK3	WR_CAS Access to Rank 0; Bank 3	0,1,2,3	0	null	0
+iMC	0xB8	0x5	UNC_M_WR_CAS_RANK0.BANK5	WR_CAS Access to Rank 0; Bank 5	0,1,2,3	0	null	0
+iMC	0xB8	0x6	UNC_M_WR_CAS_RANK0.BANK6	WR_CAS Access to Rank 0; Bank 6	0,1,2,3	0	null	0
+iMC	0xB8	0x7	UNC_M_WR_CAS_RANK0.BANK7	WR_CAS Access to Rank 0; Bank 7	0,1,2,3	0	null	0
+iMC	0xB8	0x9	UNC_M_WR_CAS_RANK0.BANK9	WR_CAS Access to Rank 0; Bank 9	0,1,2,3	0	null	0
+iMC	0xB8	0xA	UNC_M_WR_CAS_RANK0.BANK10	WR_CAS Access to Rank 0; Bank 10	0,1,2,3	0	null	0
+iMC	0xB8	0xB	UNC_M_WR_CAS_RANK0.BANK11	WR_CAS Access to Rank 0; Bank 11	0,1,2,3	0	null	0
+iMC	0xB8	0xC	UNC_M_WR_CAS_RANK0.BANK12	WR_CAS Access to Rank 0; Bank 12	0,1,2,3	0	null	0
+iMC	0xB8	0xD	UNC_M_WR_CAS_RANK0.BANK13	WR_CAS Access to Rank 0; Bank 13	0,1,2,3	0	null	0
+iMC	0xB8	0xE	UNC_M_WR_CAS_RANK0.BANK14	WR_CAS Access to Rank 0; Bank 14	0,1,2,3	0	null	0
+iMC	0xB8	0xF	UNC_M_WR_CAS_RANK0.BANK15	WR_CAS Access to Rank 0; Bank 15	0,1,2,3	0	null	0
+iMC	0xB8	0x11	UNC_M_WR_CAS_RANK0.BANKG0	WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB8	0x12	UNC_M_WR_CAS_RANK0.BANKG1	WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB8	0x13	UNC_M_WR_CAS_RANK0.BANKG2	WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB8	0x14	UNC_M_WR_CAS_RANK0.BANKG3	WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xB9	0x1	UNC_M_WR_CAS_RANK1.BANK1	WR_CAS Access to Rank 1; Bank 1	0,1,2,3	0	null	0
+iMC	0xB9	0x2	UNC_M_WR_CAS_RANK1.BANK2	WR_CAS Access to Rank 1; Bank 2	0,1,2,3	0	null	0
+iMC	0xB9	0x4	UNC_M_WR_CAS_RANK1.BANK4	WR_CAS Access to Rank 1; Bank 4	0,1,2,3	0	null	0
+iMC	0xB9	0x8	UNC_M_WR_CAS_RANK1.BANK8	WR_CAS Access to Rank 1; Bank 8	0,1,2,3	0	null	0
+iMC	0xB9	0x10	UNC_M_WR_CAS_RANK1.ALLBANKS	WR_CAS Access to Rank 1; All Banks	0,1,2,3	0	null	0
+iMC	0xB9	0x0	UNC_M_WR_CAS_RANK1.BANK0	WR_CAS Access to Rank 1; Bank 0	0,1,2,3	0	null	0
+iMC	0xB9	0x3	UNC_M_WR_CAS_RANK1.BANK3	WR_CAS Access to Rank 1; Bank 3	0,1,2,3	0	null	0
+iMC	0xB9	0x5	UNC_M_WR_CAS_RANK1.BANK5	WR_CAS Access to Rank 1; Bank 5	0,1,2,3	0	null	0
+iMC	0xB9	0x6	UNC_M_WR_CAS_RANK1.BANK6	WR_CAS Access to Rank 1; Bank 6	0,1,2,3	0	null	0
+iMC	0xB9	0x7	UNC_M_WR_CAS_RANK1.BANK7	WR_CAS Access to Rank 1; Bank 7	0,1,2,3	0	null	0
+iMC	0xB9	0x9	UNC_M_WR_CAS_RANK1.BANK9	WR_CAS Access to Rank 1; Bank 9	0,1,2,3	0	null	0
+iMC	0xB9	0xA	UNC_M_WR_CAS_RANK1.BANK10	WR_CAS Access to Rank 1; Bank 10	0,1,2,3	0	null	0
+iMC	0xB9	0xB	UNC_M_WR_CAS_RANK1.BANK11	WR_CAS Access to Rank 1; Bank 11	0,1,2,3	0	null	0
+iMC	0xB9	0xC	UNC_M_WR_CAS_RANK1.BANK12	WR_CAS Access to Rank 1; Bank 12	0,1,2,3	0	null	0
+iMC	0xB9	0xD	UNC_M_WR_CAS_RANK1.BANK13	WR_CAS Access to Rank 1; Bank 13	0,1,2,3	0	null	0
+iMC	0xB9	0xE	UNC_M_WR_CAS_RANK1.BANK14	WR_CAS Access to Rank 1; Bank 14	0,1,2,3	0	null	0
+iMC	0xB9	0xF	UNC_M_WR_CAS_RANK1.BANK15	WR_CAS Access to Rank 1; Bank 15	0,1,2,3	0	null	0
+iMC	0xB9	0x11	UNC_M_WR_CAS_RANK1.BANKG0	WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xB9	0x12	UNC_M_WR_CAS_RANK1.BANKG1	WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xB9	0x13	UNC_M_WR_CAS_RANK1.BANKG2	WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xB9	0x14	UNC_M_WR_CAS_RANK1.BANKG3	WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xBC	0x1	UNC_M_WR_CAS_RANK4.BANK1	WR_CAS Access to Rank 4; Bank 1	0,1,2,3	0	null	0
+iMC	0xBC	0x2	UNC_M_WR_CAS_RANK4.BANK2	WR_CAS Access to Rank 4; Bank 2	0,1,2,3	0	null	0
+iMC	0xBC	0x4	UNC_M_WR_CAS_RANK4.BANK4	WR_CAS Access to Rank 4; Bank 4	0,1,2,3	0	null	0
+iMC	0xBC	0x8	UNC_M_WR_CAS_RANK4.BANK8	WR_CAS Access to Rank 4; Bank 8	0,1,2,3	0	null	0
+iMC	0xBC	0x10	UNC_M_WR_CAS_RANK4.ALLBANKS	WR_CAS Access to Rank 4; All Banks	0,1,2,3	0	null	0
+iMC	0xBC	0x0	UNC_M_WR_CAS_RANK4.BANK0	WR_CAS Access to Rank 4; Bank 0	0,1,2,3	0	null	0
+iMC	0xBC	0x3	UNC_M_WR_CAS_RANK4.BANK3	WR_CAS Access to Rank 4; Bank 3	0,1,2,3	0	null	0
+iMC	0xBC	0x5	UNC_M_WR_CAS_RANK4.BANK5	WR_CAS Access to Rank 4; Bank 5	0,1,2,3	0	null	0
+iMC	0xBC	0x6	UNC_M_WR_CAS_RANK4.BANK6	WR_CAS Access to Rank 4; Bank 6	0,1,2,3	0	null	0
+iMC	0xBC	0x7	UNC_M_WR_CAS_RANK4.BANK7	WR_CAS Access to Rank 4; Bank 7	0,1,2,3	0	null	0
+iMC	0xBC	0x9	UNC_M_WR_CAS_RANK4.BANK9	WR_CAS Access to Rank 4; Bank 9	0,1,2,3	0	null	0
+iMC	0xBC	0xA	UNC_M_WR_CAS_RANK4.BANK10	WR_CAS Access to Rank 4; Bank 10	0,1,2,3	0	null	0
+iMC	0xBC	0xB	UNC_M_WR_CAS_RANK4.BANK11	WR_CAS Access to Rank 4; Bank 11	0,1,2,3	0	null	0
+iMC	0xBC	0xC	UNC_M_WR_CAS_RANK4.BANK12	WR_CAS Access to Rank 4; Bank 12	0,1,2,3	0	null	0
+iMC	0xBC	0xD	UNC_M_WR_CAS_RANK4.BANK13	WR_CAS Access to Rank 4; Bank 13	0,1,2,3	0	null	0
+iMC	0xBC	0xE	UNC_M_WR_CAS_RANK4.BANK14	WR_CAS Access to Rank 4; Bank 14	0,1,2,3	0	null	0
+iMC	0xBC	0xF	UNC_M_WR_CAS_RANK4.BANK15	WR_CAS Access to Rank 4; Bank 15	0,1,2,3	0	null	0
+iMC	0xBC	0x11	UNC_M_WR_CAS_RANK4.BANKG0	WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xBC	0x12	UNC_M_WR_CAS_RANK4.BANKG1	WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xBC	0x13	UNC_M_WR_CAS_RANK4.BANKG2	WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xBC	0x14	UNC_M_WR_CAS_RANK4.BANKG3	WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xBD	0x1	UNC_M_WR_CAS_RANK5.BANK1	WR_CAS Access to Rank 5; Bank 1	0,1,2,3	0	null	0
+iMC	0xBD	0x2	UNC_M_WR_CAS_RANK5.BANK2	WR_CAS Access to Rank 5; Bank 2	0,1,2,3	0	null	0
+iMC	0xBD	0x4	UNC_M_WR_CAS_RANK5.BANK4	WR_CAS Access to Rank 5; Bank 4	0,1,2,3	0	null	0
+iMC	0xBD	0x8	UNC_M_WR_CAS_RANK5.BANK8	WR_CAS Access to Rank 5; Bank 8	0,1,2,3	0	null	0
+iMC	0xBD	0x10	UNC_M_WR_CAS_RANK5.ALLBANKS	WR_CAS Access to Rank 5; All Banks	0,1,2,3	0	null	0
+iMC	0xBD	0x0	UNC_M_WR_CAS_RANK5.BANK0	WR_CAS Access to Rank 5; Bank 0	0,1,2,3	0	null	0
+iMC	0xBD	0x3	UNC_M_WR_CAS_RANK5.BANK3	WR_CAS Access to Rank 5; Bank 3	0,1,2,3	0	null	0
+iMC	0xBD	0x5	UNC_M_WR_CAS_RANK5.BANK5	WR_CAS Access to Rank 5; Bank 5	0,1,2,3	0	null	0
+iMC	0xBD	0x6	UNC_M_WR_CAS_RANK5.BANK6	WR_CAS Access to Rank 5; Bank 6	0,1,2,3	0	null	0
+iMC	0xBD	0x7	UNC_M_WR_CAS_RANK5.BANK7	WR_CAS Access to Rank 5; Bank 7	0,1,2,3	0	null	0
+iMC	0xBD	0x9	UNC_M_WR_CAS_RANK5.BANK9	WR_CAS Access to Rank 5; Bank 9	0,1,2,3	0	null	0
+iMC	0xBD	0xA	UNC_M_WR_CAS_RANK5.BANK10	WR_CAS Access to Rank 5; Bank 10	0,1,2,3	0	null	0
+iMC	0xBD	0xB	UNC_M_WR_CAS_RANK5.BANK11	WR_CAS Access to Rank 5; Bank 11	0,1,2,3	0	null	0
+iMC	0xBD	0xC	UNC_M_WR_CAS_RANK5.BANK12	WR_CAS Access to Rank 5; Bank 12	0,1,2,3	0	null	0
+iMC	0xBD	0xD	UNC_M_WR_CAS_RANK5.BANK13	WR_CAS Access to Rank 5; Bank 13	0,1,2,3	0	null	0
+iMC	0xBD	0xE	UNC_M_WR_CAS_RANK5.BANK14	WR_CAS Access to Rank 5; Bank 14	0,1,2,3	0	null	0
+iMC	0xBD	0xF	UNC_M_WR_CAS_RANK5.BANK15	WR_CAS Access to Rank 5; Bank 15	0,1,2,3	0	null	0
+iMC	0xBD	0x11	UNC_M_WR_CAS_RANK5.BANKG0	WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xBD	0x12	UNC_M_WR_CAS_RANK5.BANKG1	WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xBD	0x13	UNC_M_WR_CAS_RANK5.BANKG2	WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xBD	0x14	UNC_M_WR_CAS_RANK5.BANKG3	WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xBE	0x1	UNC_M_WR_CAS_RANK6.BANK1	WR_CAS Access to Rank 6; Bank 1	0,1,2,3	0	null	0
+iMC	0xBE	0x2	UNC_M_WR_CAS_RANK6.BANK2	WR_CAS Access to Rank 6; Bank 2	0,1,2,3	0	null	0
+iMC	0xBE	0x4	UNC_M_WR_CAS_RANK6.BANK4	WR_CAS Access to Rank 6; Bank 4	0,1,2,3	0	null	0
+iMC	0xBE	0x8	UNC_M_WR_CAS_RANK6.BANK8	WR_CAS Access to Rank 6; Bank 8	0,1,2,3	0	null	0
+iMC	0xBE	0x10	UNC_M_WR_CAS_RANK6.ALLBANKS	WR_CAS Access to Rank 6; All Banks	0,1,2,3	0	null	0
+iMC	0xBE	0x0	UNC_M_WR_CAS_RANK6.BANK0	WR_CAS Access to Rank 6; Bank 0	0,1,2,3	0	null	0
+iMC	0xBE	0x3	UNC_M_WR_CAS_RANK6.BANK3	WR_CAS Access to Rank 6; Bank 3	0,1,2,3	0	null	0
+iMC	0xBE	0x5	UNC_M_WR_CAS_RANK6.BANK5	WR_CAS Access to Rank 6; Bank 5	0,1,2,3	0	null	0
+iMC	0xBE	0x6	UNC_M_WR_CAS_RANK6.BANK6	WR_CAS Access to Rank 6; Bank 6	0,1,2,3	0	null	0
+iMC	0xBE	0x7	UNC_M_WR_CAS_RANK6.BANK7	WR_CAS Access to Rank 6; Bank 7	0,1,2,3	0	null	0
+iMC	0xBE	0x9	UNC_M_WR_CAS_RANK6.BANK9	WR_CAS Access to Rank 6; Bank 9	0,1,2,3	0	null	0
+iMC	0xBE	0xA	UNC_M_WR_CAS_RANK6.BANK10	WR_CAS Access to Rank 6; Bank 10	0,1,2,3	0	null	0
+iMC	0xBE	0xB	UNC_M_WR_CAS_RANK6.BANK11	WR_CAS Access to Rank 6; Bank 11	0,1,2,3	0	null	0
+iMC	0xBE	0xC	UNC_M_WR_CAS_RANK6.BANK12	WR_CAS Access to Rank 6; Bank 12	0,1,2,3	0	null	0
+iMC	0xBE	0xD	UNC_M_WR_CAS_RANK6.BANK13	WR_CAS Access to Rank 6; Bank 13	0,1,2,3	0	null	0
+iMC	0xBE	0xE	UNC_M_WR_CAS_RANK6.BANK14	WR_CAS Access to Rank 6; Bank 14	0,1,2,3	0	null	0
+iMC	0xBE	0xF	UNC_M_WR_CAS_RANK6.BANK15	WR_CAS Access to Rank 6; Bank 15	0,1,2,3	0	null	0
+iMC	0xBE	0x11	UNC_M_WR_CAS_RANK6.BANKG0	WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xBE	0x12	UNC_M_WR_CAS_RANK6.BANKG1	WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xBE	0x13	UNC_M_WR_CAS_RANK6.BANKG2	WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xBE	0x14	UNC_M_WR_CAS_RANK6.BANKG3	WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+iMC	0xBF	0x1	UNC_M_WR_CAS_RANK7.BANK1	WR_CAS Access to Rank 7; Bank 1	0,1,2,3	0	null	0
+iMC	0xBF	0x2	UNC_M_WR_CAS_RANK7.BANK2	WR_CAS Access to Rank 7; Bank 2	0,1,2,3	0	null	0
+iMC	0xBF	0x4	UNC_M_WR_CAS_RANK7.BANK4	WR_CAS Access to Rank 7; Bank 4	0,1,2,3	0	null	0
+iMC	0xBF	0x8	UNC_M_WR_CAS_RANK7.BANK8	WR_CAS Access to Rank 7; Bank 8	0,1,2,3	0	null	0
+iMC	0xBF	0x10	UNC_M_WR_CAS_RANK7.ALLBANKS	WR_CAS Access to Rank 7; All Banks	0,1,2,3	0	null	0
+iMC	0xBF	0x0	UNC_M_WR_CAS_RANK7.BANK0	WR_CAS Access to Rank 7; Bank 0	0,1,2,3	0	null	0
+iMC	0xBF	0x3	UNC_M_WR_CAS_RANK7.BANK3	WR_CAS Access to Rank 7; Bank 3	0,1,2,3	0	null	0
+iMC	0xBF	0x5	UNC_M_WR_CAS_RANK7.BANK5	WR_CAS Access to Rank 7; Bank 5	0,1,2,3	0	null	0
+iMC	0xBF	0x6	UNC_M_WR_CAS_RANK7.BANK6	WR_CAS Access to Rank 7; Bank 6	0,1,2,3	0	null	0
+iMC	0xBF	0x7	UNC_M_WR_CAS_RANK7.BANK7	WR_CAS Access to Rank 7; Bank 7	0,1,2,3	0	null	0
+iMC	0xBF	0x9	UNC_M_WR_CAS_RANK7.BANK9	WR_CAS Access to Rank 7; Bank 9	0,1,2,3	0	null	0
+iMC	0xBF	0xA	UNC_M_WR_CAS_RANK7.BANK10	WR_CAS Access to Rank 7; Bank 10	0,1,2,3	0	null	0
+iMC	0xBF	0xB	UNC_M_WR_CAS_RANK7.BANK11	WR_CAS Access to Rank 7; Bank 11	0,1,2,3	0	null	0
+iMC	0xBF	0xC	UNC_M_WR_CAS_RANK7.BANK12	WR_CAS Access to Rank 7; Bank 12	0,1,2,3	0	null	0
+iMC	0xBF	0xD	UNC_M_WR_CAS_RANK7.BANK13	WR_CAS Access to Rank 7; Bank 13	0,1,2,3	0	null	0
+iMC	0xBF	0xE	UNC_M_WR_CAS_RANK7.BANK14	WR_CAS Access to Rank 7; Bank 14	0,1,2,3	0	null	0
+iMC	0xBF	0xF	UNC_M_WR_CAS_RANK7.BANK15	WR_CAS Access to Rank 7; Bank 15	0,1,2,3	0	null	0
+iMC	0xBF	0x11	UNC_M_WR_CAS_RANK7.BANKG0	WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)	0,1,2,3	0	null	0
+iMC	0xBF	0x12	UNC_M_WR_CAS_RANK7.BANKG1	WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)	0,1,2,3	0	null	0
+iMC	0xBF	0x13	UNC_M_WR_CAS_RANK7.BANKG2	WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)	0,1,2,3	0	null	0
+iMC	0xBF	0x14	UNC_M_WR_CAS_RANK7.BANKG3	WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)	0,1,2,3	0	null	0
+UBOX	0x0	0x0	UNC_U_CLOCKTICKS	tbd	0	0	null	0
+CBO	0x11	0x2	UNC_C_RxR_OCCUPANCY.IRQ_REJ	Ingress Occupancy; IRQ Rejected	0	0	null	0
+HA	0x3	0x1	UNC_H_TRACKER_CYCLES_NE.LOCAL	Tracker Cycles Not Empty; Local Requests	0,1,2,3	0	null	0
+HA	0x3	0x2	UNC_H_TRACKER_CYCLES_NE.REMOTE	Tracker Cycles Not Empty; Remote Requests	0,1,2,3	0	null	0
+HA	0x3	0x3	UNC_H_TRACKER_CYCLES_NE.ALL	Tracker Cycles Not Empty; All Requests	0,1,2,3	0	null	0
+IRP	0x14	0x80	UNC_I_MISC0.PF_TIMEOUT	Misc Events - Set 0; Prefetch TimeOut	0,1	0	null	0
+iMC	0x0	0x0	UNC_M_DCLOCKTICKS	DRAM Clockticks	0,1,2,3	0	null	0
+CBO	0x37	0x4	UNC_C_LLC_VICTIMS.I_STATE	Lines Victimized; Lines in S State	0,1,2,3	0	null	0
+PCU	0x4E	0x0	UNC_P_PKG_RESIDENCY_C1E_CYCLES	Package C State Residency - C1E	0,1,2,3	0	null	0
+PCU	0x79	0x0	UNC_P_UFS_TRANSITIONS_RING_GV	tbd	0,1,2,3	0	null	0
diff --git a/x86data/perfmon_data/IVB/IvyBridge_core_V15.json b/x86data/perfmon_data/IVB/IvyBridge_core_V15.json
new file mode 100644
index 0000000..c238944
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_core_V15.json
@@ -0,0 +1,6575 @@
+[

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired from execution.",

+    "PublicDescription": "Instructions retired from execution.",

+    "Counter": "Fixed counter 1",

+    "CounterHTOff": "Fixed counter 1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Core cycles when the thread is not in halt state.",

+    "PublicDescription": "Core cycles when the thread is not in halt state.",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Reference cycles when the core is not in halt state.",

+    "PublicDescription": "Reference cycles when the core is not in halt state.",

+    "Counter": "Fixed counter 3",

+    "CounterHTOff": "Fixed counter 3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "LD_BLOCKS.STORE_FORWARD",

+    "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",

+    "PublicDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS.NO_SR",

+    "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "PublicDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "MISALIGN_MEM_REF.LOADS",

+    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "MISALIGN_MEM_REF.STORES",

+    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies in MOB due to partial compare on address",

+    "PublicDescription": "False dependencies in MOB due to partial compare on address",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x88",

+    "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",

+    "BriefDescription": "Page walk for a large page completed for Demand load ",

+    "PublicDescription": "Page walk for a large page completed for Demand load ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES",

+    "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_STALLS_COUNT",

+    "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "PublicDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x10",

+    "EventName": "UOPS_ISSUED.FLAGS_MERGE",

+    "BriefDescription": "Number of flags-merge uops being allocated.",

+    "PublicDescription": "Number of flags-merge uops being allocated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x20",

+    "EventName": "UOPS_ISSUED.SLOW_LEA",

+    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x40",

+    "EventName": "UOPS_ISSUED.SINGLE_MUL",

+    "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "PublicDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x01",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

+    "PublicDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x11",

+    "UMask": "0x01",

+    "EventName": "SIMD_FP_256.PACKED_SINGLE",

+    "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

+    "PublicDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x11",

+    "UMask": "0x02",

+    "EventName": "SIMD_FP_256.PACKED_DOUBLE",

+    "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

+    "PublicDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x01",

+    "EventName": "ARITH.FPU_DIV_ACTIVE",

+    "BriefDescription": "Cycles when divider is busy executing divide operations",

+    "PublicDescription": "Cycles when divider is busy executing divide operations",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x04",

+    "EventName": "ARITH.FPU_DIV",

+    "BriefDescription": "Divide operations executed",

+    "PublicDescription": "Divide operations executed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x01",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",

+    "BriefDescription": "Demand Data Read requests that hit L2 cache",

+    "PublicDescription": "Demand Data Read requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x04",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "RFO requests that hit L2 cache",

+    "PublicDescription": "RFO requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x08",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "RFO requests that miss L2 cache",

+    "PublicDescription": "RFO requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.CODE_RD_HIT",

+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",

+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.CODE_RD_MISS",

+    "BriefDescription": "L2 cache misses when fetching instructions",

+    "PublicDescription": "L2 cache misses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PF_HIT",

+    "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",

+    "PublicDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PF_MISS",

+    "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",

+    "PublicDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x03",

+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests",

+    "PublicDescription": "Demand Data Read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x0C",

+    "EventName": "L2_RQSTS.ALL_RFO",

+    "BriefDescription": "RFO requests to L2 cache",

+    "PublicDescription": "RFO requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.ALL_CODE_RD",

+    "BriefDescription": "L2 code requests",

+    "PublicDescription": "L2 code requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.ALL_PF",

+    "BriefDescription": "Requests from L2 hardware prefetchers",

+    "PublicDescription": "Requests from L2 hardware prefetchers",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x01",

+    "EventName": "L2_STORE_LOCK_RQSTS.MISS",

+    "BriefDescription": "RFOs that miss cache lines",

+    "PublicDescription": "RFOs that miss cache lines",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x08",

+    "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",

+    "BriefDescription": "RFOs that hit cache lines in M state",

+    "PublicDescription": "RFOs that hit cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x0F",

+    "EventName": "L2_STORE_LOCK_RQSTS.ALL",

+    "BriefDescription": "RFOs that access cache lines in any state",

+    "PublicDescription": "RFOs that access cache lines in any state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x01",

+    "EventName": "L2_L1D_WB_RQSTS.MISS",

+    "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",

+    "PublicDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x04",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_E",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x08",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_M",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x0F",

+    "EventName": "L2_L1D_WB_RQSTS.ALL",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Core-originated cacheable demand requests missed LLC",

+    "PublicDescription": "Core-originated cacheable demand requests missed LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",

+    "PublicDescription": "Core-originated cacheable demand requests that refer to LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Thread cycles when thread is not in halt state",

+    "PublicDescription": "Thread cycles when thread is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",

+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",

+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",

+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING",

+    "BriefDescription": "L1D miss oustandings duration in cycles",

+    "PublicDescription": "L1D miss oustandings duration in cycles",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",

+    "BriefDescription": "Cycles with L1D load Misses outstanding. ",

+    "PublicDescription": "Cycles with L1D load Misses outstanding. ",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x01",

+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x02",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x04",

+    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "Cycles when PMH is busy with page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",

+    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x01",

+    "EventName": "LOAD_HIT_PRE.SW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x02",

+    "EventName": "LOAD_HIT_PRE.HW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4F",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",

+    "PublicDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x01",

+    "EventName": "L1D.REPLACEMENT",

+    "BriefDescription": "L1D data line replacements",

+    "PublicDescription": "L1D data line replacements",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x04",

+    "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x08",

+    "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x01",

+    "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x02",

+    "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0",

+    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

+    "PublicDescription": "Unhalted core cycles when the thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x02",

+    "EventName": "CPL_CYCLES.RING123",

+    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "PublicDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0_TRANS",

+    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "PublicDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_CYCLES",

+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "PublicDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5F",

+    "UMask": "0x04",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",

+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "PublicDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",

+    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",

+    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x01",

+    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "PublicDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x02",

+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1D is locked",

+    "PublicDescription": "Cycles when L1D is locked",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x02",

+    "EventName": "IDQ.EMPTY",

+    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "PublicDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_UOPS",

+    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x20",

+    "EventName": "IDQ.MS_MITE_UOPS",

+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_CYCLES",

+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_OCCUR",

+    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles MITE is delivering 4 Uops",

+    "PublicDescription": "Cycles MITE is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles MITE is delivering any Uop",

+    "PublicDescription": "Cycles MITE is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x3c",

+    "EventName": "IDQ.MITE_ALL_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x01",

+    "EventName": "ICACHE.HIT",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x02",

+    "EventName": "ICACHE.MISSES",

+    "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",

+    "PublicDescription": "Instruction cache, streaming buffer and victim cache misses",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x04",

+    "EventName": "ICACHE.IFETCH_STALL",

+    "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",

+    "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x01",

+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Misses at all ITLB levels that cause page walks",

+    "PublicDescription": "Misses at all ITLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x02",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Misses in all ITLB levels that cause completed page walks",

+    "PublicDescription": "Misses in all ITLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x04",

+    "EventName": "ITLB_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "Cycles when PMH is busy with page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x10",

+    "EventName": "ITLB_MISSES.STLB_HIT",

+    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x80",

+    "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",

+    "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",

+    "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x01",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

+    "PublicDescription": "Stalls caused by changing prefix length of the instruction.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x04",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Stall cycles because IQ is full",

+    "PublicDescription": "Stall cycles because IQ is full",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x41",

+    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken macro-conditional branches",

+    "PublicDescription": "Not taken macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x81",

+    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired macro-conditional branches",

+    "PublicDescription": "Taken speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x82",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",

+    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x84",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x88",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x90",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired direct near calls",

+    "PublicDescription": "Taken speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xA0",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired indirect calls",

+    "PublicDescription": "Taken speculative and retired indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC1",

+    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired macro-conditional branches",

+    "PublicDescription": "Speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC2",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",

+    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC4",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC8",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Speculative and retired indirect return branches.",

+    "PublicDescription": "Speculative and retired indirect return branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xD0",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired direct near calls",

+    "PublicDescription": "Speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xFF",

+    "EventName": "BR_INST_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired  branches",

+    "PublicDescription": "Speculative and retired  branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x41",

+    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x81",

+    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x84",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x88",

+    "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xA0",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect calls",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC1",

+    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC4",

+    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xFF",

+    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",

+    "PublicDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "PublicDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "PublicDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 0",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 1",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 4",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 5",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 0",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 1",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 4",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 5",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x0C",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",

+    "PublicDescription": "Cycles per thread when load or STA uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x30",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",

+    "PublicDescription": "Cycles per thread when load or STA uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x0C",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",

+    "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired)",

+    "PublicDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x30",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",

+    "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",

+    "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x01",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource-related stall cycles",

+    "PublicDescription": "Resource-related stall cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x04",

+    "EventName": "RESOURCE_STALLS.RS",

+    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",

+    "PublicDescription": "Cycles stalled due to no eligible RS entry available.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x08",

+    "EventName": "RESOURCE_STALLS.SB",

+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "PublicDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB",

+    "BriefDescription": "Cycles stalled due to re-order buffer full.",

+    "PublicDescription": "Cycles stalled due to re-order buffer full.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",

+    "BriefDescription": "Cycles with pending L2 cache miss loads.",

+    "PublicDescription": "Cycles with pending L2 cache miss loads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",

+    "BriefDescription": "Cycles with pending L1 cache miss loads.",

+    "PublicDescription": "Cycles with pending L1 cache miss loads.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",

+    "BriefDescription": "Cycles with pending memory loads.",

+    "PublicDescription": "Cycles with pending memory loads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",

+    "BriefDescription": "Total execution stalls",

+    "PublicDescription": "Total execution stalls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",

+    "BriefDescription": "Execution stalls due to L2 cache misses.",

+    "PublicDescription": "Execution stalls due to L2 cache misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",

+    "BriefDescription": "Execution stalls due to memory subsystem.",

+    "PublicDescription": "Execution stalls due to memory subsystem.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",

+    "BriefDescription": "Execution stalls due to L1 data cache misses",

+    "PublicDescription": "Execution stalls due to L1 data cache misses",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.UOPS",

+    "BriefDescription": "Number of Uops delivered by the LSD.",

+    "PublicDescription": "Number of Uops delivered by the LSD.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_ACTIVE",

+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x01",

+    "EventName": "DSB2MITE_SWITCHES.COUNT",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x02",

+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAC",

+    "UMask": "0x08",

+    "EventName": "DSB_FILL.EXCEED_DSB_LINES",

+    "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

+    "PublicDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x01",

+    "EventName": "ITLB.ITLB_FLUSH",

+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "PublicDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests sent to uncore",

+    "PublicDescription": "Demand Data Read requests sent to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

+    "BriefDescription": "Cacheable and noncachaeble code read requests",

+    "PublicDescription": "Cacheable and noncachaeble code read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",

+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "PublicDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",

+    "BriefDescription": "Demand and prefetch data reads",

+    "PublicDescription": "Demand and prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.THREAD",

+    "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",

+    "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE",

+    "BriefDescription": "Number of uops executed on the core.",

+    "PublicDescription": "Number of uops executed on the core.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.STALL_CYCLES",

+    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "PublicDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",

+    "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",

+    "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x01",

+    "EventName": "TLB_FLUSH.DTLB_THREAD",

+    "BriefDescription": "DTLB flush attempts of the thread-specific entries",

+    "PublicDescription": "DTLB flush attempts of the thread-specific entries",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x20",

+    "EventName": "TLB_FLUSH.STLB_ANY",

+    "BriefDescription": "STLB flush attempts",

+    "PublicDescription": "STLB flush attempts",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBE",

+    "UMask": "0x01",

+    "EventName": "PAGE_WALKS.LLC_MISS",

+    "BriefDescription": "Number of any page walk that had a miss in LLC. ",

+    "PublicDescription": "Number of any page walk that had a miss in LLC. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",

+    "PublicDescription": "Number of instructions retired. General Counter   - architectural event",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.PREC_DIST",

+    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "Counter": "1",

+    "CounterHTOff": "1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x08",

+    "EventName": "OTHER_ASSISTS.AVX_STORE",

+    "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

+    "PublicDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x10",

+    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

+    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "PublicDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x20",

+    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

+    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "PublicDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x80",

+    "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",

+    "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "PublicDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.ALL",

+    "BriefDescription": "Actually retired uops. ",

+    "PublicDescription": "Actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x02",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used. ",

+    "PublicDescription": "Retirement slots used. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops. ",

+    "PublicDescription": "Cycles without actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Cycles with less than 10 actually retired uops. ",

+    "PublicDescription": "Cycles with less than 10 actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "10",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops. ",

+    "PublicDescription": "Cycles without actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "PublicDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-modifying code (SMC) detected.",

+    "PublicDescription": "Self-modifying code (SMC) detected.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x20",

+    "EventName": "MACHINE_CLEARS.MASKMOV",

+    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ",

+    "PublicDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x01",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Conditional branch instructions retired. ",

+    "PublicDescription": "Conditional branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x02",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect near call instructions retired. ",

+    "PublicDescription": "Direct and indirect near call instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All (macro) branch instructions retired.",

+    "PublicDescription": "All (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x08",

+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",

+    "BriefDescription": "Return instructions retired. ",

+    "PublicDescription": "Return instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x10",

+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Not taken branch instructions retired. ",

+    "PublicDescription": "Not taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x20",

+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "Taken branch instructions retired. ",

+    "PublicDescription": "Taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x40",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Far branch instructions retired. ",

+    "PublicDescription": "Far branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x04",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "All (macro) branch instructions retired. ",

+    "PublicDescription": "All (macro) branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x01",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional branch instructions retired. ",

+    "PublicDescription": "Mispredicted conditional branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All mispredicted macro branch instructions retired.",

+    "PublicDescription": "All mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. ",

+    "PublicDescription": "number of near branch instructions retired that were mispredicted and taken. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x04",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "Mispredicted macro branch instructions retired. ",

+    "PublicDescription": "Mispredicted macro branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x02",

+    "EventName": "FP_ASSIST.X87_OUTPUT",

+    "BriefDescription": "Number of X87 assists due to output value.",

+    "PublicDescription": "Number of X87 assists due to output value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x04",

+    "EventName": "FP_ASSIST.X87_INPUT",

+    "BriefDescription": "Number of X87 assists due to input value.",

+    "PublicDescription": "Number of X87 assists due to input value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x08",

+    "EventName": "FP_ASSIST.SIMD_OUTPUT",

+    "BriefDescription": "Number of SIMD FP assists due to Output values",

+    "PublicDescription": "Number of SIMD FP assists due to Output values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x10",

+    "EventName": "FP_ASSIST.SIMD_INPUT",

+    "BriefDescription": "Number of SIMD FP assists due to input values",

+    "PublicDescription": "Number of SIMD FP assists due to input values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x1E",

+    "EventName": "FP_ASSIST.ANY",

+    "BriefDescription": "Cycles with any input/output SSE or FP assist",

+    "PublicDescription": "Cycles with any input/output SSE or FP assist",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x20",

+    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",

+    "BriefDescription": "Count cases of saving new LBR",

+    "PublicDescription": "Count cases of saving new LBR",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x02",

+    "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",

+    "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. ",

+    "PublicDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. ",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

+    "BriefDescription": "Loads with latency value being above 4",

+    "PublicDescription": "Loads with latency value being above 4",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

+    "BriefDescription": "Loads with latency value being above 8",

+    "PublicDescription": "Loads with latency value being above 8",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

+    "BriefDescription": "Loads with latency value being above 16",

+    "PublicDescription": "Loads with latency value being above 16",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

+    "BriefDescription": "Loads with latency value being above 32",

+    "PublicDescription": "Loads with latency value being above 32",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

+    "BriefDescription": "Loads with latency value being above 64",

+    "PublicDescription": "Loads with latency value being above 64",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

+    "BriefDescription": "Loads with latency value being above 128",

+    "PublicDescription": "Loads with latency value being above 128",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "1009",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

+    "BriefDescription": "Loads with latency value being above 256",

+    "PublicDescription": "Loads with latency value being above 256",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "503",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

+    "BriefDescription": "Loads with latency value being above 512",

+    "PublicDescription": "Loads with latency value being above 512",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "101",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x11",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",

+    "BriefDescription": "Retired load uops that miss the STLB.",

+    "PublicDescription": "Retired load uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x12",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",

+    "BriefDescription": "Retired store uops that miss the STLB.",

+    "PublicDescription": "Retired store uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x21",

+    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",

+    "BriefDescription": "Retired load uops with locked access.",

+    "PublicDescription": "Retired load uops with locked access.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x41",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",

+    "BriefDescription": "Retired load uops that split across a cacheline boundary.",

+    "PublicDescription": "Retired load uops that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x42",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",

+    "BriefDescription": "Retired store uops that split across a cacheline boundary.",

+    "PublicDescription": "Retired store uops that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x81",

+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

+    "BriefDescription": "All retired load uops.",

+    "PublicDescription": "All retired load uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x82",

+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

+    "BriefDescription": "All retired store uops.",

+    "PublicDescription": "All retired store uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",

+    "BriefDescription": "Retired load uops with L1 cache hits as data sources. ",

+    "PublicDescription": "Retired load uops with L1 cache hits as data sources. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

+    "BriefDescription": "Retired load uops with L2 cache hits as data sources. ",

+    "PublicDescription": "Retired load uops with L2 cache hits as data sources. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",

+    "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ",

+    "PublicDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",

+    "BriefDescription": "Retired load uops which data sources following L1 data-cache miss",

+    "PublicDescription": "Retired load uops which data sources following L1 data-cache miss",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",

+    "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",

+    "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",

+    "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",

+    "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",

+    "PublicDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",

+    "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ",

+    "PublicDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",

+    "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ",

+    "PublicDescription": "Retired load uops which data sources were HitM responses from shared LLC. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",

+    "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",

+    "PublicDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",

+    "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1F",

+    "EventName": "BACLEARS.ANY",

+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x01",

+    "EventName": "L2_TRANS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests that access L2 cache",

+    "PublicDescription": "Demand Data Read requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x02",

+    "EventName": "L2_TRANS.RFO",

+    "BriefDescription": "RFO requests that access L2 cache",

+    "PublicDescription": "RFO requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x04",

+    "EventName": "L2_TRANS.CODE_RD",

+    "BriefDescription": "L2 cache accesses when fetching instructions",

+    "PublicDescription": "L2 cache accesses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x08",

+    "EventName": "L2_TRANS.ALL_PF",

+    "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",

+    "PublicDescription": "L2 or LLC HW prefetches that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANS.L1D_WB",

+    "BriefDescription": "L1D writebacks that access L2 cache",

+    "PublicDescription": "L1D writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANS.L2_FILL",

+    "BriefDescription": "L2 fill requests that access L2 cache",

+    "PublicDescription": "L2 fill requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANS.L2_WB",

+    "BriefDescription": "L2 writebacks that access L2 cache",

+    "PublicDescription": "L2 writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANS.ALL_REQUESTS",

+    "BriefDescription": "Transactions accessing L2 pipe",

+    "PublicDescription": "Transactions accessing L2 pipe",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_IN.I",

+    "BriefDescription": "L2 cache lines in I state filling L2",

+    "PublicDescription": "L2 cache lines in I state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_IN.S",

+    "BriefDescription": "L2 cache lines in S state filling L2",

+    "PublicDescription": "L2 cache lines in S state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_IN.E",

+    "BriefDescription": "L2 cache lines in E state filling L2",

+    "PublicDescription": "L2 cache lines in E state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x07",

+    "EventName": "L2_LINES_IN.ALL",

+    "BriefDescription": "L2 cache lines filling L2",

+    "PublicDescription": "L2 cache lines filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by demand",

+    "PublicDescription": "Clean L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by demand",

+    "PublicDescription": "Dirty L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_OUT.PF_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",

+    "PublicDescription": "Clean L2 cache lines evicted by L2 prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x08",

+    "EventName": "L2_LINES_OUT.PF_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",

+    "PublicDescription": "Dirty L2 cache lines evicted by L2 prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x0A",

+    "EventName": "L2_LINES_OUT.DIRTY_ALL",

+    "BriefDescription": "Dirty L2 cache lines filling the L2",

+    "PublicDescription": "Dirty L2 cache lines filling the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",

+    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",

+    "PublicDescription": "Cycles where at least 1 uop was executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 2 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 3 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 4 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x81",

+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x82",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x84",

+    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",

+    "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",

+    "PublicDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_END",

+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.COUNT",

+    "BriefDescription": "Number of machine clears (nukes) of any type. ",

+    "PublicDescription": "Number of machine clears (nukes) of any type. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_4_UOPS",

+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",

+    "PublicDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_SWITCHES",

+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",

+    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",

+    "BriefDescription": "Cycles while L2 cache miss load* is outstanding.",

+    "PublicDescription": "Cycles while L2 cache miss load* is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",

+    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",

+    "PublicDescription": "Cycles while memory subsystem has an outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",

+    "BriefDescription": "Total execution stalls.",

+    "PublicDescription": "Total execution stalls.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",

+    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",

+    "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",

+    "PublicDescription": "Execution stalls while L2 cache miss load* is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",

+    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",

+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",

+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",

+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",

+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",

+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",

+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",

+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",

+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.FB_FULL",

+    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC",

+    "PublicDescription": "Counts all demand & prefetch code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",

+    "PublicDescription": "Counts all demand & prefetch data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3004003f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",

+    "PublicDescription": "Counts all demand & prefetch RFOs that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",

+    "BriefDescription": "Counts all writebacks from the core to the LLC",

+    "PublicDescription": "Counts all writebacks from the core to the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10008",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that hit in the LLC",

+    "PublicDescription": "Counts all demand code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",

+    "PublicDescription": "Counts demand code reads that miss the LLC and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data reads that hit in the LLC",

+    "PublicDescription": "Counts all demand data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",

+    "PublicDescription": "Counts demand data reads that miss the LLC and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",

+    "PublicDescription": "Counts all demand data writes (RFOs) that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",

+    "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "PublicDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x18000",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",

+    "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address ",

+    "PublicDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10400",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",

+    "BriefDescription": "Counts non-temporal stores",

+    "PublicDescription": "Counts non-temporal stores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10800",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data reads ",

+    "PublicDescription": "Counts all demand data reads ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand rfo's ",

+    "PublicDescription": "Counts all demand rfo's ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads",

+    "PublicDescription": "Counts all demand code reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads",

+    "PublicDescription": "Counts all demand & prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x000105B3",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch prefetch RFOs ",

+    "PublicDescription": "Counts all demand & prefetch prefetch RFOs ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) ",

+    "PublicDescription": "Counts all data/code/rfo references (demand & prefetch) ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x000107F7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts LLC replacements",

+    "PublicDescription": "Counts LLC replacements",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x6004001b3",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/IVB/IvyBridge_core_V15.tsv b/x86data/perfmon_data/IVB/IvyBridge_core_V15.tsv
new file mode 100644
index 0000000..cf66a26
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_core_V15.tsv
@@ -0,0 +1,285 @@
+# Performance Monitoring Events for the Third Generation Intel Core Processors Based on the Ivy Bridge Microarchitecture - V15
+# 7/29/2015 2:28:28 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state.	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	null
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	null
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	Cases when loads get true Block-on-Store blocking code preventing store forwarding	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x03	0x08	LD_BLOCKS.NO_SR	This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare on address	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x88	DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED	Page walk for a large page completed for Demand load 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_STALLS_COUNT	Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	null
+0x0E	0x10	UOPS_ISSUED.FLAGS_MERGE	Number of flags-merge uops being allocated.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x20	UOPS_ISSUED.SLOW_LEA	Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x40	UOPS_ISSUED.SINGLE_MUL	Number of Multiply packed/scalar single precision uops allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x01	FP_COMP_OPS_EXE.X87	Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x10	FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE	Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x20	FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE	Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x40	FP_COMP_OPS_EXE.SSE_PACKED_SINGLE	Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x80	FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE	Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x11	0x01	SIMD_FP_256.PACKED_SINGLE	number of GSSE-256 Computational FP single precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x11	0x02	SIMD_FP_256.PACKED_DOUBLE	number of AVX-256 Computational FP double precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x14	0x01	ARITH.FPU_DIV_ACTIVE	Cycles when divider is busy executing divide operations	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x14	0x04	ARITH.FPU_DIV	Divide operations executed	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	null
+0x24	0x01	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x04	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x08	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x10	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x20	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x40	L2_RQSTS.PF_HIT	Requests from the L2 hardware prefetchers that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x80	L2_RQSTS.PF_MISS	Requests from the L2 hardware prefetchers that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x03	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x0C	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x30	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0xC0	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x01	L2_STORE_LOCK_RQSTS.MISS	RFOs that miss cache lines	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x08	L2_STORE_LOCK_RQSTS.HIT_M	RFOs that hit cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x0F	L2_STORE_LOCK_RQSTS.ALL	RFOs that access cache lines in any state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x01	L2_L1D_WB_RQSTS.MISS	Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x04	L2_L1D_WB_RQSTS.HIT_E	Not rejected writebacks from L1D to L2 cache lines in E state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x08	L2_L1D_WB_RQSTS.HIT_M	Not rejected writebacks from L1D to L2 cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x0F	L2_L1D_WB_RQSTS.ALL	Not rejected writebacks from L1D to L2 cache lines in any state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed LLC	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to LLC	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	2	2	2000003	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding. 	2	2	2000003	0	0	0	1	0	0	0	0	0	null
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x04	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x49	0x10	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4C	0x01	LOAD_HIT_PRE.SW_PF	Not software-prefetch load dispatches that hit FB allocated for software prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4C	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4F	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x58	0x04	MOVE_ELIMINATION.INT_NOT_ELIMINATED	Number of integer Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	null
+0x58	0x08	MOVE_ELIMINATION.SIMD_NOT_ELIMINATED	Number of SIMD Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	null
+0x58	0x01	MOVE_ELIMINATION.INT_ELIMINATED	Number of integer Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	null
+0x58	0x02	MOVE_ELIMINATION.SIMD_ELIMINATED	Number of SIMD Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	1	0	0	1	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5F	0x04	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD	Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO	Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x80	0x02	ICACHE.MISSES	Instruction cache, streaming buffer and victim cache misses	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x80	0x04	ICACHE.IFETCH_STALL	Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x02	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x04	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x85	0x10	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x80	ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED	Completed page walks in ITLB due to STLB load misses for large pages	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x87	0x04	ILD_STALL.IQ_FULL	Stall cycles because IQ is full	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x88	BR_MISP_EXEC.TAKEN_RETURN_NEAR	Taken speculative and retired mispredicted indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are dispatched to port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are dispatched to port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are dispatched to port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are dispatched to port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0_CORE	Cycles per core when uops are dispatched to port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1_CORE	Cycles per core when uops are dispatched to port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4_CORE	Cycles per core when uops are dispatched to port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5_CORE	Cycles per core when uops are dispatched to port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when load or STA uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when load or STA uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2_CORE	Uops dispatched to port 2, loads and stores per core (speculative and retired)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3_CORE	Cycles per core when load or STA uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Cycles with pending L2 cache miss loads.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Cycles with pending L1 cache miss loads.	2	2	2000003	0	0	0	8	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_LDM_PENDING	Cycles with pending memory loads.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_EXECUTE	Total execution stalls	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Execution stalls due to L2 cache misses.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_LDM_PENDING	Execution stalls due to memory subsystem.	0,1,2,3	0,1,2,3	2000003	0	0	0	6	0	0	0	0	0	null
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Execution stalls due to L1 data cache misses	2	2	2000003	0	0	0	12	0	0	0	0	0	null
+0xA8	0x01	LSD.UOPS	Number of Uops delivered by the LSD.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xAB	0x01	DSB2MITE_SWITCHES.COUNT	Decode Stream Buffer (DSB)-to-MITE switches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAC	0x08	DSB_FILL.EXCEED_DSB_LINES	Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAE	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xB0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.THREAD	Counts the number of uops to be executed per-thread each cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE	Number of uops executed on the core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.STALL_CYCLES	Counts number of cycles no uops were dispatched to be executed on this thread.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xB2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Cases when offcore requests buffer cannot take more entries for core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xBD	0x01	TLB_FLUSH.DTLB_THREAD	DTLB flush attempts of the thread-specific entries	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xBD	0x20	TLB_FLUSH.STLB_ANY	STLB flush attempts	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xBE	0x01	PAGE_WALKS.LLC_MISS	Number of any page walk that had a miss in LLC. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xC0	0x01	INST_RETIRED.PREC_DIST	Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution	1	1	2000003	0	0	0	0	0	0	0	2	0	null
+0xC1	0x08	OTHER_ASSISTS.AVX_STORE	Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x10	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x20	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x80	OTHER_ASSISTS.ANY_WB_ASSIST	Number of times any microcode assist is invoked by HW upon uop writeback.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	null
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	null
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.CORE_STALL_CYCLES	Cycles without actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	null
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3). 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC5	0x20	BR_MISP_RETIRED.NEAR_TAKEN	number of near branch instructions retired that were mispredicted and taken. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	null
+0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	null
+0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xCD	0x02	MEM_TRANS_RETIRED.PRECISE_STORE	Sample stores and collect precise store operation via PEBS record. PMC3 only. 	3	3	2000003	0	0	1	0	0	0	0	2	1	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32	3	3	100007	0x3F6	0x20	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	null
+0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	null
+0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x04	MEM_LOAD_UOPS_RETIRED.LLC_HIT	Retired load uops which data sources were data hits in LLC without snoops required. 	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	0	null
+0xD1	0x08	MEM_LOAD_UOPS_RETIRED.L1_MISS	Retired load uops which data sources following L1 data-cache miss	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x10	MEM_LOAD_UOPS_RETIRED.L2_MISS	Miss in mid-level (L2) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	0	null
+0xD1	0x20	MEM_LOAD_UOPS_RETIRED.LLC_MISS	Miss in last-level (L3) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	null
+0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD2	0x01	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x02	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x04	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared LLC. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x08	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in LLC without snoops required. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD3	0x01	MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM	Retired load uops which data sources missed LLC but serviced from local dram.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0xE6	0x1F	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x08	L2_TRANS.ALL_PF	L2 or LLC HW prefetches that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x01	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x02	L2_LINES_OUT.DEMAND_DIRTY	Dirty L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x04	L2_LINES_OUT.PF_CLEAN	Clean L2 cache lines evicted by L2 prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x08	L2_LINES_OUT.PF_DIRTY	Dirty L2 cache lines evicted by L2 prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x0A	L2_LINES_OUT.DIRTY_ALL	Dirty L2 cache lines filling the L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC	Cycles where at least 1 uop was executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC	Cycles where at least 2 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC	Cycles where at least 3 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC	Cycles where at least 4 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x08	0x81	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x82	DTLB_LOAD_MISSES.WALK_COMPLETED	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x84	DTLB_LOAD_MISSES.WALK_DURATION	Demand load cycles page miss handler (PMH) is busy with this walk.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	1	1	0	1	0	0	null
+0xC3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	null
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0xD3	0x01	MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM	Retired load uops which data sources missed LLC but serviced from local dram.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_MISS	Cycles while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	8	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_MISS	Cycles while L2 cache miss load* is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_MEM_ANY	Cycles while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.STALLS_TOTAL	Total execution stalls.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_MISS	Execution stalls while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	12	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_MISS	Execution stalls while L2 cache miss load* is outstanding.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_MEM_ANY	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3	2000003	0	0	0	6	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	1	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	2	2	2000003	0	0	0	1	0	1	0	0	0	null
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/IVB/IvyBridge_matrix_V15.json b/x86data/perfmon_data/IVB/IvyBridge_matrix_V15.json
new file mode 100644
index 0000000..d625e9a
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_matrix_V15.json
@@ -0,0 +1,191 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand data reads"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand data writes (RFOs)"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand code reads"
+  },
+  {
+    "MATRIX_REQUEST": "COREWB",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000008",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts core writebacks due to L2 evictions or L1 writeback requests"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000010",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to L2) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000020",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to L2) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000040",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000200",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "OTHER",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any other requests"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000090",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000120",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000240",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000091",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000122",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000244",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_READS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x00000003f7",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all data/code/rfo reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_REQUESTS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008fff",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all requests"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3f803c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.NO_SNOOP_NEEDED",
+    "MATRIX_VALUE": "0x01003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.SNOOP_MISS",
+    "MATRIX_VALUE": "0x02003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoops sent to sibling cores return clean response"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+    "MATRIX_VALUE": "0x04003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.HITM_OTHER_CORE",
+    "MATRIX_VALUE": "0x10003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3fffc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss in the LLC"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.LOCAL_DRAM",
+    "MATRIX_VALUE": "0x0600400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the LLC and the data returned from local dram"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_DRAM",
+    "MATRIX_VALUE": "0x067fc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the LLC and the data returned from local or remote dram"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/IVB/IvyBridge_matrix_V15.tsv b/x86data/perfmon_data/IVB/IvyBridge_matrix_V15.tsv
new file mode 100644
index 0000000..547d718
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_matrix_V15.tsv
@@ -0,0 +1,31 @@
+# Performance Monitoring Events for the Third Generation Intel Core Processors Based on the Ivy Bridge Microarchitecture - V15
+# 7/29/2015 2:28:29 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand data reads
+DEMAND_RFO	Null	0x0002	0,1	Counts all demand data writes (RFOs)
+DEMAND_CODE_RD	Null	0x0004	0,1	Counts all demand code reads
+COREWB	Null	0x0008	0,1	Counts core writebacks due to L2 evictions or L1 writeback requests
+PF_L2_DATA_RD	Null	0x0010	0,1	Counts prefetch (that bring data to L2) data reads
+PF_L2_RFO	Null	0x0020	0,1	Counts all prefetch (that bring data to L2) RFOs
+PF_L2_CODE_RD	Null	0x0040	0,1	Counts all prefetch (that bring data to LLC only) code reads
+PF_LLC_DATA_RD	Null	0x0080	0,1	Counts all prefetch (that bring data to LLC only) data reads
+PF_LLC_RFO	Null	0x0100	0,1	Counts all prefetch (that bring data to LLC only) RFOs
+PF_LLC_CODE_RD	Null	0x0200	0,1	Counts prefetch (that bring data to LLC only) code reads
+OTHER	Null	0x8000	0,1	Counts any other requests
+ALL_PF_DATA_RD	Null	0x0090	0,1	Counts all prefetch data reads
+ALL_PF_RFO	Null	0x0120	0,1	Counts prefetch RFOs
+ALL_PF_CODE_RD	Null	0x0240	0,1	Counts all prefetch code reads
+ALL_DATA_RD	Null	0x0091	0,1	Counts all demand & prefetch data reads
+ALL_RFO	Null	0x0122	0,1	Counts all demand & prefetch RFOs
+ALL_CODE_RD	Null	0x0244	0,1	Counts all demand & prefetch code reads
+ALL_READS	Null	0x03f7	0,1	Counts all data/code/rfo reads (demand & prefetch)
+ALL_REQUESTS	Null	0x8fff	0,1	Counts all requests
+Null	LLC_HIT.ANY_RESPONSE	0x3f803c	0,1	hit in the LLC
+Null	LLC_HIT.NO_SNOOP_NEEDED	0x01003c	0,1	hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
+Null	LLC_HIT.SNOOP_MISS	0x02003c	0,1	hit in the LLC and the snoops sent to sibling cores return clean response
+Null	LLC_HIT.HIT_OTHER_CORE_NO_FWD	0x04003c	0,1	hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
+Null	LLC_HIT.HITM_OTHER_CORE	0x10003c	0,1	hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
+Null	LLC_MISS.ANY_RESPONSE	0x3fffc0	0,1	miss in the LLC
+Null	LLC_MISS.LOCAL_DRAM	0x060040	0,1	miss the LLC and the data returned from local dram
+Null	LLC_MISS.ANY_DRAM	0x067fc0	0,1	miss the LLC and the data returned from local or remote dram
diff --git a/x86data/perfmon_data/IVB/IvyBridge_matrix_bit_definitions_V15.json b/x86data/perfmon_data/IVB/IvyBridge_matrix_bit_definitions_V15.json
new file mode 100644
index 0000000..42f185d
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_matrix_bit_definitions_V15.json
@@ -0,0 +1,254 @@
+[
+  {
+    "BitName": "DEMAND_DATA_RD",
+    "BitIndex": "0",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_RFO",
+    "BitIndex": "1",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_CODE_RD",
+    "BitIndex": "2",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "COREWB",
+    "BitIndex": "3",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_DATA_RD",
+    "BitIndex": "4",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_RFO",
+    "BitIndex": "5",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_CODE_RD",
+    "BitIndex": "6",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_DATA_RD",
+    "BitIndex": "7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_RFO",
+    "BitIndex": "8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_CODE_RD",
+    "BitIndex": "9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "OTHER",
+    "BitIndex": "15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_DATA_RD",
+    "BitIndex": "4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_RFO",
+    "BitIndex": "5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_CODE_RD",
+    "BitIndex": "6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_DATA_RD",
+    "BitIndex": "0,4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_RFO",
+    "BitIndex": "1,5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_CODE_RD",
+    "BitIndex": "2,6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_READS",
+    "BitIndex": "0,1,2,4,5,6,7,8,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_REQUESTS",
+    "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_RESPONSE",
+    "BitIndex": "16",
+    "Type": "2",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SUPPLIER_NONE",
+    "BitIndex": "17",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_M",
+    "BitIndex": "18",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_E",
+    "BitIndex": "19",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_S",
+    "BitIndex": "20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_F",
+    "BitIndex": "21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT",
+    "BitIndex": "18,19,20,21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_LOCAL_DRAM",
+    "BitIndex": "22",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_REMOTE_DRAM",
+    "BitIndex": "22,23,24,25,26,27,28,29,30",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NONE",
+    "BitIndex": "31",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NOT_NEEDED",
+    "BitIndex": "32",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_MISS",
+    "BitIndex": "33",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_NO_FWD",
+    "BitIndex": "34",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_WITH_FWD",
+    "BitIndex": "35",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "18,19,20,21"
+  },
+  {
+    "BitName": "SNOOP_HITM",
+    "BitIndex": "36",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NON_DRAM",
+    "BitIndex": "37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_SNOOP",
+    "BitIndex": "31,32,33,34,35,36,37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/IVB/IvyBridge_matrix_bit_definitions_V15.tsv b/x86data/perfmon_data/IVB/IvyBridge_matrix_bit_definitions_V15.tsv
new file mode 100644
index 0000000..e1a022f
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_matrix_bit_definitions_V15.tsv
@@ -0,0 +1,40 @@
+# Performance Monitoring Events for the Third Generation Intel Core Processors Based on the Ivy Bridge Microarchitecture - V15
+# 7/29/2015 2:28:29 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	Type	MATRIX_REG	BitsNotCombinedWith
+DEMAND_DATA_RD	0	1	0,1	Null
+DEMAND_RFO	1	1	0,1	Null
+DEMAND_CODE_RD	2	1	0,1	Null
+COREWB	3	1	0,1	Null
+PF_L2_DATA_RD	4	1	0,1	Null
+PF_L2_RFO	5	1	0,1	Null
+PF_L2_CODE_RD	6	1	0,1	Null
+PF_LLC_DATA_RD	7	1	0,1	Null
+PF_LLC_RFO	8	1	0,1	Null
+PF_LLC_CODE_RD	9	1	0,1	Null
+OTHER	15	1	0,1	Null
+ALL_PF_DATA_RD	4,7	1	0,1	Null
+ALL_PF_RFO	5,8	1	0,1	Null
+ALL_PF_CODE_RD	6,9	1	0,1	Null
+ALL_DATA_RD	0,4,7	1	0,1	Null
+ALL_RFO	1,5,8	1	0,1	Null
+ALL_CODE_RD	2,6,9	1	0,1	Null
+ALL_READS	0,1,2,4,5,6,7,8,9	1	0,1	Null
+ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	0,1	Null
+ANY_RESPONSE	16	2	0,1	Null
+SUPPLIER_NONE	17	3	0,1	Null
+LLC_HIT_M	18	3	0,1	Null
+LLC_HIT_E	19	3	0,1	Null
+LLC_HIT_S	20	3	0,1	Null
+LLC_HIT_F	21	3	0,1	Null
+LLC_HIT	18,19,20,21	3	0,1	Null
+L3_MISS_LOCAL_DRAM	22	3	0,1	Null
+L3_MISS_REMOTE_DRAM	22,23,24,25,26,27,28,29,30	3	0,1	Null
+SNOOP_NONE	31	4	0,1	Null
+SNOOP_NOT_NEEDED	32	4	0,1	Null
+SNOOP_MISS	33	4	0,1	Null
+SNOOP_HIT_NO_FWD	34	4	0,1	Null
+SNOOP_HIT_WITH_FWD	35	4	0,1	18,19,20,21
+SNOOP_HITM	36	4	0,1	Null
+SNOOP_NON_DRAM	37	4	0,1	Null
+ANY_SNOOP	31,32,33,34,35,36,37	4	0,1	Null
diff --git a/x86data/perfmon_data/IVB/IvyBridge_offcore_V15.tsv b/x86data/perfmon_data/IVB/IvyBridge_offcore_V15.tsv
new file mode 100644
index 0000000..82766b2
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_offcore_V15.tsv
@@ -0,0 +1,77 @@
+# Performance Monitoring Events for the Third Generation Intel Core Processors Based on the Ivy Bridge Microarchitecture - V15
+# 7/29/2015 2:28:29 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand & prefetch code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM_0	Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand & prefetch data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM_0	Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch RFOs that hit in the LLC	0	0	100003	0x1a6	0x3f803c0120	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0120	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM_0	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x3004003f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCE.ANY_RESPONSE_0	Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC 	0	0	100003	0x1a6	0x103F7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE_0	Counts all demand & prefetch RFOs that hit in the LLC	0	0	100003	0x1a6	0x3f803c0122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_0	Counts all writebacks from the core to the LLC	0	0	100003	0x1a6	0x10008	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM_0	Counts demand code reads that miss the LLC and the data returned from dram	0	0	100003	0x1a6	0x300400004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM_0	Counts demand data reads that miss the LLC and the data returned from dram	0	0	100003	0x1a6	0x300400001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE_0	Counts all demand data writes (RFOs) that hit in the LLC	0	0	100003	0x1a6	0x3f803c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_0	Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.OTHER.ANY_RESPONSE_0	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches	0	0	100003	0x1a6	0x18000	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_0	Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address 	0	0	100003	0x1a6	0x10400	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_0	Counts non-temporal stores	0	0	100003	0x1a6	0x10800	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand & prefetch code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM_1	Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand & prefetch data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM_1	Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC	3	3	100003	0x1a7	0x3f803c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED_1	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM_1	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x3004003f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCE_ANY.ANY_RESPONSE_1	Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC 	3	3	100003	0x1a7	0x103F7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE_1	Counts all demand & prefetch RFOs that hit in the LLC	3	3	100003	0x1a7	0x3f803c0122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_1	Counts all writebacks from the core to the LLC	3	3	100003	0x1a7	0x10008	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM_1	Counts demand code reads that miss the LLC and the data returned from dram	3	3	100003	0x1a7	0x300400004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM_1	Counts demand data reads that miss the LLC and the data returned from dram	3	3	100003	0x1a7	0x300400001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE_1	Counts all demand data writes (RFOs) that hit in the LLC	3	3	100003	0x1a7	0x3f803c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_1	Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.ANY_RESPONSE_1	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches	3	3	100003	0x1a7	0x18000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC_1	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses	3	3	100003	0x1a7	0x2380408000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_1	Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address 	3	3	100003	0x1a7	0x10400	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_1	Counts non-temporal stores	3	3	100003	0x1a7	0x10800	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE_0	Counts all demand data reads 	0	0	100003	0x1A6	0x00010001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE_0	Counts all demand rfo's 	0	0	100003	0x1A6	0x00010002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE_0	Counts all demand code reads	0	0	100003	0x1A6	0x00010004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE_0	Counts all demand & prefetch data reads	0	0	100003	0x1A6	0x000105B3	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE_0	Counts all demand & prefetch prefetch RFOs 	0	0	100003	0x1A6	0x00010122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE_0	Counts all data/code/rfo references (demand & prefetch) 	0	0	100003	0x1A6	0x000107F7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM_0	Counts LLC replacements	0	0	100003	0x1A6	0x6004001b3	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE_1	Counts all demand data reads 	3	3	100003	0x1A7	0x00010001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE_1	Counts all demand rfo's 	3	3	100003	0x1A7	0x00010002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE_1	Counts all demand code reads	3	3	100003	0x1A7	0x00010004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE_1	Counts all demand & prefetch data reads	3	3	100003	0x1A7	0x000105B3	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE_1	Counts all demand & prefetch prefetch RFOs 	3	3	100003	0x1A7	0x00010122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE_1	Counts all data/code/rfo references (demand & prefetch) 	3	3	100003	0x1A7	0x000107F7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM_1	Counts LLC replacements	3	3	100003	0x1A7	0x6004001b3	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/IVB/IvyBridge_uncore_V15.json b/x86data/perfmon_data/IVB/IvyBridge_uncore_V15.json
new file mode 100644
index 0000000..a3cef94
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_uncore_V15.json
@@ -0,0 +1,314 @@
+[
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x01",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS",
+    "BriefDescription": "A snoop misses in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x02",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL",
+    "BriefDescription": "A snoop invalidates a non-modified line in some processor core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x04",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT",
+    "BriefDescription": "A snoop hits a non-modified line in some processor core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x08",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM",
+    "BriefDescription": "A snoop hits a modified line in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x10",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M",
+    "BriefDescription": "A snoop invalidates a modified line in some processor core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x20",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER",
+    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x40",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER",
+    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x80",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER",
+    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x01",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.M",
+    "BriefDescription": "LLC lookup request that access cache and found line in M-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x02",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.E",
+    "BriefDescription": "LLC lookup request that access cache and found line in E-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x04",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.S",
+    "BriefDescription": "LLC lookup request that access cache and found line in S-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x08",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.I",
+    "BriefDescription": "LLC lookup request that access cache and found line in I-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x10",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER",
+    "BriefDescription": "Filter on processor core initiated cacheable read requests.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x20",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER",
+    "BriefDescription": "Filter on processor core initiated cacheable write requests.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x40",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER",
+    "BriefDescription": "Filter on external snoop requests.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x80",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER",
+    "BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+    "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x81",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+    "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x81",
+    "UMask": "0x20",
+    "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
+    "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x81",
+    "UMask": "0x80",
+    "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
+    "BriefDescription": "Counts the number of LLC evictions allocated.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x83",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
+    "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x84",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+    "BriefDescription": "Number of requests allocated in Coherency Tracker.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
+    "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "1",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
+    "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "10",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x0",
+    "UMask": "0x01",
+    "EventName": "UNC_CLOCK.SOCKET",
+    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
+    "PublicDescription": "tbd",
+    "Counter": "Fixed",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x06",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ES",
+    "BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/IVB/IvyBridge_uncore_V15.tsv b/x86data/perfmon_data/IVB/IvyBridge_uncore_V15.tsv
new file mode 100644
index 0000000..ada0e26
--- /dev/null
+++ b/x86data/perfmon_data/IVB/IvyBridge_uncore_V15.tsv
@@ -0,0 +1,30 @@
+# Performance Monitoring Events for the Third Generation Intel Core Processors Based on the Ivy Bridge Microarchitecture - V15
+# 7/29/2015 2:28:28 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+Unit	EventCode	UMask	EventName	Description	Counter	CounterMask	Invert	EdgeDetect
+CBO	0x22	0x01	UNC_CBO_XSNP_RESPONSE.MISS	A snoop misses in some processor core.	0,1	0	0	0
+CBO	0x22	0x02	UNC_CBO_XSNP_RESPONSE.INVAL	A snoop invalidates a non-modified line in some processor core	0,1	0	0	0
+CBO	0x22	0x04	UNC_CBO_XSNP_RESPONSE.HIT	A snoop hits a non-modified line in some processor core	0,1	0	0	0
+CBO	0x22	0x08	UNC_CBO_XSNP_RESPONSE.HITM	A snoop hits a modified line in some processor core.	0,1	0	0	0
+CBO	0x22	0x10	UNC_CBO_XSNP_RESPONSE.INVAL_M	A snoop invalidates a modified line in some processor core	0,1	0	0	0
+CBO	0x22	0x20	UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER	Filter on cross-core snoops initiated by this Cbox due to external snoop request.	0,1	0	0	0
+CBO	0x22	0x40	UNC_CBO_XSNP_RESPONSE.XCORE_FILTER	Filter on cross-core snoops initiated by this Cbox due to processor core memory request.	0,1	0	0	0
+CBO	0x22	0x80	UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER	Filter on cross-core snoops initiated by this Cbox due to LLC eviction.	0,1	0	0	0
+CBO	0x34	0x01	UNC_CBO_CACHE_LOOKUP.M	LLC lookup request that access cache and found line in M-state.	0,1	0	0	0
+CBO	0x34	0x02	UNC_CBO_CACHE_LOOKUP.E	LLC lookup request that access cache and found line in E-state.	0,1	0	0	0
+CBO	0x34	0x04	UNC_CBO_CACHE_LOOKUP.S	LLC lookup request that access cache and found line in S-state.	0,1	0	0	0
+CBO	0x34	0x08	UNC_CBO_CACHE_LOOKUP.I	LLC lookup request that access cache and found line in I-state.	0,1	0	0	0
+CBO	0x34	0x10	UNC_CBO_CACHE_LOOKUP.READ_FILTER	Filter on processor core initiated cacheable read requests.	0,1	0	0	0
+CBO	0x34	0x20	UNC_CBO_CACHE_LOOKUP.WRITE_FILTER	Filter on processor core initiated cacheable write requests.	0,1	0	0	0
+CBO	0x34	0x40	UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER	Filter on external snoop requests.	0,1	0	0	0
+CBO	0x34	0x80	UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER	Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.	0,1	0	0	0
+ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.ALL	Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.	0	0	0	0
+ARB	0x81	0x01	UNC_ARB_TRK_REQUESTS.ALL	Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.	0,1	0	0	0
+ARB	0x81	0x20	UNC_ARB_TRK_REQUESTS.WRITES	Counts the number of allocated write entries, include full, partial, and LLC evictions.	0,1	0	0	0
+ARB	0x81	0x80	UNC_ARB_TRK_REQUESTS.EVICTIONS	Counts the number of LLC evictions allocated.	0,1	0	0	0
+ARB	0x83	0x01	UNC_ARB_COH_TRK_OCCUPANCY.ALL	Cycles weighted by number of requests pending in Coherency Tracker.	0	0	0	0
+ARB	0x84	0x01	UNC_ARB_COH_TRK_REQUESTS.ALL	Number of requests allocated in Coherency Tracker.	0,1	0	0	0
+ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST	Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.	0,1	1	0	0
+ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL	Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.	0,1	10	0	0
+ARB	0x0	0x01	UNC_CLOCK.SOCKET	This 48-bit fixed counter counts the UCLK cycles	Fixed	0	0	0
+CBO	0x34	0x06	UNC_CBO_CACHE_LOOKUP.ES	LLC lookup request that access cache and found line in E-state or S-state.	0	0	0	0
diff --git a/x86data/perfmon_data/IVT/IvyTown_core_V17.json b/x86data/perfmon_data/IVT/IvyTown_core_V17.json
new file mode 100644
index 0000000..3b1158b
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_core_V17.json
@@ -0,0 +1,7331 @@
+[

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired from execution.",

+    "PublicDescription": "Instructions retired from execution.",

+    "Counter": "Fixed counter 1",

+    "CounterHTOff": "Fixed counter 1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Core cycles when the thread is not in halt state.",

+    "PublicDescription": "Core cycles when the thread is not in halt state.",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Reference cycles when the core is not in halt state.",

+    "PublicDescription": "Reference cycles when the core is not in halt state.",

+    "Counter": "Fixed counter 3",

+    "CounterHTOff": "Fixed counter 3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "LD_BLOCKS.STORE_FORWARD",

+    "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",

+    "PublicDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS.NO_SR",

+    "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "PublicDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "MISALIGN_MEM_REF.LOADS",

+    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "MISALIGN_MEM_REF.STORES",

+    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies in MOB due to partial compare on address",

+    "PublicDescription": "False dependencies in MOB due to partial compare on address",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x82",

+    "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x84",

+    "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION",

+    "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",

+    "PublicDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x88",

+    "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",

+    "BriefDescription": "Page walk for a large page completed for Demand load ",

+    "PublicDescription": "Page walk for a large page completed for Demand load ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES",

+    "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_STALLS_COUNT",

+    "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "PublicDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x10",

+    "EventName": "UOPS_ISSUED.FLAGS_MERGE",

+    "BriefDescription": "Number of flags-merge uops being allocated.",

+    "PublicDescription": "Number of flags-merge uops being allocated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x20",

+    "EventName": "UOPS_ISSUED.SLOW_LEA",

+    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x40",

+    "EventName": "UOPS_ISSUED.SINGLE_MUL",

+    "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "PublicDescription": "Number of Multiply packed/scalar single precision uops allocated",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x01",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

+    "PublicDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x11",

+    "UMask": "0x01",

+    "EventName": "SIMD_FP_256.PACKED_SINGLE",

+    "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

+    "PublicDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x11",

+    "UMask": "0x02",

+    "EventName": "SIMD_FP_256.PACKED_DOUBLE",

+    "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

+    "PublicDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x01",

+    "EventName": "ARITH.FPU_DIV_ACTIVE",

+    "BriefDescription": "Cycles when divider is busy executing divide operations",

+    "PublicDescription": "Cycles when divider is busy executing divide operations",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x04",

+    "EventName": "ARITH.FPU_DIV",

+    "BriefDescription": "Divide operations executed",

+    "PublicDescription": "Divide operations executed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x01",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",

+    "BriefDescription": "Demand Data Read requests that hit L2 cache",

+    "PublicDescription": "Demand Data Read requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x04",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "RFO requests that hit L2 cache",

+    "PublicDescription": "RFO requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x08",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "RFO requests that miss L2 cache",

+    "PublicDescription": "RFO requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.CODE_RD_HIT",

+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",

+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.CODE_RD_MISS",

+    "BriefDescription": "L2 cache misses when fetching instructions",

+    "PublicDescription": "L2 cache misses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PF_HIT",

+    "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",

+    "PublicDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PF_MISS",

+    "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",

+    "PublicDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x03",

+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests",

+    "PublicDescription": "Demand Data Read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x0C",

+    "EventName": "L2_RQSTS.ALL_RFO",

+    "BriefDescription": "RFO requests to L2 cache",

+    "PublicDescription": "RFO requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.ALL_CODE_RD",

+    "BriefDescription": "L2 code requests",

+    "PublicDescription": "L2 code requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.ALL_PF",

+    "BriefDescription": "Requests from L2 hardware prefetchers",

+    "PublicDescription": "Requests from L2 hardware prefetchers",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x01",

+    "EventName": "L2_STORE_LOCK_RQSTS.MISS",

+    "BriefDescription": "RFOs that miss cache lines",

+    "PublicDescription": "RFOs that miss cache lines",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x08",

+    "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",

+    "BriefDescription": "RFOs that hit cache lines in M state",

+    "PublicDescription": "RFOs that hit cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x0F",

+    "EventName": "L2_STORE_LOCK_RQSTS.ALL",

+    "BriefDescription": "RFOs that access cache lines in any state",

+    "PublicDescription": "RFOs that access cache lines in any state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x01",

+    "EventName": "L2_L1D_WB_RQSTS.MISS",

+    "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",

+    "PublicDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x04",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_E",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x08",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_M",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x0F",

+    "EventName": "L2_L1D_WB_RQSTS.ALL",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Core-originated cacheable demand requests missed LLC",

+    "PublicDescription": "Core-originated cacheable demand requests missed LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",

+    "PublicDescription": "Core-originated cacheable demand requests that refer to LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Thread cycles when thread is not in halt state",

+    "PublicDescription": "Thread cycles when thread is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",

+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",

+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",

+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING",

+    "BriefDescription": "L1D miss oustandings duration in cycles",

+    "PublicDescription": "L1D miss oustandings duration in cycles",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",

+    "BriefDescription": "Cycles with L1D load Misses outstanding. ",

+    "PublicDescription": "Cycles with L1D load Misses outstanding. ",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x01",

+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x02",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x04",

+    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "Cycles when PMH is busy with page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",

+    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x01",

+    "EventName": "LOAD_HIT_PRE.SW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x02",

+    "EventName": "LOAD_HIT_PRE.HW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4F",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",

+    "PublicDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x01",

+    "EventName": "L1D.REPLACEMENT",

+    "BriefDescription": "L1D data line replacements",

+    "PublicDescription": "L1D data line replacements",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x04",

+    "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x08",

+    "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x01",

+    "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",

+    "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of integer Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x58",

+    "UMask": "0x02",

+    "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

+    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "1000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0",

+    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

+    "PublicDescription": "Unhalted core cycles when the thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x02",

+    "EventName": "CPL_CYCLES.RING123",

+    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "PublicDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0_TRANS",

+    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "PublicDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_CYCLES",

+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "PublicDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5F",

+    "UMask": "0x04",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",

+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "PublicDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",

+    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",

+    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x01",

+    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "PublicDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x02",

+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1D is locked",

+    "PublicDescription": "Cycles when L1D is locked",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x02",

+    "EventName": "IDQ.EMPTY",

+    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "PublicDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_UOPS",

+    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x20",

+    "EventName": "IDQ.MS_MITE_UOPS",

+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_CYCLES",

+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_OCCUR",

+    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles MITE is delivering 4 Uops",

+    "PublicDescription": "Cycles MITE is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles MITE is delivering any Uop",

+    "PublicDescription": "Cycles MITE is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x3c",

+    "EventName": "IDQ.MITE_ALL_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x01",

+    "EventName": "ICACHE.HIT",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x02",

+    "EventName": "ICACHE.MISSES",

+    "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",

+    "PublicDescription": "Instruction cache, streaming buffer and victim cache misses",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x04",

+    "EventName": "ICACHE.IFETCH_STALL",

+    "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",

+    "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x01",

+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Misses at all ITLB levels that cause page walks",

+    "PublicDescription": "Misses at all ITLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x02",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Misses in all ITLB levels that cause completed page walks",

+    "PublicDescription": "Misses in all ITLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x04",

+    "EventName": "ITLB_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "Cycles when PMH is busy with page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x10",

+    "EventName": "ITLB_MISSES.STLB_HIT",

+    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x80",

+    "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",

+    "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",

+    "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x01",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

+    "PublicDescription": "Stalls caused by changing prefix length of the instruction.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x04",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Stall cycles because IQ is full",

+    "PublicDescription": "Stall cycles because IQ is full",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x41",

+    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken macro-conditional branches",

+    "PublicDescription": "Not taken macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x81",

+    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired macro-conditional branches",

+    "PublicDescription": "Taken speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x82",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",

+    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x84",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x88",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x90",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired direct near calls",

+    "PublicDescription": "Taken speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xA0",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired indirect calls",

+    "PublicDescription": "Taken speculative and retired indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC1",

+    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired macro-conditional branches",

+    "PublicDescription": "Speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC2",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",

+    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC4",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC8",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Speculative and retired indirect return branches.",

+    "PublicDescription": "Speculative and retired indirect return branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xD0",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired direct near calls",

+    "PublicDescription": "Speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xFF",

+    "EventName": "BR_INST_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired  branches",

+    "PublicDescription": "Speculative and retired  branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x41",

+    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x81",

+    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x84",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x88",

+    "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xA0",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect calls",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC1",

+    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC4",

+    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xFF",

+    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",

+    "PublicDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "PublicDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "PublicDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 0",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 1",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 4",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 5",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 0",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 1",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 4",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 5",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x0C",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",

+    "PublicDescription": "Cycles per thread when load or STA uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x30",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",

+    "PublicDescription": "Cycles per thread when load or STA uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x0C",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",

+    "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired)",

+    "PublicDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x30",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",

+    "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",

+    "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x01",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource-related stall cycles",

+    "PublicDescription": "Resource-related stall cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x04",

+    "EventName": "RESOURCE_STALLS.RS",

+    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",

+    "PublicDescription": "Cycles stalled due to no eligible RS entry available.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x08",

+    "EventName": "RESOURCE_STALLS.SB",

+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "PublicDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB",

+    "BriefDescription": "Cycles stalled due to re-order buffer full.",

+    "PublicDescription": "Cycles stalled due to re-order buffer full.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",

+    "BriefDescription": "Cycles with pending L2 cache miss loads.",

+    "PublicDescription": "Cycles with pending L2 cache miss loads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",

+    "BriefDescription": "Cycles with pending L1 cache miss loads.",

+    "PublicDescription": "Cycles with pending L1 cache miss loads.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",

+    "BriefDescription": "Cycles with pending memory loads.",

+    "PublicDescription": "Cycles with pending memory loads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",

+    "BriefDescription": "Total execution stalls",

+    "PublicDescription": "Total execution stalls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",

+    "BriefDescription": "Execution stalls due to L2 cache misses.",

+    "PublicDescription": "Execution stalls due to L2 cache misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",

+    "BriefDescription": "Execution stalls due to memory subsystem.",

+    "PublicDescription": "Execution stalls due to memory subsystem.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",

+    "BriefDescription": "Execution stalls due to L1 data cache misses",

+    "PublicDescription": "Execution stalls due to L1 data cache misses",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.UOPS",

+    "BriefDescription": "Number of Uops delivered by the LSD.",

+    "PublicDescription": "Number of Uops delivered by the LSD.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_ACTIVE",

+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x01",

+    "EventName": "DSB2MITE_SWITCHES.COUNT",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x02",

+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAC",

+    "UMask": "0x08",

+    "EventName": "DSB_FILL.EXCEED_DSB_LINES",

+    "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

+    "PublicDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x01",

+    "EventName": "ITLB.ITLB_FLUSH",

+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "PublicDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests sent to uncore",

+    "PublicDescription": "Demand Data Read requests sent to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

+    "BriefDescription": "Cacheable and noncachaeble code read requests",

+    "PublicDescription": "Cacheable and noncachaeble code read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",

+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "PublicDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",

+    "BriefDescription": "Demand and prefetch data reads",

+    "PublicDescription": "Demand and prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.THREAD",

+    "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",

+    "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE",

+    "BriefDescription": "Number of uops executed on the core.",

+    "PublicDescription": "Number of uops executed on the core.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.STALL_CYCLES",

+    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "PublicDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",

+    "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",

+    "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x01",

+    "EventName": "TLB_FLUSH.DTLB_THREAD",

+    "BriefDescription": "DTLB flush attempts of the thread-specific entries",

+    "PublicDescription": "DTLB flush attempts of the thread-specific entries",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x20",

+    "EventName": "TLB_FLUSH.STLB_ANY",

+    "BriefDescription": "STLB flush attempts",

+    "PublicDescription": "STLB flush attempts",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",

+    "PublicDescription": "Number of instructions retired. General Counter   - architectural event",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.PREC_DIST",

+    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "Counter": "1",

+    "CounterHTOff": "1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x08",

+    "EventName": "OTHER_ASSISTS.AVX_STORE",

+    "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

+    "PublicDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x10",

+    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

+    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "PublicDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x20",

+    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

+    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "PublicDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x80",

+    "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",

+    "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "PublicDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.ALL",

+    "BriefDescription": "Actually retired uops. ",

+    "PublicDescription": "Actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x02",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used. ",

+    "PublicDescription": "Retirement slots used. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops. ",

+    "PublicDescription": "Cycles without actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Cycles with less than 10 actually retired uops. ",

+    "PublicDescription": "Cycles with less than 10 actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "10",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops. ",

+    "PublicDescription": "Cycles without actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "PublicDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-modifying code (SMC) detected.",

+    "PublicDescription": "Self-modifying code (SMC) detected.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x20",

+    "EventName": "MACHINE_CLEARS.MASKMOV",

+    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ",

+    "PublicDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x01",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Conditional branch instructions retired. ",

+    "PublicDescription": "Conditional branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x02",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect near call instructions retired. ",

+    "PublicDescription": "Direct and indirect near call instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All (macro) branch instructions retired.",

+    "PublicDescription": "All (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x08",

+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",

+    "BriefDescription": "Return instructions retired. ",

+    "PublicDescription": "Return instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x10",

+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Not taken branch instructions retired. ",

+    "PublicDescription": "Not taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x20",

+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "Taken branch instructions retired. ",

+    "PublicDescription": "Taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x40",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Far branch instructions retired. ",

+    "PublicDescription": "Far branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x04",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "All (macro) branch instructions retired. ",

+    "PublicDescription": "All (macro) branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x01",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional branch instructions retired. ",

+    "PublicDescription": "Mispredicted conditional branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All mispredicted macro branch instructions retired.",

+    "PublicDescription": "All mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. ",

+    "PublicDescription": "number of near branch instructions retired that were mispredicted and taken. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x04",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "Mispredicted macro branch instructions retired. ",

+    "PublicDescription": "Mispredicted macro branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x02",

+    "EventName": "FP_ASSIST.X87_OUTPUT",

+    "BriefDescription": "Number of X87 assists due to output value.",

+    "PublicDescription": "Number of X87 assists due to output value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x04",

+    "EventName": "FP_ASSIST.X87_INPUT",

+    "BriefDescription": "Number of X87 assists due to input value.",

+    "PublicDescription": "Number of X87 assists due to input value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x08",

+    "EventName": "FP_ASSIST.SIMD_OUTPUT",

+    "BriefDescription": "Number of SIMD FP assists due to Output values",

+    "PublicDescription": "Number of SIMD FP assists due to Output values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x10",

+    "EventName": "FP_ASSIST.SIMD_INPUT",

+    "BriefDescription": "Number of SIMD FP assists due to input values",

+    "PublicDescription": "Number of SIMD FP assists due to input values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x1E",

+    "EventName": "FP_ASSIST.ANY",

+    "BriefDescription": "Cycles with any input/output SSE or FP assist",

+    "PublicDescription": "Cycles with any input/output SSE or FP assist",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x20",

+    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",

+    "BriefDescription": "Count cases of saving new LBR",

+    "PublicDescription": "Count cases of saving new LBR",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x02",

+    "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",

+    "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. ",

+    "PublicDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. ",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

+    "BriefDescription": "Loads with latency value being above 4",

+    "PublicDescription": "Loads with latency value being above 4",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

+    "BriefDescription": "Loads with latency value being above 8",

+    "PublicDescription": "Loads with latency value being above 8",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

+    "BriefDescription": "Loads with latency value being above 16",

+    "PublicDescription": "Loads with latency value being above 16",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

+    "BriefDescription": "Loads with latency value being above 32",

+    "PublicDescription": "Loads with latency value being above 32",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

+    "BriefDescription": "Loads with latency value being above 64",

+    "PublicDescription": "Loads with latency value being above 64",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

+    "BriefDescription": "Loads with latency value being above 128",

+    "PublicDescription": "Loads with latency value being above 128",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "1009",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

+    "BriefDescription": "Loads with latency value being above 256",

+    "PublicDescription": "Loads with latency value being above 256",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "503",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

+    "BriefDescription": "Loads with latency value being above 512",

+    "PublicDescription": "Loads with latency value being above 512",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "101",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x11",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",

+    "BriefDescription": "Retired load uops that miss the STLB.",

+    "PublicDescription": "Retired load uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x12",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",

+    "BriefDescription": "Retired store uops that miss the STLB.",

+    "PublicDescription": "Retired store uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x21",

+    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",

+    "BriefDescription": "Retired load uops with locked access.",

+    "PublicDescription": "Retired load uops with locked access.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x41",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",

+    "BriefDescription": "Retired load uops that split across a cacheline boundary.",

+    "PublicDescription": "Retired load uops that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x42",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",

+    "BriefDescription": "Retired store uops that split across a cacheline boundary.",

+    "PublicDescription": "Retired store uops that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x81",

+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

+    "BriefDescription": "All retired load uops.",

+    "PublicDescription": "All retired load uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x82",

+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

+    "BriefDescription": "All retired store uops.",

+    "PublicDescription": "All retired store uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",

+    "BriefDescription": "Retired load uops with L1 cache hits as data sources. ",

+    "PublicDescription": "Retired load uops with L1 cache hits as data sources. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

+    "BriefDescription": "Retired load uops with L2 cache hits as data sources. ",

+    "PublicDescription": "Retired load uops with L2 cache hits as data sources. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",

+    "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ",

+    "PublicDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",

+    "BriefDescription": "Retired load uops which data sources following L1 data-cache miss",

+    "PublicDescription": "Retired load uops which data sources following L1 data-cache miss",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",

+    "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",

+    "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",

+    "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",

+    "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",

+    "PublicDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",

+    "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ",

+    "PublicDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",

+    "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ",

+    "PublicDescription": "Retired load uops which data sources were HitM responses from shared LLC. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",

+    "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",

+    "PublicDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",

+    "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x0C",

+    "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",

+    "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)",

+    "PublicDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM",

+    "BriefDescription": "Remote cache HITM",

+    "PublicDescription": "Remote cache HITM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD",

+    "BriefDescription": "Data forwarded from remote cache",

+    "PublicDescription": "Data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1F",

+    "EventName": "BACLEARS.ANY",

+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x01",

+    "EventName": "L2_TRANS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests that access L2 cache",

+    "PublicDescription": "Demand Data Read requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x02",

+    "EventName": "L2_TRANS.RFO",

+    "BriefDescription": "RFO requests that access L2 cache",

+    "PublicDescription": "RFO requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x04",

+    "EventName": "L2_TRANS.CODE_RD",

+    "BriefDescription": "L2 cache accesses when fetching instructions",

+    "PublicDescription": "L2 cache accesses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x08",

+    "EventName": "L2_TRANS.ALL_PF",

+    "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",

+    "PublicDescription": "L2 or LLC HW prefetches that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANS.L1D_WB",

+    "BriefDescription": "L1D writebacks that access L2 cache",

+    "PublicDescription": "L1D writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANS.L2_FILL",

+    "BriefDescription": "L2 fill requests that access L2 cache",

+    "PublicDescription": "L2 fill requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANS.L2_WB",

+    "BriefDescription": "L2 writebacks that access L2 cache",

+    "PublicDescription": "L2 writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANS.ALL_REQUESTS",

+    "BriefDescription": "Transactions accessing L2 pipe",

+    "PublicDescription": "Transactions accessing L2 pipe",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_IN.I",

+    "BriefDescription": "L2 cache lines in I state filling L2",

+    "PublicDescription": "L2 cache lines in I state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_IN.S",

+    "BriefDescription": "L2 cache lines in S state filling L2",

+    "PublicDescription": "L2 cache lines in S state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_IN.E",

+    "BriefDescription": "L2 cache lines in E state filling L2",

+    "PublicDescription": "L2 cache lines in E state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x07",

+    "EventName": "L2_LINES_IN.ALL",

+    "BriefDescription": "L2 cache lines filling L2",

+    "PublicDescription": "L2 cache lines filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by demand",

+    "PublicDescription": "Clean L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by demand",

+    "PublicDescription": "Dirty L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_OUT.PF_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",

+    "PublicDescription": "Clean L2 cache lines evicted by L2 prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x08",

+    "EventName": "L2_LINES_OUT.PF_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",

+    "PublicDescription": "Dirty L2 cache lines evicted by L2 prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x0A",

+    "EventName": "L2_LINES_OUT.DIRTY_ALL",

+    "BriefDescription": "Dirty L2 cache lines filling the L2",

+    "PublicDescription": "Dirty L2 cache lines filling the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",

+    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",

+    "PublicDescription": "Cycles where at least 1 uop was executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 2 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 3 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 4 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x81",

+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x82",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x84",

+    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",

+    "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",

+    "PublicDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_END",

+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.COUNT",

+    "BriefDescription": "Number of machine clears (nukes) of any type. ",

+    "PublicDescription": "Number of machine clears (nukes) of any type. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_4_UOPS",

+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_SWITCHES",

+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",

+    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",

+    "BriefDescription": "Cycles while L2 cache miss load* is outstanding.",

+    "PublicDescription": "Cycles while L2 cache miss load* is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",

+    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",

+    "PublicDescription": "Cycles while memory subsystem has an outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",

+    "BriefDescription": "Total execution stalls.",

+    "PublicDescription": "Total execution stalls.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",

+    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",

+    "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",

+    "PublicDescription": "Execution stalls while L2 cache miss load* is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",

+    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",

+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",

+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",

+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",

+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",

+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",

+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",

+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",

+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.FB_FULL",

+    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC",

+    "PublicDescription": "Counts all demand & prefetch code reads that miss the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc00244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dram",

+    "PublicDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67f800244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cache",

+    "PublicDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x87f800244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads that hits the LLC",

+    "PublicDescription": "Counts all demand & prefetch data reads that hits the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch data reads that hit the LLC",

+    "PublicDescription": "Counts all prefetch data reads that hit the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc203f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dram",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x6004003f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cache",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x87f8203f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc003f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",

+    "BriefDescription": "Counts all writebacks from the core to the LLC",

+    "PublicDescription": "Counts all writebacks from the core to the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10008",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that hit in the LLC",

+    "PublicDescription": "Counts all demand code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that miss the LLC",

+    "PublicDescription": "Counts all demand code reads that miss the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",

+    "PublicDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x600400004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",

+    "PublicDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67f800004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",

+    "PublicDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x87f820004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "PublicDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc00004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data reads that hit in the LLC",

+    "PublicDescription": "Counts all demand data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",

+    "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",

+    "PublicDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67fc00001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts demand data reads that miss in the LLC",

+    "PublicDescription": "Counts demand data reads that miss in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",

+    "PublicDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x600400001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",

+    "PublicDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67f800001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",

+    "PublicDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x87f820001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "PublicDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc00001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",

+    "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "PublicDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x803c8000",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",

+    "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",

+    "PublicDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x23ffc08000",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67fc00010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x600400010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67f800010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x87f820010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc00010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",

+    "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",

+    "PublicDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10400",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",

+    "BriefDescription": "Counts non-temporal stores",

+    "PublicDescription": "Counts non-temporal stores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10800",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/IVT/IvyTown_core_V17.tsv b/x86data/perfmon_data/IVT/IvyTown_core_V17.tsv
new file mode 100644
index 0000000..e36c59b
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_core_V17.tsv
@@ -0,0 +1,288 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family and Intel(R) Xeon(R) processor E7 family Based on the Ivy Bridge-EP Microarchitecture - V17
+# 7/29/2015 2:56:14 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state.	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	null
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	null
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	Cases when loads get true Block-on-Store blocking code preventing store forwarding	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x03	0x08	LD_BLOCKS.NO_SR	This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare on address	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x82	DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x84	DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION	Demand load cycles page miss handler (PMH) is busy with this walk.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x08	0x88	DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED	Page walk for a large page completed for Demand load 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_STALLS_COUNT	Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	null
+0x0E	0x10	UOPS_ISSUED.FLAGS_MERGE	Number of flags-merge uops being allocated.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x20	UOPS_ISSUED.SLOW_LEA	Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x40	UOPS_ISSUED.SINGLE_MUL	Number of Multiply packed/scalar single precision uops allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x01	FP_COMP_OPS_EXE.X87	Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x10	FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE	Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x20	FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE	Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x40	FP_COMP_OPS_EXE.SSE_PACKED_SINGLE	Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x80	FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE	Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x11	0x01	SIMD_FP_256.PACKED_SINGLE	number of GSSE-256 Computational FP single precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x11	0x02	SIMD_FP_256.PACKED_DOUBLE	number of AVX-256 Computational FP double precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x14	0x01	ARITH.FPU_DIV_ACTIVE	Cycles when divider is busy executing divide operations	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x14	0x04	ARITH.FPU_DIV	Divide operations executed	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	null
+0x24	0x01	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x04	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x08	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x10	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x20	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x40	L2_RQSTS.PF_HIT	Requests from the L2 hardware prefetchers that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x80	L2_RQSTS.PF_MISS	Requests from the L2 hardware prefetchers that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x03	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x0C	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x30	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0xC0	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x01	L2_STORE_LOCK_RQSTS.MISS	RFOs that miss cache lines	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x08	L2_STORE_LOCK_RQSTS.HIT_M	RFOs that hit cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x0F	L2_STORE_LOCK_RQSTS.ALL	RFOs that access cache lines in any state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x01	L2_L1D_WB_RQSTS.MISS	Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x04	L2_L1D_WB_RQSTS.HIT_E	Not rejected writebacks from L1D to L2 cache lines in E state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x08	L2_L1D_WB_RQSTS.HIT_M	Not rejected writebacks from L1D to L2 cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x0F	L2_L1D_WB_RQSTS.ALL	Not rejected writebacks from L1D to L2 cache lines in any state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed LLC	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to LLC	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	2	2	2000003	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding. 	2	2	2000003	0	0	0	1	0	0	0	0	0	null
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x04	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x49	0x10	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4C	0x01	LOAD_HIT_PRE.SW_PF	Not software-prefetch load dispatches that hit FB allocated for software prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4C	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4F	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x58	0x04	MOVE_ELIMINATION.INT_NOT_ELIMINATED	Number of integer Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	null
+0x58	0x08	MOVE_ELIMINATION.SIMD_NOT_ELIMINATED	Number of SIMD Move Elimination candidate uops that were not eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	null
+0x58	0x01	MOVE_ELIMINATION.INT_ELIMINATED	Number of integer Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	null
+0x58	0x02	MOVE_ELIMINATION.SIMD_ELIMINATED	Number of SIMD Move Elimination candidate uops that were eliminated.	0,1,2,3	0,1,2,3,4,5,6,7	1000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	1	0	0	1	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5F	0x04	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD	Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO	Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x80	0x02	ICACHE.MISSES	Instruction cache, streaming buffer and victim cache misses	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x80	0x04	ICACHE.IFETCH_STALL	Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x02	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x04	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x85	0x10	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x80	ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED	Completed page walks in ITLB due to STLB load misses for large pages	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x87	0x04	ILD_STALL.IQ_FULL	Stall cycles because IQ is full	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x88	BR_MISP_EXEC.TAKEN_RETURN_NEAR	Taken speculative and retired mispredicted indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are dispatched to port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are dispatched to port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are dispatched to port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are dispatched to port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0_CORE	Cycles per core when uops are dispatched to port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1_CORE	Cycles per core when uops are dispatched to port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4_CORE	Cycles per core when uops are dispatched to port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5_CORE	Cycles per core when uops are dispatched to port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when load or STA uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when load or STA uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2_CORE	Uops dispatched to port 2, loads and stores per core (speculative and retired)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3_CORE	Cycles per core when load or STA uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Cycles with pending L2 cache miss loads.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Cycles with pending L1 cache miss loads.	2	2	2000003	0	0	0	8	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_LDM_PENDING	Cycles with pending memory loads.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_EXECUTE	Total execution stalls	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Execution stalls due to L2 cache misses.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_LDM_PENDING	Execution stalls due to memory subsystem.	0,1,2,3	0,1,2,3	2000003	0	0	0	6	0	0	0	0	0	null
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Execution stalls due to L1 data cache misses	2	2	2000003	0	0	0	12	0	0	0	0	0	null
+0xA8	0x01	LSD.UOPS	Number of Uops delivered by the LSD.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xAB	0x01	DSB2MITE_SWITCHES.COUNT	Decode Stream Buffer (DSB)-to-MITE switches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAC	0x08	DSB_FILL.EXCEED_DSB_LINES	Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAE	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xB0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.THREAD	Counts the number of uops to be executed per-thread each cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE	Number of uops executed on the core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.STALL_CYCLES	Counts number of cycles no uops were dispatched to be executed on this thread.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xB2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Cases when offcore requests buffer cannot take more entries for core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xBD	0x01	TLB_FLUSH.DTLB_THREAD	DTLB flush attempts of the thread-specific entries	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xBD	0x20	TLB_FLUSH.STLB_ANY	STLB flush attempts	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xC0	0x01	INST_RETIRED.PREC_DIST	Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution	1	1	2000003	0	0	0	0	0	0	0	2	0	null
+0xC1	0x08	OTHER_ASSISTS.AVX_STORE	Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x10	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x20	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x80	OTHER_ASSISTS.ANY_WB_ASSIST	Number of times any microcode assist is invoked by HW upon uop writeback.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	null
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	null
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.CORE_STALL_CYCLES	Cycles without actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	null
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3). 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC5	0x20	BR_MISP_RETIRED.NEAR_TAKEN	number of near branch instructions retired that were mispredicted and taken. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	null
+0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	null
+0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xCD	0x02	MEM_TRANS_RETIRED.PRECISE_STORE	Sample stores and collect precise store operation via PEBS record. PMC3 only. 	3	3	2000003	0	0	1	0	0	0	0	2	1	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32	3	3	100007	0x3F6	0x20	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	null
+0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	null
+0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x04	MEM_LOAD_UOPS_RETIRED.LLC_HIT	Retired load uops which data sources were data hits in LLC without snoops required. 	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	0	null
+0xD1	0x08	MEM_LOAD_UOPS_RETIRED.L1_MISS	Retired load uops which data sources following L1 data-cache miss	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x10	MEM_LOAD_UOPS_RETIRED.L2_MISS	Miss in mid-level (L2) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	0	null
+0xD1	0x20	MEM_LOAD_UOPS_RETIRED.LLC_MISS	Miss in last-level (L3) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	null
+0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD2	0x01	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x02	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x04	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared LLC. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x08	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in LLC without snoops required. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD3	0x01	MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM	Retired load uops which data sources missed LLC but serviced from local dram.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0xD3	0x0C	MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM	Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0xD3	0x10	MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM	Remote cache HITM	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0xD3	0x20	MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD	Data forwarded from remote cache	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0xE6	0x1F	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x08	L2_TRANS.ALL_PF	L2 or LLC HW prefetches that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x01	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x02	L2_LINES_OUT.DEMAND_DIRTY	Dirty L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x04	L2_LINES_OUT.PF_CLEAN	Clean L2 cache lines evicted by L2 prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x08	L2_LINES_OUT.PF_DIRTY	Dirty L2 cache lines evicted by L2 prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x0A	L2_LINES_OUT.DIRTY_ALL	Dirty L2 cache lines filling the L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC	Cycles where at least 1 uop was executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC	Cycles where at least 2 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC	Cycles where at least 3 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC	Cycles where at least 4 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x08	0x81	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x82	DTLB_LOAD_MISSES.WALK_COMPLETED	Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x84	DTLB_LOAD_MISSES.WALK_DURATION	Demand load cycles page miss handler (PMH) is busy with this walk.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	1	1	0	1	0	0	null
+0xC3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	null
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_MISS	Cycles while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	8	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_MISS	Cycles while L2 cache miss load* is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_MEM_ANY	Cycles while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.STALLS_TOTAL	Total execution stalls.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_MISS	Execution stalls while L1 cache miss demand load is outstanding.	2	2	2000003	0	0	0	12	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_MISS	Execution stalls while L2 cache miss load* is outstanding.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_MEM_ANY	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3	2000003	0	0	0	6	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	1	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	2	2	2000003	0	0	0	1	0	1	0	0	0	null
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/IVT/IvyTown_matrix_V17.json b/x86data/perfmon_data/IVT/IvyTown_matrix_V17.json
new file mode 100644
index 0000000..e7ee5df
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_matrix_V17.json
@@ -0,0 +1,191 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand data reads"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand data writes (RFOs)"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand code reads"
+  },
+  {
+    "MATRIX_REQUEST": "COREWB",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000008",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts core writebacks due to L2 evictions or L1 writeback requests"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_DATA_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000010",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to L2) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_RFO",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000020",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to L2) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_CODE_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000040",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_DATA_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_RFO",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_CODE_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000200",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "OTHER",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000008000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any other requests"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_DATA_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000090",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_RFO",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000120",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_CODE_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000240",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_DATA_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000091",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_RFO",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000122",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_CODE_RD",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000000244",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_READS",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x00000003f7",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all data/code/rfo reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_REQUESTS",
+    "MATRIX_RESPONSE": "NULL",
+    "MATRIX_VALUE": "0x0000008fff",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all requests"
+  },
+  {
+    "MATRIX_REQUEST": "NULL",
+    "MATRIX_RESPONSE": "LLC_HIT.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3f803c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC"
+  },
+  {
+    "MATRIX_REQUEST": "NULL",
+    "MATRIX_RESPONSE": "LLC_HIT.NO_SNOOP_NEEDED",
+    "MATRIX_VALUE": "0x01003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores"
+  },
+  {
+    "MATRIX_REQUEST": "NULL",
+    "MATRIX_RESPONSE": "LLC_HIT.SNOOP_MISS",
+    "MATRIX_VALUE": "0x02003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoops sent to sibling cores return clean response"
+  },
+  {
+    "MATRIX_REQUEST": "NULL",
+    "MATRIX_RESPONSE": "LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+    "MATRIX_VALUE": "0x04003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "NULL",
+    "MATRIX_RESPONSE": "LLC_HIT.HITM_OTHER_CORE",
+    "MATRIX_VALUE": "0x10003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "NULL",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3fffc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss in the LLC"
+  },
+  {
+    "MATRIX_REQUEST": "NULL",
+    "MATRIX_RESPONSE": "LLC_MISS.LOCAL_DRAM",
+    "MATRIX_VALUE": "0x0600400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the LLC and the data returned from local dram"
+  },
+  {
+    "MATRIX_REQUEST": "NULL",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_DRAM",
+    "MATRIX_VALUE": "0x067fc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the LLC and the data returned from local or remote dram"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/IVT/IvyTown_matrix_V17.tsv b/x86data/perfmon_data/IVT/IvyTown_matrix_V17.tsv
new file mode 100644
index 0000000..4757415
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_matrix_V17.tsv
@@ -0,0 +1,31 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family and Intel(R) Xeon(R) processor E7 family Based on the Ivy Bridge-EP Microarchitecture - V17
+# 7/29/2015 2:56:15 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	NULL	0x0001	0,1	Counts demand data reads
+DEMAND_RFO	NULL	0x0002	0,1	Counts all demand data writes (RFOs)
+DEMAND_CODE_RD	NULL	0x0004	0,1	Counts all demand code reads
+COREWB	NULL	0x0008	0,1	Counts core writebacks due to L2 evictions or L1 writeback requests
+PF_L2_DATA_RD	NULL	0x0010	0,1	Counts prefetch (that bring data to L2) data reads
+PF_L2_RFO	NULL	0x0020	0,1	Counts all prefetch (that bring data to L2) RFOs
+PF_L2_CODE_RD	NULL	0x0040	0,1	Counts all prefetch (that bring data to LLC only) code reads
+PF_LLC_DATA_RD	NULL	0x0080	0,1	Counts all prefetch (that bring data to LLC only) data reads
+PF_LLC_RFO	NULL	0x0100	0,1	Counts all prefetch (that bring data to LLC only) RFOs
+PF_LLC_CODE_RD	NULL	0x0200	0,1	Counts prefetch (that bring data to LLC only) code reads
+OTHER	NULL	0x8000	0,1	Counts any other requests
+ALL_PF_DATA_RD	NULL	0x0090	0,1	Counts all prefetch data reads
+ALL_PF_RFO	NULL	0x0120	0,1	Counts prefetch RFOs
+ALL_PF_CODE_RD	NULL	0x0240	0,1	Counts all prefetch code reads
+ALL_DATA_RD	NULL	0x0091	0,1	Counts all demand & prefetch data reads
+ALL_RFO	NULL	0x0122	0,1	Counts all demand & prefetch RFOs
+ALL_CODE_RD	NULL	0x0244	0,1	Counts all demand & prefetch code reads
+ALL_READS	NULL	0x03f7	0,1	Counts all data/code/rfo reads (demand & prefetch)
+ALL_REQUESTS	NULL	0x8fff	0,1	Counts all requests
+NULL	LLC_HIT.ANY_RESPONSE	0x3f803c	0,1	hit in the LLC
+NULL	LLC_HIT.NO_SNOOP_NEEDED	0x01003c	0,1	hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
+NULL	LLC_HIT.SNOOP_MISS	0x02003c	0,1	hit in the LLC and the snoops sent to sibling cores return clean response
+NULL	LLC_HIT.HIT_OTHER_CORE_NO_FWD	0x04003c	0,1	hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
+NULL	LLC_HIT.HITM_OTHER_CORE	0x10003c	0,1	hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
+NULL	LLC_MISS.ANY_RESPONSE	0x3fffc0	0,1	miss in the LLC
+NULL	LLC_MISS.LOCAL_DRAM	0x060040	0,1	miss the LLC and the data returned from local dram
+NULL	LLC_MISS.ANY_DRAM	0x067fc0	0,1	miss the LLC and the data returned from local or remote dram
diff --git a/x86data/perfmon_data/IVT/IvyTown_matrix_bit_definitions_V17.json b/x86data/perfmon_data/IVT/IvyTown_matrix_bit_definitions_V17.json
new file mode 100644
index 0000000..50a228c
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_matrix_bit_definitions_V17.json
@@ -0,0 +1,254 @@
+[
+  {
+    "BitName": "DEMAND_DATA_RD",
+    "BitIndex": "0",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_RFO",
+    "BitIndex": "1",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_CODE_RD",
+    "BitIndex": "2",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "COREWB",
+    "BitIndex": "3",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_DATA_RD",
+    "BitIndex": "4",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_RFO",
+    "BitIndex": "5",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_CODE_RD",
+    "BitIndex": "6",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_DATA_RD",
+    "BitIndex": "7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_RFO",
+    "BitIndex": "8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_CODE_RD",
+    "BitIndex": "9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "OTHER",
+    "BitIndex": "15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_DATA_RD",
+    "BitIndex": "4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_RFO",
+    "BitIndex": "5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_CODE_RD",
+    "BitIndex": "6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_DATA_RD",
+    "BitIndex": "0,4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_RFO",
+    "BitIndex": "1,5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_CODE_RD",
+    "BitIndex": "2,6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_READS",
+    "BitIndex": "0,1,2,4,5,6,7,8,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_REQUESTS",
+    "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_RESPONSE",
+    "BitIndex": "16",
+    "Type": "2",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SUPPLIER_NONE",
+    "BitIndex": "17",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_M",
+    "BitIndex": "18",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_E",
+    "BitIndex": "19",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_S",
+    "BitIndex": "20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_F",
+    "BitIndex": "21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT",
+    "BitIndex": "18,19,20,21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_LOCAL_DRAM",
+    "BitIndex": "22",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_REMOTE_DRAM",
+    "BitIndex": "22,23,24,25,26,27,28,29",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NONE",
+    "BitIndex": "31",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NOT_NEEDED",
+    "BitIndex": "32",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_MISS",
+    "BitIndex": "33",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_NO_FWD",
+    "BitIndex": "34",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_WITH_FWD",
+    "BitIndex": "35",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "18,19,20,21"
+  },
+  {
+    "BitName": "SNOOP_HITM",
+    "BitIndex": "36",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NON_DRAM",
+    "BitIndex": "37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_SNOOP",
+    "BitIndex": "31,32,33,34,35,36,37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/IVT/IvyTown_matrix_bit_definitions_V17.tsv b/x86data/perfmon_data/IVT/IvyTown_matrix_bit_definitions_V17.tsv
new file mode 100644
index 0000000..508d53c
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_matrix_bit_definitions_V17.tsv
@@ -0,0 +1,40 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family and Intel(R) Xeon(R) processor E7 family Based on the Ivy Bridge-EP Microarchitecture - V17
+# 7/29/2015 2:56:15 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	Type	MATRIX_REG	BitsNotCombinedWith
+DEMAND_DATA_RD	0	1	0,1	Null
+DEMAND_RFO	1	1	0,1	Null
+DEMAND_CODE_RD	2	1	0,1	Null
+COREWB	3	1	0,1	Null
+PF_L2_DATA_RD	4	1	0,1	Null
+PF_L2_RFO	5	1	0,1	Null
+PF_L2_CODE_RD	6	1	0,1	Null
+PF_LLC_DATA_RD	7	1	0,1	Null
+PF_LLC_RFO	8	1	0,1	Null
+PF_LLC_CODE_RD	9	1	0,1	Null
+OTHER	15	1	0,1	Null
+ALL_PF_DATA_RD	4,7	1	0,1	Null
+ALL_PF_RFO	5,8	1	0,1	Null
+ALL_PF_CODE_RD	6,9	1	0,1	Null
+ALL_DATA_RD	0,4,7	1	0,1	Null
+ALL_RFO	1,5,8	1	0,1	Null
+ALL_CODE_RD	2,6,9	1	0,1	Null
+ALL_READS	0,1,2,4,5,6,7,8,9	1	0,1	Null
+ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	0,1	Null
+ANY_RESPONSE	16	2	0,1	Null
+SUPPLIER_NONE	17	3	0,1	Null
+LLC_HIT_M	18	3	0,1	Null
+LLC_HIT_E	19	3	0,1	Null
+LLC_HIT_S	20	3	0,1	Null
+LLC_HIT_F	21	3	0,1	Null
+LLC_HIT	18,19,20,21	3	0,1	Null
+L3_MISS_LOCAL_DRAM	22	3	0,1	Null
+L3_MISS_REMOTE_DRAM	22,23,24,25,26,27,28,29	3	0,1	Null
+SNOOP_NONE	31	4	0,1	Null
+SNOOP_NOT_NEEDED	32	4	0,1	Null
+SNOOP_MISS	33	4	0,1	Null
+SNOOP_HIT_NO_FWD	34	4	0,1	Null
+SNOOP_HIT_WITH_FWD	35	4	0,1	18,19,20,21
+SNOOP_HITM	36	4	0,1	Null
+SNOOP_NON_DRAM	37	4	0,1	Null
+ANY_SNOOP	31,32,33,34,35,36,37	4	0,1	Null
diff --git a/x86data/perfmon_data/IVT/IvyTown_offcore_V17.tsv b/x86data/perfmon_data/IVT/IvyTown_offcore_V17.tsv
new file mode 100644
index 0000000..5d6912e
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_offcore_V17.tsv
@@ -0,0 +1,138 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family and Intel(R) Xeon(R) processor E7 family Based on the Ivy Bridge-EP Microarchitecture - V17
+# 7/29/2015 2:56:15 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE_0	Counts all demand & prefetch code reads that miss the LLC	0	0	100003	0x1a6	0x3fffc00244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM_0	Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dram	0	0	100003	0x1a6	0x67f800244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD_0	Counts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cache	0	0	100003	0x1a6	0x87f800244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response	0	0	100003	0x1a6	0x2003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE_0	Counts all demand & prefetch data reads that hits the LLC	0	0	100003	0x1a6	0x3fffc00091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch data reads that hit the LLC	0	0	100003	0x1a6	0x3f803c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response	0	0	100003	0x1a6	0x2003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE_0	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC	0	0	100003	0x1a6	0x3f803c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE_0	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED_0	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS_0	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response	0	0	100003	0x1a6	0x2003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE_0	Counts all data/code/rfo reads (demand & prefetch) that hit the LLC	0	0	100003	0x1a6	0x3fffc003f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM_0	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dram	0	0	100003	0x1a6	0x6004003f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD_0	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cache	0	0	100003	0x1a6	0x87f8003f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM_0	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from there	0	0	100003	0x1a6	0x107fc003f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCES.ANY_RESPONSE_0	Counts all data/code/rfo reads (demand & prefetch) that reference the LLC	0	0	100003	0x1a6	0x103F7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_0	Counts all writebacks from the core to the LLC	0	0	100003	0x1a6	0x10008	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE_0	Counts all demand code reads that miss the LLC	0	0	100003	0x1a6	0x3fffc00004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM_0	Counts all demand code reads that miss the LLC  and the data returned from local dram	0	0	100003	0x1a6	0x600400004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM_0	Counts all demand code reads that miss the LLC  and the data returned from remote dram	0	0	100003	0x1a6	0x67f800004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD_0	Counts all demand code reads that miss the LLC  and the data forwarded from remote cache	0	0	100003	0x1a6	0x87f800004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM_0	Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	0	0	100003	0x1a6	0x107fc00004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response	0	0	100003	0x1a6	0x2003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM_0	Counts demand data reads that miss the LLC  and the data returned from remote & local dram	0	0	100003	0x1a6	0x67fc00001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE_0	Counts demand data reads that miss in the LLC	0	0	100003	0x1a6	0x3fffc00001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM_0	Counts demand data reads that miss the LLC  and the data returned from local dram	0	0	100003	0x1a6	0x600400001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM_0	Counts demand data reads that miss the LLC  and the data returned from remote dram	0	0	100003	0x1a6	0x67f800001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_0	Counts demand data reads that miss the LLC  and the data forwarded from remote cache	0	0	100003	0x1a6	0x87f800001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM_0	Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	0	0	100003	0x1a6	0x107fc00001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_0	Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.OTHER.LRU_HINTS_0	Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches	0	0	100003	0x1a6	0x803c8000	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC_0	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses	0	0	100003	0x1a6	0x23ffc08000	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to L2) code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE_0	Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram	0	0	100003	0x1a6	0x3fffc20040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM_0	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram	0	0	100003	0x1a6	0x67fc00010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE_0	Counts prefetch (that bring data to L2) data reads that miss in the LLC	0	0	100003	0x1a6	0x3fffc00010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM_0	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram	0	0	100003	0x1a6	0x600400010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM_0	Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram	0	0	100003	0x1a6	0x67f800010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_0	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache	0	0	100003	0x1a6	0x87f800010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM_0	Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	0	0	100003	0x1a6	0x107fc00010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE_0	Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC	0	0	100003	0x1a6	0x3fffc00200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE_0	Counts prefetch (that bring data to LLC only) data reads that miss in the LLC	0	0	100003	0x1a6	0x3fffc00080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_0	Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address	0	0	100003	0x1a6	0x10400	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_0	Counts non-temporal stores	0	0	100003	0x1a6	0x10800	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE_1	Counts all demand & prefetch code reads that miss the LLC	3	3	100003	0x1a7	0x3fffc00244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM_1	Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dram	3	3	100003	0x1a7	0x67f800244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD_1	Counts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cache	3	3	100003	0x1a7	0x87f800244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response	3	3	100003	0x1a7	0x2003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE_1	Counts all demand & prefetch data reads that hits the LLC	3	3	100003	0x1a7	0x3fffc20091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch data reads that hit the LLC	3	3	100003	0x1a7	0x3f803c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response	3	3	100003	0x1a7	0x2003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC	3	3	100003	0x1a7	0x3f803c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response	3	3	100003	0x1a7	0x2003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE_1	Counts all data/code/rfo reads (demand & prefetch) that hit the LLC	3	3	100003	0x1a7	0x3fffc203f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM_1	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dram	3	3	100003	0x1a7	0x6004003f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD_1	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cache	3	3	100003	0x1a7	0x87f8203f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM_1	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from there	3	3	100003	0x1a7	0x107fc003f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCE.ANY_RESPONSE_1	Counts all data/code/rfo reads (demand & prefetch) that reference the LLC	3	3	100003	0x1a7	0x103F7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_1	Counts all writebacks from the core to the LLC	3	3	100003	0x1a7	0x10008	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE_1	Counts all demand code reads that miss the LLC	3	3	100003	0x1a7	0x3fffc20004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM_1	Counts all demand code reads that miss the LLC  and the data returned from local dram	3	3	100003	0x1a7	0x600400004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM_1	Counts all demand code reads that miss the LLC  and the data returned from remote dram	3	3	100003	0x1a7	0x67f800004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD_1	Counts all demand code reads that miss the LLC  and the data forwarded from remote cache	3	3	100003	0x1a7	0x87f820004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM_1	Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	3	3	100003	0x1a7	0x107fc00004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response	3	3	100003	0x1a7	0x2003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM_1	Counts demand data reads that miss the LLC  and the data returned from remote & local dram	3	3	100003	0x1a7	0x67fc00001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE_1	Counts demand data reads that miss in the LLC	3	3	100003	0x1a7	0x3fffc20001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM_1	Counts demand data reads that miss the LLC  and the data returned from local dram	3	3	100003	0x1a7	0x600400001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM_1	Counts demand data reads that miss the LLC  and the data returned from remote dram	3	3	100003	0x1a7	0x67f800001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_1	Counts demand data reads that miss the LLC  and the data forwarded from remote cache	3	3	100003	0x1a7	0x87f820001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM_1	Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	3	3	100003	0x1a7	0x107fc00001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_1	Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.LRU_HINTS_1	Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches	3	3	100003	0x1a7	0x803c8000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC_1	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses	3	3	100003	0x1a7	0x23ffc08000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to L2) code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE_1	Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram	3	3	100003	0x1a7	0x3fffc20040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM_1	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram	3	3	100003	0x1a7	0x67fc00010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE_1	Counts prefetch (that bring data to L2) data reads that miss in the LLC	3	3	100003	0x1a7	0x3fffc20010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM_1	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram	3	3	100003	0x1a7	0x600400010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM_1	Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram	3	3	100003	0x1a7	0x67f800010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_1	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache	3	3	100003	0x1a7	0x87f820010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM_1	Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	3	3	100003	0x1a7	0x107fc00010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE_1	Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC	3	3	100003	0x1a7	0x3fffc20200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE_1	Counts prefetch (that bring data to LLC only) data reads that miss in the LLC	3	3	100003	0x1a7	0x3fffc20080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_1	Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address	3	3	100003	0x1a7	0x10400	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_1	Counts non-temporal stores	3	3	100003	0x1a7	0x10800	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/IVT/IvyTown_uncore_V17.json b/x86data/perfmon_data/IVT/IvyTown_uncore_V17.json
new file mode 100644
index 0000000..36ea501
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_uncore_V17.json
@@ -0,0 +1,12914 @@
+[
+  {
+    "Unit": "CBO",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_C_CLOCKTICKS",
+    "BriefDescription": "Uncore Clocks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1f",
+    "UMask": "0x0",
+    "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+    "BriefDescription": "Counter 0 Occupancy",
+    "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+    "Counter": "1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x11",
+    "EventName": "UNC_C_LLC_LOOKUP.ANY",
+    "BriefDescription": "Cache Lookups; Any Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x3",
+    "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+    "BriefDescription": "Cache Lookups; Data Read Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Read transactions",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x41",
+    "EventName": "UNC_C_LLC_LOOKUP.NID",
+    "BriefDescription": "Cache Lookups; Lookups that Match NID",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x9",
+    "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+    "BriefDescription": "Cache Lookups; External Snoop Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x5",
+    "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+    "BriefDescription": "Cache Lookups; Write Requests",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter0[23:17]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x2",
+    "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+    "BriefDescription": "Lines Victimized; Lines in E state",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x8",
+    "EventName": "UNC_C_LLC_VICTIMS.MISS",
+    "BriefDescription": "Lines Victimized",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x1",
+    "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+    "BriefDescription": "Lines Victimized; Lines in M state",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x40",
+    "EventName": "UNC_C_LLC_VICTIMS.NID",
+    "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x4",
+    "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+    "BriefDescription": "Lines Victimized; Lines in S State",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x8",
+    "EventName": "UNC_C_MISC.RFO_HIT_S",
+    "BriefDescription": "Cbo Misc; RFO HitS",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state.  This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x1",
+    "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+    "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x4",
+    "EventName": "UNC_C_MISC.STARTED",
+    "BriefDescription": "Cbo Misc",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x2",
+    "EventName": "UNC_C_MISC.WC_ALIASING",
+    "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+    "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3c",
+    "UMask": "0x1",
+    "EventName": "UNC_C_QLRU.AGE0",
+    "BriefDescription": "LRU Queue; LRU Age 0",
+    "PublicDescription": "How often age was set to 0",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3c",
+    "UMask": "0x2",
+    "EventName": "UNC_C_QLRU.AGE1",
+    "BriefDescription": "LRU Queue; LRU Age 1",
+    "PublicDescription": "How often age was set to 1",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3c",
+    "UMask": "0x4",
+    "EventName": "UNC_C_QLRU.AGE2",
+    "BriefDescription": "LRU Queue; LRU Age 2",
+    "PublicDescription": "How often age was set to 2",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3c",
+    "UMask": "0x8",
+    "EventName": "UNC_C_QLRU.AGE3",
+    "BriefDescription": "LRU Queue; LRU Age 3",
+    "PublicDescription": "How often age was set to 3",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3c",
+    "UMask": "0x10",
+    "EventName": "UNC_C_QLRU.LRU_DECREMENT",
+    "BriefDescription": "LRU Queue; LRU Bits Decremented",
+    "PublicDescription": "How often all LRU bits were decremented by 1",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3c",
+    "UMask": "0x20",
+    "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
+    "BriefDescription": "LRU Queue; Non-0 Aged Victim",
+    "PublicDescription": "How often we picked a victim that had a non-zero age",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_VR0_EVEN",
+    "BriefDescription": "AD Ring In Use; Down and Even on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_VR0_ODD",
+    "BriefDescription": "AD Ring In Use; Down and Odd on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_VR1_EVEN",
+    "BriefDescription": "AD Ring In Use; Down and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x80",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_VR1_ODD",
+    "BriefDescription": "AD Ring In Use; Down and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_AD_USED.UP_VR0_EVEN",
+    "BriefDescription": "AD Ring In Use; Up and Even on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_AD_USED.UP_VR0_ODD",
+    "BriefDescription": "AD Ring In Use; Up and Odd on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RING_AD_USED.UP_VR1_EVEN",
+    "BriefDescription": "AD Ring In Use; Up and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RING_AD_USED.UP_VR1_ODD",
+    "BriefDescription": "AD Ring In Use; Up and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_VR0_EVEN",
+    "BriefDescription": "AK Ring In Use; Down and Even on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_VR0_ODD",
+    "BriefDescription": "AK Ring In Use; Down and Odd on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_VR1_EVEN",
+    "BriefDescription": "AK Ring In Use; Down and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x80",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_VR1_ODD",
+    "BriefDescription": "AK Ring In Use; Down and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_AK_USED.UP_VR0_EVEN",
+    "BriefDescription": "AK Ring In Use; Up and Even on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_AK_USED.UP_VR0_ODD",
+    "BriefDescription": "AK Ring In Use; Up and Odd on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RING_AK_USED.UP_VR1_EVEN",
+    "BriefDescription": "AK Ring In Use; Up and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RING_AK_USED.UP_VR1_ODD",
+    "BriefDescription": "AK Ring In Use; Up and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_VR0_EVEN",
+    "BriefDescription": "BL Ring in Use; Down and Even on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_VR0_ODD",
+    "BriefDescription": "BL Ring in Use; Down and Odd on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x40",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_VR1_EVEN",
+    "BriefDescription": "BL Ring in Use; Down and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x80",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_VR1_ODD",
+    "BriefDescription": "BL Ring in Use; Down and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_BL_USED.UP_VR0_EVEN",
+    "BriefDescription": "BL Ring in Use; Up and Even on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BL_USED.UP_VR0_ODD",
+    "BriefDescription": "BL Ring in Use; Up and Odd on Vring 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RING_BL_USED.UP_VR1_EVEN",
+    "BriefDescription": "BL Ring in Use; Up and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RING_BL_USED.UP_VR1_ODD",
+    "BriefDescription": "BL Ring in Use; Up and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BOUNCES.AK_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.: Acknowledgements to core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BOUNCES.BL_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.: Data Responses to core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_BOUNCES.IV_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.: Snoops of processor's cache.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1e",
+    "UMask": "0xF",
+    "EventName": "UNC_C_RING_IV_USED.ANY",
+    "BriefDescription": "IV Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1e",
+    "UMask": "0xCC",
+    "EventName": "UNC_C_RING_IV_USED.DOWN",
+    "BriefDescription": "IV Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1e",
+    "UMask": "0x33",
+    "EventName": "UNC_C_RING_IV_USED.UP",
+    "BriefDescription": "IV Ring in Use; Up",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Up polarity",
+    "Counter": "2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_C_RING_SRC_THRTL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles: ISMQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues. IRQ is blocking the ingress queue and causing the starvation.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_INSERTS.IPQ",
+    "BriefDescription": "Ingress Allocations; IPQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ",
+    "BriefDescription": "Ingress Allocations; IRQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED",
+    "BriefDescription": "Ingress Allocations: IRQ Rejected",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_INSERTS.VFIFO",
+    "BriefDescription": "Ingress Allocations; VFIFO",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.; Counts the number of allocations into the IRQ Ordering FIFO.  In JKT, it is necessary to keep IO requests in order.  Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other).  This event, in conjunction with the Occupancy Accumulator event, can be used to calculate average lifetime in the FIFO.  Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
+    "BriefDescription": "Probe Queue Retries; Address Conflict",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts.  Address conflicts out of the IPQ should be rare.  They will generally only occur if two different sockets are sending requests to the same address at the same time.  This is a true 'conflict' case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
+    "BriefDescription": "Probe Queue Retries; Any Reject",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject.  TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
+    "BriefDescription": "Probe Queue Retries; No Egress Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full.  IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "Probe Queue Retries; No QPI Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+    "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+    "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR.  In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo.  Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete.  This comes up most commonly with prefetches.  Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC.  Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
+    "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
+    "PublicDescription": "Counts the number of IRQ retries that occur.  Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons.  Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
+    "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
+    "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress.  The egress is the buffer that queues up for allocating onto the ring.  IRQ requests can make use of all four rings and all four Egresses.  If any of the queues that a given request needs to make use of are full, the request will be retried.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
+    "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
+    "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
+    "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits.  These credits are required in order to send transactions to the QPI agent.  Please see the QPI_IGR_CREDITS events for more information.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+    "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
+    "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available.  RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory.  If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available.  Note that there are multiple RTID pools for the different sockets.  There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available.  This event does not provide any filtering for this case.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
+    "BriefDescription": "ISMQ Retries; Any Reject",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject.  ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries).  ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID.  Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
+    "BriefDescription": "ISMQ Retries; No Egress Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring.  If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+    "BriefDescription": "ISMQ Retries; No IIO Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "ISMQ Retries; No QPI Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+    "BriefDescription": "ISMQ Retries; No RTIDs",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs.  M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory.  If no RTIDs are available, they will be retried.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x80",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
+    "BriefDescription": "ISMQ Retries; No WB Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Retries of writes to local memory due to lack of HT WB credits",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+    "BriefDescription": "Ingress Occupancy; IPQ",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
+    "BriefDescription": "Ingress Occupancy; IRQ",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJECTED",
+    "BriefDescription": "IRQ Rejected",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_OCCUPANCY.VFIFO",
+    "BriefDescription": "Ingress Occupancy; VFIFO",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.; Accumulates the number of used entries in the IRQ Ordering FIFO in each cycle.  In JKT, it is necessary to keep IO requests in order.  Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other).  This event, in conjunction with the Allocations event, can be used to calculate average lifetime in the FIFO.  This event can be used in conjunction with the Not Empty event to calculate average queue occupancy. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TOR_INSERTS.ALL",
+    "BriefDescription": "TOR Inserts; All",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR.    This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TOR_INSERTS.EVICTION",
+    "BriefDescription": "TOR Inserts; Evictions",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Eviction transactions inserted into the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x28",
+    "EventName": "UNC_C_TOR_INSERTS.LOCAL",
+    "BriefDescription": "TOR Inserts; Local Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x21",
+    "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
+    "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x2A",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
+    "BriefDescription": "TOR Inserts; Misses to Local Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x23",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
+    "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x3",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
+    "BriefDescription": "TOR Inserts; Miss Opcode Match",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x8A",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
+    "BriefDescription": "TOR Inserts; Misses to Remote Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x83",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
+    "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x48",
+    "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
+    "BriefDescription": "TOR Inserts; NID Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.  In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x44",
+    "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
+    "BriefDescription": "TOR Inserts; NID Matched Evictions",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x4A",
+    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+    "BriefDescription": "TOR Inserts; NID Matched Miss All",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x43",
+    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+    "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x41",
+    "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
+    "BriefDescription": "TOR Inserts; NID and Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x50",
+    "EventName": "UNC_C_TOR_INSERTS.NID_WB",
+    "BriefDescription": "TOR Inserts; NID Matched Writebacks",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched write transactions inserted into the TOR.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TOR_INSERTS.OPCODE",
+    "BriefDescription": "TOR Inserts; Opcode Match",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x88",
+    "EventName": "UNC_C_TOR_INSERTS.REMOTE",
+    "BriefDescription": "TOR Inserts; Remote Memory",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x81",
+    "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
+    "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TOR_INSERTS.WB",
+    "BriefDescription": "TOR Inserts; Writebacks",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Write transactions inserted into the TOR.   This does not include 'RFO', but actual operations that contain data being sent from the core.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+    "BriefDescription": "TOR Occupancy; Any",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries.  This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
+    "BriefDescription": "TOR Occupancy; Evictions",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x28",
+    "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x21",
+    "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
+    "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0xA",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
+    "BriefDescription": "TOR Occupancy; Miss All",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x2A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x23",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
+    "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x3",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
+    "BriefDescription": "TOR Occupancy; Miss Opcode Match",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x8A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x83",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+    "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x48",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+    "BriefDescription": "TOR Occupancy; NID Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x44",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
+    "BriefDescription": "TOR Occupancy; NID Matched Evictions",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x4A",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
+    "BriefDescription": "TOR Occupancy; NID Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x43",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
+    "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x41",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+    "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20], CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x50",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
+    "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[15:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+    "BriefDescription": "TOR Occupancy; Opcode Match",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x88",
+    "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
+    "BriefDescription": "TOR Occupancy",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x81",
+    "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
+    "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by remote caches or remote memory.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "CBoFilter1[28:20]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TOR_OCCUPANCY.WB",
+    "BriefDescription": "TOR Occupancy; Writebacks",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR.   This does not include 'RFO', but actual operations that contain data being sent from the core.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TxR_ADS_USED.AD",
+    "BriefDescription": "Onto AD Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_ADS_USED.AK",
+    "BriefDescription": "Onto AK Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_ADS_USED.BL",
+    "BriefDescription": "Onto BL Ring",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
+    "BriefDescription": "Egress Allocations; AD - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
+    "BriefDescription": "Egress Allocations; AD - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring.  This is commonly used for outbound requests.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
+    "BriefDescription": "Egress Allocations; AK - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x20",
+    "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
+    "BriefDescription": "Egress Allocations; AK - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring.  This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
+    "BriefDescription": "Egress Allocations; BL - Cacheno",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x40",
+    "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
+    "BriefDescription": "Egress Allocations; BL - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring.  This is commonly used for transfering writeback data to the cache.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
+    "BriefDescription": "Egress Allocations; IV - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring.  This is commonly used for snoops to the cores.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TxR_STARVED.AD_CORE",
+    "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
+    "BriefDescription": "Injection Starvation; Onto AK Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TxR_STARVED.IV",
+    "BriefDescription": "Injection Starvation; Onto IV Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CLOCKTICKS",
+    "BriefDescription": "pclk Cycles",
+    "PublicDescription": "The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x70",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
+    "BriefDescription": "Core 0 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x7a",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
+    "BriefDescription": "Core 10 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x7b",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
+    "BriefDescription": "Core 11 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x7c",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
+    "BriefDescription": "Core 12 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x7d",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
+    "BriefDescription": "Core 13 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x7e",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
+    "BriefDescription": "Core 14 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x71",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
+    "BriefDescription": "Core 1 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x72",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
+    "BriefDescription": "Core 2 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x73",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
+    "BriefDescription": "Core 3 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x74",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
+    "BriefDescription": "Core 4 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x75",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
+    "BriefDescription": "Core 5 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x76",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
+    "BriefDescription": "Core 6 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x77",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
+    "BriefDescription": "Core 7 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x78",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
+    "BriefDescription": "Core 8 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x79",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
+    "BriefDescription": "Core 9 C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x17",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE0",
+    "BriefDescription": "Deep C State Rejection - Core 0",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x18",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE1",
+    "BriefDescription": "Deep C State Rejection - Core 1",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x21",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE10",
+    "BriefDescription": "Deep C State Rejection - Core 10",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x22",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE11",
+    "BriefDescription": "Deep C State Rejection - Core 11",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x23",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE12",
+    "BriefDescription": "Deep C State Rejection - Core 12",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x24",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE13",
+    "BriefDescription": "Deep C State Rejection - Core 13",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x25",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE14",
+    "BriefDescription": "Deep C State Rejection - Core 14",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x19",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE2",
+    "BriefDescription": "Deep C State Rejection - Core 2",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1a",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE3",
+    "BriefDescription": "Deep C State Rejection - Core 3",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1b",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE4",
+    "BriefDescription": "Deep C State Rejection - Core 4",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1c",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE5",
+    "BriefDescription": "Deep C State Rejection - Core 5",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1d",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE6",
+    "BriefDescription": "Deep C State Rejection - Core 6",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1e",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE7",
+    "BriefDescription": "Deep C State Rejection - Core 7",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1f",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE8",
+    "BriefDescription": "Deep C State Rejection - Core 8",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x20",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE9",
+    "BriefDescription": "Deep C State Rejection - Core 9",
+    "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1e",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE0",
+    "BriefDescription": "Core 0 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1f",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE1",
+    "BriefDescription": "Core 1 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x20",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE2",
+    "BriefDescription": "Core 2 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x21",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE3",
+    "BriefDescription": "Core 3 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x22",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE4",
+    "BriefDescription": "Core 4 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x23",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE5",
+    "BriefDescription": "Core 5 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x24",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE6",
+    "BriefDescription": "Core 6 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x25",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE7",
+    "BriefDescription": "Core 7 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xb",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND0_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xc",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND1_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[15:8]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xd",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND2_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[23:16]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xe",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND3_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "PCUFilter[31:24]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES",
+    "BriefDescription": "Current Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when current is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
+    "BriefDescription": "Thermal Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
+    "BriefDescription": "OS Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
+    "BriefDescription": "Power Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x61",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
+    "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x62",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES",
+    "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x60",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_TRANS_CYCLES",
+    "BriefDescription": "Cycles spent changing Frequency",
+    "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2f",
+    "UMask": "0x0",
+    "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
+    "BriefDescription": "Memory Phase Shedding Cycles",
+    "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x26",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_C_EXIT_LATENCY_SEL",
+    "BriefDescription": "Package C State Exit Latency",
+    "PublicDescription": "Counts the number of cycles that the package is transitioning from package C2 to C3.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2a",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C0_CYCLES",
+    "BriefDescription": "Package C State Residency - C0",
+    "PublicDescription": "Counts the number of cycles that the package is in C0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2b",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C2_CYCLES",
+    "BriefDescription": "Package C State Residency - C2",
+    "PublicDescription": "Counts the number of cycles that the package is in C2",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2c",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C3_CYCLES",
+    "BriefDescription": "Package C State Residency - C3",
+    "PublicDescription": "Counts the number of cycles that the package is in C3",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2d",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C6_CYCLES",
+    "BriefDescription": "Package C State Residency - C6",
+    "PublicDescription": "Counts the number of cycles that the package is in C6",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0x40",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+    "BriefDescription": "Number of cores in C-State; C0 and C1",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0x80",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+    "BriefDescription": "Number of cores in C-State; C3",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0xC0",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+    "BriefDescription": "Number of cores in C-State; C6 and C7",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xa",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+    "BriefDescription": "External Prochot",
+    "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+    "BriefDescription": "Internal Prochot",
+    "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x63",
+    "UMask": "0x0",
+    "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+    "BriefDescription": "Total Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE",
+    "BriefDescription": "Cycles Changing Voltage",
+    "PublicDescription": "Counts the number of cycles when the system is changing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.  This event is calculated by or'ing together the increasing and decreasing events.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE",
+    "BriefDescription": "Cycles Decreasing Voltage",
+    "PublicDescription": "Counts the number of cycles when the system is decreasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE",
+    "BriefDescription": "Cycles Increasing Voltage",
+    "PublicDescription": "Counts the number of cycles when the system is increasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x32",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VR_HOT_CYCLES",
+    "BriefDescription": "VR Hot",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x8",
+    "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x10",
+    "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x4",
+    "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x2",
+    "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x1",
+    "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x2",
+    "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x1",
+    "EventName": "UNC_U_FILTER_MATCH.ENABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "UBoxFilter[3:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x8",
+    "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x4",
+    "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "UBoxFilter[3:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x44",
+    "UMask": "0x0",
+    "EventName": "UNC_U_LOCK_CYCLES",
+    "BriefDescription": "IDI Lock/SplitLock Cycles",
+    "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x45",
+    "UMask": "0x1",
+    "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+    "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+    "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x10",
+    "EventName": "UNC_U_U2C_EVENTS.CMC",
+    "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x4",
+    "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
+    "BriefDescription": "Monitor Sent to T0; Livelock",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x8",
+    "EventName": "UNC_U_U2C_EVENTS.LTERROR",
+    "BriefDescription": "Monitor Sent to T0; LTError",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x1",
+    "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
+    "BriefDescription": "Monitor Sent to T0; Monitor T0",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x2",
+    "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+    "BriefDescription": "Monitor Sent to T0; Monitor T1",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x80",
+    "EventName": "UNC_U_U2C_EVENTS.OTHER",
+    "BriefDescription": "Monitor Sent to T0; Other",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x40",
+    "EventName": "UNC_U_U2C_EVENTS.TRAP",
+    "BriefDescription": "Monitor Sent to T0; Trap",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x20",
+    "EventName": "UNC_U_U2C_EVENTS.UMC",
+    "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x2",
+    "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT",
+    "BriefDescription": "Address Match (Conflict) Count; Conflict Merges",
+    "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When two requests to the same address from the same source are received back to back, it is possible to merge the two of them together.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT",
+    "BriefDescription": "Address Match (Conflict) Count; Conflict Stalls",
+    "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When it is not possible to merge two conflicting requests, a stall event occurs.  This is bad for performance.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
+    "BriefDescription": "Write Ack Pending Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
+    "BriefDescription": "Write Ack Pending Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY",
+    "BriefDescription": "Outstanding Write Ownership Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks all requests from any source port.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
+    "BriefDescription": "Outstanding Write Ownership Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY",
+    "BriefDescription": "Outstanding Read Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks all requests from any source port.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
+    "BriefDescription": "Outstanding Read Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+    "BriefDescription": "Total Write Cache Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
+    "BriefDescription": "Total Write Cache Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
+    "BriefDescription": "Outstanding Write Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks all requests from any source port.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
+    "BriefDescription": "Outstanding Write Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_I_CLOCKTICKS",
+    "BriefDescription": "Clocks in the IRP",
+    "PublicDescription": "Number of clocks in the IRP.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xb",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_AK_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the AK Ingress is full.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xa",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_AK_INSERTS",
+    "BriefDescription": "AK Ingress Occupancy",
+    "PublicDescription": "Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xc",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_AK_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the AK Ingress in each cycles.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - DRS",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x2",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - NCB",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x8",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x3",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - NCS",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP",
+    "BriefDescription": "Tickle Count; Ownership Lost",
+    "PublicDescription": "Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of requests that lost ownership as a result of a tickle.  When a tickle comes in, if the request is not at the head of the queue in the switch, then that request as well as any requests behind it in the switch queue will lose ownership and have to re-acquire it later when they get to the head of the queue.  This will therefore track the number of requests that lost ownership and not just the number of tickles.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE",
+    "BriefDescription": "Tickle Count; Data Returned",
+    "PublicDescription": "Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of cases when a tickle was received but the requests was at the head of the queue in the switch.  In this case, data is returned rather than releasing ownership.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+    "BriefDescription": "Inbound Transaction Count; Select Source",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.  If this bit is not set, then requests from all sources will be counted.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "IRPFilter[4:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES",
+    "BriefDescription": "Inbound Transaction Count: Read Prefetches",
+    "PublicDescription": "Counts the number of \\Inbound\\' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.'",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_I_TRANSACTIONS.READS",
+    "BriefDescription": "Inbound Transaction Count; Reads",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_I_TRANSACTIONS.WRITES",
+    "BriefDescription": "Inbound Transaction Count; Writes",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x18",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
+    "BriefDescription": "No AD Egress Credit Stalls",
+    "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x19",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
+    "BriefDescription": "No BL Egress Credit Stalls",
+    "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xe",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
+    "BriefDescription": "Outbound Read Requests",
+    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xf",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
+    "BriefDescription": "Outbound Read Requests",
+    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xd",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
+    "BriefDescription": "Outbound Request Queue Occupancy",
+    "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x1a",
+    "UMask": "0x0",
+    "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES",
+    "BriefDescription": "Write Ordering Stalls",
+    "PublicDescription": "Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x14",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_CLOCKTICKS",
+    "BriefDescription": "Number of qfclks",
+    "PublicDescription": "Counts the number of clocks in the QPI LL.  This clock runs at 1/8th the 'GT/s' speed of the QPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  JKT does not support dynamic link speeds, so this frequency is fixed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_CTO_COUNT",
+    "BriefDescription": "Count of CTO Events",
+    "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "QPIMask0[17:0],QPIMatch0[17:0],QPIMask1[19:16],QPIMatch1[19:16]",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits.  Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits.   The valid bit was set.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x80",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction.  This is common for IO transactions.  There were enough Egress credits and the RBT tag matched but the valid bit was not set.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x40",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful.  There were sufficient credits, the RBT valid bit was set and there was an RBT tag match.  The message was marked to spawn direct2core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_L1_POWER_CYCLES",
+    "BriefDescription": "Cycles in L1",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x10",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL0P_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0p",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xf",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL0_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_BYPASSED",
+    "BriefDescription": "Rx Flit Buffer Bypassed",
+    "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
+    "BriefDescription": "CRC Errors Detected; LinkInit",
+    "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
+    "BriefDescription": "CRC Errors Detected; Normal Operations",
+    "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
+    "BriefDescription": "VN0 Credit Consumed; DRS",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
+    "BriefDescription": "VN0 Credit Consumed; HOM",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
+    "BriefDescription": "VN0 Credit Consumed; NCB",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
+    "BriefDescription": "VN0 Credit Consumed; NCS",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
+    "BriefDescription": "VN0 Credit Consumed; NDR",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
+    "BriefDescription": "VN0 Credit Consumed; SNP",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
+    "BriefDescription": "VN1 Credit Consumed; DRS",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
+    "BriefDescription": "VN1 Credit Consumed; HOM",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
+    "BriefDescription": "VN1 Credit Consumed; NCB",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
+    "BriefDescription": "VN1 Credit Consumed; NCS",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
+    "BriefDescription": "VN1 Credit Consumed; NDR",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x39",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
+    "BriefDescription": "VN1 Credit Consumed; SNP",
+    "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1d",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
+    "BriefDescription": "VNA Credit Consumed",
+    "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xa",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_CYCLES_NE",
+    "BriefDescription": "RxQ Cycles Not Empty",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_FLITS_G0.DATA",
+    "BriefDescription": "Flits Received - Group 0; Data Tx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flitsreceived over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
+    "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload.  When QPI is not in a power saving state, it continuously transmits flits across the link.  When there are no protocol flits to send, it will send IDLE and NULL flits  across.  These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA",
+    "BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits received across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x18",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
+    "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
+    "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
+    "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x6",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
+    "BriefDescription": "Flits Received - Group 1; HOM Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
+    "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
+    "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel.  This basically counts the number of remote memory requests received over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
+    "BriefDescription": "Flits Received - Group 1; SNP Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are received on the home channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0xC",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI.    This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
+    "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
+    "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x8",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS",
+    "BriefDescription": "Rx Flit Buffer Allocations",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_DRS",
+    "BriefDescription": "Rx Flit Buffer Allocations - DRS",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xc",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_HOM",
+    "BriefDescription": "Rx Flit Buffer Allocations - HOM",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xa",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_NCB",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCB",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xb",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_NCS",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCS",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xe",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_NDR",
+    "BriefDescription": "Rx Flit Buffer Allocations - NDR",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xd",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_SNP",
+    "BriefDescription": "Rx Flit Buffer Allocations - SNP",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xb",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY",
+    "BriefDescription": "RxQ Occupancy - All Packets",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x15",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_DRS",
+    "BriefDescription": "RxQ Occupancy - DRS",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x18",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_HOM",
+    "BriefDescription": "RxQ Occupancy - HOM",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x16",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCB",
+    "BriefDescription": "RxQ Occupancy - NCB",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x17",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCS",
+    "BriefDescription": "RxQ Occupancy - NCS",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1a",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NDR",
+    "BriefDescription": "RxQ Occupancy - NDR",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x19",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_SNP",
+    "BriefDescription": "RxQ Occupancy - SNP",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x40",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits.  For details on a message class granularity, use the Egress Credit Occupancy events.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x80",
+    "EventName": "UNC_Q_RxL_STALLS_VN0.GV",
+    "BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3a",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3a",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3a",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3a",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3a",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3a",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
+    "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
+    "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xd",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0p",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xc",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL0_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_BYPASSED",
+    "BriefDescription": "Tx Flit Buffer Bypassed",
+    "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
+    "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
+    "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
+    "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
+    "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_CYCLES_NE",
+    "BriefDescription": "Tx Flit Buffer Cycles not Empty",
+    "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
+    "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
+    "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
+    "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
+    "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x18",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x6",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel.  This basically counts the number of remote memory requests transmitted over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
+    "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are transmitted on the home channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0xC",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not te NCB headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI.    This includes extended headers.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_INSERTS",
+    "BriefDescription": "Tx Flit Buffer Allocations",
+    "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_OCCUPANCY",
+    "BriefDescription": "Tx Flit Buffer Occupancy",
+    "PublicDescription": "Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x26",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x26",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x22",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x22",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x24",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x24",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x27",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x27",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
+    "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x23",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x23",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN0",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN1",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x25",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x25",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2a",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2a",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2a",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1f",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1f",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1f",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2b",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2b",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x20",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x20",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2c",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2c",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x21",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x21",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1c",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_VNA_CREDIT_RETURNS",
+    "BriefDescription": "VNA Credits Returned",
+    "PublicDescription": "Number of VNA credits returned.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1b",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
+    "BriefDescription": "VNA Credits Pending Return - Occupancy",
+    "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_CLOCKTICKS",
+    "BriefDescription": "Number of uclks in domain",
+    "PublicDescription": "Counts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2c",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2c",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2c",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2c",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2c",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2c",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2c",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2b",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2b",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2b",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2b",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2b",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2b",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2b",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2b",
+    "UMask": "0x80",
+    "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
+    "BriefDescription": "CBox AD Credits Empty",
+    "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2f",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
+    "BriefDescription": "HA/R2 AD Credits Empty",
+    "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2f",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
+    "BriefDescription": "HA/R2 AD Credits Empty",
+    "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2f",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
+    "BriefDescription": "HA/R2 AD Credits Empty",
+    "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2f",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
+    "BriefDescription": "HA/R2 AD Credits Empty",
+    "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
+    "BriefDescription": "QPI0 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2d",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2d",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2d",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2d",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2d",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2d",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2d",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
+    "BriefDescription": "QPI0 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2a",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2a",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2a",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2a",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2a",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2a",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2a",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
+    "BriefDescription": "QPI1 AD Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2e",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2e",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2e",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2e",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2e",
+    "UMask": "0x40",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2e",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x2e",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
+    "BriefDescription": "QPI1 BL Credits Empty",
+    "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_EVEN",
+    "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_ODD",
+    "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_AD_USED.CW_VR0_EVEN",
+    "BriefDescription": "R3 AD Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_AD_USED.CW_VR0_ODD",
+    "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_EVEN",
+    "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_ODD",
+    "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_AK_USED.CW_VR0_EVEN",
+    "BriefDescription": "R3 AK Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_AK_USED.CW_VR0_ODD",
+    "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_EVEN",
+    "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_ODD",
+    "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_BL_USED.CW_VR0_EVEN",
+    "BriefDescription": "R3 BL Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_BL_USED.CW_VR0_ODD",
+    "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xa",
+    "UMask": "0xCC",
+    "EventName": "UNC_R3_RING_IV_USED.CCW",
+    "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xa",
+    "UMask": "0x33",
+    "EventName": "UNC_R3_RING_IV_USED.CW",
+    "BriefDescription": "R2 IV Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity",
+    "Counter": "0,1,2",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_BYPASSED.AD",
+    "BriefDescription": "Ingress Bypassed",
+    "PublicDescription": "Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
+    "BriefDescription": "Ingress Cycles Not Empty; HOM",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+    "BriefDescription": "Ingress Cycles Not Empty; NDR",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
+    "BriefDescription": "Ingress Cycles Not Empty; SNP",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_INSERTS.DRS",
+    "BriefDescription": "Ingress Allocations; DRS",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_INSERTS.HOM",
+    "BriefDescription": "Ingress Allocations; HOM",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_INSERTS.NCB",
+    "BriefDescription": "Ingress Allocations; NCB",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_INSERTS.NCS",
+    "BriefDescription": "Ingress Allocations; NCS",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_INSERTS.NDR",
+    "BriefDescription": "Ingress Allocations; NDR",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_INSERTS.SNP",
+    "BriefDescription": "Ingress Allocations; SNP",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.DRS",
+    "BriefDescription": "Ingress Occupancy Accumulator; DRS",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.HOM",
+    "BriefDescription": "Ingress Occupancy Accumulator; HOM",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.NCB",
+    "BriefDescription": "Ingress Occupancy Accumulator; NCB",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.NCS",
+    "BriefDescription": "Ingress Occupancy Accumulator; NCS",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.NDR",
+    "BriefDescription": "Ingress Occupancy Accumulator; NDR",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.SNP",
+    "BriefDescription": "Ingress Occupancy Accumulator; SNP",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_TxR_NACK_CCW.AD",
+    "BriefDescription": "Egress NACK; AK CCW",
+    "PublicDescription": "BL CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_TxR_NACK_CCW.AK",
+    "BriefDescription": "Egress NACK; BL CW",
+    "PublicDescription": "AD Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x28",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_TxR_NACK_CCW.BL",
+    "BriefDescription": "Egress NACK; BL CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_TxR_NACK_CW.AD",
+    "BriefDescription": "Egress NACK; AD CW",
+    "PublicDescription": "AD Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_TxR_NACK_CW.AK",
+    "BriefDescription": "Egress NACK; AD CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x26",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_TxR_NACK_CW.BL",
+    "BriefDescription": "Egress NACK; AK CW",
+    "PublicDescription": "BL Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
+    "BriefDescription": "VN0 Credit Used; DRS Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
+    "BriefDescription": "VN0 Credit Used; HOM Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
+    "BriefDescription": "VN0 Credit Used; NCB Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
+    "BriefDescription": "VN0 Credit Used; NCS Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
+    "BriefDescription": "VN0 Credit Used; NDR Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
+    "BriefDescription": "VN0 Credit Used; SNP Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x39",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
+    "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
+    "BriefDescription": "VN1 Credit Used; DRS Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
+    "BriefDescription": "VN1 Credit Used; HOM Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
+    "BriefDescription": "VN1 Credit Used; NCB Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
+    "BriefDescription": "VN1 Credit Used; NCS Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+    "BriefDescription": "VN1 Credit Used; NDR Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x38",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+    "BriefDescription": "VN1 Credit Used; SNP Message Class",
+    "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x33",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED",
+    "BriefDescription": "VNA credit Acquisitions",
+    "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
+    "BriefDescription": "VNA Credit Reject; DRS Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
+    "BriefDescription": "VNA Credit Reject; HOM Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
+    "BriefDescription": "VNA Credit Reject; NCB Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
+    "BriefDescription": "VNA Credit Reject; NCS Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
+    "BriefDescription": "VNA Credit Reject; NDR Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
+    "BriefDescription": "VNA Credit Reject; SNP Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x31",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT",
+    "BriefDescription": "Cycles with no VNA credits available",
+    "PublicDescription": "Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel.  Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit.  Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x32",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED",
+    "BriefDescription": "Cycles with 1 or more VNA credits in use",
+    "PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_R2_CLOCKTICKS",
+    "BriefDescription": "Number of uclks in domain",
+    "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x34",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS",
+    "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS",
+    "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
+    "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
+    "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
+    "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x40",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x80",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AD_USED.CW_VR0_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AD_USED.CW_VR0_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RING_AD_USED.CW_VR1_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RING_AD_USED.CW_VR1_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x40",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x80",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AK_USED.CW_VR0_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AK_USED.CW_VR0_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RING_AK_USED.CW_VR1_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RING_AK_USED.CW_VR1_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x40",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x80",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_BL_USED.CW_VR0_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_BL_USED.CW_VR0_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RING_BL_USED.CW_VR1_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RING_BL_USED.CW_VR1_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xa",
+    "UMask": "0xCC",
+    "EventName": "UNC_R2_RING_IV_USED.CCW",
+    "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xa",
+    "UMask": "0x33",
+    "EventName": "UNC_R2_RING_IV_USED.CW",
+    "BriefDescription": "R2 IV Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_R2_RxR_AK_BOUNCES",
+    "BriefDescription": "AK Ingress Bounced",
+    "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
+    "BriefDescription": "Ingress Cycles Not Empty; NCB",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
+    "BriefDescription": "Ingress Cycles Not Empty; NCS",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RxR_INSERTS.NCB",
+    "BriefDescription": "Ingress Allocations; NCB",
+    "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RxR_INSERTS.NCS",
+    "BriefDescription": "Ingress Allocations; NCS",
+    "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
+    "BriefDescription": "Ingress Occupancy Accumulator; DRS",
+    "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
+    "BriefDescription": "Egress Cycles Full; AD",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
+    "BriefDescription": "Egress Cycles Full; AK",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
+    "BriefDescription": "Egress Cycles Full; BL",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.AD",
+    "BriefDescription": "Egress Cycles Not Empty; AD",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AD Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.AK",
+    "BriefDescription": "Egress Cycles Not Empty; AK",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AK Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.BL",
+    "BriefDescription": "Egress Cycles Not Empty; BL",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; BL Egress Queue",
+    "Counter": "0",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x3",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
+    "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x52",
+    "UMask": "0x0",
+    "EventName": "UNC_H_BT_BYPASS",
+    "BriefDescription": "BT Bypass",
+    "PublicDescription": "Number of transactions that bypass the BT (fifo) to HT",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x42",
+    "UMask": "0x1",
+    "EventName": "UNC_H_BT_CYCLES_NE.LOCAL",
+    "BriefDescription": "BT Cycles Not Empty: Local",
+    "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x42",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BT_CYCLES_NE.REMOTE",
+    "BriefDescription": "BT Cycles Not Empty: Remote",
+    "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x43",
+    "UMask": "0x1",
+    "EventName": "UNC_H_BT_OCCUPANCY.LOCAL",
+    "BriefDescription": "BT Occupancy; Local",
+    "PublicDescription": "Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x43",
+    "UMask": "0x4",
+    "EventName": "UNC_H_BT_OCCUPANCY.READS_LOCAL",
+    "BriefDescription": "BT Occupancy; Reads Local",
+    "PublicDescription": "Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x43",
+    "UMask": "0x8",
+    "EventName": "UNC_H_BT_OCCUPANCY.READS_REMOTE",
+    "BriefDescription": "BT Occupancy; Reads Remote",
+    "PublicDescription": "Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x43",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BT_OCCUPANCY.REMOTE",
+    "BriefDescription": "BT Occupancy; Remote",
+    "PublicDescription": "Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x43",
+    "UMask": "0x10",
+    "EventName": "UNC_H_BT_OCCUPANCY.WRITES_LOCAL",
+    "BriefDescription": "BT Occupancy; Writes Local",
+    "PublicDescription": "Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x43",
+    "UMask": "0x20",
+    "EventName": "UNC_H_BT_OCCUPANCY.WRITES_REMOTE",
+    "BriefDescription": "BT Occupancy; Writes Remote",
+    "PublicDescription": "Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x4",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
+    "BriefDescription": "HA to iMC Bypass; Not Taken",
+    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_H_BYPASS_IMC.TAKEN",
+    "BriefDescription": "HA to iMC Bypass; Taken",
+    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_H_CLOCKTICKS",
+    "BriefDescription": "uclks",
+    "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xb",
+    "UMask": "0x8",
+    "EventName": "UNC_H_CONFLICT_CYCLES.ACKCNFLTS",
+    "BriefDescription": "Conflict Checks; Acknowledge Conflicts",
+    "PublicDescription": "Count the number of Ackcnflts",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xb",
+    "UMask": "0x10",
+    "EventName": "UNC_H_CONFLICT_CYCLES.CMP_FWDS",
+    "BriefDescription": "Conflict Checks; Cmp Fwds",
+    "PublicDescription": "Count the number of Cmp_Fwd. This will give the number of late conflicts.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xb",
+    "UMask": "0x2",
+    "EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT",
+    "BriefDescription": "Conflict Checks; Conflict Detected",
+    "PublicDescription": "Counts the number of cycles that we are handling conflicts.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xb",
+    "UMask": "0x4",
+    "EventName": "UNC_H_CONFLICT_CYCLES.LAST",
+    "BriefDescription": "Conflict Checks; Last in conflict chain",
+    "PublicDescription": "Count every last conflictor in conflict chain. Can be used to compute the average conflict chain length as (#Ackcnflts/#LastConflictor)+1. This can be used to give a feel for the conflict chain lenghts while analyzing lock kernels.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x11",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_COUNT",
+    "BriefDescription": "Direct2Core Messages Sent",
+    "PublicDescription": "Number of Direct2Core messages sent",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
+    "BriefDescription": "Cycles when Direct2Core was Disabled",
+    "PublicDescription": "Number of cycles in which Direct2Core was disabled",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x13",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
+    "BriefDescription": "Number of Reads that had Direct2Core Overridden",
+    "PublicDescription": "Number of Reads where Direct2Core overridden",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x41",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECTORY_LAT_OPT",
+    "BriefDescription": "Directory Lat Opt Return",
+    "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x10",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.ANY",
+    "BriefDescription": "Directory Lookups: Any state",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
+    "BriefDescription": "Directory Lookups; Snoop Not Needed",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x8",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_A",
+    "BriefDescription": "Directory Lookups: Snoop A",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_S",
+    "BriefDescription": "Directory Lookups: Snoop S",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x1",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
+    "BriefDescription": "Directory Lookups; Snoop Needed",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x80",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_A",
+    "BriefDescription": "Directory Lookups: A State",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x20",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_I",
+    "BriefDescription": "Directory Lookups: I State",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x40",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_S",
+    "BriefDescription": "Directory Lookups: S State",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x20",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.A2I",
+    "BriefDescription": "Directory Updates: A2I",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x40",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.A2S",
+    "BriefDescription": "Directory Updates: A2S",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x3",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
+    "BriefDescription": "Directory Updates; Any Directory Update",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x4",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.I2A",
+    "BriefDescription": "Directory Updates: I2A",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.I2S",
+    "BriefDescription": "Directory Updates: I2S",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x10",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.S2A",
+    "BriefDescription": "Directory Updates: S2A",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x8",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.S2I",
+    "BriefDescription": "Directory Updates: S2I",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x59",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IGR_AD_QPI2_ACCUMULATOR",
+    "BriefDescription": "AD QPI Link 2 Credit Accumulator",
+    "PublicDescription": "Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x5a",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IGR_BL_QPI2_ACCUMULATOR",
+    "BriefDescription": "BL QPI Link 2 Credit Accumulator",
+    "PublicDescription": "Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
+    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
+    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x8",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IMC_READS.NORMAL",
+    "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
+    "PublicDescription": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1e",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IMC_RETRY",
+    "BriefDescription": "Retry Events",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0xF",
+    "EventName": "UNC_H_IMC_WRITES.ALL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IMC_WRITES.FULL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0x8",
+    "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x57",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IODC_CONFLICTS.REMOTE_INVI2E_SAME_RTID",
+    "BriefDescription": "IODC Conflicts: Remote InvItoE - Same RTID",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x57",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IODC_CONFLICTS.REMOTE_OTHER_SAME_ADDR",
+    "BriefDescription": "IODC Conflicts: Remote (Other) - Same Addr",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x56",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IODC_INSERTS",
+    "BriefDescription": "IODC Inserts",
+    "PublicDescription": "IODC Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x58",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IODC_OLEN_WBMTOI",
+    "BriefDescription": "Num IODC 0 Length Writes",
+    "PublicDescription": "Num IODC 0 Length Writebacks M to I - All of which are dropped.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x4",
+    "EventName": "UNC_H_OSB.INVITOE_LOCAL",
+    "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x2",
+    "EventName": "UNC_H_OSB.READS_LOCAL",
+    "BriefDescription": "OSB Snoop Broadcast; Local Reads",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x53",
+    "UMask": "0x8",
+    "EventName": "UNC_H_OSB.REMOTE",
+    "BriefDescription": "OSB Snoop Broadcast; Remote",
+    "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x1",
+    "EventName": "UNC_H_OSB_EDR.ALL",
+    "BriefDescription": "OSB Early Data Return; All",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x2",
+    "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
+    "BriefDescription": "OSB Early Data Return; Reads to Local  I",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x8",
+    "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
+    "BriefDescription": "OSB Early Data Return; Reads to Local S",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x4",
+    "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
+    "BriefDescription": "OSB Early Data Return; Reads to Remote I",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x54",
+    "UMask": "0x10",
+    "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
+    "BriefDescription": "OSB Early Data Return; Reads to Remote S",
+    "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x10",
+    "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local InvItoEs",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x20",
+    "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote InvItoEs",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x3",
+    "EventName": "UNC_H_REQUESTS.READS",
+    "BriefDescription": "Read and Write Requests; Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests.  This is a good proxy for LLC Read Misses (including RFOs).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket.  This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_H_REQUESTS.READS_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket.  This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0xC",
+    "EventName": "UNC_H_REQUESTS.WRITES",
+    "BriefDescription": "Read and Write Requests; Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+    "BriefDescription": "Read and Write Requests; Local Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
+    "BriefDescription": "Read and Write Requests; Remote Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_AD_USED.CCW_VR0_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_AD_USED.CCW_VR0_ODD",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x40",
+    "EventName": "UNC_H_RING_AD_USED.CCW_VR1_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x80",
+    "EventName": "UNC_H_RING_AD_USED.CCW_VR1_ODD",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_AD_USED.CW_VR0_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_AD_USED.CW_VR0_ODD",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x10",
+    "EventName": "UNC_H_RING_AD_USED.CW_VR1_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x20",
+    "EventName": "UNC_H_RING_AD_USED.CW_VR1_ODD",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_AK_USED.CCW_VR0_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_AK_USED.CCW_VR0_ODD",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x40",
+    "EventName": "UNC_H_RING_AK_USED.CCW_VR1_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x80",
+    "EventName": "UNC_H_RING_AK_USED.CCW_VR1_ODD",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_AK_USED.CW_VR0_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_AK_USED.CW_VR0_ODD",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x10",
+    "EventName": "UNC_H_RING_AK_USED.CW_VR1_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x20",
+    "EventName": "UNC_H_RING_AK_USED.CW_VR1_ODD",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_BL_USED.CCW_VR0_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_BL_USED.CCW_VR0_ODD",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x40",
+    "EventName": "UNC_H_RING_BL_USED.CCW_VR1_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x80",
+    "EventName": "UNC_H_RING_BL_USED.CCW_VR1_ODD",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_BL_USED.CW_VR0_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_BL_USED.CW_VR0_ODD",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing 0",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x10",
+    "EventName": "UNC_H_RING_BL_USED.CW_VR1_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x20",
+    "EventName": "UNC_H_RING_BL_USED.CW_VR1_ODD",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing 1",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x40",
+    "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+    "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNOOP_RESP.RSPI",
+    "BriefDescription": "Snoop Responses Received; RspI",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x4",
+    "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+    "BriefDescription": "Snoop Responses Received; RspIFwd",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNOOP_RESP.RSPS",
+    "BriefDescription": "Snoop Responses Received; RspS",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x8",
+    "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+    "BriefDescription": "Snoop Responses Received; RspSFwd",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x20",
+    "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+    "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x21",
+    "UMask": "0x10",
+    "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+    "BriefDescription": "Snoop Responses Received; Rsp*WB",
+    "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x80",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
+    "BriefDescription": "Snoop Responses Received Local; Other",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for all other snoop responses.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x40",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
+    "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x1",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
+    "BriefDescription": "Snoop Responses Received Local; RspI",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x4",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
+    "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x2",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
+    "BriefDescription": "Snoop Responses Received Local; RspS",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x8",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
+    "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x20",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
+    "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x60",
+    "UMask": "0x10",
+    "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
+    "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+    "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x10",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x20",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x40",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x80",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1c",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1c",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1c",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1c",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3",
+    "UMask": "0x0",
+    "EventName": "UNC_H_TRACKER_CYCLES_NE",
+    "BriefDescription": "Tracker Cycles Not Empty",
+    "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2a",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+    "BriefDescription": "AD Egress Full; All",
+    "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2a",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
+    "BriefDescription": "AD Egress Full; Scheduler 0",
+    "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2a",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
+    "BriefDescription": "AD Egress Full; Scheduler 1",
+    "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+    "BriefDescription": "AD Egress Not Empty; All",
+    "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
+    "BriefDescription": "AD Egress Not Empty; Scheduler 0",
+    "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
+    "BriefDescription": "AD Egress Not Empty; Scheduler 1",
+    "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+    "BriefDescription": "AD Egress Allocations; All",
+    "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
+    "BriefDescription": "AD Egress Allocations; Scheduler 0",
+    "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
+    "BriefDescription": "AD Egress Allocations; Scheduler 1",
+    "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0",
+    "BriefDescription": "AD Egress Occupancy; Scheduler 0",
+    "PublicDescription": "AD Egress Occupancy; Filter for occupancy from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1",
+    "BriefDescription": "AD Egress Occupancy; Scheduler 1",
+    "PublicDescription": "AD Egress Occupancy; Filter for occupancy from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xe",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK.CRD_CBO",
+    "BriefDescription": "Outbound Ring Transactions on AK: CRD Transactions to Cbo",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+    "BriefDescription": "AK Egress Full; All",
+    "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
+    "BriefDescription": "AK Egress Full; Scheduler 0",
+    "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
+    "BriefDescription": "AK Egress Full; Scheduler 1",
+    "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+    "BriefDescription": "AK Egress Not Empty; All",
+    "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
+    "BriefDescription": "AK Egress Not Empty; Scheduler 0",
+    "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
+    "BriefDescription": "AK Egress Not Empty; Scheduler 1",
+    "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2f",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
+    "BriefDescription": "AK Egress Allocations; All",
+    "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2f",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
+    "BriefDescription": "AK Egress Allocations; Scheduler 0",
+    "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2f",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
+    "BriefDescription": "AK Egress Allocations; Scheduler 1",
+    "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x30",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0",
+    "BriefDescription": "AK Egress Occupancy; Scheduler 0",
+    "PublicDescription": "AK Egress Occupancy; Filter for occupancy from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x30",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1",
+    "BriefDescription": "AK Egress Occupancy; Scheduler 1",
+    "PublicDescription": "AK Egress Occupancy; Filter for occupancy from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL.DRS_CACHE",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to the cache.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL.DRS_CORE",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TxR_BL.DRS_QPI",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+    "BriefDescription": "BL Egress Full; All",
+    "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
+    "BriefDescription": "BL Egress Full; Scheduler 0",
+    "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
+    "BriefDescription": "BL Egress Full; Scheduler 1",
+    "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+    "BriefDescription": "BL Egress Not Empty; All",
+    "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
+    "BriefDescription": "BL Egress Not Empty; Scheduler 0",
+    "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
+    "BriefDescription": "BL Egress Not Empty; Scheduler 1",
+    "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
+    "BriefDescription": "BL Egress Allocations; All",
+    "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
+    "BriefDescription": "BL Egress Allocations; Scheduler 0",
+    "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
+    "BriefDescription": "BL Egress Allocations; Scheduler 1",
+    "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x34",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL",
+    "BriefDescription": "BL Egress Occupancy: All",
+    "PublicDescription": "BL Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x34",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0",
+    "BriefDescription": "BL Egress Occupancy; Scheduler 0",
+    "PublicDescription": "BL Egress Occupancy; Filter for occupancy from scheduler bank 0",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x34",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1",
+    "BriefDescription": "BL Egress Occupancy; Scheduler 1",
+    "PublicDescription": "BL Egress Occupancy; Filter for occupancy from scheduler bank 1",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x1",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x2",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x4",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x8",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x1",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x2",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x4",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x8",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_M_ACT_COUNT.RD",
+    "BriefDescription": "DRAM Activate Count; Activate due to Read",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_M_ACT_COUNT.WR",
+    "BriefDescription": "DRAM Activate Count; Activate due to Write",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xa1",
+    "UMask": "0x1",
+    "EventName": "UNC_M_BYP_CMDS.ACT",
+    "BriefDescription": "ACT command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xa1",
+    "UMask": "0x2",
+    "EventName": "UNC_M_BYP_CMDS.CAS",
+    "BriefDescription": "CAS command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xa1",
+    "UMask": "0x4",
+    "EventName": "UNC_M_BYP_CMDS.PRE",
+    "BriefDescription": "PRE command issued by 2 cycle bypass",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0xF",
+    "EventName": "UNC_M_CAS_COUNT.ALL",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x3",
+    "EventName": "UNC_M_CAS_COUNT.RD",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x1",
+    "EventName": "UNC_M_CAS_COUNT.RD_REG",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x20",
+    "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x2",
+    "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller.  This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ.  While it is possible for underfills to be issed in both WMM and RMM, this event counts both.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x10",
+    "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0xC",
+    "EventName": "UNC_M_CAS_COUNT.WR",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x8",
+    "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic' DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_M_DRAM_PRE_ALL",
+    "BriefDescription": "DRAM Precharge All Commands",
+    "PublicDescription": "Counts the number of times that the precharge all command was sent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+    "BriefDescription": "Number of DRAM Refreshes Issued",
+    "PublicDescription": "Counts the number of refreshes issued.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+    "BriefDescription": "Number of DRAM Refreshes Issued",
+    "PublicDescription": "Counts the number of refreshes issued.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
+    "BriefDescription": "ECC Correctable Errors",
+    "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+    "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+    "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_M_MAJOR_MODES.READ",
+    "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_M_MAJOR_MODES.WRITE",
+    "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x84",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
+    "BriefDescription": "Channel DLLOFF Cycles",
+    "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x85",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CHANNEL_PPD",
+    "BriefDescription": "Channel PPD Cycles",
+    "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x1",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x2",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x4",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x8",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x10",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x20",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x40",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x80",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x86",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
+    "BriefDescription": "Critical Throttle Cycles",
+    "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x43",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_SELF_REFRESH",
+    "BriefDescription": "Clock-Enabled Self-Refresh",
+    "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x1",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x2",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x4",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x8",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x10",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x20",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x40",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x80",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
+    "BriefDescription": "Read Preemption Count; Read over Read Preemption",
+    "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
+    "BriefDescription": "Read Preemption Count; Read over Write Preemption",
+    "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+    "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses.  This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode.  This does not include PRE commands sent as a result of the page close counter expiration.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_M_PRE_COUNT.RD",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to read",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_M_PRE_COUNT.WR",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to write",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xa0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
+    "BriefDescription": "Read CAS issued with HIGH priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xa0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_RD_CAS_PRIO.LOW",
+    "BriefDescription": "Read CAS issued with LOW priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xa0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_RD_CAS_PRIO.MED",
+    "BriefDescription": "Read CAS issued with MEDIUM priority",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xa0",
+    "UMask": "0x8",
+    "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
+    "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb0",
+    "UMask": "0x8",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb0",
+    "UMask": "0x10",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb0",
+    "UMask": "0x20",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb0",
+    "UMask": "0x40",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb0",
+    "UMask": "0x80",
+    "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+    "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x11",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_CYCLES_NE",
+    "BriefDescription": "Read Pending Queue Not Empty",
+    "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x10",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_INSERTS",
+    "BriefDescription": "Read Pending Queue Allocations",
+    "PublicDescription": "Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x91",
+    "UMask": "0x0",
+    "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
+    "BriefDescription": "VMSE MXB write buffer occupancy",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x90",
+    "UMask": "0x2",
+    "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
+    "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x90",
+    "UMask": "0x1",
+    "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
+    "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xc0",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xc0",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WMM_TO_RMM.STARVE",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xc0",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
+    "BriefDescription": "Transition from WMM to RMM because of low threshold",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x22",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_CYCLES_FULL",
+    "BriefDescription": "Write Pending Queue Full Cycles",
+    "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x21",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_CYCLES_NE",
+    "BriefDescription": "Write Pending Queue Not Empty",
+    "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x20",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_INSERTS",
+    "BriefDescription": "Write Pending Queue Allocations",
+    "PublicDescription": "Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x23",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_READ_HIT",
+    "BriefDescription": "Write Pending Queue CAM Match",
+    "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x24",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_WRITE_HIT",
+    "BriefDescription": "Write Pending Queue CAM Match",
+    "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xc1",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WRONG_MM",
+    "BriefDescription": "Not getting the requested Major Mode",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb8",
+    "UMask": "0x1",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb8",
+    "UMask": "0x2",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb8",
+    "UMask": "0x4",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb8",
+    "UMask": "0x8",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb8",
+    "UMask": "0x10",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb8",
+    "UMask": "0x20",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb8",
+    "UMask": "0x40",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xb8",
+    "UMask": "0x80",
+    "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.AnyResp9flits",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.AnyResp11flits",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.DataC_M",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.WbIData",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.WbSData",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.WbEData",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.AnyResp",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.AnyDataC",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.NCB.AnyInt",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.DataC_F",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_FrcAckCnflt",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_Cmp",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.DataC_E",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_FrcAckCnflt",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_Cmp",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.RespFwd",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.RespFwdI",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.RespFwdS",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.RespFwdIWb",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.RespFwdSWb",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.RespIWb",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.RespSWb",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.AnyReq",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.HOM.AnyResp",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.SNP.AnySnp",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.NDR.AnyCmp",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.NCS.NcRd",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg1or2flits",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg3flits",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg9flits",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg11flits",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_MATCH_MASK",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x33",
+    "EventName": "UNC_C_RING_AD_USED.UP",
+    "BriefDescription": "AD Ring In Use; Up",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0xCC",
+    "EventName": "UNC_C_RING_AD_USED.DOWN",
+    "BriefDescription": "AD Ring In Use; Down",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x33",
+    "EventName": "UNC_C_RING_AK_USED.UP",
+    "BriefDescription": "AK Ring In Use; Up",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0xCC",
+    "EventName": "UNC_C_RING_AK_USED.DOWN",
+    "BriefDescription": "AK Ring In Use; Down",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x33",
+    "EventName": "UNC_C_RING_BL_USED.UP",
+    "BriefDescription": "BL Ring in Use; Up",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0xCC",
+    "EventName": "UNC_C_RING_BL_USED.DOWN",
+    "BriefDescription": "BL Ring in Use; Down",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BOUNCES.AD_IRQ",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BOUNCES.AK",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_BOUNCES.BL",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RING_BOUNCES.IV",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_SINK_STARVED.AD_IRQ",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_SINK_STARVED.AD_IPQ",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RING_SINK_STARVED.IV",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles",
+    "PublicDescription": "IRQ is blocking the ingress queue and causing the starvation.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
+    "BriefDescription": "Ingress Allocations; IRQ Rejected",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x1",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
+    "BriefDescription": "QPI Address/Opcode Match; Address",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x2",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
+    "BriefDescription": "QPI Address/Opcode Match; Opcode",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x4",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
+    "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x8",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
+    "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x10",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
+    "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_H_BT_CYCLES_NE",
+    "BriefDescription": "BT Cycles Not Empty",
+    "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x8",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x51",
+    "UMask": "0x10",
+    "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
+    "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+    "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xD",
+    "UMask": "0x1",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
+    "BriefDescription": "Directory Updates; Directory Set",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory sets.  This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xD",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
+    "BriefDescription": "Directory Updates; Directory Clear",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory clears.  This occurs when snoops were sent and all returned with RspI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x59",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IGR_CREDITS_AD_QPI2",
+    "BriefDescription": "AD QPI Link 2 Credit Accumulator",
+    "PublicDescription": "Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x5A",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IGR_CREDITS_BL_QPI2",
+    "BriefDescription": "BL QPI Link 2 Credit Accumulator",
+    "PublicDescription": "Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x57",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IODC_CONFLICTS.ANY",
+    "BriefDescription": "IODC Conflicts; Any Conflict",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x57",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IODC_CONFLICTS.LAST",
+    "BriefDescription": "IODC Conflicts; Last Conflict",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0x33",
+    "EventName": "UNC_H_RING_AD_USED.CW",
+    "BriefDescription": "HA AD Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3E",
+    "UMask": "0xCC",
+    "EventName": "UNC_H_RING_AD_USED.CCW",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0x33",
+    "EventName": "UNC_H_RING_AK_USED.CW",
+    "BriefDescription": "HA AK Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3F",
+    "UMask": "0xCC",
+    "EventName": "UNC_H_RING_AK_USED.CCW",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x33",
+    "EventName": "UNC_H_RING_BL_USED.CW",
+    "BriefDescription": "HA BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0xCC",
+    "EventName": "UNC_H_RING_BL_USED.CCW",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xF",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TxR_AD.HOM",
+    "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
+    "PublicDescription": "Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring.  NDR stands for 'non-data response' and is generally used for completions that do not include data.  AD NDR is used for transactions to remote sockets.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_I_TRANSACTIONS.RD_PREFETCHES",
+    "BriefDescription": "Inbound Transaction Count; Read Prefetches",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE10",
+    "BriefDescription": "Core 10 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x43",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE11",
+    "BriefDescription": "Core 11 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x44",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE12",
+    "BriefDescription": "Core 12 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x45",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE13",
+    "BriefDescription": "Core 13 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x46",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE14",
+    "BriefDescription": "Core 14 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x40",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE8",
+    "BriefDescription": "Core 8 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x41",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE9",
+    "BriefDescription": "Core 9 C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES",
+    "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x26",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PKG_C_EXIT_LATENCY",
+    "BriefDescription": "Package C State Exit Latency",
+    "PublicDescription": "Counts the number of cycles that the package is transitioning from package C2 to C3.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xF",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xF",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
+    "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
+    "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xC",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xC",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xA",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xA",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xB",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xB",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xE",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xE",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xD",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
+    "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xD",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
+    "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
+    "BriefDescription": "RxQ Occupancy - DRS; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
+    "BriefDescription": "RxQ Occupancy - DRS; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x18",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
+    "BriefDescription": "RxQ Occupancy - HOM; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x18",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
+    "BriefDescription": "RxQ Occupancy - HOM; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
+    "BriefDescription": "RxQ Occupancy - NCB; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
+    "BriefDescription": "RxQ Occupancy - NCB; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
+    "BriefDescription": "RxQ Occupancy - NCS; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x17",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
+    "BriefDescription": "RxQ Occupancy - NCS; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1A",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
+    "BriefDescription": "RxQ Occupancy - NDR; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1A",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
+    "BriefDescription": "RxQ Occupancy - NDR; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x19",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
+    "BriefDescription": "RxQ Occupancy - SNP; for VN0",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x19",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
+    "BriefDescription": "RxQ Occupancy - SNP; for VN1",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x29",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
+    "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x25",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
+    "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
+    "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x33",
+    "EventName": "UNC_R2_RING_AD_USED.CW",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0xCC",
+    "EventName": "UNC_R2_RING_AD_USED.CCW",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x33",
+    "EventName": "UNC_R2_RING_AK_USED.CW",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0xCC",
+    "EventName": "UNC_R2_RING_AK_USED.CCW",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x33",
+    "EventName": "UNC_R2_RING_BL_USED.CW",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0xCC",
+    "EventName": "UNC_R2_RING_BL_USED.CCW",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xA",
+    "UMask": "0xFF",
+    "EventName": "UNC_R2_RING_IV_USED.ANY",
+    "BriefDescription": "R2 IV Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RxR_AK_BOUNCES.CW",
+    "BriefDescription": "AK Ingress Bounced; Clockwise",
+    "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RxR_AK_BOUNCES.CCW",
+    "BriefDescription": "AK Ingress Bounced; Counterclockwise",
+    "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_NACK_CCW.AD",
+    "BriefDescription": "Egress CCW NACK; AD CCW",
+    "PublicDescription": "AD CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_NACK_CCW.AK",
+    "BriefDescription": "Egress CCW NACK; AK CCW",
+    "PublicDescription": "AK CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x28",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_NACK_CCW.BL",
+    "BriefDescription": "Egress CCW NACK; BL CCW",
+    "PublicDescription": "BL CounterClockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_NACK_CW.AD",
+    "BriefDescription": "Egress CW NACK; AD CW",
+    "PublicDescription": "AD Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_NACK_CW.AK",
+    "BriefDescription": "Egress CW NACK; AK CW",
+    "PublicDescription": "AK Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_NACK_CW.BL",
+    "BriefDescription": "Egress CW NACK; BL CW",
+    "PublicDescription": "BL Clockwise Egress Queue",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x33",
+    "EventName": "UNC_R3_RING_AD_USED.CW",
+    "BriefDescription": "R3 AD Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0xCC",
+    "EventName": "UNC_R3_RING_AD_USED.CCW",
+    "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x33",
+    "EventName": "UNC_R3_RING_AK_USED.CW",
+    "BriefDescription": "R3 AK Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0xCC",
+    "EventName": "UNC_R3_RING_AK_USED.CCW",
+    "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x33",
+    "EventName": "UNC_R3_RING_BL_USED.CW",
+    "BriefDescription": "R3 BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0xCC",
+    "EventName": "UNC_R3_RING_BL_USED.CCW",
+    "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xA",
+    "UMask": "0xFF",
+    "EventName": "UNC_R3_RING_IV_USED.ANY",
+    "BriefDescription": "R2 IV Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_RxR_AD_BYPASSED",
+    "BriefDescription": "AD Ingress Bypassed",
+    "PublicDescription": "Counts the number of times when the AD Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
+    "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
+    "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x33",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
+    "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
+    "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x46",
+    "UMask": "0x0",
+    "EventName": "UNC_U_RACU_REQUESTS",
+    "BriefDescription": "RACU Request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_M_ACT_COUNT.BYP",
+    "BriefDescription": "DRAM Activate Count; Activate due to Write",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_M_DCLOCKTICKS",
+    "BriefDescription": "DRAM Clockticks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x42",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_PCU_THROTTLING",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_M_PRE_COUNT.BYP",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB1",
+    "UMask": "0x1",
+    "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
+    "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB1",
+    "UMask": "0x2",
+    "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
+    "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB1",
+    "UMask": "0x4",
+    "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
+    "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB1",
+    "UMask": "0x8",
+    "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
+    "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xB1",
+    "UMask": "0x10",
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+    "EventCode": "0xBF",
+    "UMask": "0x40",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0xBF",
+    "UMask": "0x80",
+    "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
+    "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_U_CLOCKTICKS",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_AD_USED.CW",
+    "BriefDescription": "AD Ring In Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1B",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_AD_USED.CCW",
+    "BriefDescription": "AD Ring In Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_AK_USED.CW",
+    "BriefDescription": "AK Ring In Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1C",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_AK_USED.CCW",
+    "BriefDescription": "AK Ring In Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0x3",
+    "EventName": "UNC_C_RING_BL_USED.CW",
+    "BriefDescription": "BL Ring in Use; Clockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1D",
+    "UMask": "0xC",
+    "EventName": "UNC_C_RING_BL_USED.CCW",
+    "BriefDescription": "BL Ring in Use; Counterclockwise",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
+    "BriefDescription": "Ingress Occupancy; IRQ Rejected",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/IVT/IvyTown_uncore_V17.tsv b/x86data/perfmon_data/IVT/IvyTown_uncore_V17.tsv
new file mode 100644
index 0000000..f958b1d
--- /dev/null
+++ b/x86data/perfmon_data/IVT/IvyTown_uncore_V17.tsv
@@ -0,0 +1,1080 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family and Intel(R) Xeon(R) processor E7 family Based on the Ivy Bridge-EP Microarchitecture - V17
+# 7/29/2015 2:56:13 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+Unit	EventCode	UMask	EventName	Description	Counter	MSRValue	Filter	Internal
+CBO	0x0	0x0	UNC_C_CLOCKTICKS	tbd	0,1,2,3	0x0	null	0
+CBO	0x1f	0x0	UNC_C_COUNTER0_OCCUPANCY	Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.	1,2,3	0x0	null	0
+CBO	0x34	0x11	UNC_C_LLC_LOOKUP.ANY	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.	0,1	0x0	CBoFilter0[23:17]	0
+CBO	0x34	0x3	UNC_C_LLC_LOOKUP.DATA_READ	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Read transactions	0,1	0x0	CBoFilter0[23:17]	0
+CBO	0x34	0x41	UNC_C_LLC_LOOKUP.NID	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.	0,1	0x0	CBoFilter0[23:17]	0
+CBO	0x34	0x9	UNC_C_LLC_LOOKUP.REMOTE_SNOOP	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.	0,1	0x0	CBoFilter0[23:17]	0
+CBO	0x34	0x5	UNC_C_LLC_LOOKUP.WRITE	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.	0,1	0x0	CBoFilter0[23:17]	0
+CBO	0x37	0x2	UNC_C_LLC_VICTIMS.E_STATE	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0x0	null	0
+CBO	0x37	0x8	UNC_C_LLC_VICTIMS.MISS	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0x0	null	0
+CBO	0x37	0x1	UNC_C_LLC_VICTIMS.M_STATE	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0x0	null	0
+CBO	0x37	0x40	UNC_C_LLC_VICTIMS.NID	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.	0,1	0x0	CBoFilter1[15:0]	0
+CBO	0x37	0x4	UNC_C_LLC_VICTIMS.S_STATE	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0x0	null	0
+CBO	0x39	0x8	UNC_C_MISC.RFO_HIT_S	Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state.  This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.	0,1	0x0	null	0
+CBO	0x39	0x1	UNC_C_MISC.RSPI_WAS_FSE	Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.	0,1	0x0	null	0
+CBO	0x39	0x4	UNC_C_MISC.STARTED	Miscellaneous events in the Cbo.	0,1	0x0	null	0
+CBO	0x39	0x2	UNC_C_MISC.WC_ALIASING	Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.	0,1	0x0	null	0
+CBO	0x3c	0x1	UNC_C_QLRU.AGE0	How often age was set to 0	0,1	0x0	null	0
+CBO	0x3c	0x2	UNC_C_QLRU.AGE1	How often age was set to 1	0,1	0x0	null	0
+CBO	0x3c	0x4	UNC_C_QLRU.AGE2	How often age was set to 2	0,1	0x0	null	0
+CBO	0x3c	0x8	UNC_C_QLRU.AGE3	How often age was set to 3	0,1	0x0	null	0
+CBO	0x3c	0x10	UNC_C_QLRU.LRU_DECREMENT	How often all LRU bits were decremented by 1	0,1	0x0	null	0
+CBO	0x3c	0x20	UNC_C_QLRU.VICTIM_NON_ZERO	How often we picked a victim that had a non-zero age	0,1	0x0	null	0
+CBO	0x1b	0x4	UNC_C_RING_AD_USED.DOWN_VR0_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1b	0x8	UNC_C_RING_AD_USED.DOWN_VR0_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1b	0x40	UNC_C_RING_AD_USED.DOWN_VR1_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1b	0x80	UNC_C_RING_AD_USED.DOWN_VR1_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1b	0x1	UNC_C_RING_AD_USED.UP_VR0_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1b	0x2	UNC_C_RING_AD_USED.UP_VR0_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1b	0x10	UNC_C_RING_AD_USED.UP_VR1_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1b	0x20	UNC_C_RING_AD_USED.UP_VR1_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1c	0x4	UNC_C_RING_AK_USED.DOWN_VR0_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1c	0x8	UNC_C_RING_AK_USED.DOWN_VR0_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1c	0x40	UNC_C_RING_AK_USED.DOWN_VR1_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1c	0x80	UNC_C_RING_AK_USED.DOWN_VR1_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1c	0x1	UNC_C_RING_AK_USED.UP_VR0_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1c	0x2	UNC_C_RING_AK_USED.UP_VR0_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1c	0x10	UNC_C_RING_AK_USED.UP_VR1_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1c	0x20	UNC_C_RING_AK_USED.UP_VR1_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1d	0x4	UNC_C_RING_BL_USED.DOWN_VR0_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1d	0x8	UNC_C_RING_BL_USED.DOWN_VR0_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1d	0x40	UNC_C_RING_BL_USED.DOWN_VR1_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1d	0x80	UNC_C_RING_BL_USED.DOWN_VR1_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1d	0x1	UNC_C_RING_BL_USED.UP_VR0_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1d	0x2	UNC_C_RING_BL_USED.UP_VR0_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.	2,3	0x0	null	0
+CBO	0x1d	0x10	UNC_C_RING_BL_USED.UP_VR1_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x1d	0x20	UNC_C_RING_BL_USED.UP_VR1_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.	2,3	0x0	null	0
+CBO	0x5	0x2	UNC_C_RING_BOUNCES.AK_CORE	tbd	0,1	0x0	null	0
+CBO	0x5	0x4	UNC_C_RING_BOUNCES.BL_CORE	tbd	0,1	0x0	null	0
+CBO	0x5	0x8	UNC_C_RING_BOUNCES.IV_CORE	tbd	0,1	0x0	null	0
+CBO	0x1e	0xF	UNC_C_RING_IV_USED.ANY	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity	2,3	0x0	null	0
+CBO	0x1e	0xCC	UNC_C_RING_IV_USED.DOWN	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity	2,3	0x0	null	0
+CBO	0x1e	0x33	UNC_C_RING_IV_USED.UP	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Up polarity	2,3	0x0	null	0
+CBO	0x7	0x0	UNC_C_RING_SRC_THRTL	tbd	0,1	0x0	null	0
+CBO	0x12	0x2	UNC_C_RxR_EXT_STARVED.IPQ	Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.	0,1	0x0	null	0
+CBO	0x12	0x1	UNC_C_RxR_EXT_STARVED.IRQ	Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.	0,1	0x0	null	0
+CBO	0x12	0x4	UNC_C_RxR_EXT_STARVED.PRQ	Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues. IRQ is blocking the ingress queue and causing the starvation.	0,1	0x0	null	0
+CBO	0x12	0x8	UNC_C_RxR_EXT_STARVED.ISMQ_BIDS	Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.	0,1	0x0	null	0
+CBO	0x13	0x4	UNC_C_RxR_INSERTS.IPQ	Counts number of allocations per cycle into the specified Ingress queue.	0,1	0x0	null	0
+CBO	0x13	0x1	UNC_C_RxR_INSERTS.IRQ	Counts number of allocations per cycle into the specified Ingress queue.	0,1	0x0	null	0
+CBO	0x13	0x2	UNC_C_RxR_INSERTS.IRQ_REJECTED	Counts number of allocations per cycle into the specified Ingress queue.	0,1	0x0	null	0
+CBO	0x13	0x10	UNC_C_RxR_INSERTS.VFIFO	Counts number of allocations per cycle into the specified Ingress queue.; Counts the number of allocations into the IRQ Ordering FIFO.  In JKT, it is necessary to keep IO requests in order.  Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other).  This event, in conjunction with the Occupancy Accumulator event, can be used to calculate average lifetime in the FIFO.  Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ.	0,1	0x0	null	0
+CBO	0x14	0x4	UNC_C_RxR_INT_STARVED.IPQ	Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.	0,1	0x0	null	0
+CBO	0x14	0x1	UNC_C_RxR_INT_STARVED.IRQ	Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.	0,1	0x0	null	0
+CBO	0x14	0x8	UNC_C_RxR_INT_STARVED.ISMQ	Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.	0,1	0x0	null	0
+CBO	0x31	0x4	UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT	Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts.  Address conflicts out of the IPQ should be rare.  They will generally only occur if two different sockets are sending requests to the same address at the same time.  This is a true 'conflict' case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.	0,1	0x0	null	0
+CBO	0x31	0x1	UNC_C_RxR_IPQ_RETRY.ANY	Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject.  TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.	0,1	0x0	null	0
+CBO	0x31	0x2	UNC_C_RxR_IPQ_RETRY.FULL	Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full.  IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.	0,1	0x0	null	0
+CBO	0x31	0x10	UNC_C_RxR_IPQ_RETRY.QPI_CREDITS	Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.	0,1	0x0	null	0
+CBO	0x32	0x4	UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT	Counts the number of times that a request from the IRQ was retried because of an address match in the TOR.  In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo.  Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete.  This comes up most commonly with prefetches.  Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC.  Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.	0,1	0x0	null	0
+CBO	0x32	0x1	UNC_C_RxR_IRQ_RETRY.ANY	Counts the number of IRQ retries that occur.  Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons.  Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.	0,1	0x0	null	0
+CBO	0x32	0x2	UNC_C_RxR_IRQ_RETRY.FULL	Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress.  The egress is the buffer that queues up for allocating onto the ring.  IRQ requests can make use of all four rings and all four Egresses.  If any of the queues that a given request needs to make use of are full, the request will be retried.	0,1	0x0	null	0
+CBO	0x32	0x20	UNC_C_RxR_IRQ_RETRY.IIO_CREDITS	Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.	0,1	0x0	null	0
+CBO	0x32	0x10	UNC_C_RxR_IRQ_RETRY.QPI_CREDITS	Number of requests rejects because of lack of QPI Ingress credits.  These credits are required in order to send transactions to the QPI agent.  Please see the QPI_IGR_CREDITS events for more information.	0,1	0x0	null	0
+CBO	0x32	0x8	UNC_C_RxR_IRQ_RETRY.RTID	Counts the number of times that requests from the IRQ were retried because there were no RTIDs available.  RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory.  If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available.  Note that there are multiple RTID pools for the different sockets.  There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available.  This event does not provide any filtering for this case.	0,1	0x0	null	0
+CBO	0x33	0x1	UNC_C_RxR_ISMQ_RETRY.ANY	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject.  ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries).  ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID.  Most ISMQ requests already have an RTID, so eviction retries will be less common here.	0,1	0x0	null	0
+CBO	0x33	0x2	UNC_C_RxR_ISMQ_RETRY.FULL	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring.  If any of the Egress queues that a given request needs to make use of are full, the request will be retried.	0,1	0x0	null	0
+CBO	0x33	0x20	UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.	0,1	0x0	null	0
+CBO	0x33	0x10	UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.	0,1	0x0	null	0
+CBO	0x33	0x8	UNC_C_RxR_ISMQ_RETRY.RTID	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs.  M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory.  If no RTIDs are available, they will be retried.	0,1	0x0	null	0
+CBO	0x33	0x80	UNC_C_RxR_ISMQ_RETRY.WB_CREDITS	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Retries of writes to local memory due to lack of HT WB credits	0,1	0x0	null	0
+CBO	0x11	0x4	UNC_C_RxR_OCCUPANCY.IPQ	Counts number of entries in the specified Ingress queue in each cycle.	0	0x0	null	0
+CBO	0x11	0x1	UNC_C_RxR_OCCUPANCY.IRQ	Counts number of entries in the specified Ingress queue in each cycle.	0	0x0	null	0
+CBO	0x11	0x2	UNC_C_RxR_OCCUPANCY.IRQ_REJECTED	Counts number of entries in the specified Ingress queue in each cycle.	0	0x0	null	0
+CBO	0x11	0x10	UNC_C_RxR_OCCUPANCY.VFIFO	Counts number of entries in the specified Ingress queue in each cycle.; Accumulates the number of used entries in the IRQ Ordering FIFO in each cycle.  In JKT, it is necessary to keep IO requests in order.  Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other).  This event, in conjunction with the Allocations event, can be used to calculate average lifetime in the FIFO.  This event can be used in conjunction with the Not Empty event to calculate average queue occupancy. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ.	0	0x0	null	0
+CBO	0x35	0x8	UNC_C_TOR_INSERTS.ALL	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR.    This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.	0,1	0x0	null	0
+CBO	0x35	0x4	UNC_C_TOR_INSERTS.EVICTION	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Eviction transactions inserted into the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).	0,1	0x0	null	0
+CBO	0x35	0x28	UNC_C_TOR_INSERTS.LOCAL	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.	0,1	0x0	null	0
+CBO	0x35	0x21	UNC_C_TOR_INSERTS.LOCAL_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by locally HOMed memory.	0,1	0x0	CBoFilter1[28:20]	0
+CBO	0x35	0x2A	UNC_C_TOR_INSERTS.MISS_LOCAL	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.	0,1	0x0	null	0
+CBO	0x35	0x23	UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.	0,1	0x0	CBoFilter1[28:20]	0
+CBO	0x35	0x3	UNC_C_TOR_INSERTS.MISS_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.	0,1	0x0	CBoFilter1[28:20]	0
+CBO	0x35	0x8A	UNC_C_TOR_INSERTS.MISS_REMOTE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.	0,1	0x0	null	0
+CBO	0x35	0x83	UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.	0,1	0x0	CBoFilter1[28:20]	0
+CBO	0x35	0x48	UNC_C_TOR_INSERTS.NID_ALL	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.  In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.	0,1	0x0	CBoFilter1[15:0]	0
+CBO	0x35	0x44	UNC_C_TOR_INSERTS.NID_EVICTION	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched eviction transactions inserted into the TOR.	0,1	0x0	CBoFilter1[15:0]	0
+CBO	0x35	0x4A	UNC_C_TOR_INSERTS.NID_MISS_ALL	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.	0,1	0x0	CBoFilter1[15:0]	0
+CBO	0x35	0x43	UNC_C_TOR_INSERTS.NID_MISS_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.	0,1	0x0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x35	0x41	UNC_C_TOR_INSERTS.NID_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.	0,1	0x0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x35	0x50	UNC_C_TOR_INSERTS.NID_WB	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched write transactions inserted into the TOR.	0,1	0x0	CBoFilter1[15:0]	0
+CBO	0x35	0x1	UNC_C_TOR_INSERTS.OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)	0,1	0x0	CBoFilter1[28:20]	0
+CBO	0x35	0x88	UNC_C_TOR_INSERTS.REMOTE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.	0,1	0x0	null	0
+CBO	0x35	0x81	UNC_C_TOR_INSERTS.REMOTE_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.	0,1	0x0	CBoFilter1[28:20]	0
+CBO	0x35	0x10	UNC_C_TOR_INSERTS.WB	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Write transactions inserted into the TOR.   This does not include 'RFO', but actual operations that contain data being sent from the core.	0,1	0x0	null	0
+CBO	0x36	0x8	UNC_C_TOR_OCCUPANCY.ALL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries.  This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.	0	0x0	null	0
+CBO	0x36	0x4	UNC_C_TOR_OCCUPANCY.EVICTION	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).	0	0x0	null	0
+CBO	0x36	0x28	UNC_C_TOR_OCCUPANCY.LOCAL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0x0	null	0
+CBO	0x36	0x21	UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by locally HOMed memory.	0	0x0	CBoFilter1[28:20]	0
+CBO	0x36	0xA	UNC_C_TOR_OCCUPANCY.MISS_ALL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.	0	0x0	null	0
+CBO	0x36	0x2A	UNC_C_TOR_OCCUPANCY.MISS_LOCAL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0x0	null	0
+CBO	0x36	0x23	UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.	0	0x0	CBoFilter1[28:20]	0
+CBO	0x36	0x3	UNC_C_TOR_OCCUPANCY.MISS_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.	0	0x0	CBoFilter1[28:20]	0
+CBO	0x36	0x8A	UNC_C_TOR_OCCUPANCY.MISS_REMOTE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0x0	null	0
+CBO	0x36	0x83	UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.	0	0x0	CBoFilter1[28:20]	0
+CBO	0x36	0x48	UNC_C_TOR_OCCUPANCY.NID_ALL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.	0	0x0	CBoFilter1[15:0]	0
+CBO	0x36	0x44	UNC_C_TOR_OCCUPANCY.NID_EVICTION	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .	0	0x0	CBoFilter1[15:0]	0
+CBO	0x36	0x4A	UNC_C_TOR_OCCUPANCY.NID_MISS_ALL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.	0	0x0	CBoFilter1[15:0]	0
+CBO	0x36	0x43	UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.	0	0x0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x36	0x41	UNC_C_TOR_OCCUPANCY.NID_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.	0	0x0	CBoFilter1[28:20], CBoFilter1[15:0]	0
+CBO	0x36	0x50	UNC_C_TOR_OCCUPANCY.NID_WB	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.	0	0x0	CBoFilter1[15:0]	0
+CBO	0x36	0x1	UNC_C_TOR_OCCUPANCY.OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).	0	0x0	CBoFilter1[28:20]	0
+CBO	0x36	0x88	UNC_C_TOR_OCCUPANCY.REMOTE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0x0	null	0
+CBO	0x36	0x81	UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by remote caches or remote memory.	0	0x0	CBoFilter1[28:20]	0
+CBO	0x36	0x10	UNC_C_TOR_OCCUPANCY.WB	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR.   This does not include 'RFO', but actual operations that contain data being sent from the core.	0	0x0	null	0
+CBO	0x4	0x1	UNC_C_TxR_ADS_USED.AD	tbd	0,1	0x0	null	0
+CBO	0x4	0x2	UNC_C_TxR_ADS_USED.AK	tbd	0,1	0x0	null	0
+CBO	0x4	0x4	UNC_C_TxR_ADS_USED.BL	tbd	0,1	0x0	null	0
+CBO	0x2	0x1	UNC_C_TxR_INSERTS.AD_CACHE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.	0,1	0x0	null	0
+CBO	0x2	0x10	UNC_C_TxR_INSERTS.AD_CORE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring.  This is commonly used for outbound requests.	0,1	0x0	null	0
+CBO	0x2	0x2	UNC_C_TxR_INSERTS.AK_CACHE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring.  This is commonly used for credit returns and GO responses.	0,1	0x0	null	0
+CBO	0x2	0x20	UNC_C_TxR_INSERTS.AK_CORE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring.  This is commonly used for snoop responses coming from the core and destined for a Cachebo.	0,1	0x0	null	0
+CBO	0x2	0x4	UNC_C_TxR_INSERTS.BL_CACHE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring.  This is commonly used to send data from the cache to various destinations.	0,1	0x0	null	0
+CBO	0x2	0x40	UNC_C_TxR_INSERTS.BL_CORE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring.  This is commonly used for transfering writeback data to the cache.	0,1	0x0	null	0
+CBO	0x2	0x8	UNC_C_TxR_INSERTS.IV_CACHE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring.  This is commonly used for snoops to the cores.	0,1	0x0	null	0
+CBO	0x3	0x10	UNC_C_TxR_STARVED.AD_CORE	Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation	0,1	0x0	null	0
+CBO	0x3	0x2	UNC_C_TxR_STARVED.AK_BOTH	Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation	0,1	0x0	null	0
+CBO	0x3	0x8	UNC_C_TxR_STARVED.IV	Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation	0,1	0x0	null	0
+PCU	0x0	0x0	UNC_P_CLOCKTICKS	The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.	0,1,2,3	0x0	null	0
+PCU	0x70	0x0	UNC_P_CORE0_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x7a	0x0	UNC_P_CORE10_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x7b	0x0	UNC_P_CORE11_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x7c	0x0	UNC_P_CORE12_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x7d	0x0	UNC_P_CORE13_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x7e	0x0	UNC_P_CORE14_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x71	0x0	UNC_P_CORE1_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x72	0x0	UNC_P_CORE2_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x73	0x0	UNC_P_CORE3_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x74	0x0	UNC_P_CORE4_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x75	0x0	UNC_P_CORE5_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x76	0x0	UNC_P_CORE6_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x77	0x0	UNC_P_CORE7_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x78	0x0	UNC_P_CORE8_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x79	0x0	UNC_P_CORE9_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0x0	null	0
+PCU	0x17	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE0	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x18	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE1	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x21	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE10	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x22	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE11	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x23	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE12	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x24	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE13	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x25	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE14	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x19	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE2	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x1a	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE3	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x1b	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE4	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x1c	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE5	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x1d	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE6	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x1e	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE7	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x1f	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE8	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x20	0x0	UNC_P_DELAYED_C_STATE_ABORT_CORE9	Number of times that a deep C state was requested, but the delayed C state algorithm 'rejected' the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.	0,1,2,3	0x0	null	1
+PCU	0x1e	0x0	UNC_P_DEMOTIONS_CORE0	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0x1f	0x0	UNC_P_DEMOTIONS_CORE1	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0x20	0x0	UNC_P_DEMOTIONS_CORE2	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0x21	0x0	UNC_P_DEMOTIONS_CORE3	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0x22	0x0	UNC_P_DEMOTIONS_CORE4	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0x23	0x0	UNC_P_DEMOTIONS_CORE5	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0x24	0x0	UNC_P_DEMOTIONS_CORE6	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0x25	0x0	UNC_P_DEMOTIONS_CORE7	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0xb	0x0	UNC_P_FREQ_BAND0_CYCLES	Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.	0,1,2,3	0x0	PCUFilter[7:0]	0
+PCU	0xc	0x0	UNC_P_FREQ_BAND1_CYCLES	Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.	0,1,2,3	0x0	PCUFilter[15:8]	0
+PCU	0xd	0x0	UNC_P_FREQ_BAND2_CYCLES	Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.	0,1,2,3	0x0	PCUFilter[23:16]	0
+PCU	0xe	0x0	UNC_P_FREQ_BAND3_CYCLES	Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.	0,1,2,3	0x0	PCUFilter[31:24]	0
+PCU	0x7	0x0	UNC_P_FREQ_MAX_CURRENT_CYCLES	Counts the number of cycles when current is the upper limit on frequency.	0,1,2,3	0x0	null	0
+PCU	0x4	0x0	UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES	Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.	0,1,2,3	0x0	null	0
+PCU	0x6	0x0	UNC_P_FREQ_MAX_OS_CYCLES	Counts the number of cycles when the OS is the upper limit on frequency.	0,1,2,3	0x0	null	0
+PCU	0x5	0x0	UNC_P_FREQ_MAX_POWER_CYCLES	Counts the number of cycles when power is the upper limit on frequency.	0,1,2,3	0x0	null	0
+PCU	0x61	0x0	UNC_P_FREQ_MIN_IO_P_CYCLES	Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.	0,1,2,3	0x0	null	0
+PCU	0x62	0x0	UNC_P_FREQ_MIN_PERF_P_CYCLES	Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies.	0,1,2,3	0x0	null	0
+PCU	0x60	0x0	UNC_P_FREQ_TRANS_CYCLES	Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.	0,1,2,3	0x0	null	0
+PCU	0x2f	0x0	UNC_P_MEMORY_PHASE_SHEDDING_CYCLES	Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.	0,1,2,3	0x0	null	0
+PCU	0x26	0x0	UNC_P_PKG_C_EXIT_LATENCY_SEL	Counts the number of cycles that the package is transitioning from package C2 to C3.	0,1,2,3	0x0	null	1
+PCU	0x2a	0x0	UNC_P_PKG_C_STATE_RESIDENCY_C0_CYCLES	Counts the number of cycles that the package is in C0	0,1,2,3	0x0	null	1
+PCU	0x2b	0x0	UNC_P_PKG_C_STATE_RESIDENCY_C2_CYCLES	Counts the number of cycles that the package is in C2	0,1,2,3	0x0	null	1
+PCU	0x2c	0x0	UNC_P_PKG_C_STATE_RESIDENCY_C3_CYCLES	Counts the number of cycles that the package is in C3	0,1,2,3	0x0	null	1
+PCU	0x2d	0x0	UNC_P_PKG_C_STATE_RESIDENCY_C6_CYCLES	Counts the number of cycles that the package is in C6	0,1,2,3	0x0	null	1
+PCU	0x80	0x40	UNC_P_POWER_STATE_OCCUPANCY.CORES_C0	This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.	0,1,2,3	0x0	null	0
+PCU	0x80	0x80	UNC_P_POWER_STATE_OCCUPANCY.CORES_C3	This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.	0,1,2,3	0x0	null	0
+PCU	0x80	0xC0	UNC_P_POWER_STATE_OCCUPANCY.CORES_C6	This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.	0,1,2,3	0x0	null	0
+PCU	0xa	0x0	UNC_P_PROCHOT_EXTERNAL_CYCLES	Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.	0,1,2,3	0x0	null	0
+PCU	0x9	0x0	UNC_P_PROCHOT_INTERNAL_CYCLES	Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.	0,1,2,3	0x0	null	0
+PCU	0x63	0x0	UNC_P_TOTAL_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions across all cores.	0,1,2,3	0x0	null	0
+PCU	0x3	0x0	UNC_P_VOLT_TRANS_CYCLES_CHANGE	Counts the number of cycles when the system is changing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.  This event is calculated by or'ing together the increasing and decreasing events.	0,1,2,3	0x0	null	0
+PCU	0x2	0x0	UNC_P_VOLT_TRANS_CYCLES_DECREASE	Counts the number of cycles when the system is decreasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.	0,1,2,3	0x0	null	0
+PCU	0x1	0x0	UNC_P_VOLT_TRANS_CYCLES_INCREASE	Counts the number of cycles when the system is increasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.	0,1,2,3	0x0	null	0
+PCU	0x32	0x0	UNC_P_VR_HOT_CYCLES	tbd	0,1,2,3	0x0	null	0
+UBOX	0x42	0x8	UNC_U_EVENT_MSG.DOORBELL_RCVD	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	null	0
+UBOX	0x42	0x10	UNC_U_EVENT_MSG.INT_PRIO	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	null	0
+UBOX	0x42	0x4	UNC_U_EVENT_MSG.IPI_RCVD	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	null	0
+UBOX	0x42	0x2	UNC_U_EVENT_MSG.MSI_RCVD	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	null	0
+UBOX	0x42	0x1	UNC_U_EVENT_MSG.VLW_RCVD	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	null	0
+UBOX	0x41	0x2	UNC_U_FILTER_MATCH.DISABLE	Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	null	0
+UBOX	0x41	0x1	UNC_U_FILTER_MATCH.ENABLE	Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	UBoxFilter[3:0]	0
+UBOX	0x41	0x8	UNC_U_FILTER_MATCH.U2C_DISABLE	Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	null	0
+UBOX	0x41	0x4	UNC_U_FILTER_MATCH.U2C_ENABLE	Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0x0	UBoxFilter[3:0]	0
+UBOX	0x44	0x0	UNC_U_LOCK_CYCLES	Number of times an IDI Lock/SplitLock sequence was started	0,1	0x0	null	0
+UBOX	0x45	0x1	UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK	PHOLD cycles.  Filter from source CoreID.	0,1	0x0	null	0
+UBOX	0x43	0x10	UNC_U_U2C_EVENTS.CMC	Events coming from Uncore can be sent to one or all cores	0,1	0x0	null	0
+UBOX	0x43	0x4	UNC_U_U2C_EVENTS.LIVELOCK	Events coming from Uncore can be sent to one or all cores; Filter by core	0,1	0x0	null	0
+UBOX	0x43	0x8	UNC_U_U2C_EVENTS.LTERROR	Events coming from Uncore can be sent to one or all cores; Filter by core	0,1	0x0	null	0
+UBOX	0x43	0x1	UNC_U_U2C_EVENTS.MONITOR_T0	Events coming from Uncore can be sent to one or all cores; Filter by core	0,1	0x0	null	0
+UBOX	0x43	0x2	UNC_U_U2C_EVENTS.MONITOR_T1	Events coming from Uncore can be sent to one or all cores; Filter by core	0,1	0x0	null	0
+UBOX	0x43	0x80	UNC_U_U2C_EVENTS.OTHER	Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI	0,1	0x0	null	0
+UBOX	0x43	0x40	UNC_U_U2C_EVENTS.TRAP	Events coming from Uncore can be sent to one or all cores	0,1	0x0	null	0
+UBOX	0x43	0x20	UNC_U_U2C_EVENTS.UMC	Events coming from Uncore can be sent to one or all cores	0,1	0x0	null	0
+IRP	0x17	0x2	UNC_I_ADDRESS_MATCH.MERGE_COUNT	Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When two requests to the same address from the same source are received back to back, it is possible to merge the two of them together.	0,1	0x0	null	0
+IRP	0x17	0x1	UNC_I_ADDRESS_MATCH.STALL_COUNT	Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When it is not possible to merge two conflicting requests, a stall event occurs.  This is bad for performance.	0,1	0x0	null	0
+IRP	0x14	0x1	UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY	Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.	0,1	0x0	null	0
+IRP	0x14	0x2	UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE	Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port.	0,1	0x0	null	0
+IRP	0x13	0x1	UNC_I_CACHE_OWN_OCCUPANCY.ANY	Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks all requests from any source port.	0,1	0x0	null	0
+IRP	0x13	0x2	UNC_I_CACHE_OWN_OCCUPANCY.SOURCE	Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.	0,1	0x0	null	0
+IRP	0x10	0x1	UNC_I_CACHE_READ_OCCUPANCY.ANY	Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks all requests from any source port.	0,1	0x0	null	0
+IRP	0x10	0x2	UNC_I_CACHE_READ_OCCUPANCY.SOURCE	Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.	0,1	0x0	null	0
+IRP	0x12	0x1	UNC_I_CACHE_TOTAL_OCCUPANCY.ANY	Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.	0,1	0x0	null	0
+IRP	0x12	0x2	UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE	Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.	0,1	0x0	null	0
+IRP	0x11	0x1	UNC_I_CACHE_WRITE_OCCUPANCY.ANY	Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks all requests from any source port.	0,1	0x0	null	0
+IRP	0x11	0x2	UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE	Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.	0,1	0x0	null	0
+IRP	0x0	0x0	UNC_I_CLOCKTICKS	Number of clocks in the IRP.	0,1	0x0	null	0
+IRP	0xb	0x0	UNC_I_RxR_AK_CYCLES_FULL	Counts the number of cycles when the AK Ingress is full.  This queue is where the IRP receives responses from R2PCIe (the ring).	0,1	0x0	null	0
+IRP	0xa	0x0	UNC_I_RxR_AK_INSERTS	Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).	0,1	0x0	null	0
+IRP	0xc	0x0	UNC_I_RxR_AK_OCCUPANCY	Accumulates the occupancy of the AK Ingress in each cycles.  This queue is where the IRP receives responses from R2PCIe (the ring).	0,1	0x0	null	0
+IRP	0x4	0x0	UNC_I_RxR_BL_DRS_CYCLES_FULL	Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x1	0x0	UNC_I_RxR_BL_DRS_INSERTS	Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x7	0x0	UNC_I_RxR_BL_DRS_OCCUPANCY	Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x5	0x0	UNC_I_RxR_BL_NCB_CYCLES_FULL	Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x2	0x0	UNC_I_RxR_BL_NCB_INSERTS	Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x8	0x0	UNC_I_RxR_BL_NCB_OCCUPANCY	Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x6	0x0	UNC_I_RxR_BL_NCS_CYCLES_FULL	Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x3	0x0	UNC_I_RxR_BL_NCS_INSERTS	Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x9	0x0	UNC_I_RxR_BL_NCS_OCCUPANCY	Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0x0	null	0
+IRP	0x16	0x1	UNC_I_TICKLES.LOST_OWNERSHIP	Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of requests that lost ownership as a result of a tickle.  When a tickle comes in, if the request is not at the head of the queue in the switch, then that request as well as any requests behind it in the switch queue will lose ownership and have to re-acquire it later when they get to the head of the queue.  This will therefore track the number of requests that lost ownership and not just the number of tickles.	0,1	0x0	null	0
+IRP	0x16	0x2	UNC_I_TICKLES.TOP_OF_QUEUE	Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of cases when a tickle was received but the requests was at the head of the queue in the switch.  In this case, data is returned rather than releasing ownership.	0,1	0x0	null	0
+IRP	0x15	0x8	UNC_I_TRANSACTIONS.ORDERINGQ	Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.  If this bit is not set, then requests from all sources will be counted.	0,1	0x0	IRPFilter[4:0]	0
+IRP	0x15	0x4	UNC_I_TRANSACTIONS.PD_PREFETCHES	Counts the number of \Inbound\' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.'	0,1	0x0	null	0
+IRP	0x15	0x1	UNC_I_TRANSACTIONS.READS	Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).	0,1	0x0	null	0
+IRP	0x15	0x2	UNC_I_TRANSACTIONS.WRITES	Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.	0,1	0x0	null	0
+IRP	0x18	0x0	UNC_I_TxR_AD_STALL_CREDIT_CYCLES	Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.	0,1	0x0	null	0
+IRP	0x19	0x0	UNC_I_TxR_BL_STALL_CREDIT_CYCLES	Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.	0,1	0x0	null	0
+IRP	0xe	0x0	UNC_I_TxR_DATA_INSERTS_NCB	Counts the number of requests issued to the switch (towards the devices).	0,1	0x0	null	0
+IRP	0xf	0x0	UNC_I_TxR_DATA_INSERTS_NCS	Counts the number of requests issued to the switch (towards the devices).	0,1	0x0	null	0
+IRP	0xd	0x0	UNC_I_TxR_REQUEST_OCCUPANCY	Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.	0,1	0x0	null	0
+IRP	0x1a	0x0	UNC_I_WRITE_ORDERING_STALL_CYCLES	Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized.	0,1	0x0	null	0
+QPI LL	0x14	0x0	UNC_Q_CLOCKTICKS	Counts the number of clocks in the QPI LL.  This clock runs at 1/8th the 'GT/s' speed of the QPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  JKT does not support dynamic link speeds, so this frequency is fixed.	0,1,2,3	0x0	null	0
+QPI LL	0x38	0x0	UNC_Q_CTO_COUNT	Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.	0,1,2,3	0x0	QPIMask0[17:0],QPIMatch0[17:0],QPIMask1[19:16],QPIMatch1[19:16]	1
+QPI LL	0x13	0x2	UNC_Q_DIRECT2CORE.FAILURE_CREDITS	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits.  Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.	0,1,2,3	0x0	null	0
+QPI LL	0x13	0x20	UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits.   The valid bit was set.	0,1,2,3	0x0	null	0
+QPI LL	0x13	0x8	UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.	0,1,2,3	0x0	null	0
+QPI LL	0x13	0x80	UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.	0,1,2,3	0x0	null	0
+QPI LL	0x13	0x10	UNC_Q_DIRECT2CORE.FAILURE_MISS	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.	0,1,2,3	0x0	null	0
+QPI LL	0x13	0x4	UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction.  This is common for IO transactions.  There were enough Egress credits and the RBT tag matched but the valid bit was not set.	0,1,2,3	0x0	null	0
+QPI LL	0x13	0x40	UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.	0,1,2,3	0x0	null	0
+QPI LL	0x13	0x1	UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful.  There were sufficient credits, the RBT valid bit was set and there was an RBT tag match.  The message was marked to spawn direct2core.	0,1,2,3	0x0	null	0
+QPI LL	0x12	0x0	UNC_Q_L1_POWER_CYCLES	Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.	0,1,2,3	0x0	null	0
+QPI LL	0x10	0x0	UNC_Q_RxL0P_POWER_CYCLES	Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.	0,1,2,3	0x0	null	0
+QPI LL	0xf	0x0	UNC_Q_RxL0_POWER_CYCLES	Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.	0,1,2,3	0x0	null	0
+QPI LL	0x9	0x0	UNC_Q_RxL_BYPASSED	Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.	0,1,2,3	0x0	null	0
+QPI LL	0x3	0x1	UNC_Q_RxL_CRC_ERRORS.LINK_INIT	Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.	0,1,2,3	0x0	null	0
+QPI LL	0x3	0x2	UNC_Q_RxL_CRC_ERRORS.NORMAL_OP	Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.	0,1,2,3	0x0	null	0
+QPI LL	0x1e	0x1	UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.	0,1,2,3	0x0	null	1
+QPI LL	0x1e	0x8	UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.	0,1,2,3	0x0	null	1
+QPI LL	0x1e	0x2	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.	0,1,2,3	0x0	null	1
+QPI LL	0x1e	0x4	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.	0,1,2,3	0x0	null	1
+QPI LL	0x1e	0x20	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.	0,1,2,3	0x0	null	1
+QPI LL	0x1e	0x10	UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.	0,1,2,3	0x0	null	1
+QPI LL	0x39	0x1	UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS	Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.	0,1,2,3	0x0	null	1
+QPI LL	0x39	0x8	UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM	Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.	0,1,2,3	0x0	null	1
+QPI LL	0x39	0x2	UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB	Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.	0,1,2,3	0x0	null	1
+QPI LL	0x39	0x4	UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS	Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.	0,1,2,3	0x0	null	1
+QPI LL	0x39	0x20	UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR	Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.	0,1,2,3	0x0	null	1
+QPI LL	0x39	0x10	UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP	Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.	0,1,2,3	0x0	null	1
+QPI LL	0x1d	0x0	UNC_Q_RxL_CREDITS_CONSUMED_VNA	Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.	0,1,2,3	0x0	null	1
+QPI LL	0xa	0x0	UNC_Q_RxL_CYCLES_NE	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.	0,1,2,3	0x0	null	0
+QPI LL	0x1	0x2	UNC_Q_RxL_FLITS_G0.DATA	Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flitsreceived over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.	0,1,2,3	0x0	null	0
+QPI LL	0x1	0x1	UNC_Q_RxL_FLITS_G0.IDLE	Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload.  When QPI is not in a power saving state, it continuously transmits flits across the link.  When there are no protocol flits to send, it will send IDLE and NULL flits  across.  These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth.	0,1,2,3	0x0	null	0
+QPI LL	0x1	0x4	UNC_Q_RxL_FLITS_G0.NON_DATA	Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits received across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.	0,1,2,3	0x0	null	0
+QPI LL	0x2	0x18	UNC_Q_RxL_FLITS_G1.DRS	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.	0,1,2,3	0x0	null	1
+QPI LL	0x2	0x8	UNC_Q_RxL_FLITS_G1.DRS_DATA	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).	0,1,2,3	0x0	null	1
+QPI LL	0x2	0x10	UNC_Q_RxL_FLITS_G1.DRS_NONDATA	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.	0,1,2,3	0x0	null	1
+QPI LL	0x2	0x6	UNC_Q_RxL_FLITS_G1.HOM	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.	0,1,2,3	0x0	null	1
+QPI LL	0x2	0x4	UNC_Q_RxL_FLITS_G1.HOM_NONREQ	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.	0,1,2,3	0x0	null	1
+QPI LL	0x2	0x2	UNC_Q_RxL_FLITS_G1.HOM_REQ	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel.  This basically counts the number of remote memory requests received over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.	0,1,2,3	0x0	null	1
+QPI LL	0x2	0x1	UNC_Q_RxL_FLITS_G1.SNP	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are received on the home channel.	0,1,2,3	0x0	null	1
+QPI LL	0x3	0xC	UNC_Q_RxL_FLITS_G2.NCB	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.	0,1,2,3	0x0	null	1
+QPI LL	0x3	0x4	UNC_Q_RxL_FLITS_G2.NCB_DATA	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers.	0,1,2,3	0x0	null	1
+QPI LL	0x3	0x8	UNC_Q_RxL_FLITS_G2.NCB_NONDATA	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.	0,1,2,3	0x0	null	1
+QPI LL	0x3	0x10	UNC_Q_RxL_FLITS_G2.NCS	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI.    This includes extended headers.	0,1,2,3	0x0	null	1
+QPI LL	0x3	0x1	UNC_Q_RxL_FLITS_G2.NDR_AD	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.	0,1,2,3	0x0	null	1
+QPI LL	0x3	0x2	UNC_Q_RxL_FLITS_G2.NDR_AK	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.	0,1,2,3	0x0	null	1
+QPI LL	0x8	0x0	UNC_Q_RxL_INSERTS	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.	0,1,2,3	0x0	null	0
+QPI LL	0x9	0x0	UNC_Q_RxL_INSERTS_DRS	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.	0,1,2,3	0x0	null	1
+QPI LL	0xc	0x0	UNC_Q_RxL_INSERTS_HOM	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.	0,1,2,3	0x0	null	1
+QPI LL	0xa	0x0	UNC_Q_RxL_INSERTS_NCB	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.	0,1,2,3	0x0	null	1
+QPI LL	0xb	0x0	UNC_Q_RxL_INSERTS_NCS	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.	0,1,2,3	0x0	null	1
+QPI LL	0xe	0x0	UNC_Q_RxL_INSERTS_NDR	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.	0,1,2,3	0x0	null	1
+QPI LL	0xd	0x0	UNC_Q_RxL_INSERTS_SNP	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.	0,1,2,3	0x0	null	1
+QPI LL	0xb	0x0	UNC_Q_RxL_OCCUPANCY	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.	0,1,2,3	0x0	null	0
+QPI LL	0x15	0x0	UNC_Q_RxL_OCCUPANCY_DRS	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.	0,1,2,3	0x0	null	1
+QPI LL	0x18	0x0	UNC_Q_RxL_OCCUPANCY_HOM	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.	0,1,2,3	0x0	null	1
+QPI LL	0x16	0x0	UNC_Q_RxL_OCCUPANCY_NCB	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.	0,1,2,3	0x0	null	1
+QPI LL	0x17	0x0	UNC_Q_RxL_OCCUPANCY_NCS	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.	0,1,2,3	0x0	null	1
+QPI LL	0x1a	0x0	UNC_Q_RxL_OCCUPANCY_NDR	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.	0,1,2,3	0x0	null	1
+QPI LL	0x19	0x0	UNC_Q_RxL_OCCUPANCY_SNP	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.	0,1,2,3	0x0	null	1
+QPI LL	0x35	0x1	UNC_Q_RxL_STALLS_VN0.BGF_DRS	Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x35	0x8	UNC_Q_RxL_STALLS_VN0.BGF_HOM	Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x35	0x2	UNC_Q_RxL_STALLS_VN0.BGF_NCB	Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x35	0x4	UNC_Q_RxL_STALLS_VN0.BGF_NCS	Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x35	0x20	UNC_Q_RxL_STALLS_VN0.BGF_NDR	Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x35	0x10	UNC_Q_RxL_STALLS_VN0.BGF_SNP	Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x35	0x40	UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS	Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits.  For details on a message class granularity, use the Egress Credit Occupancy events.	0,1,2,3	0x0	null	1
+QPI LL	0x35	0x80	UNC_Q_RxL_STALLS_VN0.GV	Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.	0,1,2,3	0x0	null	1
+QPI LL	0x3a	0x1	UNC_Q_RxL_STALLS_VN1.BGF_DRS	Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x3a	0x8	UNC_Q_RxL_STALLS_VN1.BGF_HOM	Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x3a	0x2	UNC_Q_RxL_STALLS_VN1.BGF_NCB	Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x3a	0x4	UNC_Q_RxL_STALLS_VN1.BGF_NCS	Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x3a	0x20	UNC_Q_RxL_STALLS_VN1.BGF_NDR	Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0x3a	0x10	UNC_Q_RxL_STALLS_VN1.BGF_SNP	Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.	0,1,2,3	0x0	null	1
+QPI LL	0xd	0x0	UNC_Q_TxL0P_POWER_CYCLES	Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.	0,1,2,3	0x0	null	0
+QPI LL	0xc	0x0	UNC_Q_TxL0_POWER_CYCLES	Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.	0,1,2,3	0x0	null	0
+QPI LL	0x5	0x0	UNC_Q_TxL_BYPASSED	Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.	0,1,2,3	0x0	null	0
+QPI LL	0x2	0x2	UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL	Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.	0,1,2,3	0x0	null	0
+QPI LL	0x2	0x1	UNC_Q_TxL_CRC_NO_CREDITS.FULL	Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.	0,1,2,3	0x0	null	0
+QPI LL	0x6	0x0	UNC_Q_TxL_CYCLES_NE	Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.	0,1,2,3	0x0	null	0
+QPI LL	0x0	0x2	UNC_Q_TxL_FLITS_G0.DATA	Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.	0,1,2,3	0x0	null	0
+QPI LL	0x0	0x4	UNC_Q_TxL_FLITS_G0.NON_DATA	Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.	0,1,2,3	0x0	null	0
+QPI LL	0x0	0x18	UNC_Q_TxL_FLITS_G1.DRS	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.	0,1,2,3	0x0	null	1
+QPI LL	0x0	0x8	UNC_Q_TxL_FLITS_G1.DRS_DATA	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).	0,1,2,3	0x0	null	1
+QPI LL	0x0	0x10	UNC_Q_TxL_FLITS_G1.DRS_NONDATA	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.	0,1,2,3	0x0	null	1
+QPI LL	0x0	0x6	UNC_Q_TxL_FLITS_G1.HOM	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.	0,1,2,3	0x0	null	1
+QPI LL	0x0	0x4	UNC_Q_TxL_FLITS_G1.HOM_NONREQ	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.	0,1,2,3	0x0	null	1
+QPI LL	0x0	0x2	UNC_Q_TxL_FLITS_G1.HOM_REQ	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel.  This basically counts the number of remote memory requests transmitted over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.	0,1,2,3	0x0	null	1
+QPI LL	0x0	0x1	UNC_Q_TxL_FLITS_G1.SNP	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are transmitted on the home channel.	0,1,2,3	0x0	null	1
+QPI LL	0x1	0xC	UNC_Q_TxL_FLITS_G2.NCB	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.	0,1,2,3	0x0	null	1
+QPI LL	0x1	0x4	UNC_Q_TxL_FLITS_G2.NCB_DATA	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not te NCB headers.	0,1,2,3	0x0	null	1
+QPI LL	0x1	0x8	UNC_Q_TxL_FLITS_G2.NCB_NONDATA	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.	0,1,2,3	0x0	null	1
+QPI LL	0x1	0x10	UNC_Q_TxL_FLITS_G2.NCS	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI.    This includes extended headers.	0,1,2,3	0x0	null	1
+QPI LL	0x1	0x1	UNC_Q_TxL_FLITS_G2.NDR_AD	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.	0,1,2,3	0x0	null	1
+QPI LL	0x1	0x2	UNC_Q_TxL_FLITS_G2.NDR_AK	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.	0,1,2,3	0x0	null	1
+QPI LL	0x4	0x0	UNC_Q_TxL_INSERTS	Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.	0,1,2,3	0x0	null	0
+QPI LL	0x7	0x0	UNC_Q_TxL_OCCUPANCY	Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.	0,1,2,3	0x0	null	0
+QPI LL	0x26	0x1	UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0	Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x26	0x2	UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1	Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x22	0x1	UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0	Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x22	0x2	UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1	Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x28	0x1	UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0	Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x28	0x2	UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1	Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x24	0x1	UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0	Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x24	0x2	UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1	Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x27	0x1	UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0	Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x27	0x2	UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1	Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x23	0x1	UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0	Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x23	0x2	UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1	Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.	0,1,2,3	0x0	null	1
+QPI LL	0x29	0x1	UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN0	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x29	0x2	UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN1	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x25	0x1	UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN0	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x25	0x2	UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN1	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x2a	0x1	UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x2a	0x2	UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x2a	0x4	UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x1f	0x1	UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x1f	0x2	UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x1f	0x4	UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x2b	0x1	UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x2b	0x2	UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x20	0x1	UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x20	0x2	UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x2c	0x1	UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x2c	0x2	UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x21	0x1	UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x21	0x2	UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.	0,1,2,3	0x0	null	1
+QPI LL	0x1c	0x0	UNC_Q_VNA_CREDIT_RETURNS	Number of VNA credits returned.	0,1,2,3	0x0	null	1
+QPI LL	0x1b	0x0	UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY	Number of VNA credits in the Rx side that are waitng to be returned back across the link.	0,1,2,3	0x0	null	1
+R3QPI	0x1	0x0	UNC_R3_CLOCKTICKS	Counts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.	0,1,2	0x0	null	0
+R3QPI	0x2c	0x4	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10	No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10	0,1	0x0	null	0
+R3QPI	0x2c	0x8	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11	No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11	0,1	0x0	null	0
+R3QPI	0x2c	0x10	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12	No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12	0,1	0x0	null	0
+R3QPI	0x2c	0x20	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13	No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13	0,1	0x0	null	0
+R3QPI	0x2c	0x40	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14	No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16	0,1	0x0	null	0
+R3QPI	0x2c	0x1	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8	No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8	0,1	0x0	null	0
+R3QPI	0x2c	0x2	UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9	No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9	0,1	0x0	null	0
+R3QPI	0x2b	0x1	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0	No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0	0,1	0x0	null	0
+R3QPI	0x2b	0x2	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1	No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1	0,1	0x0	null	0
+R3QPI	0x2b	0x4	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2	No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2	0,1	0x0	null	0
+R3QPI	0x2b	0x8	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3	No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3	0,1	0x0	null	0
+R3QPI	0x2b	0x10	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4	No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4	0,1	0x0	null	0
+R3QPI	0x2b	0x20	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5	No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5	0,1	0x0	null	0
+R3QPI	0x2b	0x40	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6	No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6	0,1	0x0	null	0
+R3QPI	0x2b	0x80	UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7	No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7	0,1	0x0	null	0
+R3QPI	0x2f	0x1	UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0	No credits available to send to either HA or R2 on the BL Ring; HA0	0,1	0x0	null	0
+R3QPI	0x2f	0x2	UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1	No credits available to send to either HA or R2 on the BL Ring; HA1	0,1	0x0	null	0
+R3QPI	0x2f	0x4	UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB	No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages	0,1	0x0	null	0
+R3QPI	0x2f	0x8	UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS	No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages	0,1	0x0	null	0
+R3QPI	0x29	0x2	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM	No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages	0,1	0x0	null	0
+R3QPI	0x29	0x8	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR	No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages	0,1	0x0	null	0
+R3QPI	0x29	0x4	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP	No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages	0,1	0x0	null	0
+R3QPI	0x29	0x10	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM	No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages	0,1	0x0	null	0
+R3QPI	0x29	0x40	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR	No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages	0,1	0x0	null	0
+R3QPI	0x29	0x20	UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP	No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages	0,1	0x0	null	0
+R3QPI	0x29	0x1	UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA	No credits available to send to QPI0 on the AD Ring; VNA	0,1	0x0	null	0
+R3QPI	0x2d	0x2	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM	No credits available to send to QPI0 on the BL Ring; VN0 HOM Messages	0,1	0x0	null	0
+R3QPI	0x2d	0x8	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR	No credits available to send to QPI0 on the BL Ring; VN0 NDR Messages	0,1	0x0	null	0
+R3QPI	0x2d	0x4	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP	No credits available to send to QPI0 on the BL Ring; VN0 SNP Messages	0,1	0x0	null	0
+R3QPI	0x2d	0x10	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM	No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages	0,1	0x0	null	0
+R3QPI	0x2d	0x40	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR	No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages	0,1	0x0	null	0
+R3QPI	0x2d	0x20	UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP	No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages	0,1	0x0	null	0
+R3QPI	0x2d	0x1	UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA	No credits available to send to QPI0 on the BL Ring; VNA	0,1	0x0	null	0
+R3QPI	0x2a	0x2	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM	No credits available to send to QPI1 on the AD Ring; VN0 HOM Messages	0,1	0x0	null	0
+R3QPI	0x2a	0x8	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR	No credits available to send to QPI1 on the AD Ring; VN0 NDR Messages	0,1	0x0	null	0
+R3QPI	0x2a	0x4	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP	No credits available to send to QPI1 on the AD Ring; VN0 SNP Messages	0,1	0x0	null	0
+R3QPI	0x2a	0x10	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM	No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages	0,1	0x0	null	0
+R3QPI	0x2a	0x40	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR	No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages	0,1	0x0	null	0
+R3QPI	0x2a	0x20	UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP	No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages	0,1	0x0	null	0
+R3QPI	0x2a	0x1	UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA	No credits available to send to QPI1 on the AD Ring; VNA	0,1	0x0	null	0
+R3QPI	0x2e	0x2	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM	No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages	0,1	0x0	null	0
+R3QPI	0x2e	0x8	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR	No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages	0,1	0x0	null	0
+R3QPI	0x2e	0x4	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP	No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages	0,1	0x0	null	0
+R3QPI	0x2e	0x10	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM	No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages	0,1	0x0	null	0
+R3QPI	0x2e	0x40	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR	No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages	0,1	0x0	null	0
+R3QPI	0x2e	0x20	UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP	No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages	0,1	0x0	null	0
+R3QPI	0x2e	0x1	UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA	No credits available to send to QPI1 on the BL Ring; VNA	0,1	0x0	null	0
+R3QPI	0x7	0x4	UNC_R3_RING_AD_USED.CCW_VR0_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x7	0x8	UNC_R3_RING_AD_USED.CCW_VR0_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x7	0x1	UNC_R3_RING_AD_USED.CW_VR0_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x7	0x2	UNC_R3_RING_AD_USED.CW_VR0_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x8	0x4	UNC_R3_RING_AK_USED.CCW_VR0_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x8	0x8	UNC_R3_RING_AK_USED.CCW_VR0_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x8	0x1	UNC_R3_RING_AK_USED.CW_VR0_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x8	0x2	UNC_R3_RING_AK_USED.CW_VR0_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x9	0x4	UNC_R3_RING_BL_USED.CCW_VR0_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x9	0x8	UNC_R3_RING_BL_USED.CCW_VR0_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x9	0x1	UNC_R3_RING_BL_USED.CW_VR0_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0x9	0x2	UNC_R3_RING_BL_USED.CW_VR0_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2	0x0	null	0
+R3QPI	0xa	0xCC	UNC_R3_RING_IV_USED.CCW	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity	0,1,2	0x0	null	0
+R3QPI	0xa	0x33	UNC_R3_RING_IV_USED.CW	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity	0,1,2	0x0	null	0
+R3QPI	0x12	0x1	UNC_R3_RxR_BYPASSED.AD	Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.	0,1	0x0	null	0
+R3QPI	0x10	0x1	UNC_R3_RxR_CYCLES_NE.HOM	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue	0,1	0x0	null	0
+R3QPI	0x10	0x4	UNC_R3_RxR_CYCLES_NE.NDR	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue	0,1	0x0	null	0
+R3QPI	0x10	0x2	UNC_R3_RxR_CYCLES_NE.SNP	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue	0,1	0x0	null	0
+R3QPI	0x11	0x8	UNC_R3_RxR_INSERTS.DRS	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue	0,1	0x0	null	0
+R3QPI	0x11	0x1	UNC_R3_RxR_INSERTS.HOM	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue	0,1	0x0	null	0
+R3QPI	0x11	0x10	UNC_R3_RxR_INSERTS.NCB	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue	0,1	0x0	null	0
+R3QPI	0x11	0x20	UNC_R3_RxR_INSERTS.NCS	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue	0,1	0x0	null	0
+R3QPI	0x11	0x4	UNC_R3_RxR_INSERTS.NDR	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue	0,1	0x0	null	0
+R3QPI	0x11	0x2	UNC_R3_RxR_INSERTS.SNP	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue	0,1	0x0	null	0
+R3QPI	0x13	0x8	UNC_R3_RxR_OCCUPANCY.DRS	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue	0	0x0	null	0
+R3QPI	0x13	0x1	UNC_R3_RxR_OCCUPANCY.HOM	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue	0	0x0	null	0
+R3QPI	0x13	0x10	UNC_R3_RxR_OCCUPANCY.NCB	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue	0	0x0	null	0
+R3QPI	0x13	0x20	UNC_R3_RxR_OCCUPANCY.NCS	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue	0	0x0	null	0
+R3QPI	0x13	0x4	UNC_R3_RxR_OCCUPANCY.NDR	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue	0	0x0	null	0
+R3QPI	0x13	0x2	UNC_R3_RxR_OCCUPANCY.SNP	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue	0	0x0	null	0
+R3QPI	0x28	0x1	UNC_R3_TxR_NACK_CCW.AD	BL CounterClockwise Egress Queue	0,1	0x0	null	0
+R3QPI	0x28	0x2	UNC_R3_TxR_NACK_CCW.AK	AD Clockwise Egress Queue	0,1	0x0	null	0
+R3QPI	0x28	0x4	UNC_R3_TxR_NACK_CCW.BL	AD CounterClockwise Egress Queue	0,1	0x0	null	0
+R3QPI	0x26	0x1	UNC_R3_TxR_NACK_CW.AD	AD Clockwise Egress Queue	0,1	0x0	null	0
+R3QPI	0x26	0x2	UNC_R3_TxR_NACK_CW.AK	AD CounterClockwise Egress Queue	0,1	0x0	null	0
+R3QPI	0x26	0x4	UNC_R3_TxR_NACK_CW.BL	BL Clockwise Egress Queue	0,1	0x0	null	0
+R3QPI	0x37	0x8	UNC_R3_VN0_CREDITS_REJECT.DRS	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.	0,1	0x0	null	0
+R3QPI	0x37	0x1	UNC_R3_VN0_CREDITS_REJECT.HOM	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.	0,1	0x0	null	0
+R3QPI	0x37	0x10	UNC_R3_VN0_CREDITS_REJECT.NCB	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.	0,1	0x0	null	0
+R3QPI	0x37	0x20	UNC_R3_VN0_CREDITS_REJECT.NCS	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?	0,1	0x0	null	0
+R3QPI	0x37	0x4	UNC_R3_VN0_CREDITS_REJECT.NDR	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).	0,1	0x0	null	0
+R3QPI	0x37	0x2	UNC_R3_VN0_CREDITS_REJECT.SNP	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.	0,1	0x0	null	0
+R3QPI	0x36	0x8	UNC_R3_VN0_CREDITS_USED.DRS	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.	0,1	0x0	null	0
+R3QPI	0x36	0x1	UNC_R3_VN0_CREDITS_USED.HOM	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.	0,1	0x0	null	0
+R3QPI	0x36	0x10	UNC_R3_VN0_CREDITS_USED.NCB	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.	0,1	0x0	null	0
+R3QPI	0x36	0x20	UNC_R3_VN0_CREDITS_USED.NCS	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?	0,1	0x0	null	0
+R3QPI	0x36	0x4	UNC_R3_VN0_CREDITS_USED.NDR	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).	0,1	0x0	null	0
+R3QPI	0x36	0x2	UNC_R3_VN0_CREDITS_USED.SNP	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.	0,1	0x0	null	0
+R3QPI	0x39	0x8	UNC_R3_VN1_CREDITS_REJECT.DRS	Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.	0,1	0x0	null	0
+R3QPI	0x39	0x1	UNC_R3_VN1_CREDITS_REJECT.HOM	Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.	0,1	0x0	null	0
+R3QPI	0x39	0x10	UNC_R3_VN1_CREDITS_REJECT.NCB	Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.	0,1	0x0	null	0
+R3QPI	0x39	0x20	UNC_R3_VN1_CREDITS_REJECT.NCS	Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?	0,1	0x0	null	0
+R3QPI	0x39	0x4	UNC_R3_VN1_CREDITS_REJECT.NDR	Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).	0,1	0x0	null	0
+R3QPI	0x39	0x2	UNC_R3_VN1_CREDITS_REJECT.SNP	Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.	0,1	0x0	null	0
+R3QPI	0x38	0x8	UNC_R3_VN1_CREDITS_USED.DRS	Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.	0,1	0x0	null	0
+R3QPI	0x38	0x1	UNC_R3_VN1_CREDITS_USED.HOM	Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.	0,1	0x0	null	0
+R3QPI	0x38	0x10	UNC_R3_VN1_CREDITS_USED.NCB	Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.	0,1	0x0	null	0
+R3QPI	0x38	0x20	UNC_R3_VN1_CREDITS_USED.NCS	Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?	0,1	0x0	null	0
+R3QPI	0x38	0x4	UNC_R3_VN1_CREDITS_USED.NDR	Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).	0,1	0x0	null	0
+R3QPI	0x38	0x2	UNC_R3_VN1_CREDITS_USED.SNP	Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.	0,1	0x0	null	0
+R3QPI	0x33	0x0	UNC_R3_VNA_CREDITS_ACQUIRED	Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.	0,1	0x0	null	0
+R3QPI	0x34	0x8	UNC_R3_VNA_CREDITS_REJECT.DRS	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.	0,1	0x0	null	0
+R3QPI	0x34	0x1	UNC_R3_VNA_CREDITS_REJECT.HOM	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.	0,1	0x0	null	0
+R3QPI	0x34	0x10	UNC_R3_VNA_CREDITS_REJECT.NCB	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.	0,1	0x0	null	0
+R3QPI	0x34	0x20	UNC_R3_VNA_CREDITS_REJECT.NCS	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).	0,1	0x0	null	0
+R3QPI	0x34	0x4	UNC_R3_VNA_CREDITS_REJECT.NDR	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).	0,1	0x0	null	0
+R3QPI	0x34	0x2	UNC_R3_VNA_CREDITS_REJECT.SNP	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.	0,1	0x0	null	0
+R3QPI	0x31	0x0	UNC_R3_VNA_CREDIT_CYCLES_OUT	Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel.  Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit.  Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth.	0,1	0x0	null	0
+R3QPI	0x32	0x0	UNC_R3_VNA_CREDIT_CYCLES_USED	Number of QPI uclk cycles with one or more VNA credits in use.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.	0,1	0x0	null	0
+R2PCIe	0x1	0x0	UNC_R2_CLOCKTICKS	Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.	0,1,2,3	0x0	null	0
+R2PCIe	0x33	0x8	UNC_R2_IIO_CREDITS_ACQUIRED.DRS	Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.	0,1	0x0	null	0
+R2PCIe	0x33	0x10	UNC_R2_IIO_CREDITS_ACQUIRED.NCB	Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.	0,1	0x0	null	0
+R2PCIe	0x33	0x20	UNC_R2_IIO_CREDITS_ACQUIRED.NCS	Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.	0,1	0x0	null	0
+R2PCIe	0x34	0x8	UNC_R2_IIO_CREDITS_REJECT.DRS	Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.	0,1	0x0	null	0
+R2PCIe	0x32	0x8	UNC_R2_IIO_CREDITS_USED.DRS	Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.	0,1	0x0	null	0
+R2PCIe	0x32	0x10	UNC_R2_IIO_CREDITS_USED.NCB	Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.	0,1	0x0	null	0
+R2PCIe	0x32	0x20	UNC_R2_IIO_CREDITS_USED.NCS	Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.	0,1	0x0	null	0
+R2PCIe	0x7	0x4	UNC_R2_RING_AD_USED.CCW_VR0_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x7	0x8	UNC_R2_RING_AD_USED.CCW_VR0_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x7	0x40	UNC_R2_RING_AD_USED.CCW_VR1_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x7	0x80	UNC_R2_RING_AD_USED.CCW_VR1_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x7	0x1	UNC_R2_RING_AD_USED.CW_VR0_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x7	0x2	UNC_R2_RING_AD_USED.CW_VR0_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x7	0x10	UNC_R2_RING_AD_USED.CW_VR1_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x7	0x20	UNC_R2_RING_AD_USED.CW_VR1_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x8	0x4	UNC_R2_RING_AK_USED.CCW_VR0_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x8	0x8	UNC_R2_RING_AK_USED.CCW_VR0_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x8	0x40	UNC_R2_RING_AK_USED.CCW_VR1_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x8	0x80	UNC_R2_RING_AK_USED.CCW_VR1_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x8	0x1	UNC_R2_RING_AK_USED.CW_VR0_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x8	0x2	UNC_R2_RING_AK_USED.CW_VR0_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x8	0x10	UNC_R2_RING_AK_USED.CW_VR1_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x8	0x20	UNC_R2_RING_AK_USED.CW_VR1_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x9	0x4	UNC_R2_RING_BL_USED.CCW_VR0_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x9	0x8	UNC_R2_RING_BL_USED.CCW_VR0_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x9	0x40	UNC_R2_RING_BL_USED.CCW_VR1_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x9	0x80	UNC_R2_RING_BL_USED.CCW_VR1_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x9	0x1	UNC_R2_RING_BL_USED.CW_VR0_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x9	0x2	UNC_R2_RING_BL_USED.CW_VR0_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+R2PCIe	0x9	0x10	UNC_R2_RING_BL_USED.CW_VR1_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0x9	0x20	UNC_R2_RING_BL_USED.CW_VR1_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+R2PCIe	0xa	0xCC	UNC_R2_RING_IV_USED.CCW	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity	0,1,2,3	0x0	null	0
+R2PCIe	0xa	0x33	UNC_R2_RING_IV_USED.CW	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity	0,1,2,3	0x0	null	0
+R2PCIe	0x12	0x0	UNC_R2_RxR_AK_BOUNCES	Counts the number of times when a request destined for the AK ingress bounced.	0	0x0	null	0
+R2PCIe	0x10	0x10	UNC_R2_RxR_CYCLES_NE.NCB	Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue	0,1	0x0	null	0
+R2PCIe	0x10	0x20	UNC_R2_RxR_CYCLES_NE.NCS	Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue	0,1	0x0	null	0
+R2PCIe	0x11	0x10	UNC_R2_RxR_INSERTS.NCB	Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue	0,1	0x0	null	0
+R2PCIe	0x11	0x20	UNC_R2_RxR_INSERTS.NCS	Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue	0,1	0x0	null	0
+R2PCIe	0x13	0x8	UNC_R2_RxR_OCCUPANCY.DRS	Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue	0	0x0	null	0
+R2PCIe	0x25	0x1	UNC_R2_TxR_CYCLES_FULL.AD	Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue	0	0x0	null	0
+R2PCIe	0x25	0x2	UNC_R2_TxR_CYCLES_FULL.AK	Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue	0	0x0	null	0
+R2PCIe	0x25	0x4	UNC_R2_TxR_CYCLES_FULL.BL	Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue	0	0x0	null	0
+R2PCIe	0x23	0x1	UNC_R2_TxR_CYCLES_NE.AD	Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AD Egress Queue	0	0x0	null	0
+R2PCIe	0x23	0x2	UNC_R2_TxR_CYCLES_NE.AK	Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AK Egress Queue	0	0x0	null	0
+R2PCIe	0x23	0x4	UNC_R2_TxR_CYCLES_NE.BL	Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; BL Egress Queue	0	0x0	null	0
+HA	0x20	0x3	UNC_H_ADDR_OPC_MATCH.FILT	tbd	0,1,2,3	0x0	HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]	0
+HA	0x52	0x0	UNC_H_BT_BYPASS	Number of transactions that bypass the BT (fifo) to HT	0,1,2,3	0x0	null	0
+HA	0x42	0x1	UNC_H_BT_CYCLES_NE.LOCAL	Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.	0,1,2,3	0x0	null	0
+HA	0x42	0x2	UNC_H_BT_CYCLES_NE.REMOTE	Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.	0,1,2,3	0x0	null	0
+HA	0x43	0x1	UNC_H_BT_OCCUPANCY.LOCAL	Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.	0,1,2,3	0x0	null	0
+HA	0x43	0x4	UNC_H_BT_OCCUPANCY.READS_LOCAL	Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.	0,1,2,3	0x0	null	0
+HA	0x43	0x8	UNC_H_BT_OCCUPANCY.READS_REMOTE	Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.	0,1,2,3	0x0	null	0
+HA	0x43	0x2	UNC_H_BT_OCCUPANCY.REMOTE	Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.	0,1,2,3	0x0	null	0
+HA	0x43	0x10	UNC_H_BT_OCCUPANCY.WRITES_LOCAL	Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.	0,1,2,3	0x0	null	0
+HA	0x43	0x20	UNC_H_BT_OCCUPANCY.WRITES_REMOTE	Accumulates the occupancy of the HA BT pool in every cycle.  This can be used with the 'not empty' stat to calculate average queue occupancy or the 'allocations' stat in order to calculate average queue latency.  HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.	0,1,2,3	0x0	null	0
+HA	0x51	0x4	UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD	Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard	0,1,2,3	0x0	null	0
+HA	0x51	0x2	UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD	Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard	0,1,2,3	0x0	null	0
+HA	0x14	0x2	UNC_H_BYPASS_IMC.NOT_TAKEN	Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.	0,1,2,3	0x0	null	0
+HA	0x14	0x1	UNC_H_BYPASS_IMC.TAKEN	Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.	0,1,2,3	0x0	null	0
+HA	0x0	0x0	UNC_H_CLOCKTICKS	Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.	0,1,2,3	0x0	null	0
+HA	0xb	0x8	UNC_H_CONFLICT_CYCLES.ACKCNFLTS	Count the number of Ackcnflts	0,1,2,3	0x0	null	0
+HA	0xb	0x10	UNC_H_CONFLICT_CYCLES.CMP_FWDS	Count the number of Cmp_Fwd. This will give the number of late conflicts.	0,1,2,3	0x0	null	0
+HA	0xb	0x2	UNC_H_CONFLICT_CYCLES.CONFLICT	Counts the number of cycles that we are handling conflicts.	0,1,2,3	0x0	null	0
+HA	0xb	0x4	UNC_H_CONFLICT_CYCLES.LAST	Count every last conflictor in conflict chain. Can be used to compute the average conflict chain length as (#Ackcnflts/#LastConflictor)+1. This can be used to give a feel for the conflict chain lenghts while analyzing lock kernels.	0,1,2,3	0x0	null	0
+HA	0x11	0x0	UNC_H_DIRECT2CORE_COUNT	Number of Direct2Core messages sent	0,1,2,3	0x0	null	0
+HA	0x12	0x0	UNC_H_DIRECT2CORE_CYCLES_DISABLED	Number of cycles in which Direct2Core was disabled	0,1,2,3	0x0	null	0
+HA	0x13	0x0	UNC_H_DIRECT2CORE_TXN_OVERRIDE	Number of Reads where Direct2Core overridden	0,1,2,3	0x0	null	0
+HA	0x41	0x0	UNC_H_DIRECTORY_LAT_OPT	Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).	0,1,2,3	0x0	null	0
+HA	0xc	0x10	UNC_H_DIRECTORY_LOOKUP.ANY	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.	0,1,2,3	0x0	null	0
+HA	0xc	0x2	UNC_H_DIRECTORY_LOOKUP.NO_SNP	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.	0,1,2,3	0x0	null	0
+HA	0xc	0x8	UNC_H_DIRECTORY_LOOKUP.SNOOP_A	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.	0,1,2,3	0x0	null	0
+HA	0xc	0x2	UNC_H_DIRECTORY_LOOKUP.SNOOP_S	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.	0,1,2,3	0x0	null	0
+HA	0xc	0x1	UNC_H_DIRECTORY_LOOKUP.SNP	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.	0,1,2,3	0x0	null	0
+HA	0xc	0x80	UNC_H_DIRECTORY_LOOKUP.STATE_A	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.	0,1,2,3	0x0	null	0
+HA	0xc	0x20	UNC_H_DIRECTORY_LOOKUP.STATE_I	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.	0,1,2,3	0x0	null	0
+HA	0xc	0x40	UNC_H_DIRECTORY_LOOKUP.STATE_S	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.	0,1,2,3	0x0	null	0
+HA	0xd	0x20	UNC_H_DIRECTORY_UPDATE.A2I	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0x0	null	0
+HA	0xd	0x40	UNC_H_DIRECTORY_UPDATE.A2S	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0x0	null	0
+HA	0xd	0x3	UNC_H_DIRECTORY_UPDATE.ANY	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0x0	null	0
+HA	0xd	0x4	UNC_H_DIRECTORY_UPDATE.I2A	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0x0	null	0
+HA	0xd	0x2	UNC_H_DIRECTORY_UPDATE.I2S	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0x0	null	0
+HA	0xd	0x10	UNC_H_DIRECTORY_UPDATE.S2A	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0x0	null	0
+HA	0xd	0x8	UNC_H_DIRECTORY_UPDATE.S2I	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0x0	null	0
+HA	0x59	0x0	UNC_H_IGR_AD_QPI2_ACCUMULATOR	Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer.	0,1,2,3	0x0	null	0
+HA	0x5a	0x0	UNC_H_IGR_BL_QPI2_ACCUMULATOR	Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer.	0,1,2,3	0x0	null	0
+HA	0x22	0x1	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0	Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.	0,1,2,3	0x0	null	0
+HA	0x22	0x2	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1	Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.	0,1,2,3	0x0	null	0
+HA	0x22	0x4	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0	Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.	0,1,2,3	0x0	null	0
+HA	0x22	0x8	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1	Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.	0,1,2,3	0x0	null	0
+HA	0x17	0x1	UNC_H_IMC_READS.NORMAL	Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.	0,1,2,3	0x0	null	0
+HA	0x1e	0x0	UNC_H_IMC_RETRY	tbd	0,1,2,3	0x0	null	0
+HA	0x1a	0xF	UNC_H_IMC_WRITES.ALL	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0x0	null	0
+HA	0x1a	0x1	UNC_H_IMC_WRITES.FULL	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0x0	null	0
+HA	0x1a	0x4	UNC_H_IMC_WRITES.FULL_ISOCH	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0x0	null	0
+HA	0x1a	0x2	UNC_H_IMC_WRITES.PARTIAL	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0x0	null	0
+HA	0x1a	0x8	UNC_H_IMC_WRITES.PARTIAL_ISOCH	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0x0	null	0
+HA	0x57	0x1	UNC_H_IODC_CONFLICTS.REMOTE_INVI2E_SAME_RTID	tbd	0,1,2,3	0x0	null	0
+HA	0x57	0x4	UNC_H_IODC_CONFLICTS.REMOTE_OTHER_SAME_ADDR	tbd	0,1,2,3	0x0	null	0
+HA	0x56	0x0	UNC_H_IODC_INSERTS	IODC Allocations	0,1,2,3	0x0	null	0
+HA	0x58	0x0	UNC_H_IODC_OLEN_WBMTOI	Num IODC 0 Length Writebacks M to I - All of which are dropped.	0,1,2,3	0x0	null	0
+HA	0x53	0x4	UNC_H_OSB.INVITOE_LOCAL	Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.	0,1,2,3	0x0	null	0
+HA	0x53	0x2	UNC_H_OSB.READS_LOCAL	Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.	0,1,2,3	0x0	null	0
+HA	0x53	0x8	UNC_H_OSB.REMOTE	Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.	0,1,2,3	0x0	null	0
+HA	0x54	0x1	UNC_H_OSB_EDR.ALL	Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return	0,1,2,3	0x0	null	0
+HA	0x54	0x2	UNC_H_OSB_EDR.READS_LOCAL_I	Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return	0,1,2,3	0x0	null	0
+HA	0x54	0x8	UNC_H_OSB_EDR.READS_LOCAL_S	Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return	0,1,2,3	0x0	null	0
+HA	0x54	0x4	UNC_H_OSB_EDR.READS_REMOTE_I	Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return	0,1,2,3	0x0	null	0
+HA	0x54	0x10	UNC_H_OSB_EDR.READS_REMOTE_S	Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return	0,1,2,3	0x0	null	0
+HA	0x1	0x10	UNC_H_REQUESTS.INVITOE_LOCAL	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.	0,1,2,3	0x0	null	0
+HA	0x1	0x20	UNC_H_REQUESTS.INVITOE_REMOTE	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.	0,1,2,3	0x0	null	0
+HA	0x1	0x3	UNC_H_REQUESTS.READS	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests.  This is a good proxy for LLC Read Misses (including RFOs).	0,1,2,3	0x0	null	0
+HA	0x1	0x1	UNC_H_REQUESTS.READS_LOCAL	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket.  This is a good proxy for LLC Read Misses (including RFOs) from the local socket.	0,1,2,3	0x0	null	0
+HA	0x1	0x2	UNC_H_REQUESTS.READS_REMOTE	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket.  This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.	0,1,2,3	0x0	null	0
+HA	0x1	0xC	UNC_H_REQUESTS.WRITES	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.	0,1,2,3	0x0	null	0
+HA	0x1	0x4	UNC_H_REQUESTS.WRITES_LOCAL	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.	0,1,2,3	0x0	null	0
+HA	0x1	0x8	UNC_H_REQUESTS.WRITES_REMOTE	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.	0,1,2,3	0x0	null	0
+HA	0x3e	0x4	UNC_H_RING_AD_USED.CCW_VR0_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x3e	0x8	UNC_H_RING_AD_USED.CCW_VR0_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x3e	0x40	UNC_H_RING_AD_USED.CCW_VR1_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x3e	0x80	UNC_H_RING_AD_USED.CCW_VR1_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x3e	0x1	UNC_H_RING_AD_USED.CW_VR0_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x3e	0x2	UNC_H_RING_AD_USED.CW_VR0_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x3e	0x10	UNC_H_RING_AD_USED.CW_VR1_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x3e	0x20	UNC_H_RING_AD_USED.CW_VR1_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x3f	0x4	UNC_H_RING_AK_USED.CCW_VR0_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x3f	0x8	UNC_H_RING_AK_USED.CCW_VR0_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x3f	0x40	UNC_H_RING_AK_USED.CCW_VR1_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x3f	0x80	UNC_H_RING_AK_USED.CCW_VR1_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x3f	0x1	UNC_H_RING_AK_USED.CW_VR0_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x3f	0x2	UNC_H_RING_AK_USED.CW_VR0_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x3f	0x10	UNC_H_RING_AK_USED.CW_VR1_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x3f	0x20	UNC_H_RING_AK_USED.CW_VR1_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x40	0x4	UNC_H_RING_BL_USED.CCW_VR0_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x40	0x8	UNC_H_RING_BL_USED.CCW_VR0_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x40	0x40	UNC_H_RING_BL_USED.CCW_VR1_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x40	0x80	UNC_H_RING_BL_USED.CCW_VR1_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x40	0x1	UNC_H_RING_BL_USED.CW_VR0_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x40	0x2	UNC_H_RING_BL_USED.CW_VR0_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.	0,1,2,3	0x0	null	0
+HA	0x40	0x10	UNC_H_RING_BL_USED.CW_VR1_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x40	0x20	UNC_H_RING_BL_USED.CW_VR1_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.	0,1,2,3	0x0	null	0
+HA	0x15	0x1	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0	Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.	0,1,2,3	0x0	null	0
+HA	0x15	0x2	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1	Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.	0,1,2,3	0x0	null	0
+HA	0x15	0x4	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2	Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.	0,1,2,3	0x0	null	0
+HA	0x15	0x8	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3	Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.	0,1,2,3	0x0	null	0
+HA	0x16	0x1	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0	Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.	0,1,2,3	0x0	null	0
+HA	0x16	0x2	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1	Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.	0,1,2,3	0x0	null	0
+HA	0x16	0x4	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2	Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.	0,1,2,3	0x0	null	0
+HA	0x16	0x8	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3	Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.	0,1,2,3	0x0	null	0
+HA	0x21	0x40	UNC_H_SNOOP_RESP.RSPCNFLCT	Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.	0,1,2,3	0x0	null	0
+HA	0x21	0x1	UNC_H_SNOOP_RESP.RSPI	Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).	0,1,2,3	0x0	null	0
+HA	0x21	0x4	UNC_H_SNOOP_RESP.RSPIFWD	Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.	0,1,2,3	0x0	null	0
+HA	0x21	0x2	UNC_H_SNOOP_RESP.RSPS	Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.	0,1,2,3	0x0	null	0
+HA	0x21	0x8	UNC_H_SNOOP_RESP.RSPSFWD	Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.	0,1,2,3	0x0	null	0
+HA	0x21	0x20	UNC_H_SNOOP_RESP.RSP_FWD_WB	Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.	0,1,2,3	0x0	null	0
+HA	0x21	0x10	UNC_H_SNOOP_RESP.RSP_WB	Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.	0,1,2,3	0x0	null	0
+HA	0x60	0x80	UNC_H_SNP_RESP_RECV_LOCAL.OTHER	Number of snoop responses received for a Local  request; Filters for all other snoop responses.	0,1,2,3	0x0	null	0
+HA	0x60	0x40	UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT	Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.	0,1,2,3	0x0	null	0
+HA	0x60	0x1	UNC_H_SNP_RESP_RECV_LOCAL.RSPI	Number of snoop responses received for a Local  request; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).	0,1,2,3	0x0	null	0
+HA	0x60	0x4	UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD	Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.	0,1,2,3	0x0	null	0
+HA	0x60	0x2	UNC_H_SNP_RESP_RECV_LOCAL.RSPS	Number of snoop responses received for a Local  request; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.	0,1,2,3	0x0	null	0
+HA	0x60	0x8	UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD	Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.	0,1,2,3	0x0	null	0
+HA	0x60	0x20	UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB	Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.	0,1,2,3	0x0	null	0
+HA	0x60	0x10	UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB	Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.	0,1,2,3	0x0	null	0
+HA	0x1b	0x1	UNC_H_TAD_REQUESTS_G0.REGION0	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0	0,1,2,3	0x0	null	0
+HA	0x1b	0x2	UNC_H_TAD_REQUESTS_G0.REGION1	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1	0,1,2,3	0x0	null	0
+HA	0x1b	0x4	UNC_H_TAD_REQUESTS_G0.REGION2	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2	0,1,2,3	0x0	null	0
+HA	0x1b	0x8	UNC_H_TAD_REQUESTS_G0.REGION3	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3	0,1,2,3	0x0	null	0
+HA	0x1b	0x10	UNC_H_TAD_REQUESTS_G0.REGION4	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4	0,1,2,3	0x0	null	0
+HA	0x1b	0x20	UNC_H_TAD_REQUESTS_G0.REGION5	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5	0,1,2,3	0x0	null	0
+HA	0x1b	0x40	UNC_H_TAD_REQUESTS_G0.REGION6	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6	0,1,2,3	0x0	null	0
+HA	0x1b	0x80	UNC_H_TAD_REQUESTS_G0.REGION7	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7	0,1,2,3	0x0	null	0
+HA	0x1c	0x4	UNC_H_TAD_REQUESTS_G1.REGION10	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10	0,1,2,3	0x0	null	0
+HA	0x1c	0x8	UNC_H_TAD_REQUESTS_G1.REGION11	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11	0,1,2,3	0x0	null	0
+HA	0x1c	0x1	UNC_H_TAD_REQUESTS_G1.REGION8	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8	0,1,2,3	0x0	null	0
+HA	0x1c	0x2	UNC_H_TAD_REQUESTS_G1.REGION9	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9	0,1,2,3	0x0	null	0
+HA	0x3	0x0	UNC_H_TRACKER_CYCLES_NE	Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.	0,1,2,3	0x0	null	0
+HA	0x2a	0x3	UNC_H_TxR_AD_CYCLES_FULL.ALL	AD Egress Full; Cycles full from both schedulers	0,1,2,3	0x0	null	0
+HA	0x2a	0x1	UNC_H_TxR_AD_CYCLES_FULL.SCHED0	AD Egress Full; Filter for cycles full  from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x2a	0x2	UNC_H_TxR_AD_CYCLES_FULL.SCHED1	AD Egress Full; Filter for cycles full  from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x29	0x3	UNC_H_TxR_AD_CYCLES_NE.ALL	AD Egress Not Empty; Cycles full from both schedulers	0,1,2,3	0x0	null	0
+HA	0x29	0x1	UNC_H_TxR_AD_CYCLES_NE.SCHED0	AD Egress Not Empty; Filter for cycles not empty  from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x29	0x2	UNC_H_TxR_AD_CYCLES_NE.SCHED1	AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x27	0x3	UNC_H_TxR_AD_INSERTS.ALL	AD Egress Allocations; Allocations from both schedulers	0,1,2,3	0x0	null	0
+HA	0x27	0x1	UNC_H_TxR_AD_INSERTS.SCHED0	AD Egress Allocations; Filter for allocations from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x27	0x2	UNC_H_TxR_AD_INSERTS.SCHED1	AD Egress Allocations; Filter for allocations from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x28	0x1	UNC_H_TxR_AD_OCCUPANCY.SCHED0	AD Egress Occupancy; Filter for occupancy from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x28	0x2	UNC_H_TxR_AD_OCCUPANCY.SCHED1	AD Egress Occupancy; Filter for occupancy from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0xe	0x2	UNC_H_TxR_AK.CRD_CBO	tbd	0,1,2,3	0x0	null	0
+HA	0x32	0x3	UNC_H_TxR_AK_CYCLES_FULL.ALL	AK Egress Full; Cycles full from both schedulers	0,1,2,3	0x0	null	0
+HA	0x32	0x1	UNC_H_TxR_AK_CYCLES_FULL.SCHED0	AK Egress Full; Filter for cycles full  from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x32	0x2	UNC_H_TxR_AK_CYCLES_FULL.SCHED1	AK Egress Full; Filter for cycles full  from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x31	0x3	UNC_H_TxR_AK_CYCLES_NE.ALL	AK Egress Not Empty; Cycles full from both schedulers	0,1,2,3	0x0	null	0
+HA	0x31	0x1	UNC_H_TxR_AK_CYCLES_NE.SCHED0	AK Egress Not Empty; Filter for cycles not empty  from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x31	0x2	UNC_H_TxR_AK_CYCLES_NE.SCHED1	AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x2f	0x3	UNC_H_TxR_AK_INSERTS.ALL	AK Egress Allocations; Allocations from both schedulers	0,1,2,3	0x0	null	0
+HA	0x2f	0x1	UNC_H_TxR_AK_INSERTS.SCHED0	AK Egress Allocations; Filter for allocations from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x2f	0x2	UNC_H_TxR_AK_INSERTS.SCHED1	AK Egress Allocations; Filter for allocations from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x30	0x1	UNC_H_TxR_AK_OCCUPANCY.SCHED0	AK Egress Occupancy; Filter for occupancy from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x30	0x2	UNC_H_TxR_AK_OCCUPANCY.SCHED1	AK Egress Occupancy; Filter for occupancy from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x10	0x1	UNC_H_TxR_BL.DRS_CACHE	Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to the cache.	0,1,2,3	0x0	null	0
+HA	0x10	0x2	UNC_H_TxR_BL.DRS_CORE	Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent directly to the requesting core.	0,1,2,3	0x0	null	0
+HA	0x10	0x4	UNC_H_TxR_BL.DRS_QPI	Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.	0,1,2,3	0x0	null	0
+HA	0x36	0x3	UNC_H_TxR_BL_CYCLES_FULL.ALL	BL Egress Full; Cycles full from both schedulers	0,1,2,3	0x0	null	0
+HA	0x36	0x1	UNC_H_TxR_BL_CYCLES_FULL.SCHED0	BL Egress Full; Filter for cycles full  from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x36	0x2	UNC_H_TxR_BL_CYCLES_FULL.SCHED1	BL Egress Full; Filter for cycles full  from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x35	0x3	UNC_H_TxR_BL_CYCLES_NE.ALL	BL Egress Not Empty; Cycles full from both schedulers	0,1,2,3	0x0	null	0
+HA	0x35	0x1	UNC_H_TxR_BL_CYCLES_NE.SCHED0	BL Egress Not Empty; Filter for cycles not empty  from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x35	0x2	UNC_H_TxR_BL_CYCLES_NE.SCHED1	BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x33	0x3	UNC_H_TxR_BL_INSERTS.ALL	BL Egress Allocations; Allocations from both schedulers	0,1,2,3	0x0	null	0
+HA	0x33	0x1	UNC_H_TxR_BL_INSERTS.SCHED0	BL Egress Allocations; Filter for allocations from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x33	0x2	UNC_H_TxR_BL_INSERTS.SCHED1	BL Egress Allocations; Filter for allocations from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x34	0x3	UNC_H_TxR_BL_OCCUPANCY.ALL	BL Egress Occupancy	0,1,2,3	0x0	null	0
+HA	0x34	0x1	UNC_H_TxR_BL_OCCUPANCY.SCHED0	BL Egress Occupancy; Filter for occupancy from scheduler bank 0	0,1,2,3	0x0	null	0
+HA	0x34	0x2	UNC_H_TxR_BL_OCCUPANCY.SCHED1	BL Egress Occupancy; Filter for occupancy from scheduler bank 1	0,1,2,3	0x0	null	0
+HA	0x18	0x1	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0	Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.	0,1,2,3	0x0	null	0
+HA	0x18	0x2	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1	Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.	0,1,2,3	0x0	null	0
+HA	0x18	0x4	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2	Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.	0,1,2,3	0x0	null	0
+HA	0x18	0x8	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3	Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.	0,1,2,3	0x0	null	0
+HA	0x19	0x1	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0	Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.	0,1,2,3	0x0	null	0
+HA	0x19	0x2	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1	Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.	0,1,2,3	0x0	null	0
+HA	0x19	0x4	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2	Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.	0,1,2,3	0x0	null	0
+HA	0x19	0x8	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3	Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.	0,1,2,3	0x0	null	0
+iMC	0x1	0x1	UNC_M_ACT_COUNT.RD	Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.	0,1,2,3	0x0	null	0
+iMC	0x1	0x2	UNC_M_ACT_COUNT.WR	Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.	0,1,2,3	0x0	null	0
+iMC	0xa1	0x1	UNC_M_BYP_CMDS.ACT	tbd	0,1,2,3	0x0	null	0
+iMC	0xa1	0x2	UNC_M_BYP_CMDS.CAS	tbd	0,1,2,3	0x0	null	0
+iMC	0xa1	0x4	UNC_M_BYP_CMDS.PRE	tbd	0,1,2,3	0x0	null	0
+iMC	0x4	0xF	UNC_M_CAS_COUNT.ALL	DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.	0,1,2,3	0x0	null	0
+iMC	0x4	0x3	UNC_M_CAS_COUNT.RD	DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).	0,1,2,3	0x0	null	0
+iMC	0x4	0x1	UNC_M_CAS_COUNT.RD_REG	DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).	0,1,2,3	0x0	null	0
+iMC	0x4	0x20	UNC_M_CAS_COUNT.RD_RMM	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0x0	null	0
+iMC	0x4	0x2	UNC_M_CAS_COUNT.RD_UNDERFILL	DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller.  This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ.  While it is possible for underfills to be issed in both WMM and RMM, this event counts both.	0,1,2,3	0x0	null	0
+iMC	0x4	0x10	UNC_M_CAS_COUNT.RD_WMM	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0x0	null	0
+iMC	0x4	0xC	UNC_M_CAS_COUNT.WR	DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.	0,1,2,3	0x0	null	0
+iMC	0x4	0x8	UNC_M_CAS_COUNT.WR_RMM	DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic' DRAM Write CAS commands issued on this channel while in Read-Major-Mode.	0,1,2,3	0x0	null	0
+iMC	0x4	0x4	UNC_M_CAS_COUNT.WR_WMM	DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.	0,1,2,3	0x0	null	0
+iMC	0x6	0x0	UNC_M_DRAM_PRE_ALL	Counts the number of times that the precharge all command was sent.	0,1,2,3	0x0	null	0
+iMC	0x5	0x4	UNC_M_DRAM_REFRESH.HIGH	Counts the number of refreshes issued.	0,1,2,3	0x0	null	0
+iMC	0x5	0x2	UNC_M_DRAM_REFRESH.PANIC	Counts the number of refreshes issued.	0,1,2,3	0x0	null	0
+iMC	0x9	0x0	UNC_M_ECC_CORRECTABLE_ERRORS	Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.	0,1,2,3	0x0	null	0
+iMC	0x7	0x8	UNC_M_MAJOR_MODES.ISOCH	Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed.	0,1,2,3	0x0	null	0
+iMC	0x7	0x4	UNC_M_MAJOR_MODES.PARTIAL	Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed.	0,1,2,3	0x0	null	0
+iMC	0x7	0x1	UNC_M_MAJOR_MODES.READ	Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.	0,1,2,3	0x0	null	0
+iMC	0x7	0x2	UNC_M_MAJOR_MODES.WRITE	Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.	0,1,2,3	0x0	null	0
+iMC	0x84	0x0	UNC_M_POWER_CHANNEL_DLLOFF	Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.	0,1,2,3	0x0	null	0
+iMC	0x85	0x0	UNC_M_POWER_CHANNEL_PPD	Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.	0,1,2,3	0x0	null	0
+iMC	0x83	0x1	UNC_M_POWER_CKE_CYCLES.RANK0	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0x0	null	0
+iMC	0x83	0x2	UNC_M_POWER_CKE_CYCLES.RANK1	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0x0	null	0
+iMC	0x83	0x4	UNC_M_POWER_CKE_CYCLES.RANK2	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0x0	null	0
+iMC	0x83	0x8	UNC_M_POWER_CKE_CYCLES.RANK3	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0x0	null	0
+iMC	0x83	0x10	UNC_M_POWER_CKE_CYCLES.RANK4	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0x0	null	0
+iMC	0x83	0x20	UNC_M_POWER_CKE_CYCLES.RANK5	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0x0	null	0
+iMC	0x83	0x40	UNC_M_POWER_CKE_CYCLES.RANK6	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0x0	null	0
+iMC	0x83	0x80	UNC_M_POWER_CKE_CYCLES.RANK7	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0x0	null	0
+iMC	0x86	0x0	UNC_M_POWER_CRITICAL_THROTTLE_CYCLES	Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.	0,1,2,3	0x0	null	0
+iMC	0x43	0x0	UNC_M_POWER_SELF_REFRESH	Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.	0,1,2,3	0x0	null	0
+iMC	0x41	0x1	UNC_M_POWER_THROTTLE_CYCLES.RANK0	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.	0,1,2,3	0x0	null	0
+iMC	0x41	0x2	UNC_M_POWER_THROTTLE_CYCLES.RANK1	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0x0	null	0
+iMC	0x41	0x4	UNC_M_POWER_THROTTLE_CYCLES.RANK2	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0x0	null	0
+iMC	0x41	0x8	UNC_M_POWER_THROTTLE_CYCLES.RANK3	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0x0	null	0
+iMC	0x41	0x10	UNC_M_POWER_THROTTLE_CYCLES.RANK4	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0x0	null	0
+iMC	0x41	0x20	UNC_M_POWER_THROTTLE_CYCLES.RANK5	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0x0	null	0
+iMC	0x41	0x40	UNC_M_POWER_THROTTLE_CYCLES.RANK6	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0x0	null	0
+iMC	0x41	0x80	UNC_M_POWER_THROTTLE_CYCLES.RANK7	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0x0	null	0
+iMC	0x8	0x1	UNC_M_PREEMPTION.RD_PREEMPT_RD	Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.	0,1,2,3	0x0	null	0
+iMC	0x8	0x2	UNC_M_PREEMPTION.RD_PREEMPT_WR	Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.	0,1,2,3	0x0	null	0
+iMC	0x2	0x2	UNC_M_PRE_COUNT.PAGE_CLOSE	Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode.	0,1,2,3	0x0	null	0
+iMC	0x2	0x1	UNC_M_PRE_COUNT.PAGE_MISS	Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses.  This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode.  This does not include PRE commands sent as a result of the page close counter expiration.	0,1,2,3	0x0	null	0
+iMC	0x2	0x4	UNC_M_PRE_COUNT.RD	Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	0x0	null	0
+iMC	0x2	0x8	UNC_M_PRE_COUNT.WR	Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	0x0	null	0
+iMC	0xa0	0x4	UNC_M_RD_CAS_PRIO.HIGH	tbd	0,1,2,3	0x0	null	0
+iMC	0xa0	0x1	UNC_M_RD_CAS_PRIO.LOW	tbd	0,1,2,3	0x0	null	0
+iMC	0xa0	0x2	UNC_M_RD_CAS_PRIO.MED	tbd	0,1,2,3	0x0	null	0
+iMC	0xa0	0x8	UNC_M_RD_CAS_PRIO.PANIC	tbd	0,1,2,3	0x0	null	0
+iMC	0xb0	0x1	UNC_M_RD_CAS_RANK0.BANK0	tbd	0,1,2,3	0x0	null	0
+iMC	0xb0	0x2	UNC_M_RD_CAS_RANK0.BANK1	tbd	0,1,2,3	0x0	null	0
+iMC	0xb0	0x4	UNC_M_RD_CAS_RANK0.BANK2	tbd	0,1,2,3	0x0	null	0
+iMC	0xb0	0x8	UNC_M_RD_CAS_RANK0.BANK3	tbd	0,1,2,3	0x0	null	0
+iMC	0xb0	0x10	UNC_M_RD_CAS_RANK0.BANK4	tbd	0,1,2,3	0x0	null	0
+iMC	0xb0	0x20	UNC_M_RD_CAS_RANK0.BANK5	tbd	0,1,2,3	0x0	null	0
+iMC	0xb0	0x40	UNC_M_RD_CAS_RANK0.BANK6	tbd	0,1,2,3	0x0	null	0
+iMC	0xb0	0x80	UNC_M_RD_CAS_RANK0.BANK7	tbd	0,1,2,3	0x0	null	0
+iMC	0x11	0x0	UNC_M_RPQ_CYCLES_NE	Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.	0,1,2,3	0x0	null	0
+iMC	0x10	0x0	UNC_M_RPQ_INSERTS	Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.	0,1,2,3	0x0	null	0
+iMC	0x91	0x0	UNC_M_VMSE_MXB_WR_OCCUPANCY	tbd	0,1,2,3	0x0	null	0
+iMC	0x90	0x2	UNC_M_VMSE_WR_PUSH.RMM	tbd	0,1,2,3	0x0	null	0
+iMC	0x90	0x1	UNC_M_VMSE_WR_PUSH.WMM	tbd	0,1,2,3	0x0	null	0
+iMC	0xc0	0x1	UNC_M_WMM_TO_RMM.LOW_THRESH	tbd	0,1,2,3	0x0	null	0
+iMC	0xc0	0x2	UNC_M_WMM_TO_RMM.STARVE	tbd	0,1,2,3	0x0	null	0
+iMC	0xc0	0x4	UNC_M_WMM_TO_RMM.VMSE_RETRY	tbd	0,1,2,3	0x0	null	0
+iMC	0x22	0x0	UNC_M_WPQ_CYCLES_FULL	Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.	0,1,2,3	0x0	null	0
+iMC	0x21	0x0	UNC_M_WPQ_CYCLES_NE	Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.	0,1,2,3	0x0	null	0
+iMC	0x20	0x0	UNC_M_WPQ_INSERTS	Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.	0,1,2,3	0x0	null	0
+iMC	0x23	0x0	UNC_M_WPQ_READ_HIT	Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.	0,1,2,3	0x0	null	0
+iMC	0x24	0x0	UNC_M_WPQ_WRITE_HIT	Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.	0,1,2,3	0x0	null	0
+iMC	0xc1	0x0	UNC_M_WRONG_MM	tbd	0,1,2,3	0x0	null	0
+iMC	0xb8	0x1	UNC_M_WR_CAS_RANK0.BANK0	tbd	0,1,2,3	0x0	null	0
+iMC	0xb8	0x2	UNC_M_WR_CAS_RANK0.BANK1	tbd	0,1,2,3	0x0	null	0
+iMC	0xb8	0x4	UNC_M_WR_CAS_RANK0.BANK2	tbd	0,1,2,3	0x0	null	0
+iMC	0xb8	0x8	UNC_M_WR_CAS_RANK0.BANK3	tbd	0,1,2,3	0x0	null	0
+iMC	0xb8	0x10	UNC_M_WR_CAS_RANK0.BANK4	tbd	0,1,2,3	0x0	null	0
+iMC	0xb8	0x20	UNC_M_WR_CAS_RANK0.BANK5	tbd	0,1,2,3	0x0	null	0
+iMC	0xb8	0x40	UNC_M_WR_CAS_RANK0.BANK6	tbd	0,1,2,3	0x0	null	0
+iMC	0xb8	0x80	UNC_M_WR_CAS_RANK0.BANK7	tbd	0,1,2,3	0x0	null	0
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.AnyResp9flits	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.AnyResp11flits	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.DataC_M	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.WbIData	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.WbSData	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.WbEData	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.AnyResp	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.AnyDataC	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.NCB.AnyMsg	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.NCB.AnyInt	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.DataC_F	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.DataC_F_FrcAckCnflt	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.DataC_F_Cmp	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.DataC_E	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.DataC_E_FrcAckCnflt	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.DRS.DataC_E_Cmp	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.RespFwd	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.RespFwdI	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.RespFwdS	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.RespFwdIWb	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.RespFwdSWb	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.RespIWb	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.RespSWb	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.AnyReq	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.HOM.AnyResp	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.SNP.AnySnp	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.NDR.AnyCmp	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.NCS.NcRd	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.NCS.AnyMsg1or2flits	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.NCS.AnyMsg3flits	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.NCB.AnyMsg9flits	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MESSAGE.NCB.AnyMsg11flits	tbd	0,1,2,3	0x0	null	1
+QPI LL	0x38	0x0	UNC_Q_MATCH_MASK	tbd	0,1,2,3	0x0	null	1
+CBO	0x1B	0x33	UNC_C_RING_AD_USED.UP	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1B	0xCC	UNC_C_RING_AD_USED.DOWN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1C	0x33	UNC_C_RING_AK_USED.UP	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1C	0xCC	UNC_C_RING_AK_USED.DOWN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1D	0x33	UNC_C_RING_BL_USED.UP	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1D	0xCC	UNC_C_RING_BL_USED.DOWN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x5	0x2	UNC_C_RING_BOUNCES.AD_IRQ	tbd	0,1	0	null	0
+CBO	0x5	0x4	UNC_C_RING_BOUNCES.AK	tbd	0,1	0	null	0
+CBO	0x5	0x8	UNC_C_RING_BOUNCES.BL	tbd	0,1	0	null	0
+CBO	0x5	0x10	UNC_C_RING_BOUNCES.IV	tbd	0,1	0	null	0
+CBO	0x6	0x1	UNC_C_RING_SINK_STARVED.AD_IRQ	tbd	0,1	0	null	0
+CBO	0x6	0x2	UNC_C_RING_SINK_STARVED.AD_IPQ	tbd	0,1	0	null	0
+CBO	0x6	0x10	UNC_C_RING_SINK_STARVED.IV	tbd	0,1	0	null	0
+CBO	0x12	0x4	UNC_C_RxR_EXT_STARVED.PRQ	IRQ is blocking the ingress queue and causing the starvation.	0,1	0	null	0
+CBO	0x13	0x2	UNC_C_RxR_INSERTS.IRQ_REJ	Counts number of allocations per cycle into the specified Ingress queue.	0,1	0	null	0
+HA	0x20	0x1	UNC_H_ADDR_OPC_MATCH.ADDR	tbd	0,1,2,3	0	HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]	0
+HA	0x20	0x2	UNC_H_ADDR_OPC_MATCH.OPC	tbd	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x4	UNC_H_ADDR_OPC_MATCH.AD	tbd	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x8	UNC_H_ADDR_OPC_MATCH.BL	tbd	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x20	0x10	UNC_H_ADDR_OPC_MATCH.AK	tbd	0,1,2,3	0	HA_OpcodeMatch[5:0]	0
+HA	0x42	0x0	UNC_H_BT_CYCLES_NE	Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.	0,1,2,3	0	null	0
+HA	0x51	0x8	UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD	Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard	0,1,2,3	0	null	0
+HA	0x51	0x10	UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD	Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard	0,1,2,3	0	null	0
+HA	0xD	0x1	UNC_H_DIRECTORY_UPDATE.SET	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory sets.  This occurs when a remote read transaction requests memory, bringing it to a remote cache.	0,1,2,3	0	null	0
+HA	0xD	0x2	UNC_H_DIRECTORY_UPDATE.CLEAR	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory clears.  This occurs when snoops were sent and all returned with RspI.	0,1,2,3	0	null	0
+HA	0x59	0x0	UNC_H_IGR_CREDITS_AD_QPI2	Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer.	0,1,2,3	0	null	0
+HA	0x5A	0x0	UNC_H_IGR_CREDITS_BL_QPI2	Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer.	0,1,2,3	0	null	0
+HA	0x57	0x1	UNC_H_IODC_CONFLICTS.ANY	tbd	0,1,2,3	0	null	0
+HA	0x57	0x4	UNC_H_IODC_CONFLICTS.LAST	tbd	0,1,2,3	0	null	0
+HA	0x3E	0x33	UNC_H_RING_AD_USED.CW	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3E	0xCC	UNC_H_RING_AD_USED.CCW	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3F	0x33	UNC_H_RING_AK_USED.CW	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3F	0xCC	UNC_H_RING_AK_USED.CCW	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x40	0x33	UNC_H_RING_BL_USED.CW	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x40	0xCC	UNC_H_RING_BL_USED.CCW	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0xF	0x4	UNC_H_TxR_AD.HOM	Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring.  NDR stands for 'non-data response' and is generally used for completions that do not include data.  AD NDR is used for transactions to remote sockets.	0,1,2,3	0	null	0
+IRP	0x15	0x4	UNC_I_TRANSACTIONS.RD_PREFETCHES	Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.	0,1	0	null	0
+PCU	0x42	0x0	UNC_P_DEMOTIONS_CORE10	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x43	0x0	UNC_P_DEMOTIONS_CORE11	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x44	0x0	UNC_P_DEMOTIONS_CORE12	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x45	0x0	UNC_P_DEMOTIONS_CORE13	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x46	0x0	UNC_P_DEMOTIONS_CORE14	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x40	0x0	UNC_P_DEMOTIONS_CORE8	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x41	0x0	UNC_P_DEMOTIONS_CORE9	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x2	0x0	UNC_P_FREQ_MIN_PERF_P_CYCLES	Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies.	0,1,2,3	0	null	1
+PCU	0x26	0x0	UNC_P_PKG_C_EXIT_LATENCY	Counts the number of cycles that the package is transitioning from package C2 to C3.	0,1,2,3	0	null	1
+QPI LL	0xF	0x1	UNC_Q_RxL_CYCLES_NE_DRS.VN0	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.	0,1,2,3	0	null	1
+QPI LL	0xF	0x2	UNC_Q_RxL_CYCLES_NE_DRS.VN1	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.	0,1,2,3	0	null	1
+QPI LL	0x12	0x1	UNC_Q_RxL_CYCLES_NE_HOM.VN0	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.	0,1,2,3	0	null	1
+QPI LL	0x12	0x2	UNC_Q_RxL_CYCLES_NE_HOM.VN1	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.	0,1,2,3	0	null	1
+QPI LL	0x10	0x1	UNC_Q_RxL_CYCLES_NE_NCB.VN0	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.	0,1,2,3	0	null	1
+QPI LL	0x10	0x2	UNC_Q_RxL_CYCLES_NE_NCB.VN1	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.	0,1,2,3	0	null	1
+QPI LL	0x11	0x1	UNC_Q_RxL_CYCLES_NE_NCS.VN0	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.	0,1,2,3	0	null	1
+QPI LL	0x11	0x2	UNC_Q_RxL_CYCLES_NE_NCS.VN1	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.	0,1,2,3	0	null	1
+QPI LL	0x14	0x1	UNC_Q_RxL_CYCLES_NE_NDR.VN0	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.	0,1,2,3	0	null	1
+QPI LL	0x14	0x2	UNC_Q_RxL_CYCLES_NE_NDR.VN1	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.	0,1,2,3	0	null	1
+QPI LL	0x13	0x1	UNC_Q_RxL_CYCLES_NE_SNP.VN0	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.	0,1,2,3	0	null	1
+QPI LL	0x13	0x2	UNC_Q_RxL_CYCLES_NE_SNP.VN1	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.	0,1,2,3	0	null	1
+QPI LL	0x9	0x1	UNC_Q_RxL_INSERTS_DRS.VN0	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.	0,1,2,3	0	null	1
+QPI LL	0x9	0x2	UNC_Q_RxL_INSERTS_DRS.VN1	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.	0,1,2,3	0	null	1
+QPI LL	0xC	0x1	UNC_Q_RxL_INSERTS_HOM.VN0	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.	0,1,2,3	0	null	1
+QPI LL	0xC	0x2	UNC_Q_RxL_INSERTS_HOM.VN1	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.	0,1,2,3	0	null	1
+QPI LL	0xA	0x1	UNC_Q_RxL_INSERTS_NCB.VN0	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.	0,1,2,3	0	null	1
+QPI LL	0xA	0x2	UNC_Q_RxL_INSERTS_NCB.VN1	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.	0,1,2,3	0	null	1
+QPI LL	0xB	0x1	UNC_Q_RxL_INSERTS_NCS.VN0	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.	0,1,2,3	0	null	1
+QPI LL	0xB	0x2	UNC_Q_RxL_INSERTS_NCS.VN1	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.	0,1,2,3	0	null	1
+QPI LL	0xE	0x1	UNC_Q_RxL_INSERTS_NDR.VN0	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.	0,1,2,3	0	null	1
+QPI LL	0xE	0x2	UNC_Q_RxL_INSERTS_NDR.VN1	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.	0,1,2,3	0	null	1
+QPI LL	0xD	0x1	UNC_Q_RxL_INSERTS_SNP.VN0	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.	0,1,2,3	0	null	1
+QPI LL	0xD	0x2	UNC_Q_RxL_INSERTS_SNP.VN1	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.	0,1,2,3	0	null	1
+QPI LL	0x15	0x1	UNC_Q_RxL_OCCUPANCY_DRS.VN0	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.	0,1,2,3	0	null	1
+QPI LL	0x15	0x2	UNC_Q_RxL_OCCUPANCY_DRS.VN1	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.	0,1,2,3	0	null	1
+QPI LL	0x18	0x1	UNC_Q_RxL_OCCUPANCY_HOM.VN0	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.	0,1,2,3	0	null	1
+QPI LL	0x18	0x2	UNC_Q_RxL_OCCUPANCY_HOM.VN1	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.	0,1,2,3	0	null	1
+QPI LL	0x16	0x1	UNC_Q_RxL_OCCUPANCY_NCB.VN0	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.	0,1,2,3	0	null	1
+QPI LL	0x16	0x2	UNC_Q_RxL_OCCUPANCY_NCB.VN1	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.	0,1,2,3	0	null	1
+QPI LL	0x17	0x1	UNC_Q_RxL_OCCUPANCY_NCS.VN0	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.	0,1,2,3	0	null	1
+QPI LL	0x17	0x2	UNC_Q_RxL_OCCUPANCY_NCS.VN1	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.	0,1,2,3	0	null	1
+QPI LL	0x1A	0x1	UNC_Q_RxL_OCCUPANCY_NDR.VN0	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.	0,1,2,3	0	null	1
+QPI LL	0x1A	0x2	UNC_Q_RxL_OCCUPANCY_NDR.VN1	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.	0,1,2,3	0	null	1
+QPI LL	0x19	0x1	UNC_Q_RxL_OCCUPANCY_SNP.VN0	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.	0,1,2,3	0	null	1
+QPI LL	0x19	0x2	UNC_Q_RxL_OCCUPANCY_SNP.VN1	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.	0,1,2,3	0	null	1
+QPI LL	0x29	0x0	UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED	Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.	0,1,2,3	0	null	1
+QPI LL	0x25	0x0	UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY	Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.	0,1,2,3	0	null	1
+R2PCIe	0x7	0x33	UNC_R2_RING_AD_USED.CW	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x7	0xCC	UNC_R2_RING_AD_USED.CCW	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x8	0x33	UNC_R2_RING_AK_USED.CW	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x8	0xCC	UNC_R2_RING_AK_USED.CCW	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x9	0x33	UNC_R2_RING_BL_USED.CW	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x9	0xCC	UNC_R2_RING_BL_USED.CCW	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0xA	0xFF	UNC_R2_RING_IV_USED.ANY	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity	0,1,2,3	0	null	0
+R2PCIe	0x12	0x1	UNC_R2_RxR_AK_BOUNCES.CW	Counts the number of times when a request destined for the AK ingress bounced.	0	0	null	0
+R2PCIe	0x12	0x2	UNC_R2_RxR_AK_BOUNCES.CCW	Counts the number of times when a request destined for the AK ingress bounced.	0	0	null	0
+R2PCIe	0x28	0x1	UNC_R2_TxR_NACK_CCW.AD	AD CounterClockwise Egress Queue	0,1	0	null	0
+R2PCIe	0x28	0x2	UNC_R2_TxR_NACK_CCW.AK	AK CounterClockwise Egress Queue	0,1	0	null	0
+R2PCIe	0x28	0x4	UNC_R2_TxR_NACK_CCW.BL	BL CounterClockwise Egress Queue	0,1	0	null	0
+R2PCIe	0x26	0x1	UNC_R2_TxR_NACK_CW.AD	AD Clockwise Egress Queue	0,1	0	null	0
+R2PCIe	0x26	0x2	UNC_R2_TxR_NACK_CW.AK	AK Clockwise Egress Queue	0,1	0	null	0
+R2PCIe	0x26	0x4	UNC_R2_TxR_NACK_CW.BL	BL Clockwise Egress Queue	0,1	0	null	0
+R3QPI	0x7	0x33	UNC_R3_RING_AD_USED.CW	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x7	0xCC	UNC_R3_RING_AD_USED.CCW	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x8	0x33	UNC_R3_RING_AK_USED.CW	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x8	0xCC	UNC_R3_RING_AK_USED.CCW	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x9	0x33	UNC_R3_RING_BL_USED.CW	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x9	0xCC	UNC_R3_RING_BL_USED.CCW	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0xA	0xFF	UNC_R3_RING_IV_USED.ANY	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity	0,1,2	0	null	0
+R3QPI	0x12	0x0	UNC_R3_RxR_AD_BYPASSED	Counts the number of times when the AD Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.	0,1	0	null	0
+R3QPI	0x33	0x1	UNC_R3_VNA_CREDITS_ACQUIRED.AD	Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.	0,1	0	null	0
+R3QPI	0x33	0x4	UNC_R3_VNA_CREDITS_ACQUIRED.BL	Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.	0,1	0	null	0
+UBOX	0x46	0x0	UNC_U_RACU_REQUESTS	tbd	0,1	0	null	0
+iMC	0x1	0x8	UNC_M_ACT_COUNT.BYP	Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.	0,1,2,3	0	null	0
+iMC	0x0	0x0	UNC_M_DCLOCKTICKS	tbd	0,1,2,3	0	null	0
+iMC	0x42	0x0	UNC_M_POWER_PCU_THROTTLING	tbd	0,1,2,3	0	null	0
+iMC	0x2	0x10	UNC_M_PRE_COUNT.BYP	Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	0	null	0
+iMC	0xB1	0x1	UNC_M_RD_CAS_RANK1.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xB1	0x2	UNC_M_RD_CAS_RANK1.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xB1	0x4	UNC_M_RD_CAS_RANK1.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xB1	0x8	UNC_M_RD_CAS_RANK1.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xB1	0x10	UNC_M_RD_CAS_RANK1.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xB1	0x20	UNC_M_RD_CAS_RANK1.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xB1	0x40	UNC_M_RD_CAS_RANK1.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xB1	0x80	UNC_M_RD_CAS_RANK1.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xB2	0x1	UNC_M_RD_CAS_RANK2.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xB2	0x2	UNC_M_RD_CAS_RANK2.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xB2	0x4	UNC_M_RD_CAS_RANK2.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xB2	0x8	UNC_M_RD_CAS_RANK2.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xB2	0x10	UNC_M_RD_CAS_RANK2.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xB2	0x20	UNC_M_RD_CAS_RANK2.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xB2	0x40	UNC_M_RD_CAS_RANK2.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xB2	0x80	UNC_M_RD_CAS_RANK2.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xB3	0x1	UNC_M_RD_CAS_RANK3.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xB3	0x2	UNC_M_RD_CAS_RANK3.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xB3	0x4	UNC_M_RD_CAS_RANK3.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xB3	0x8	UNC_M_RD_CAS_RANK3.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xB3	0x10	UNC_M_RD_CAS_RANK3.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xB3	0x20	UNC_M_RD_CAS_RANK3.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xB3	0x40	UNC_M_RD_CAS_RANK3.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xB3	0x80	UNC_M_RD_CAS_RANK3.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xB4	0x1	UNC_M_RD_CAS_RANK4.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xB4	0x2	UNC_M_RD_CAS_RANK4.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xB4	0x4	UNC_M_RD_CAS_RANK4.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xB4	0x8	UNC_M_RD_CAS_RANK4.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xB4	0x10	UNC_M_RD_CAS_RANK4.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xB4	0x20	UNC_M_RD_CAS_RANK4.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xB4	0x40	UNC_M_RD_CAS_RANK4.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xB4	0x80	UNC_M_RD_CAS_RANK4.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xB5	0x1	UNC_M_RD_CAS_RANK5.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xB5	0x2	UNC_M_RD_CAS_RANK5.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xB5	0x4	UNC_M_RD_CAS_RANK5.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xB5	0x8	UNC_M_RD_CAS_RANK5.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xB5	0x10	UNC_M_RD_CAS_RANK5.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xB5	0x20	UNC_M_RD_CAS_RANK5.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xB5	0x40	UNC_M_RD_CAS_RANK5.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xB5	0x80	UNC_M_RD_CAS_RANK5.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xB6	0x1	UNC_M_RD_CAS_RANK6.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xB6	0x2	UNC_M_RD_CAS_RANK6.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xB6	0x4	UNC_M_RD_CAS_RANK6.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xB6	0x8	UNC_M_RD_CAS_RANK6.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xB6	0x10	UNC_M_RD_CAS_RANK6.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xB6	0x20	UNC_M_RD_CAS_RANK6.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xB6	0x40	UNC_M_RD_CAS_RANK6.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xB6	0x80	UNC_M_RD_CAS_RANK6.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xB7	0x1	UNC_M_RD_CAS_RANK7.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xB7	0x2	UNC_M_RD_CAS_RANK7.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xB7	0x4	UNC_M_RD_CAS_RANK7.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xB7	0x8	UNC_M_RD_CAS_RANK7.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xB7	0x10	UNC_M_RD_CAS_RANK7.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xB7	0x20	UNC_M_RD_CAS_RANK7.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xB7	0x40	UNC_M_RD_CAS_RANK7.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xB7	0x80	UNC_M_RD_CAS_RANK7.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xB9	0x1	UNC_M_WR_CAS_RANK1.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xB9	0x2	UNC_M_WR_CAS_RANK1.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xB9	0x4	UNC_M_WR_CAS_RANK1.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xB9	0x8	UNC_M_WR_CAS_RANK1.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xB9	0x10	UNC_M_WR_CAS_RANK1.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xB9	0x20	UNC_M_WR_CAS_RANK1.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xB9	0x40	UNC_M_WR_CAS_RANK1.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xB9	0x80	UNC_M_WR_CAS_RANK1.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xBA	0x1	UNC_M_WR_CAS_RANK2.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xBA	0x2	UNC_M_WR_CAS_RANK2.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xBA	0x4	UNC_M_WR_CAS_RANK2.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xBA	0x8	UNC_M_WR_CAS_RANK2.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xBA	0x10	UNC_M_WR_CAS_RANK2.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xBA	0x20	UNC_M_WR_CAS_RANK2.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xBA	0x40	UNC_M_WR_CAS_RANK2.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xBA	0x80	UNC_M_WR_CAS_RANK2.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xBB	0x1	UNC_M_WR_CAS_RANK3.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xBB	0x2	UNC_M_WR_CAS_RANK3.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xBB	0x4	UNC_M_WR_CAS_RANK3.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xBB	0x8	UNC_M_WR_CAS_RANK3.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xBB	0x10	UNC_M_WR_CAS_RANK3.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xBB	0x20	UNC_M_WR_CAS_RANK3.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xBB	0x40	UNC_M_WR_CAS_RANK3.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xBB	0x80	UNC_M_WR_CAS_RANK3.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xBC	0x1	UNC_M_WR_CAS_RANK4.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xBC	0x2	UNC_M_WR_CAS_RANK4.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xBC	0x4	UNC_M_WR_CAS_RANK4.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xBC	0x8	UNC_M_WR_CAS_RANK4.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xBC	0x10	UNC_M_WR_CAS_RANK4.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xBC	0x20	UNC_M_WR_CAS_RANK4.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xBC	0x40	UNC_M_WR_CAS_RANK4.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xBC	0x80	UNC_M_WR_CAS_RANK4.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xBD	0x1	UNC_M_WR_CAS_RANK5.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xBD	0x2	UNC_M_WR_CAS_RANK5.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xBD	0x4	UNC_M_WR_CAS_RANK5.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xBD	0x8	UNC_M_WR_CAS_RANK5.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xBD	0x10	UNC_M_WR_CAS_RANK5.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xBD	0x20	UNC_M_WR_CAS_RANK5.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xBD	0x40	UNC_M_WR_CAS_RANK5.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xBD	0x80	UNC_M_WR_CAS_RANK5.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xBE	0x1	UNC_M_WR_CAS_RANK6.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xBE	0x2	UNC_M_WR_CAS_RANK6.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xBE	0x4	UNC_M_WR_CAS_RANK6.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xBE	0x8	UNC_M_WR_CAS_RANK6.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xBE	0x10	UNC_M_WR_CAS_RANK6.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xBE	0x20	UNC_M_WR_CAS_RANK6.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xBE	0x40	UNC_M_WR_CAS_RANK6.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xBE	0x80	UNC_M_WR_CAS_RANK6.BANK7	tbd	0,1,2,3	0	null	0
+iMC	0xBF	0x1	UNC_M_WR_CAS_RANK7.BANK0	tbd	0,1,2,3	0	null	0
+iMC	0xBF	0x2	UNC_M_WR_CAS_RANK7.BANK1	tbd	0,1,2,3	0	null	0
+iMC	0xBF	0x4	UNC_M_WR_CAS_RANK7.BANK2	tbd	0,1,2,3	0	null	0
+iMC	0xBF	0x8	UNC_M_WR_CAS_RANK7.BANK3	tbd	0,1,2,3	0	null	0
+iMC	0xBF	0x10	UNC_M_WR_CAS_RANK7.BANK4	tbd	0,1,2,3	0	null	0
+iMC	0xBF	0x20	UNC_M_WR_CAS_RANK7.BANK5	tbd	0,1,2,3	0	null	0
+iMC	0xBF	0x40	UNC_M_WR_CAS_RANK7.BANK6	tbd	0,1,2,3	0	null	0
+iMC	0xBF	0x80	UNC_M_WR_CAS_RANK7.BANK7	tbd	0,1,2,3	0	null	0
+UBOX	0x0	0x0	UNC_U_CLOCKTICKS	tbd	0	0	null	0
+CBO	0x1B	0x3	UNC_C_RING_AD_USED.CW	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1B	0xC	UNC_C_RING_AD_USED.CCW	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1C	0x3	UNC_C_RING_AK_USED.CW	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1C	0xC	UNC_C_RING_AK_USED.CCW	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1D	0x3	UNC_C_RING_BL_USED.CW	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1D	0xC	UNC_C_RING_BL_USED.CCW	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x11	0x2	UNC_C_RxR_OCCUPANCY.IRQ_REJ	Counts number of entries in the specified Ingress queue in each cycle.	0	0	null	0
diff --git a/x86data/perfmon_data/JKT/Jaketown_core_V18.json b/x86data/perfmon_data/JKT/Jaketown_core_V18.json
new file mode 100644
index 0000000..98cf8e4
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_core_V18.json
@@ -0,0 +1,7374 @@
+[

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired from execution.",

+    "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. ",

+    "Counter": "Fixed counter 1",

+    "CounterHTOff": "Fixed counter 1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Core cycles when the thread is not in halt state.",

+    "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Reference cycles when the core is not in halt state.",

+    "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ",

+    "Counter": "Fixed counter 3",

+    "CounterHTOff": "Fixed counter 3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x41",

+    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken macro-conditional branches",

+    "PublicDescription": "Not taken macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x81",

+    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired macro-conditional branches",

+    "PublicDescription": "Taken speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x82",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",

+    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x84",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x88",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x90",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired direct near calls",

+    "PublicDescription": "Taken speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xA0",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired indirect calls",

+    "PublicDescription": "Taken speculative and retired indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC1",

+    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired macro-conditional branches",

+    "PublicDescription": "Speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC2",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",

+    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC4",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC8",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Speculative and retired indirect return branches.",

+    "PublicDescription": "Speculative and retired indirect return branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xD0",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired direct near calls",

+    "PublicDescription": "Speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x41",

+    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x81",

+    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x84",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x88",

+    "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x90",

+    "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted direct near calls",

+    "PublicDescription": "Taken speculative and retired mispredicted direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xA0",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect calls",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC1",

+    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC4",

+    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xD0",

+    "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired mispredicted direct near calls",

+    "PublicDescription": "Speculative and retired mispredicted direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Thread cycles when thread is not in halt state",

+    "PublicDescription": "Thread cycles when thread is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x01",

+    "EventName": "ITLB.ITLB_FLUSH",

+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "PublicDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x01",

+    "EventName": "ICACHE.HIT",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x02",

+    "EventName": "ICACHE.MISSES",

+    "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",

+    "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.UOPS",

+    "BriefDescription": "Number of Uops delivered by the LSD. ",

+    "PublicDescription": "Number of Uops delivered by the LSD. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_ACTIVE",

+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x01",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

+    "PublicDescription": "Stalls caused by changing prefix length of the instruction.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x04",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Stall cycles because IQ is full",

+    "PublicDescription": "Stall cycles because IQ is full",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x17",

+    "UMask": "0x01",

+    "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",

+    "BriefDescription": "Valid instructions written to IQ per cycle",

+    "PublicDescription": "Valid instructions written to IQ per cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x02",

+    "EventName": "IDQ.EMPTY",

+    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "PublicDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_UOPS",

+    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x20",

+    "EventName": "IDQ.MS_MITE_UOPS",

+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",

+    "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "PublicDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "PublicDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x01",

+    "EventName": "DSB2MITE_SWITCHES.COUNT",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x02",

+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",

+    "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAC",

+    "UMask": "0x02",

+    "EventName": "DSB_FILL.OTHER_CANCEL",

+    "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit",

+    "PublicDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAC",

+    "UMask": "0x08",

+    "EventName": "DSB_FILL.EXCEED_DSB_LINES",

+    "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

+    "PublicDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x40",

+    "EventName": "INT_MISC.RAT_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x59",

+    "UMask": "0x20",

+    "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",

+    "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",

+    "PublicDescription": "Increments the number of flags-merge uops in flight each cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x59",

+    "UMask": "0x40",

+    "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",

+    "BriefDescription": "Cycles with at least one slow LEA uop being allocated",

+    "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x59",

+    "UMask": "0x80",

+    "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",

+    "BriefDescription": "Multiply packed/scalar single precision uops allocated",

+    "PublicDescription": "Multiply packed/scalar single precision uops allocated",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x01",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource-related stall cycles",

+    "PublicDescription": "Resource-related stall cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x02",

+    "EventName": "RESOURCE_STALLS.LB",

+    "BriefDescription": "Counts the cycles of stall due to lack of load buffers.",

+    "PublicDescription": "Counts the cycles of stall due to lack of load buffers.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x04",

+    "EventName": "RESOURCE_STALLS.RS",

+    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",

+    "PublicDescription": "Cycles stalled due to no eligible RS entry available.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x08",

+    "EventName": "RESOURCE_STALLS.SB",

+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "PublicDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB",

+    "BriefDescription": "Cycles stalled due to re-order buffer full.",

+    "PublicDescription": "Cycles stalled due to re-order buffer full.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5B",

+    "UMask": "0x40",

+    "EventName": "RESOURCE_STALLS2.BOB_FULL",

+    "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it",

+    "PublicDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_CYCLES",

+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "PublicDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0",

+    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

+    "PublicDescription": "Unhalted core cycles when the thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0_TRANS",

+    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "PublicDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x02",

+    "EventName": "CPL_CYCLES.RING123",

+    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "PublicDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x20",

+    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",

+    "BriefDescription": "Count cases of saving new LBR",

+    "PublicDescription": "Count cases of saving new LBR",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-modifying code (SMC) detected.",

+    "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x20",

+    "EventName": "MACHINE_CLEARS.MASKMOV",

+    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ",

+    "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",

+    "PublicDescription": "Number of instructions retired. General Counter   - architectural event",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.ALL",

+    "BriefDescription": "Actually retired uops. ",

+    "PublicDescription": "This event counts the number of micro-ops retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x02",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used. ",

+    "PublicDescription": "This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops. ",

+    "PublicDescription": "Cycles without actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Cycles with less than 10 actually retired uops. ",

+    "PublicDescription": "Cycles with less than 10 actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "10",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x01",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Conditional branch instructions retired. ",

+    "PublicDescription": "Conditional branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x02",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect near call instructions retired. ",

+    "PublicDescription": "Direct and indirect near call instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All (macro) branch instructions retired.",

+    "PublicDescription": "All (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x08",

+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",

+    "BriefDescription": "Return instructions retired. ",

+    "PublicDescription": "Return instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x10",

+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Not taken branch instructions retired. ",

+    "PublicDescription": "Not taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x20",

+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "Taken branch instructions retired. ",

+    "PublicDescription": "Taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x40",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Far branch instructions retired. ",

+    "PublicDescription": "Far branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x04",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",

+    "PublicDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x01",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional branch instructions retired. ",

+    "PublicDescription": "Mispredicted conditional branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x02",

+    "EventName": "BR_MISP_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect mispredicted near call instructions retired. ",

+    "PublicDescription": "Direct and indirect mispredicted near call instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All mispredicted macro branch instructions retired.",

+    "PublicDescription": "All mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x10",

+    "EventName": "BR_MISP_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Mispredicted not taken branch instructions retired. ",

+    "PublicDescription": "Mispredicted not taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_RETIRED.TAKEN",

+    "BriefDescription": "Mispredicted taken branch instructions retired. ",

+    "PublicDescription": "Mispredicted taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x04",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",

+    "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x02",

+    "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",

+    "BriefDescription": "Retired instructions experiencing ITLB misses. ",

+    "PublicDescription": "Retired instructions experiencing ITLB misses. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x08",

+    "EventName": "OTHER_ASSISTS.AVX_STORE",

+    "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

+    "PublicDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x10",

+    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

+    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "PublicDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x20",

+    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

+    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "PublicDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x02",

+    "EventName": "FP_ASSIST.X87_OUTPUT",

+    "BriefDescription": "Number of X87 assists due to output value.",

+    "PublicDescription": "Number of X87 assists due to output value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x04",

+    "EventName": "FP_ASSIST.X87_INPUT",

+    "BriefDescription": "Number of X87 assists due to input value.",

+    "PublicDescription": "Number of X87 assists due to input value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x08",

+    "EventName": "FP_ASSIST.SIMD_OUTPUT",

+    "BriefDescription": "Number of SIMD FP assists due to Output values",

+    "PublicDescription": "Number of SIMD FP assists due to Output values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x10",

+    "EventName": "FP_ASSIST.SIMD_INPUT",

+    "BriefDescription": "Number of SIMD FP assists due to input values",

+    "PublicDescription": "Number of SIMD FP assists due to input values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

+    "BriefDescription": "Loads with latency value being above 4 ",

+    "PublicDescription": "Loads with latency value being above 4 ",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

+    "BriefDescription": "Loads with latency value being above 8",

+    "PublicDescription": "Loads with latency value being above 8",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

+    "BriefDescription": "Loads with latency value being above 16",

+    "PublicDescription": "Loads with latency value being above 16",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

+    "BriefDescription": "Loads with latency value being above 32",

+    "PublicDescription": "Loads with latency value being above 32",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

+    "BriefDescription": "Loads with latency value being above 64",

+    "PublicDescription": "Loads with latency value being above 64",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

+    "BriefDescription": "Loads with latency value being above 128",

+    "PublicDescription": "Loads with latency value being above 128",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "1009",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

+    "BriefDescription": "Loads with latency value being above 256",

+    "PublicDescription": "Loads with latency value being above 256",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "503",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

+    "BriefDescription": "Loads with latency value being above 512",

+    "PublicDescription": "Loads with latency value being above 512",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "101",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x02",

+    "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",

+    "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS)",

+    "PublicDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS)",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x11",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",

+    "BriefDescription": "Retired load uops that miss the STLB.",

+    "PublicDescription": "Retired load uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x12",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",

+    "BriefDescription": "Retired store uops that miss the STLB.",

+    "PublicDescription": "Retired store uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x21",

+    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",

+    "BriefDescription": "Retired load uops with locked access.",

+    "PublicDescription": "Retired load uops with locked access.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x41",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",

+    "BriefDescription": "Retired load uops that split across a cacheline boundary.",

+    "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x42",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",

+    "BriefDescription": "Retired store uops that split across a cacheline boundary.",

+    "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x81",

+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

+    "BriefDescription": "All retired load uops.",

+    "PublicDescription": "This event counts the number of load uops retired",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x82",

+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

+    "BriefDescription": "All retired store uops.",

+    "PublicDescription": "This event counts the number of store uops retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",

+    "BriefDescription": "Retired load uops with L1 cache hits as data sources. ",

+    "PublicDescription": "Retired load uops with L1 cache hits as data sources. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

+    "BriefDescription": "Retired load uops with L2 cache hits as data sources. ",

+    "PublicDescription": "Retired load uops with L2 cache hits as data sources. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",

+    "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ",

+    "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",

+    "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",

+    "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",

+    "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",

+    "PublicDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",

+    "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ",

+    "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified state.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",

+    "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ",

+    "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",

+    "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",

+    "PublicDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "PublicDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD3",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",

+    "BriefDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "PublicDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x01",

+    "EventName": "ARITH.FPU_DIV_ACTIVE",

+    "BriefDescription": "Cycles when divider is busy executing divide operations",

+    "PublicDescription": "Cycles when divider is busy executing divide operations",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x01",

+    "EventName": "ARITH.FPU_DIV",

+    "BriefDescription": "Divide operations executed",

+    "PublicDescription": "This event counts the number of the divide operations executed.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x01",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

+    "PublicDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x11",

+    "UMask": "0x01",

+    "EventName": "SIMD_FP_256.PACKED_SINGLE",

+    "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

+    "PublicDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x11",

+    "UMask": "0x02",

+    "EventName": "SIMD_FP_256.PACKED_DOUBLE",

+    "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

+    "PublicDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED.THREAD",

+    "BriefDescription": "Uops dispatched per thread",

+    "PublicDescription": "Uops dispatched per thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED.CORE",

+    "BriefDescription": "Uops dispatched from any thread",

+    "PublicDescription": "Uops dispatched from any thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 0",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 1",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 4",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 5",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",

+    "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",

+    "PublicDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",

+    "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",

+    "PublicDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",

+    "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",

+    "PublicDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",

+    "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",

+    "PublicDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",

+    "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",

+    "PublicDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4F",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",

+    "PublicDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x01",

+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Misses at all ITLB levels that cause page walks",

+    "PublicDescription": "Misses at all ITLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x02",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Misses in all ITLB levels that cause completed page walks",

+    "PublicDescription": "Misses in all ITLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x04",

+    "EventName": "ITLB_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x10",

+    "EventName": "ITLB_MISSES.STLB_HIT",

+    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x01",

+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Load misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Load misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x02",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Load misses at all DTLB levels that cause completed page walks",

+    "PublicDescription": "Load misses at all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x04",

+    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x01",

+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x02",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x04",

+    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "Cycles when PMH is busy with page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",

+    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x01",

+    "EventName": "TLB_FLUSH.DTLB_THREAD",

+    "BriefDescription": "DTLB flush attempts of the thread-specific entries",

+    "PublicDescription": "DTLB flush attempts of the thread-specific entries",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x20",

+    "EventName": "TLB_FLUSH.STLB_ANY",

+    "BriefDescription": "STLB flush attempts",

+    "PublicDescription": "STLB flush attempts",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x01",

+    "EventName": "L1D.REPLACEMENT",

+    "BriefDescription": "L1D data line replacements",

+    "PublicDescription": "This event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.  ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x02",

+    "EventName": "L1D.ALLOCATED_IN_M",

+    "BriefDescription": "Allocated L1D data cache lines in M state",

+    "PublicDescription": "Allocated L1D data cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x04",

+    "EventName": "L1D.EVICTION",

+    "BriefDescription": "L1D data cache lines in M state evicted due to replacement",

+    "PublicDescription": "L1D data cache lines in M state evicted due to replacement",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x08",

+    "EventName": "L1D.ALL_M_REPLACEMENT",

+    "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement",

+    "PublicDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING",

+    "BriefDescription": "L1D miss oustandings duration in cycles",

+    "PublicDescription": "L1D miss oustandings duration in cycles",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",

+    "BriefDescription": "Cycles with L1D load Misses outstanding. ",

+    "PublicDescription": "Cycles with L1D load Misses outstanding. ",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x01",

+    "EventName": "LOAD_HIT_PRE.SW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x02",

+    "EventName": "LOAD_HIT_PRE.HW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x02",

+    "EventName": "HW_PRE_REQ.DL1_MISS",

+    "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for ",

+    "PublicDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x01",

+    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "PublicDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x02",

+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1D is locked",

+    "PublicDescription": "Cycles when L1D is locked",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS.DATA_UNKNOWN",

+    "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data",

+    "PublicDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "LD_BLOCKS.STORE_FORWARD",

+    "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",

+    "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS.NO_SR",

+    "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "PublicDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x10",

+    "EventName": "LD_BLOCKS.ALL_BLOCK",

+    "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)",

+    "PublicDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies in MOB due to partial compare",

+    "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline.  The enhanced address check typically has a performance penalty of 5 cycles.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",

+    "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",

+    "PublicDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "MISALIGN_MEM_REF.LOADS",

+    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "MISALIGN_MEM_REF.STORES",

+    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB6",

+    "UMask": "0x01",

+    "EventName": "AGU_BYPASS_CANCEL.COUNT",

+    "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an",

+    "PublicDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",

+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "PublicDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests sent to uncore",

+    "PublicDescription": "Demand Data Read requests sent to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

+    "BriefDescription": "Cacheable and noncachaeble code read requests",

+    "PublicDescription": "Cacheable and noncachaeble code read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",

+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "PublicDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",

+    "BriefDescription": "Demand and prefetch data reads",

+    "PublicDescription": "Demand and prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",

+    "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",

+    "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x01",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",

+    "BriefDescription": "Demand Data Read requests that hit L2 cache",

+    "PublicDescription": "Demand Data Read requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x04",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "RFO requests that hit L2 cache",

+    "PublicDescription": "RFO requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x08",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "RFO requests that miss L2 cache",

+    "PublicDescription": "RFO requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.CODE_RD_HIT",

+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",

+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.CODE_RD_MISS",

+    "BriefDescription": "L2 cache misses when fetching instructions",

+    "PublicDescription": "L2 cache misses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PF_HIT",

+    "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",

+    "PublicDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PF_MISS",

+    "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",

+    "PublicDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x01",

+    "EventName": "L2_STORE_LOCK_RQSTS.MISS",

+    "BriefDescription": "RFOs that miss cache lines",

+    "PublicDescription": "RFOs that miss cache lines",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x04",

+    "EventName": "L2_STORE_LOCK_RQSTS.HIT_E",

+    "BriefDescription": "RFOs that hit cache lines in E state",

+    "PublicDescription": "RFOs that hit cache lines in E state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x08",

+    "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",

+    "BriefDescription": "RFOs that hit cache lines in M state",

+    "PublicDescription": "RFOs that hit cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x0F",

+    "EventName": "L2_STORE_LOCK_RQSTS.ALL",

+    "BriefDescription": "RFOs that access cache lines in any state",

+    "PublicDescription": "RFOs that access cache lines in any state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x01",

+    "EventName": "L2_L1D_WB_RQSTS.MISS",

+    "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",

+    "PublicDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x02",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_S",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in S state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x04",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_E",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x08",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_M",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x0F",

+    "EventName": "L2_L1D_WB_RQSTS.ALL",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x01",

+    "EventName": "L2_TRANS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests that access L2 cache",

+    "PublicDescription": "Demand Data Read requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x02",

+    "EventName": "L2_TRANS.RFO",

+    "BriefDescription": "RFO requests that access L2 cache",

+    "PublicDescription": "RFO requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x04",

+    "EventName": "L2_TRANS.CODE_RD",

+    "BriefDescription": "L2 cache accesses when fetching instructions",

+    "PublicDescription": "L2 cache accesses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x08",

+    "EventName": "L2_TRANS.ALL_PF",

+    "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",

+    "PublicDescription": "L2 or LLC HW prefetches that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANS.L1D_WB",

+    "BriefDescription": "L1D writebacks that access L2 cache",

+    "PublicDescription": "L1D writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANS.L2_FILL",

+    "BriefDescription": "L2 fill requests that access L2 cache",

+    "PublicDescription": "L2 fill requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANS.L2_WB",

+    "BriefDescription": "L2 writebacks that access L2 cache",

+    "PublicDescription": "L2 writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANS.ALL_REQUESTS",

+    "BriefDescription": "Transactions accessing L2 pipe",

+    "PublicDescription": "Transactions accessing L2 pipe",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_IN.I",

+    "BriefDescription": "L2 cache lines in I state filling L2",

+    "PublicDescription": "L2 cache lines in I state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_IN.S",

+    "BriefDescription": "L2 cache lines in S state filling L2",

+    "PublicDescription": "L2 cache lines in S state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_IN.E",

+    "BriefDescription": "L2 cache lines in E state filling L2",

+    "PublicDescription": "L2 cache lines in E state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x07",

+    "EventName": "L2_LINES_IN.ALL",

+    "BriefDescription": "L2 cache lines filling L2",

+    "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by demand",

+    "PublicDescription": "Clean L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by demand",

+    "PublicDescription": "Dirty L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_OUT.PF_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",

+    "PublicDescription": "Clean L2 cache lines evicted by L2 prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x08",

+    "EventName": "L2_LINES_OUT.PF_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",

+    "PublicDescription": "Dirty L2 cache lines evicted by L2 prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x0A",

+    "EventName": "L2_LINES_OUT.DIRTY_ALL",

+    "BriefDescription": "Dirty L2 cache lines filling the L2",

+    "PublicDescription": "Dirty L2 cache lines filling the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Core-originated cacheable demand requests missed LLC",

+    "PublicDescription": "Core-originated cacheable demand requests missed LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",

+    "PublicDescription": "Core-originated cacheable demand requests that refer to LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x10",

+    "EventName": "SQ_MISC.SPLIT_LOCK",

+    "BriefDescription": "Split locks in SQ",

+    "PublicDescription": "Split locks in SQ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",

+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",

+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",

+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 0",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 1",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 4",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 5",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x0C",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",

+    "PublicDescription": "Cycles per thread when load or STA uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x30",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",

+    "PublicDescription": "Cycles per thread when load or STA uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_CYCLES",

+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_OCCUR",

+    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x0C",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",

+    "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2",

+    "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x30",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",

+    "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",

+    "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.PREC_DIST",

+    "BriefDescription": "Instructions retired. (Precise Event - PEBS)",

+    "PublicDescription": "Instructions retired. (Precise Event - PEBS)",

+    "Counter": "1",

+    "CounterHTOff": "1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x03",

+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests",

+    "PublicDescription": "Demand Data Read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x0C",

+    "EventName": "L2_RQSTS.ALL_RFO",

+    "BriefDescription": "RFO requests to L2 cache",

+    "PublicDescription": "RFO requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.ALL_CODE_RD",

+    "BriefDescription": "L2 code requests",

+    "PublicDescription": "L2 code requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.ALL_PF",

+    "BriefDescription": "Requests from L2 hardware prefetchers",

+    "PublicDescription": "Requests from L2 hardware prefetchers",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBF",

+    "UMask": "0x05",

+    "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",

+    "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports",

+    "PublicDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5B",

+    "UMask": "0x0F",

+    "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",

+    "BriefDescription": "Resource stalls2 control structures full for physical registers",

+    "PublicDescription": "Resource stalls2 control structures full for physical registers",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end",

+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end",

+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5B",

+    "UMask": "0x0C",

+    "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",

+    "BriefDescription": "Cycles with either free list is empty",

+    "PublicDescription": "Cycles with either free list is empty",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x0E",

+    "EventName": "RESOURCE_STALLS.MEM_RS",

+    "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized",

+    "PublicDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0xF0",

+    "EventName": "RESOURCE_STALLS.OOO_RSRC",

+    "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER",

+    "PublicDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5B",

+    "UMask": "0x4F",

+    "EventName": "RESOURCE_STALLS2.OOO_RSRC",

+    "BriefDescription": "Resource stalls out of order resources full",

+    "PublicDescription": "Resource stalls out of order resources full",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x0A",

+    "EventName": "RESOURCE_STALLS.LB_SB",

+    "BriefDescription": "Resource stalls due to load or store buffers all being in use",

+    "PublicDescription": "Resource stalls due to load or store buffers all being in use",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES",

+    "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x59",

+    "UMask": "0x20",

+    "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",

+    "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch",

+    "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",

+    "PublicDescription": "Cycles when 1 or more uops were delivered to the by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_STALLS_COUNT",

+    "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles MITE is delivering 4 Uops",

+    "PublicDescription": "Cycles MITE is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles MITE is delivering any Uop",

+    "PublicDescription": "Cycles MITE is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAC",

+    "UMask": "0x0A",

+    "EventName": "DSB_FILL.ALL_CANCEL",

+    "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit",

+    "PublicDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x1E",

+    "EventName": "FP_ASSIST.ANY",

+    "BriefDescription": "Cycles with any input/output SSE or FP assist",

+    "PublicDescription": "Cycles with any input/output SSE or FP assist",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1F",

+    "EventName": "BACLEARS.ANY",

+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xFF",

+    "EventName": "BR_INST_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired  branches",

+    "PublicDescription": "Speculative and retired  branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xFF",

+    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x3c",

+    "EventName": "IDQ.MITE_ALL_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops. ",

+    "PublicDescription": "Cycles without actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_4_UOPS",

+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.COUNT",

+    "BriefDescription": "Number of machine clears (nukes) of any type.",

+    "PublicDescription": "Number of machine clears (nukes) of any type.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_END",

+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_SWITCHES",

+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",

+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6",

+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",

+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",

+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",

+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",

+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",

+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",

+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.FB_FULL",

+    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  }

+,

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch data reads that hit the LLC",

+    "PublicDescription": "Counts all prefetch data reads that hit the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",

+    "BriefDescription": "Counts all writebacks from the core to the LLC",

+    "PublicDescription": "Counts all writebacks from the core to the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10008",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that hit in the LLC",

+    "PublicDescription": "Counts all demand code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that miss the LLC",

+    "PublicDescription": "Counts all demand code reads that miss the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",

+    "PublicDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x600400004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",

+    "PublicDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67f800004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",

+    "PublicDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x87f820004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "PublicDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc00004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data reads that hit in the LLC",

+    "PublicDescription": "Counts all demand data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",

+    "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",

+    "PublicDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67fc00001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts demand data reads that miss in the LLC",

+    "PublicDescription": "Counts demand data reads that miss in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",

+    "PublicDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x600400001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",

+    "PublicDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67f800001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",

+    "PublicDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x87f820001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "PublicDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc00001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",

+    "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "PublicDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x803c8000",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",

+    "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",

+    "PublicDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x23ffc08000",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67fc00010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x600400010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x67f800010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x87f820010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x107fc00010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fffc20080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",

+    "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",

+    "PublicDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10400",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",

+    "BriefDescription": "Counts non-temporal stores",

+    "PublicDescription": "Counts non-temporal stores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10800",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data reads",

+    "PublicDescription": "Counts all demand data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand rfo's",

+    "PublicDescription": "Counts all demand rfo's",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads",

+    "PublicDescription": "Counts all demand code reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010008",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads",

+    "PublicDescription": "Counts all demand & prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x000105B3",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch prefetch RFOs",

+    "PublicDescription": "Counts all demand & prefetch prefetch RFOs",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",

+    "PublicDescription": "Counts all data/code/rfo references (demand & prefetch)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x000107F7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",

+    "PublicDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x600400077",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",

+    "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",

+    "PublicDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3FFFC20077",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",

+    "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",

+    "PublicDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x187FC20077",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/JKT/Jaketown_core_V18.tsv b/x86data/perfmon_data/JKT/Jaketown_core_V18.tsv
new file mode 100644
index 0000000..2b539a3
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_core_V18.tsv
@@ -0,0 +1,289 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family Based on the Sandy Bridge-EP Microarchitecture - V18
+# 8/16/2015 9:39:33 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state.	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	null
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	null
+0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x88	BR_MISP_EXEC.TAKEN_RETURN_NEAR	Taken speculative and retired mispredicted indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x90	BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired mispredicted direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xD0	BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired mispredicted direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAE	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x80	0x02	ICACHE.MISSES	Instruction cache, streaming buffer and victim cache misses	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xA8	0x01	LSD.UOPS	Number of Uops delivered by the LSD. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x87	0x04	ILD_STALL.IQ_FULL	Stall cycles because IQ is full	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x17	0x01	INSTS_WRITTEN_TO_IQ.INSTS	Valid instructions written to IQ per cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	null
+0xAB	0x01	DSB2MITE_SWITCHES.COUNT	Decode Stream Buffer (DSB)-to-MITE switches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAC	0x02	DSB_FILL.OTHER_CANCEL	Cases of cancelling valid DSB fill not because of exceeding way limit	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAC	0x08	DSB_FILL.EXCEED_DSB_LINES	Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0D	0x40	INT_MISC.RAT_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x59	0x20	PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP	Increments the number of flags-merge uops in flight each cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x59	0x40	PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW	Cycles with at least one slow LEA uop being allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x59	0x80	PARTIAL_RAT_STALLS.MUL_SINGLE_UOP	Multiply packed/scalar single precision uops allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x02	RESOURCE_STALLS.LB	Counts the cycles of stall due to lack of load buffers.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5B	0x40	RESOURCE_STALLS2.BOB_FULL	Cycles when Allocator is stalled if BOB is full and new branch needs it	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	1	0	0	1	0	0	null
+0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	null
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	null
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	null
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. (Precise Event - PEBS)	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	null
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x02	BR_MISP_RETIRED.NEAR_CALL	Direct and indirect mispredicted near call instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC5	0x10	BR_MISP_RETIRED.NOT_TAKEN	Mispredicted not taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x20	BR_MISP_RETIRED.TAKEN	Mispredicted taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. (Precise Event - PEBS)	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	null
+0xC1	0x02	OTHER_ASSISTS.ITLB_MISS_RETIRED	Retired instructions experiencing ITLB misses. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x08	OTHER_ASSISTS.AVX_STORE	Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x10	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x20	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4 	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32	3	3	100007	0x3F6	0x20	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	null
+0xCD	0x02	MEM_TRANS_RETIRED.PRECISE_STORE	Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS)	3	3	2000003	0	0	1	0	0	0	0	2	1	null
+0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	null
+0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x04	MEM_LOAD_UOPS_RETIRED.LLC_HIT	Retired load uops which data sources were data hits in LLC without snoops required. 	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	0	0	null
+0xD1	0x20	MEM_LOAD_UOPS_RETIRED.LLC_MISS	Miss in last-level (L3) cache. Excludes Unknown data-source.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD2	0x01	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	0	0	null
+0xD2	0x02	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	0	0	null
+0xD2	0x04	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared LLC. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	0	0	null
+0xD2	0x08	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in LLC without snoops required. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	0	0	null
+0xD3	0x01	MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM	Data from local DRAM either Snoop not needed or Snoop Miss (RspI)	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0xD3	0x04	MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM	Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	0	0	null
+0x14	0x01	ARITH.FPU_DIV_ACTIVE	Cycles when divider is busy executing divide operations	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x14	0x01	ARITH.FPU_DIV	Divide operations executed	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	null
+0x10	0x01	FP_COMP_OPS_EXE.X87	Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x10	FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE	Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x20	FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE	Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x40	FP_COMP_OPS_EXE.SSE_PACKED_SINGLE	Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x80	FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE	Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x11	0x01	SIMD_FP_256.PACKED_SINGLE	number of GSSE-256 Computational FP single precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x11	0x02	SIMD_FP_256.PACKED_DOUBLE	number of AVX-256 Computational FP double precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_DISPATCHED.THREAD	Uops dispatched per thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_DISPATCHED.CORE	Uops dispatched from any thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are dispatched to port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are dispatched to port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are dispatched to port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are dispatched to port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_DISPATCH	Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.	2	2	2000003	0	0	0	2	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.	2	2	2000003	0	0	0	6	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	null
+0x4F	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x02	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x04	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x85	0x10	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x01	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Load misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED	Load misses at all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x04	DTLB_LOAD_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x08	0x10	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x04	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x49	0x10	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xBD	0x01	TLB_FLUSH.DTLB_THREAD	DTLB flush attempts of the thread-specific entries	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xBD	0x20	TLB_FLUSH.STLB_ANY	STLB flush attempts	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x51	0x02	L1D.ALLOCATED_IN_M	Allocated L1D data cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x51	0x04	L1D.EVICTION	L1D data cache lines in M state evicted due to replacement	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x51	0x08	L1D.ALL_M_REPLACEMENT	Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	2	2	2000003	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding. 	2	2	2000003	0	0	0	1	0	0	0	0	0	null
+0x4C	0x01	LOAD_HIT_PRE.SW_PF	Not software-prefetch load dispatches that hit FB allocated for software prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4C	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4E	0x02	HW_PRE_REQ.DL1_MISS	Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x03	0x01	LD_BLOCKS.DATA_UNKNOWN	Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	Cases when loads get true Block-on-Store blocking code preventing store forwarding	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x03	0x08	LD_BLOCKS.NO_SR	This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x03	0x10	LD_BLOCKS.ALL_BLOCK	Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x07	0x08	LD_BLOCKS_PARTIAL.ALL_STA_BLOCK	This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB6	0x01	AGU_BYPASS_CANCEL.COUNT	This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xB0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Cases when offcore requests buffer cannot take more entries for core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x24	0x01	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x04	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x08	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x10	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x20	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x40	L2_RQSTS.PF_HIT	Requests from the L2 hardware prefetchers that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x80	L2_RQSTS.PF_MISS	Requests from the L2 hardware prefetchers that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x01	L2_STORE_LOCK_RQSTS.MISS	RFOs that miss cache lines	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x04	L2_STORE_LOCK_RQSTS.HIT_E	RFOs that hit cache lines in E state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x08	L2_STORE_LOCK_RQSTS.HIT_M	RFOs that hit cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x0F	L2_STORE_LOCK_RQSTS.ALL	RFOs that access cache lines in any state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x01	L2_L1D_WB_RQSTS.MISS	Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x02	L2_L1D_WB_RQSTS.HIT_S	Not rejected writebacks from L1D to L2 cache lines in S state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x04	L2_L1D_WB_RQSTS.HIT_E	Not rejected writebacks from L1D to L2 cache lines in E state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x08	L2_L1D_WB_RQSTS.HIT_M	Not rejected writebacks from L1D to L2 cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x0F	L2_L1D_WB_RQSTS.ALL	Not rejected writebacks from L1D to L2 cache lines in any state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x08	L2_TRANS.ALL_PF	L2 or LLC HW prefetches that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x01	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x02	L2_LINES_OUT.DEMAND_DIRTY	Dirty L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x04	L2_LINES_OUT.PF_CLEAN	Clean L2 cache lines evicted by L2 prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x08	L2_LINES_OUT.PF_DIRTY	Dirty L2 cache lines evicted by L2 prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x0A	L2_LINES_OUT.DIRTY_ALL	Dirty L2 cache lines filling the L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed LLC	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to LLC	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF4	0x10	SQ_MISC.SPLIT_LOCK	Split locks in SQ	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3). 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0_CORE	Cycles per core when uops are dispatched to port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1_CORE	Cycles per core when uops are dispatched to port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4_CORE	Cycles per core when uops are dispatched to port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5_CORE	Cycles per core when uops are dispatched to port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when load or STA uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when load or STA uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2_CORE	Cycles per core when load or STA uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3_CORE	Cycles per core when load or STA uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xC0	0x01	INST_RETIRED.PREC_DIST	Instructions retired. (Precise Event - PEBS)	1	1	2000003	0	0	1	0	0	0	0	2	0	null
+0x24	0x03	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x0C	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x30	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0xC0	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xBF	0x05	L1D_BLOCKS.BANK_CONFLICT_CYCLES	Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	0	0	0	null
+0x5B	0x0F	RESOURCE_STALLS2.ALL_PRF_CONTROL	Resource stalls2 control structures full for physical registers	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	null
+0x5B	0x0C	RESOURCE_STALLS2.ALL_FL_EMPTY	Cycles with either free list is empty	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x0E	RESOURCE_STALLS.MEM_RS	Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0xF0	RESOURCE_STALLS.OOO_RSRC	Resource stalls due to Rob being full, FCSW, MXCSR and OTHER	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5B	0x4F	RESOURCE_STALLS2.OOO_RSRC	Resource stalls out of order resources full	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x0A	RESOURCE_STALLS.LB_SB	Resource stalls due to load or store buffers all being in use	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x59	0x20	PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES	Performance sensitive flags-merging uops added by Sandy Bridge u-arch	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE	Cycles when 1 or more uops were delivered to the by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	1	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_STALLS_COUNT	Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xAC	0x0A	DSB_FILL.ALL_CANCEL	Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	null
+0xE6	0x1F	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO	Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.CORE_STALL_CYCLES	Cycles without actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0xc3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	1	0	0	null
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	1	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	2	2	2000003	0	0	0	1	0	1	0	0	0	null
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/JKT/Jaketown_matrix_V18.json b/x86data/perfmon_data/JKT/Jaketown_matrix_V18.json
new file mode 100644
index 0000000..d625e9a
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_matrix_V18.json
@@ -0,0 +1,191 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand data reads"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand data writes (RFOs)"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand code reads"
+  },
+  {
+    "MATRIX_REQUEST": "COREWB",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000008",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts core writebacks due to L2 evictions or L1 writeback requests"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000010",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to L2) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000020",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to L2) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000040",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000200",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "OTHER",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any other requests"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000090",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000120",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000240",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000091",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000122",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000244",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_READS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x00000003f7",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all data/code/rfo reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_REQUESTS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008fff",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all requests"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3f803c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.NO_SNOOP_NEEDED",
+    "MATRIX_VALUE": "0x01003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.SNOOP_MISS",
+    "MATRIX_VALUE": "0x02003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoops sent to sibling cores return clean response"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+    "MATRIX_VALUE": "0x04003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.HITM_OTHER_CORE",
+    "MATRIX_VALUE": "0x10003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3fffc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss in the LLC"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.LOCAL_DRAM",
+    "MATRIX_VALUE": "0x0600400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the LLC and the data returned from local dram"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_DRAM",
+    "MATRIX_VALUE": "0x067fc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the LLC and the data returned from local or remote dram"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/JKT/Jaketown_matrix_V18.tsv b/x86data/perfmon_data/JKT/Jaketown_matrix_V18.tsv
new file mode 100644
index 0000000..88a0489
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_matrix_V18.tsv
@@ -0,0 +1,31 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family Based on the Sandy Bridge-EP Microarchitecture - V18
+# 7/28/2015 3:43:43 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand data reads
+DEMAND_RFO	Null	0x0002	0,1	Counts all demand data writes (RFOs)
+DEMAND_CODE_RD	Null	0x0004	0,1	Counts all demand code reads
+COREWB	Null	0x0008	0,1	Counts core writebacks due to L2 evictions or L1 writeback requests
+PF_L2_DATA_RD	Null	0x0010	0,1	Counts prefetch (that bring data to L2) data reads
+PF_L2_RFO	Null	0x0020	0,1	Counts all prefetch (that bring data to L2) RFOs
+PF_L2_CODE_RD	Null	0x0040	0,1	Counts all prefetch (that bring data to LLC only) code reads
+PF_LLC_DATA_RD	Null	0x0080	0,1	Counts all prefetch (that bring data to LLC only) data reads
+PF_LLC_RFO	Null	0x0100	0,1	Counts all prefetch (that bring data to LLC only) RFOs
+PF_LLC_CODE_RD	Null	0x0200	0,1	Counts prefetch (that bring data to LLC only) code reads
+OTHER	Null	0x8000	0,1	Counts any other requests
+ALL_PF_DATA_RD	Null	0x0090	0,1	Counts all prefetch data reads
+ALL_PF_RFO	Null	0x0120	0,1	Counts prefetch RFOs
+ALL_PF_CODE_RD	Null	0x0240	0,1	Counts all prefetch code reads
+ALL_DATA_RD	Null	0x0091	0,1	Counts all demand & prefetch data reads
+ALL_RFO	Null	0x0122	0,1	Counts all demand & prefetch RFOs
+ALL_CODE_RD	Null	0x0244	0,1	Counts all demand & prefetch code reads
+ALL_READS	Null	0x03f7	0,1	Counts all data/code/rfo reads (demand & prefetch)
+ALL_REQUESTS	Null	0x8fff	0,1	Counts all requests
+Null	LLC_HIT.ANY_RESPONSE	0x3f803c	0,1	hit in the LLC
+Null	LLC_HIT.NO_SNOOP_NEEDED	0x01003c	0,1	hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
+Null	LLC_HIT.SNOOP_MISS	0x02003c	0,1	hit in the LLC and the snoops sent to sibling cores return clean response
+Null	LLC_HIT.HIT_OTHER_CORE_NO_FWD	0x04003c	0,1	hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
+Null	LLC_HIT.HITM_OTHER_CORE	0x10003c	0,1	hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
+Null	LLC_MISS.ANY_RESPONSE	0x3fffc0	0,1	miss in the LLC
+Null	LLC_MISS.LOCAL_DRAM	0x060040	0,1	miss the LLC and the data returned from local dram
+Null	LLC_MISS.ANY_DRAM	0x067fc0	0,1	miss the LLC and the data returned from local or remote dram
diff --git a/x86data/perfmon_data/JKT/Jaketown_matrix_bit_definitions_V18.json b/x86data/perfmon_data/JKT/Jaketown_matrix_bit_definitions_V18.json
new file mode 100644
index 0000000..0851e27
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_matrix_bit_definitions_V18.json
@@ -0,0 +1,268 @@
+[
+  {
+    "BitName": "DEMAND_DATA_RD",
+    "BitIndex": "0",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_RFO",
+    "BitIndex": "1",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_CODE_RD",
+    "BitIndex": "2",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "COREWB",
+    "BitIndex": "3",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_DATA_RD",
+    "BitIndex": "4",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_RFO",
+    "BitIndex": "5",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_CODE_RD",
+    "BitIndex": "6",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_DATA_RD",
+    "BitIndex": "7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_RFO",
+    "BitIndex": "8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_CODE_RD",
+    "BitIndex": "9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SPLIT_LOCK_UC_LOCK",
+    "BitIndex": "10",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "STREAMING_STORES",
+    "BitIndex": "11",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "OTHER",
+    "BitIndex": "15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_DATA_RD",
+    "BitIndex": "4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_RFO",
+    "BitIndex": "5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_CODE_RD",
+    "BitIndex": "6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_DATA_RD",
+    "BitIndex": "0,4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_RFO",
+    "BitIndex": "1,5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_CODE_RD",
+    "BitIndex": "2,6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_READS",
+    "BitIndex": "0,1,2,4,5,6,7,8,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_REQUESTS",
+    "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_RESPONSE",
+    "BitIndex": "16",
+    "Type": "2",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SUPPLIER_NONE",
+    "BitIndex": "17",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_M",
+    "BitIndex": "18",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_E",
+    "BitIndex": "19",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_S",
+    "BitIndex": "20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_F",
+    "BitIndex": "21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT",
+    "BitIndex": "18,19,20,21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_LOCAL_DRAM",
+    "BitIndex": "22",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_REMOTE_DRAM",
+    "BitIndex": "22,23,24,25,26,27,28,29,30",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NONE",
+    "BitIndex": "31",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NOT_NEEDED",
+    "BitIndex": "32",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_MISS",
+    "BitIndex": "33",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_NO_FWD",
+    "BitIndex": "34",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_WITH_FWD",
+    "BitIndex": "35",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "18,19,20,21"
+  },
+  {
+    "BitName": "SNOOP_HITM",
+    "BitIndex": "36",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NON_DRAM",
+    "BitIndex": "37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_SNOOP",
+    "BitIndex": "31,32,33,34,35,36,37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/JKT/Jaketown_matrix_bit_definitions_V18.tsv b/x86data/perfmon_data/JKT/Jaketown_matrix_bit_definitions_V18.tsv
new file mode 100644
index 0000000..b7e16c8
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_matrix_bit_definitions_V18.tsv
@@ -0,0 +1,42 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family Based on the Sandy Bridge-EP Microarchitecture - V18
+# 7/28/2015 3:43:44 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	Type	MATRIX_REG	BitsNotCombinedWith
+DEMAND_DATA_RD	0	1	0,1	Null
+DEMAND_RFO	1	1	0,1	Null
+DEMAND_CODE_RD	2	1	0,1	Null
+COREWB	3	1	0,1	Null
+PF_L2_DATA_RD	4	1	0,1	Null
+PF_L2_RFO	5	1	0,1	Null
+PF_L2_CODE_RD	6	1	0,1	Null
+PF_LLC_DATA_RD	7	1	0,1	Null
+PF_LLC_RFO	8	1	0,1	Null
+PF_LLC_CODE_RD	9	1	0,1	Null
+SPLIT_LOCK_UC_LOCK	10	1	0,1	Null
+STREAMING_STORES	11	1	0,1	Null
+OTHER	15	1	0,1	Null
+ALL_PF_DATA_RD	4,7	1	0,1	Null
+ALL_PF_RFO	5,8	1	0,1	Null
+ALL_PF_CODE_RD	6,9	1	0,1	Null
+ALL_DATA_RD	0,4,7	1	0,1	Null
+ALL_RFO	1,5,8	1	0,1	Null
+ALL_CODE_RD	2,6,9	1	0,1	Null
+ALL_READS	0,1,2,4,5,6,7,8,9	1	0,1	Null
+ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	0,1	Null
+ANY_RESPONSE	16	2	0,1	Null
+SUPPLIER_NONE	17	3	0,1	Null
+LLC_HIT_M	18	3	0,1	Null
+LLC_HIT_E	19	3	0,1	Null
+LLC_HIT_S	20	3	0,1	Null
+LLC_HIT_F	21	3	0,1	Null
+LLC_HIT	18,19,20,21	3	0,1	Null
+L3_MISS_LOCAL_DRAM	22	3	0,1	Null
+L3_MISS_REMOTE_DRAM	22,23,24,25,26,27,28,29,30	3	0,1	Null
+SNOOP_NONE	31	4	0,1	Null
+SNOOP_NOT_NEEDED	32	4	0,1	Null
+SNOOP_MISS	33	4	0,1	Null
+SNOOP_HIT_NO_FWD	34	4	0,1	Null
+SNOOP_HIT_WITH_FWD	35	4	0,1	18,19,20,21
+SNOOP_HITM	36	4	0,1	Null
+SNOOP_NON_DRAM	37	4	0,1	Null
+ANY_SNOOP	31,32,33,34,35,36,37	4	0,1	Null
diff --git a/x86data/perfmon_data/JKT/Jaketown_offcore_V18.tsv b/x86data/perfmon_data/JKT/Jaketown_offcore_V18.tsv
new file mode 100644
index 0000000..07d782d
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_offcore_V18.tsv
@@ -0,0 +1,140 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family Based on the Sandy Bridge-EP Microarchitecture - V18
+# 7/28/2015 3:43:43 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE_0	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC	0	0	100003	0x1a6	0x3f803c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE_0	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED_0	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS_0	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCES.ANY_RESPONSE_0	Counts all data/code/rfo reads (demand & prefetch) that reference the LLC	0	0	100003	0x1a6	0x103F7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_0	Counts all writebacks from the core to the LLC	0	0	100003	0x1a6	0x10008	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE_0	Counts all demand code reads that miss the LLC	0	0	100003	0x1a6	0x3fffc20004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM_0	Counts all demand code reads that miss the LLC  and the data returned from local dram	0	0	100003	0x1a6	0x600400004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM_0	Counts all demand code reads that miss the LLC  and the data returned from remote dram	0	0	100003	0x1a6	0x67f800004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD_0	Counts all demand code reads that miss the LLC  and the data forwarded from remote cache	0	0	100003	0x1a6	0x87f820004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM_0	Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	0	0	100003	0x1a6	0x107fc00004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response	0	0	100003	0x1a6	0x2003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM_0	Counts demand data reads that miss the LLC  and the data returned from remote & local dram	0	0	100003	0x1a6	0x67fc00001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE_0	Counts demand data reads that miss in the LLC	0	0	100003	0x1a6	0x3fffc20001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM_0	Counts demand data reads that miss the LLC  and the data returned from local dram	0	0	100003	0x1a6	0x600400001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM_0	Counts demand data reads that miss the LLC  and the data returned from remote dram	0	0	100003	0x1a6	0x67f800001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_0	Counts demand data reads that miss the LLC  and the data forwarded from remote cache	0	0	100003	0x1a6	0x87f820001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM_0	Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	0	0	100003	0x1a6	0x107fc00001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.OTHER.LRU_HINTS_0	Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches	0	0	100003	0x1a6	0x803c8000	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC_0	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses	0	0	100003	0x1a6	0x23ffc08000	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to L2) code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE_0	Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram	0	0	100003	0x1a6	0x3fffc20040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM_0	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram	0	0	100003	0x1a6	0x67fc00010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE_0	Counts prefetch (that bring data to L2) data reads that miss in the LLC	0	0	100003	0x1a6	0x3fffc20010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM_0	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram	0	0	100003	0x1a6	0x600400010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM_0	Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram	0	0	100003	0x1a6	0x67f800010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_0	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache	0	0	100003	0x1a6	0x87f820010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM_0	Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	0	0	100003	0x1a6	0x107fc00010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE_0	Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC	0	0	100003	0x1a6	0x3fffc20200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE_0	Counts prefetch (that bring data to LLC only) data reads that miss in the LLC	0	0	100003	0x1a6	0x3fffc20080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_0	Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address	0	0	100003	0x1a6	0x10400	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_0	Counts non-temporal stores	0	0	100003	0x1a6	0x10800	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response	3	3	100003	0x1a7	0x2003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch data reads that hit the LLC	3	3	100003	0x1a7	0x3f803c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response	3	3	100003	0x1a7	0x2003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC	3	3	100003	0x1a7	0x3f803c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response	3	3	100003	0x1a7	0x2003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCE_ANY.ANY_RESPONSE_1	Counts all data/code/rfo reads (demand & prefetch) that reference the LLC	3	3	100003	0x1a7	0x103F7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_1	Counts all writebacks from the core to the LLC	3	3	100003	0x1a7	0x10008	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE_1	Counts all demand code reads that miss the LLC	3	3	100003	0x1a7	0x3fffc20004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM_1	Counts all demand code reads that miss the LLC  and the data returned from local dram	3	3	100003	0x1a7	0x600400004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM_1	Counts all demand code reads that miss the LLC  and the data returned from remote dram	3	3	100003	0x1a7	0x67f800004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD_1	Counts all demand code reads that miss the LLC  and the data forwarded from remote cache	3	3	100003	0x1a7	0x87f820004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM_1	Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	3	3	100003	0x1a7	0x107fc00004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response	3	3	100003	0x1a7	0x2003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM_1	Counts demand data reads that miss the LLC  and the data returned from remote & local dram	3	3	100003	0x1a7	0x67fc00001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE_1	Counts demand data reads that miss in the LLC	3	3	100003	0x1a7	0x3fffc20001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM_1	Counts demand data reads that miss the LLC  and the data returned from local dram	3	3	100003	0x1a7	0x600400001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM_1	Counts demand data reads that miss the LLC  and the data returned from remote dram	3	3	100003	0x1a7	0x67f800001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_1	Counts demand data reads that miss the LLC  and the data forwarded from remote cache	3	3	100003	0x1a7	0x87f820001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM_1	Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	3	3	100003	0x1a7	0x107fc00001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.LRU_HINTS_1	Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches	3	3	100003	0x1a7	0x803c8000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC_1	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses	3	3	100003	0x1a7	0x23ffc08000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to L2) code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE_1	Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram	3	3	100003	0x1a7	0x3fffc20040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM_1	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram	3	3	100003	0x1a7	0x67fc00010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE_1	Counts prefetch (that bring data to L2) data reads that miss in the LLC	3	3	100003	0x1a7	0x3fffc20010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM_1	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram	3	3	100003	0x1a7	0x600400010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM_1	Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram	3	3	100003	0x1a7	0x67f800010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_1	Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache	3	3	100003	0x1a7	0x87f820010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM_1	Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there	3	3	100003	0x1a7	0x107fc00010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE_1	Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC	3	3	100003	0x1a7	0x3fffc20200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x3fffc20080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_1	Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address	3	3	100003	0x1a7	0x10400	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_1	Counts non-temporal stores	3	3	100003	0x1a7	0x10800	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE_0	Counts all demand data reads	0	0	100003	0x1A6	0x00010001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE_0	Counts all demand rfo's	0	0	100003	0x1A6	0x00010002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE_0	Counts all demand code reads	0	0	100003	0x1A6	0x00010004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1A6	0x00010008	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE_0	Counts all demand & prefetch data reads	0	0	100003	0x1A6	0x000105B3	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE_0	Counts all demand & prefetch prefetch RFOs	0	0	100003	0x1A6	0x00010122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE_0	Counts all data/code/rfo references (demand & prefetch)	0	0	100003	0x1A6	0x000107F7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE_1	Counts all demand data reads	3	3	100003	0x1A7	0x00010001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE_1	Counts all demand rfo's	3	3	100003	0x1A7	0x00010002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE_1	Counts all demand code reads	3	3	100003	0x1A7	0x00010004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1A7	0x00010008	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE_1	Counts all demand & prefetch data reads	3	3	100003	0x1A7	0x000105B3	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE_1	Counts all demand & prefetch prefetch RFOs	3	3	100003	0x1A7	0x00010122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE_1	Counts all data/code/rfo references (demand & prefetch)	3	3	100003	0x1A7	0x000107F7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM_0	Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.	3	3	100003	0x1A6	0x600400077	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM_1	Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.	0	0	100003	0x1a7	0x600400077	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE_0	This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.	3	3	100003	0x1A6	0x3FFFC20077	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE_1	This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.	0	0	100003	0x1a7	0x3FFFC20077	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD_0	This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.	3	3	100003	0x1A6	0x187FC20077	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD_1	This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.	0	0	100003	0x1a7	0x187FC20077	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/JKT/Jaketown_uncore_V18.json b/x86data/perfmon_data/JKT/Jaketown_uncore_V18.json
new file mode 100644
index 0000000..69b8879
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_uncore_V18.json
@@ -0,0 +1,6482 @@
+[
+  {
+    "Unit": "CBO",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_C_CLOCKTICKS",
+    "BriefDescription": "Uncore Clocks",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1f",
+    "UMask": "0x0",
+    "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+    "BriefDescription": "Counter 0 Occupancy",
+    "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+    "Counter": "1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x21",
+    "UMask": "0x0",
+    "EventName": "UNC_C_ISMQ_DRD_MISS_OCC",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x3",
+    "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+    "BriefDescription": "Cache Lookups; Data Read Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[22:18]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x41",
+    "EventName": "UNC_C_LLC_LOOKUP.NID",
+    "BriefDescription": "Cache Lookups; RTID",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[22:18], CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x9",
+    "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+    "BriefDescription": "Cache Lookups; External Snoop Request",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[22:18]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x5",
+    "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+    "BriefDescription": "Cache Lookups; Write Requests",
+    "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[22:18]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x2",
+    "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+    "BriefDescription": "Lines Victimized; Lines in E state",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x8",
+    "EventName": "UNC_C_LLC_VICTIMS.MISS",
+    "BriefDescription": "Lines Victimized",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x1",
+    "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+    "BriefDescription": "Lines Victimized; Lines in M state",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x40",
+    "EventName": "UNC_C_LLC_VICTIMS.NID",
+    "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x37",
+    "UMask": "0x4",
+    "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+    "BriefDescription": "Lines Victimized; Lines in S State",
+    "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x8",
+    "EventName": "UNC_C_MISC.RFO_HIT_S",
+    "BriefDescription": "Cbo Misc; RFO HitS",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x1",
+    "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+    "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x4",
+    "EventName": "UNC_C_MISC.STARTED",
+    "BriefDescription": "Cbo Misc",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x39",
+    "UMask": "0x2",
+    "EventName": "UNC_C_MISC.WC_ALIASING",
+    "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+    "PublicDescription": "Miscellaneous events in the Cbo.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
+    "BriefDescription": "AD Ring In Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
+    "BriefDescription": "AD Ring In Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+    "BriefDescription": "AD Ring In Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1b",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_AD_USED.UP_ODD",
+    "BriefDescription": "AD Ring In Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
+    "BriefDescription": "AK Ring In Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
+    "BriefDescription": "AK Ring In Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
+    "BriefDescription": "AK Ring In Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1c",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_AK_USED.UP_ODD",
+    "BriefDescription": "AK Ring In Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
+    "BriefDescription": "BL Ring in Use; Down and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
+    "BriefDescription": "BL Ring in Use; Down and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
+    "BriefDescription": "BL Ring in Use; Up and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1d",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BL_USED.UP_ODD",
+    "BriefDescription": "BL Ring in Use; Up and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_BOUNCES.AK_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_BOUNCES.BL_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x5",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_BOUNCES.IV_CORE",
+    "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x1e",
+    "UMask": "0xf",
+    "EventName": "UNC_C_RING_IV_USED.ANY",
+    "BriefDescription": "BL Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in JKT.  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.",
+    "Counter": "2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RING_SINK_STARVED.AD_CACHE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RING_SINK_STARVED.AK_CORE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RING_SINK_STARVED.BL_CORE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x6",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RING_SINK_STARVED.IV_CORE",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_C_RING_SRC_THRTL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x12",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+    "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
+    "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_INSERTS.IPQ",
+    "BriefDescription": "Ingress Allocations; IPQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ",
+    "BriefDescription": "Ingress Allocations; IRQ",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED",
+    "BriefDescription": "Ingress Allocations; IRQ Rejected",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_INSERTS.VFIFO",
+    "BriefDescription": "Ingress Allocations; VFIFO",
+    "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x14",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
+    "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
+    "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
+    "BriefDescription": "Probe Queue Retries; Address Conflict",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
+    "BriefDescription": "Probe Queue Retries; Any Reject",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
+    "BriefDescription": "Probe Queue Retries; No Egress Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x31",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "Probe Queue Retries; No QPI Credits",
+    "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+    "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
+    "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
+    "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x32",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+    "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
+    "BriefDescription": "ISMQ Retries; Any Reject",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
+    "BriefDescription": "ISMQ Retries; No Egress Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x20",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+    "BriefDescription": "ISMQ Retries; No IIO Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+    "BriefDescription": "ISMQ Retries; No QPI Credits",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x33",
+    "UMask": "0x8",
+    "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+    "BriefDescription": "ISMQ Retries; No RTIDs",
+    "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x4",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+    "BriefDescription": "Ingress Occupancy; IPQ",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
+    "BriefDescription": "Ingress Occupancy; IRQ",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJECTED",
+    "BriefDescription": "Ingress Occupancy; IRQ Rejected",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_C_RxR_OCCUPANCY.VFIFO",
+    "BriefDescription": "Ingress Occupancy; VFIFO",
+    "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TOR_INSERTS.EVICTION",
+    "BriefDescription": "TOR Inserts; Evictions",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0xa",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_ALL",
+    "BriefDescription": "TOR Inserts; Miss All",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x3",
+    "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
+    "BriefDescription": "TOR Inserts; Miss Opcode Match",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[31:23]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x48",
+    "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
+    "BriefDescription": "TOR Inserts; NID Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x44",
+    "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
+    "BriefDescription": "TOR Inserts; NID Matched Evictions",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x4a",
+    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+    "BriefDescription": "TOR Inserts; NID Matched Miss All",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x43",
+    "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+    "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[31:23], CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x41",
+    "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
+    "BriefDescription": "TOR Inserts; NID and Opcode Matched",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[31:23], CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x50",
+    "EventName": "UNC_C_TOR_INSERTS.NID_WB",
+    "BriefDescription": "TOR Inserts; NID Matched Writebacks",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TOR_INSERTS.OPCODE",
+    "BriefDescription": "TOR Inserts; Opcode Match",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[31:23]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x35",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TOR_INSERTS.WB",
+    "BriefDescription": "TOR Inserts; Writebacks",
+    "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+    "BriefDescription": "TOR Occupancy; Any",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
+    "BriefDescription": "TOR Occupancy; Evictions",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0xa",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
+    "BriefDescription": "TOR Occupancy; Miss All",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x3",
+    "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
+    "BriefDescription": "TOR Occupancy; Miss Opcode Match",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[31:23]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x48",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+    "BriefDescription": "TOR Occupancy; NID Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x44",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
+    "BriefDescription": "TOR Occupancy; NID Matched Evictions",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x4a",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
+    "BriefDescription": "TOR Occupancy; NID Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x43",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
+    "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[31:23], CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x41",
+    "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+    "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[31:23], CBoFilter[17:10]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+    "BriefDescription": "TOR Occupancy; Opcode Match",
+    "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "CBoFilter[31:23]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_C_TxR_ADS_USED",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
+    "BriefDescription": "Egress Allocations; AD - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
+    "BriefDescription": "Egress Allocations; AD - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
+    "BriefDescription": "Egress Allocations; AK - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x20",
+    "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
+    "BriefDescription": "Egress Allocations; AK - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
+    "BriefDescription": "Egress Allocations; BL - Cacheno",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x40",
+    "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
+    "BriefDescription": "Egress Allocations; BL - Corebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
+    "BriefDescription": "Egress Allocations; IV - Cachebo",
+    "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_C_TxR_STARVED.AK",
+    "BriefDescription": "Injection Starvation; Onto AK Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x3",
+    "UMask": "0x4",
+    "EventName": "UNC_C_TxR_STARVED.BL",
+    "BriefDescription": "Injection Starvation; Onto BL Ring",
+    "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CLOCKTICKS",
+    "BriefDescription": "pclk Cycles",
+    "PublicDescription": "The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x8",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xa",
+    "UMask": "0x0",
+    "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
+    "BriefDescription": "Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1e",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE0",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1f",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE1",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x20",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE2",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x21",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE3",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x22",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE4",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x23",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE5",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x24",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE6",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x25",
+    "UMask": "0x0",
+    "EventName": "UNC_P_DEMOTIONS_CORE7",
+    "BriefDescription": "Core C State Demotions",
+    "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xb",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND0_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[7:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xc",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND1_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[15:8]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xd",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND2_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[23:16]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xe",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_BAND3_CYCLES",
+    "BriefDescription": "Frequency Residency",
+    "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "PCUFilter[31:24]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES",
+    "BriefDescription": "Current Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when current is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
+    "BriefDescription": "Thermal Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
+    "BriefDescription": "OS Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
+    "BriefDescription": "Power Strongest Upper Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
+    "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES",
+    "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles",
+    "PublicDescription": "Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_P_FREQ_TRANS_CYCLES",
+    "BriefDescription": "Cycles spent changing Frequency",
+    "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2f",
+    "UMask": "0x0",
+    "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
+    "BriefDescription": "Memory Phase Shedding Cycles",
+    "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0x40",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+    "BriefDescription": "Number of cores in C0",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0x80",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+    "BriefDescription": "Number of cores in C0",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x80",
+    "UMask": "0xc0",
+    "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+    "BriefDescription": "Number of cores in C0",
+    "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xa",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+    "BriefDescription": "External Prochot",
+    "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+    "BriefDescription": "Internal Prochot",
+    "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0xb",
+    "UMask": "0x0",
+    "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+    "BriefDescription": "Total Core C State Transition Cycles",
+    "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x3",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE",
+    "BriefDescription": "Cycles Changing Voltage",
+    "PublicDescription": "Counts the number of cycles when the system is changing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.  This event is calculated by or'ing together the increasing and decreasing events.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x2",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE",
+    "BriefDescription": "Cycles Decreasing Voltage",
+    "PublicDescription": "Counts the number of cycles when the system is decreasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE",
+    "BriefDescription": "Cycles Increasing Voltage",
+    "PublicDescription": "Counts the number of cycles when the system is increasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "PCU",
+    "EventCode": "0x32",
+    "UMask": "0x0",
+    "EventName": "UNC_P_VR_HOT_CYCLES",
+    "BriefDescription": "VR Hot",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x8",
+    "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x10",
+    "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x4",
+    "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x2",
+    "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x42",
+    "UMask": "0x1",
+    "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+    "BriefDescription": "VLW Received",
+    "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x2",
+    "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x1",
+    "EventName": "UNC_U_FILTER_MATCH.ENABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "UBoxFilter[3:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x8",
+    "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x41",
+    "UMask": "0x4",
+    "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
+    "BriefDescription": "Filter Match",
+    "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "UBoxFilter[3:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x44",
+    "UMask": "0x0",
+    "EventName": "UNC_U_LOCK_CYCLES",
+    "BriefDescription": "IDI Lock/SplitLock Cycles",
+    "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x47",
+    "UMask": "0x1",
+    "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.4B",
+    "BriefDescription": "MsgCh Requests by Size; 4B Requests",
+    "PublicDescription": "Number of transactions on the message channel filtered by request size.  This includes both reads and writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x47",
+    "UMask": "0x2",
+    "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.8B",
+    "BriefDescription": "MsgCh Requests by Size; 8B Requests",
+    "PublicDescription": "Number of transactions on the message channel filtered by request size.  This includes both reads and writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x45",
+    "UMask": "0x2",
+    "EventName": "UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT",
+    "BriefDescription": "Cycles PHOLD Assert to Ack; ACK to Deassert",
+    "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x45",
+    "UMask": "0x1",
+    "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+    "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+    "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x46",
+    "UMask": "0x1",
+    "EventName": "UNC_U_RACU_REQUESTS.COUNT",
+    "BriefDescription": "RACU Request",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x10",
+    "EventName": "UNC_U_U2C_EVENTS.CMC",
+    "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x4",
+    "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
+    "BriefDescription": "Monitor Sent to T0; Livelock",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x8",
+    "EventName": "UNC_U_U2C_EVENTS.LTERROR",
+    "BriefDescription": "Monitor Sent to T0; LTError",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x1",
+    "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
+    "BriefDescription": "Monitor Sent to T0; Monitor T0",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x2",
+    "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+    "BriefDescription": "Monitor Sent to T0; Monitor T1",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x80",
+    "EventName": "UNC_U_U2C_EVENTS.OTHER",
+    "BriefDescription": "Monitor Sent to T0; Other",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x40",
+    "EventName": "UNC_U_U2C_EVENTS.TRAP",
+    "BriefDescription": "Monitor Sent to T0; Trap",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x43",
+    "UMask": "0x20",
+    "EventName": "UNC_U_U2C_EVENTS.UMC",
+    "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+    "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x14",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_CLOCKTICKS",
+    "BriefDescription": "Number of qfclks",
+    "PublicDescription": "Counts the number of clocks in the QPI LL.  This clock runs at 1/8th the 'GT/s' speed of the QPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  JKT does not support dynamic link speeds, so this frequency is fixed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x38",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_CTO_COUNT",
+    "BriefDescription": "Count of CTO Events",
+    "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Not Set",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_DIRECT2CORE.SUCCESS",
+    "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
+    "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_L1_POWER_CYCLES",
+    "BriefDescription": "Cycles in L1",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x10",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL0P_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0p",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xf",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL0_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_BYPASSED",
+    "BriefDescription": "Rx Flit Buffer Bypassed",
+    "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
+    "BriefDescription": "CRC Errors Detected; LinkInit",
+    "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
+    "BriefDescription": "CRC Errors Detected; Normal Operations",
+    "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
+    "BriefDescription": "VN0 Credit Consumed; DRS",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
+    "BriefDescription": "VN0 Credit Consumed; HOM",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
+    "BriefDescription": "VN0 Credit Consumed; NCB",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
+    "BriefDescription": "VN0 Credit Consumed; NCS",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
+    "BriefDescription": "VN0 Credit Consumed; NDR",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1e",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
+    "BriefDescription": "VN0 Credit Consumed; SNP",
+    "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1d",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
+    "BriefDescription": "VNA Credit Consumed",
+    "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xa",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_CYCLES_NE",
+    "BriefDescription": "RxQ Cycles Not Empty",
+    "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_FLITS_G0.DATA",
+    "BriefDescription": "Flits Received - Group 0; Data Tx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
+    "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA",
+    "BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x18",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
+    "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
+    "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
+    "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x6",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
+    "BriefDescription": "Flits Received - Group 1; HOM Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
+    "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
+    "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
+    "BriefDescription": "Flits Received - Group 1; SNP Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0xc",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
+    "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
+    "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x3",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
+    "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+    "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x8",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS",
+    "BriefDescription": "Rx Flit Buffer Allocations",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_DRS",
+    "BriefDescription": "Rx Flit Buffer Allocations - DRS",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xc",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_HOM",
+    "BriefDescription": "Rx Flit Buffer Allocations - HOM",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xa",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_NCB",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCB",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xb",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_NCS",
+    "BriefDescription": "Rx Flit Buffer Allocations - NCS",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xe",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_NDR",
+    "BriefDescription": "Rx Flit Buffer Allocations - NDR",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xd",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_INSERTS_SNP",
+    "BriefDescription": "Rx Flit Buffer Allocations - SNP",
+    "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xb",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY",
+    "BriefDescription": "RxQ Occupancy - All Packets",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x15",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_DRS",
+    "BriefDescription": "RxQ Occupancy - DRS",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x18",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_HOM",
+    "BriefDescription": "RxQ Occupancy - HOM",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x16",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCB",
+    "BriefDescription": "RxQ Occupancy - NCB",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x17",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NCS",
+    "BriefDescription": "RxQ Occupancy - NCS",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1a",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_NDR",
+    "BriefDescription": "RxQ Occupancy - NDR",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x19",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_RxL_OCCUPANCY_SNP",
+    "BriefDescription": "RxQ Occupancy - SNP",
+    "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_RxL_STALLS.BGF_DRS",
+    "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - HOM",
+    "PublicDescription": "Number of stalls trying to send to R3QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_RxL_STALLS.BGF_HOM",
+    "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - DRS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_RxL_STALLS.BGF_NCB",
+    "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - SNP",
+    "PublicDescription": "Number of stalls trying to send to R3QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_RxL_STALLS.BGF_NCS",
+    "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NDR",
+    "PublicDescription": "Number of stalls trying to send to R3QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x20",
+    "EventName": "UNC_Q_RxL_STALLS.BGF_NDR",
+    "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCS",
+    "PublicDescription": "Number of stalls trying to send to R3QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_RxL_STALLS.BGF_SNP",
+    "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCB",
+    "PublicDescription": "Number of stalls trying to send to R3QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x40",
+    "EventName": "UNC_Q_RxL_STALLS.EGRESS_CREDITS",
+    "BriefDescription": "Stalls Sending to R3QPI; Egress Credits",
+    "PublicDescription": "Number of stalls trying to send to R3QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x35",
+    "UMask": "0x80",
+    "EventName": "UNC_Q_RxL_STALLS.GV",
+    "BriefDescription": "Stalls Sending to R3QPI; GV",
+    "PublicDescription": "Number of stalls trying to send to R3QPI.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xd",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0p",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0xc",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL0_POWER_CYCLES",
+    "BriefDescription": "Cycles in L0",
+    "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_BYPASSED",
+    "BriefDescription": "Tx Flit Buffer Bypassed",
+    "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
+    "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
+    "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
+    "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
+    "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_CYCLES_NE",
+    "BriefDescription": "Tx Flit Buffer Cycles not Empty",
+    "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
+    "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
+    "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_FLITS_G0.IDLE",
+    "BriefDescription": "Flits Transferred - Group 0; Idle and Null Flits",
+    "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
+    "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
+    "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x18",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
+    "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x6",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
+    "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x0",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
+    "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0xc",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x4",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x8",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x10",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x1",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1",
+    "UMask": "0x2",
+    "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
+    "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
+    "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_INSERTS",
+    "BriefDescription": "Tx Flit Buffer Allocations",
+    "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_TxL_OCCUPANCY",
+    "BriefDescription": "Tx Flit Buffer Occupancy",
+    "PublicDescription": "Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1c",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_VNA_CREDIT_RETURNS",
+    "BriefDescription": "VNA Credits Returned",
+    "PublicDescription": "Number of VNA credits returned.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "QPI LL",
+    "EventCode": "0x1b",
+    "UMask": "0x0",
+    "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
+    "BriefDescription": "VNA Credits Pending Return - Occupancy",
+    "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "1"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_CLOCKTICKS",
+    "BriefDescription": "Number of uclks in domain",
+    "PublicDescription": "Counts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS",
+    "BriefDescription": "to IIO BL Credit Acquired",
+    "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB",
+    "BriefDescription": "to IIO BL Credit Acquired",
+    "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x20",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS",
+    "BriefDescription": "to IIO BL Credit Acquired",
+    "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x21",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS",
+    "BriefDescription": "to IIO BL Credit Rejected",
+    "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x21",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB",
+    "BriefDescription": "to IIO BL Credit Rejected",
+    "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x21",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS",
+    "BriefDescription": "to IIO BL Credit Rejected",
+    "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_IIO_CREDITS_USED.DRS",
+    "BriefDescription": "to IIO BL Credit In Use",
+    "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_IIO_CREDITS_USED.NCB",
+    "BriefDescription": "to IIO BL Credit In Use",
+    "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x22",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_IIO_CREDITS_USED.NCS",
+    "BriefDescription": "to IIO BL Credit In Use",
+    "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
+    "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
+    "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
+    "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+    "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
+    "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
+    "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
+    "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+    "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
+    "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
+    "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
+    "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
+    "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0xa",
+    "UMask": "0xf",
+    "EventName": "UNC_R3_RING_IV_USED.ANY",
+    "BriefDescription": "R3 IV Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.",
+    "Counter": "0,1,2",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_BYPASSED.AD",
+    "BriefDescription": "Ingress Bypassed",
+    "PublicDescription": "Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.DRS",
+    "BriefDescription": "Ingress Cycles Not Empty; DRS",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
+    "BriefDescription": "Ingress Cycles Not Empty; HOM",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.NCB",
+    "BriefDescription": "Ingress Cycles Not Empty; NCB",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.NCS",
+    "BriefDescription": "Ingress Cycles Not Empty; NCS",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+    "BriefDescription": "Ingress Cycles Not Empty; NDR",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
+    "BriefDescription": "Ingress Cycles Not Empty; SNP",
+    "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_INSERTS.DRS",
+    "BriefDescription": "Ingress Allocations; DRS",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_INSERTS.HOM",
+    "BriefDescription": "Ingress Allocations; HOM",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_INSERTS.NCB",
+    "BriefDescription": "Ingress Allocations; NCB",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_INSERTS.NCS",
+    "BriefDescription": "Ingress Allocations; NCS",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_INSERTS.NDR",
+    "BriefDescription": "Ingress Allocations; NDR",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_INSERTS.SNP",
+    "BriefDescription": "Ingress Allocations; SNP",
+    "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.DRS",
+    "BriefDescription": "Ingress Occupancy Accumulator; DRS",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.HOM",
+    "BriefDescription": "Ingress Occupancy Accumulator; HOM",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.NCB",
+    "BriefDescription": "Ingress Occupancy Accumulator; NCB",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.NCS",
+    "BriefDescription": "Ingress Occupancy Accumulator; NCS",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.NDR",
+    "BriefDescription": "Ingress Occupancy Accumulator; NDR",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_RxR_OCCUPANCY.SNP",
+    "BriefDescription": "Ingress Occupancy Accumulator; SNP",
+    "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x37",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
+    "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+    "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
+    "BriefDescription": "VN0 Credit Used; DRS Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
+    "BriefDescription": "VN0 Credit Used; HOM Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
+    "BriefDescription": "VN0 Credit Used; NCB Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
+    "BriefDescription": "VN0 Credit Used; NCS Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
+    "BriefDescription": "VN0 Credit Used; NDR Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x36",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
+    "BriefDescription": "VN0 Credit Used; SNP Message Class",
+    "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x33",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED",
+    "BriefDescription": "VNA credit Acquisitions",
+    "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x8",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
+    "BriefDescription": "VNA Credit Reject; DRS Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x1",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
+    "BriefDescription": "VNA Credit Reject; HOM Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x10",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
+    "BriefDescription": "VNA Credit Reject; NCB Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x20",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
+    "BriefDescription": "VNA Credit Reject; NCS Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x4",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
+    "BriefDescription": "VNA Credit Reject; NDR Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x34",
+    "UMask": "0x2",
+    "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
+    "BriefDescription": "VNA Credit Reject; SNP Message Class",
+    "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x31",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT",
+    "BriefDescription": "Cycles with no VNA credits available",
+    "PublicDescription": "Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel.  Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit.  Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R3QPI",
+    "EventCode": "0x32",
+    "UMask": "0x0",
+    "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED",
+    "BriefDescription": "Cycles with 1 or more VNA credits in use",
+    "PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_R2_CLOCKTICKS",
+    "BriefDescription": "Number of uclks in domain",
+    "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x33",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
+    "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
+    "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x34",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS",
+    "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS",
+    "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x34",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCB",
+    "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCB",
+    "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x34",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCS",
+    "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCS",
+    "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
+    "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
+    "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x32",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
+    "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
+    "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
+    "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
+    "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x9",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+    "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0xa",
+    "UMask": "0xf",
+    "EventName": "UNC_R2_RING_IV_USED.ANY",
+    "BriefDescription": "R2 IV Ring in Use; Any",
+    "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_R2_RxR_AK_BOUNCES",
+    "BriefDescription": "AK Ingress Bounced",
+    "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x8",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.DRS",
+    "BriefDescription": "Ingress Cycles Not Empty; DRS",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x10",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
+    "BriefDescription": "Ingress Cycles Not Empty; NCB",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x10",
+    "UMask": "0x20",
+    "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
+    "BriefDescription": "Ingress Cycles Not Empty; NCS",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
+    "BriefDescription": "Egress Cycles Full; AD",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
+    "BriefDescription": "Egress Cycles Full; AK",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x25",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
+    "BriefDescription": "Egress Cycles Full; BL",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.AD",
+    "BriefDescription": "Egress Cycles Not Empty; AD",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.AK",
+    "BriefDescription": "Egress Cycles Not Empty; AK",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x23",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_CYCLES_NE.BL",
+    "BriefDescription": "Egress Cycles Not Empty; BL",
+    "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x1",
+    "EventName": "UNC_R2_TxR_NACKS.AD",
+    "BriefDescription": "Egress NACK; AD",
+    "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x2",
+    "EventName": "UNC_R2_TxR_NACKS.AK",
+    "BriefDescription": "Egress NACK; AK",
+    "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "R2PCIe",
+    "EventCode": "0x26",
+    "UMask": "0x4",
+    "EventName": "UNC_R2_TxR_NACKS.BL",
+    "BriefDescription": "Egress NACK; BL",
+    "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x20",
+    "UMask": "0x3",
+    "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
+    "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
+    "BriefDescription": "HA to iMC Bypass; Not Taken",
+    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_H_BYPASS_IMC.TAKEN",
+    "BriefDescription": "HA to iMC Bypass; Taken",
+    "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_H_CLOCKTICKS",
+    "BriefDescription": "uclks",
+    "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xb",
+    "UMask": "0x2",
+    "EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT",
+    "BriefDescription": "Conflict Checks; Conflict Detected",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xb",
+    "UMask": "0x1",
+    "EventName": "UNC_H_CONFLICT_CYCLES.NO_CONFLICT",
+    "BriefDescription": "Conflict Checks; No Conflict",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x11",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_COUNT",
+    "BriefDescription": "Direct2Core Messages Sent",
+    "PublicDescription": "Number of Direct2Core messages sent",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
+    "BriefDescription": "Cycles when Direct2Core was Disabled",
+    "PublicDescription": "Number of cycles in which Direct2Core was disabled",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x13",
+    "UMask": "0x0",
+    "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
+    "BriefDescription": "Number of Reads that had Direct2Core Overridden",
+    "PublicDescription": "Number of Reads where Direct2Core overridden",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
+    "BriefDescription": "Directory Lookups; Snoop Not Needed",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xc",
+    "UMask": "0x1",
+    "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
+    "BriefDescription": "Directory Lookups; Snoop Needed",
+    "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x3",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
+    "BriefDescription": "Directory Updates; Any Directory Update",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x2",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
+    "BriefDescription": "Directory Updates; Directory Clear",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xd",
+    "UMask": "0x1",
+    "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
+    "BriefDescription": "Directory Updates; Directory Set",
+    "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
+    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
+    "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x22",
+    "UMask": "0x8",
+    "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+    "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+    "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1e",
+    "UMask": "0x0",
+    "EventName": "UNC_H_IMC_RETRY",
+    "BriefDescription": "Retry Events",
+    "PublicDescription": "tbd",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0xf",
+    "EventName": "UNC_H_IMC_WRITES.ALL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0x1",
+    "EventName": "UNC_H_IMC_WRITES.FULL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0x4",
+    "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0x2",
+    "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1a",
+    "UMask": "0x8",
+    "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+    "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
+    "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0x3",
+    "EventName": "UNC_H_REQUESTS.READS",
+    "BriefDescription": "Read and Write Requests; Reads",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1",
+    "UMask": "0xc",
+    "EventName": "UNC_H_REQUESTS.WRITES",
+    "BriefDescription": "Read and Write Requests; Writes",
+    "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
+    "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3e",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_AD_USED.CW_ODD",
+    "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
+    "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x3f",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_AK_USED.CW_ODD",
+    "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
+    "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x40",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RING_BL_USED.CW_ODD",
+    "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+    "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
+    "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x4",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x16",
+    "UMask": "0x8",
+    "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+    "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x10",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x20",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x40",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1b",
+    "UMask": "0x80",
+    "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
+    "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1c",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1c",
+    "UMask": "0x8",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1c",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x1c",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
+    "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
+    "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x6",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TRACKER_INSERTS.ALL",
+    "BriefDescription": "Tracker Allocations; All Requests",
+    "PublicDescription": "Counts the number of allocations into the local HA tracker pool.  This can be used in conjunction with the occupancy accumulation event in order to calculate average latency.  One cannot filter between reads and writes.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xf",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD.NDR",
+    "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
+    "PublicDescription": "Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xf",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD.SNP",
+    "BriefDescription": "Outbound NDR Ring Transactions; Snoops",
+    "PublicDescription": "Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2a",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+    "BriefDescription": "AD Egress Full; All",
+    "PublicDescription": "AD Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2a",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
+    "BriefDescription": "AD Egress Full; Scheduler 0",
+    "PublicDescription": "AD Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2a",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
+    "BriefDescription": "AD Egress Full; Scheduler 1",
+    "PublicDescription": "AD Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+    "BriefDescription": "AD Egress Not Empty; All",
+    "PublicDescription": "AD Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
+    "BriefDescription": "AD Egress Not Empty; Scheduler 0",
+    "PublicDescription": "AD Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x29",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
+    "BriefDescription": "AD Egress Not Empty; Scheduler 1",
+    "PublicDescription": "AD Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+    "BriefDescription": "AD Egress Allocations; All",
+    "PublicDescription": "AD Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
+    "BriefDescription": "AD Egress Allocations; Scheduler 0",
+    "PublicDescription": "AD Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x27",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
+    "BriefDescription": "AD Egress Allocations; Scheduler 1",
+    "PublicDescription": "AD Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x28",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AD_OCCUPANCY.ALL",
+    "BriefDescription": "AD Egress Occupancy; All",
+    "PublicDescription": "AD Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x28",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0",
+    "BriefDescription": "AD Egress Occupancy; Scheduler 0",
+    "PublicDescription": "AD Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x28",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1",
+    "BriefDescription": "AD Egress Occupancy; Scheduler 1",
+    "PublicDescription": "AD Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+    "BriefDescription": "AK Egress Full; All",
+    "PublicDescription": "AK Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
+    "BriefDescription": "AK Egress Full; Scheduler 0",
+    "PublicDescription": "AK Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x32",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
+    "BriefDescription": "AK Egress Full; Scheduler 1",
+    "PublicDescription": "AK Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+    "BriefDescription": "AK Egress Not Empty; All",
+    "PublicDescription": "AK Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
+    "BriefDescription": "AK Egress Not Empty; Scheduler 0",
+    "PublicDescription": "AK Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x31",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
+    "BriefDescription": "AK Egress Not Empty; Scheduler 1",
+    "PublicDescription": "AK Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2f",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
+    "BriefDescription": "AK Egress Allocations; All",
+    "PublicDescription": "AK Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2f",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
+    "BriefDescription": "AK Egress Allocations; Scheduler 0",
+    "PublicDescription": "AK Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x2f",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
+    "BriefDescription": "AK Egress Allocations; Scheduler 1",
+    "PublicDescription": "AK Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0xe",
+    "UMask": "0x0",
+    "EventName": "UNC_H_TxR_AK_NDR",
+    "BriefDescription": "Outbound NDR Ring Transactions",
+    "PublicDescription": "Counts the number of outbound NDR transactions sent on the AK ring.  NDR stands for 'non-data response' and is generally used for completions that do not include data.  AK NDR is used for messages to the local socket.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x30",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_AK_OCCUPANCY.ALL",
+    "BriefDescription": "AK Egress Occupancy; All",
+    "PublicDescription": "AK Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x30",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0",
+    "BriefDescription": "AK Egress Occupancy; Scheduler 0",
+    "PublicDescription": "AK Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x30",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1",
+    "BriefDescription": "AK Egress Occupancy; Scheduler 1",
+    "PublicDescription": "AK Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL.DRS_CACHE",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL.DRS_CORE",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x10",
+    "UMask": "0x4",
+    "EventName": "UNC_H_TxR_BL.DRS_QPI",
+    "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+    "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+    "BriefDescription": "BL Egress Full; All",
+    "PublicDescription": "BL Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
+    "BriefDescription": "BL Egress Full; Scheduler 0",
+    "PublicDescription": "BL Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x36",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
+    "BriefDescription": "BL Egress Full; Scheduler 1",
+    "PublicDescription": "BL Egress Full",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+    "BriefDescription": "BL Egress Not Empty; All",
+    "PublicDescription": "BL Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
+    "BriefDescription": "BL Egress Not Empty; Scheduler 0",
+    "PublicDescription": "BL Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x35",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
+    "BriefDescription": "BL Egress Not Empty; Scheduler 1",
+    "PublicDescription": "BL Egress Not Empty",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
+    "BriefDescription": "BL Egress Allocations; All",
+    "PublicDescription": "BL Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
+    "BriefDescription": "BL Egress Allocations; Scheduler 0",
+    "PublicDescription": "BL Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x33",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
+    "BriefDescription": "BL Egress Allocations; Scheduler 1",
+    "PublicDescription": "BL Egress Allocations",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x34",
+    "UMask": "0x3",
+    "EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL",
+    "BriefDescription": "BL Egress Occupancy; All",
+    "PublicDescription": "BL Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x34",
+    "UMask": "0x1",
+    "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0",
+    "BriefDescription": "BL Egress Occupancy; Scheduler 0",
+    "PublicDescription": "BL Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x34",
+    "UMask": "0x2",
+    "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1",
+    "BriefDescription": "BL Egress Occupancy; Scheduler 1",
+    "PublicDescription": "BL Egress Occupancy",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x1",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x2",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x4",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x18",
+    "UMask": "0x8",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x1",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x2",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x4",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "HA",
+    "EventCode": "0x19",
+    "UMask": "0x8",
+    "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+    "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
+    "PublicDescription": "Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_M_ACT_COUNT",
+    "BriefDescription": "DRAM Activate Count",
+    "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0xf",
+    "EventName": "UNC_M_CAS_COUNT.ALL",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x3",
+    "EventName": "UNC_M_CAS_COUNT.RD",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x1",
+    "EventName": "UNC_M_CAS_COUNT.RD_REG",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x2",
+    "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0xc",
+    "EventName": "UNC_M_CAS_COUNT.WR",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x8",
+    "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x4",
+    "UMask": "0x4",
+    "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+    "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
+    "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_M_DRAM_PRE_ALL",
+    "BriefDescription": "DRAM Precharge All Commands",
+    "PublicDescription": "Counts the number of times that the precharge all command was sent.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x5",
+    "UMask": "0x4",
+    "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+    "BriefDescription": "Number of DRAM Refreshes Issued",
+    "PublicDescription": "Counts the number of refreshes issued.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x5",
+    "UMask": "0x2",
+    "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+    "BriefDescription": "Number of DRAM Refreshes Issued",
+    "PublicDescription": "Counts the number of refreshes issued.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
+    "BriefDescription": "ECC Correctable Errors",
+    "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x8",
+    "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+    "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x4",
+    "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+    "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x1",
+    "EventName": "UNC_M_MAJOR_MODES.READ",
+    "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x7",
+    "UMask": "0x2",
+    "EventName": "UNC_M_MAJOR_MODES.WRITE",
+    "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
+    "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x84",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
+    "BriefDescription": "Channel DLLOFF Cycles",
+    "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x85",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CHANNEL_PPD",
+    "BriefDescription": "Channel PPD Cycles",
+    "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x1",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x2",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x4",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x8",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x10",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x20",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x40",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x83",
+    "UMask": "0x80",
+    "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
+    "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
+    "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x86",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
+    "BriefDescription": "Critical Throttle Cycles",
+    "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x43",
+    "UMask": "0x0",
+    "EventName": "UNC_M_POWER_SELF_REFRESH",
+    "BriefDescription": "Clock-Enabled Self-Refresh",
+    "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x1",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x2",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x4",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x8",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x10",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x20",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x40",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x41",
+    "UMask": "0x80",
+    "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
+    "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
+    "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x8",
+    "UMask": "0x1",
+    "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
+    "BriefDescription": "Read Preemption Count; Read over Read Preemption",
+    "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x8",
+    "UMask": "0x2",
+    "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
+    "BriefDescription": "Read Preemption Count; Read over Write Preemption",
+    "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x2",
+    "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
+    "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x2",
+    "UMask": "0x1",
+    "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+    "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+    "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x12",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_CYCLES_FULL",
+    "BriefDescription": "Read Pending Queue Full Cycles",
+    "PublicDescription": "Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x11",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_CYCLES_NE",
+    "BriefDescription": "Read Pending Queue Not Empty",
+    "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x10",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_INSERTS",
+    "BriefDescription": "Read Pending Queue Allocations",
+    "PublicDescription": "Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x80",
+    "UMask": "0x0",
+    "EventName": "UNC_M_RPQ_OCCUPANCY",
+    "BriefDescription": "Read Pending Queue Occupancy",
+    "PublicDescription": "Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x22",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_CYCLES_FULL",
+    "BriefDescription": "Write Pending Queue Full Cycles",
+    "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x21",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_CYCLES_NE",
+    "BriefDescription": "Write Pending Queue Not Empty",
+    "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x20",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_INSERTS",
+    "BriefDescription": "Write Pending Queue Allocations",
+    "PublicDescription": "Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x81",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_OCCUPANCY",
+    "BriefDescription": "Write Pending Queue Occupancy",
+    "PublicDescription": "Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x23",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_READ_HIT",
+    "BriefDescription": "Write Pending Queue CAM Match",
+    "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x24",
+    "UMask": "0x0",
+    "EventName": "UNC_M_WPQ_WRITE_HIT",
+    "BriefDescription": "Write Pending Queue CAM Match",
+    "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "UBOX",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_U_CLOCKTICKS",
+    "BriefDescription": "tbd",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "iMC",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_M_CLOCKTICKS",
+    "BriefDescription": "uclks",
+    "PublicDescription": "Uncore Fixed Counter - uclks",
+    "Counter": "0,1,2,3",
+    "MSRValue": "0x0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x1",
+    "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT",
+    "BriefDescription": "Address Match (Conflict) Count; Conflict Stalls",
+    "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x17",
+    "UMask": "0x2",
+    "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT",
+    "BriefDescription": "Address Match (Conflict) Count; Conflict Merges",
+    "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
+    "BriefDescription": "Write Ack Pending Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x14",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
+    "BriefDescription": "Write Ack Pending Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY",
+    "BriefDescription": "Outstanding Write Ownership Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x13",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
+    "BriefDescription": "Outstanding Write Ownership Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x10",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY",
+    "BriefDescription": "Outstanding Read Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x10",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
+    "BriefDescription": "Outstanding Read Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x12",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+    "BriefDescription": "Total Write Cache Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x12",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
+    "BriefDescription": "Total Write Cache Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x11",
+    "UMask": "0x1",
+    "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
+    "BriefDescription": "Outstanding Write Occupancy; Any Source",
+    "PublicDescription": "Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x11",
+    "UMask": "0x2",
+    "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
+    "BriefDescription": "Outstanding Write Occupancy; Select Source",
+    "PublicDescription": "Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x0",
+    "UMask": "0x0",
+    "EventName": "UNC_I_CLOCKTICKS",
+    "BriefDescription": "Clocks in the IRP",
+    "PublicDescription": "Number of clocks in the IRP.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xB",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_AK_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the AK Ingress is full.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xA",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_AK_INSERTS",
+    "BriefDescription": "AK Ingress Occupancy",
+    "PublicDescription": "Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xC",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_AK_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the AK Ingress in each cycles.  This queue is where the IRP receives responses from R2PCIe (the ring).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x4",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x1",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - DRS",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x7",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x5",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x2",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - NCB",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x8",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x6",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x3",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
+    "BriefDescription": "BL Ingress Occupancy - NCS",
+    "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x9",
+    "UMask": "0x0",
+    "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
+    "BriefDescription": "tbd",
+    "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x1",
+    "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP",
+    "BriefDescription": "Tickle Count; Ownership Lost",
+    "PublicDescription": "Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x16",
+    "UMask": "0x2",
+    "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE",
+    "BriefDescription": "Tickle Count; Data Returned",
+    "PublicDescription": "Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x1",
+    "EventName": "UNC_I_TRANSACTIONS.READS",
+    "BriefDescription": "Inbound Transaction Count; Reads",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x2",
+    "EventName": "UNC_I_TRANSACTIONS.WRITES",
+    "BriefDescription": "Inbound Transaction Count; Writes",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x4",
+    "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES",
+    "BriefDescription": "Inbound Transaction Count; Read Prefetches",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x15",
+    "UMask": "0x8",
+    "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+    "BriefDescription": "Inbound Transaction Count; Select Source",
+    "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "IRPFilter[4:0]",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x18",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
+    "BriefDescription": "No AD Egress Credit Stalls",
+    "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x19",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
+    "BriefDescription": "No BL Egress Credit Stalls",
+    "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xE",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
+    "BriefDescription": "Outbound Read Requests",
+    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xF",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
+    "BriefDescription": "Outbound Read Requests",
+    "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0xD",
+    "UMask": "0x0",
+    "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
+    "BriefDescription": "Outbound Request Queue Occupancy",
+    "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  },
+  {
+    "Unit": "IRP",
+    "EventCode": "0x1A",
+    "UMask": "0x0",
+    "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES",
+    "BriefDescription": "Write Ordering Stalls",
+    "PublicDescription": "Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized.",
+    "Counter": "0,1",
+    "MSRValue": "0",
+    "Filter": "null",
+    "ExtSel": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/JKT/Jaketown_uncore_V18.tsv b/x86data/perfmon_data/JKT/Jaketown_uncore_V18.tsv
new file mode 100644
index 0000000..55bc730
--- /dev/null
+++ b/x86data/perfmon_data/JKT/Jaketown_uncore_V18.tsv
@@ -0,0 +1,544 @@
+# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family Based on the Sandy Bridge-EP Microarchitecture - V18
+# 7/28/2015 3:43:34 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+Unit	EventCode	UMask	EventName	Description	Counter	MSRValue	Filter	Internal
+CBO	0x0	0x0	UNC_C_CLOCKTICKS	tbd	0,1,2,3	0	null	0
+CBO	0x1f	0x0	UNC_C_COUNTER0_OCCUPANCY	Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.	1,2,3	0	null	0
+CBO	0x21	0x0	UNC_C_ISMQ_DRD_MISS_OCC	tbd	0,1	0	null	0
+CBO	0x34	0x3	UNC_C_LLC_LOOKUP.DATA_READ	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.	0,1	0	CBoFilter[22:18]	0
+CBO	0x34	0x41	UNC_C_LLC_LOOKUP.NID	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.	0,1	0	CBoFilter[22:18], CBoFilter[17:10]	0
+CBO	0x34	0x9	UNC_C_LLC_LOOKUP.REMOTE_SNOOP	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.	0,1	0	CBoFilter[22:18]	0
+CBO	0x34	0x5	UNC_C_LLC_LOOKUP.WRITE	Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set filter mask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.	0,1	0	CBoFilter[22:18]	0
+CBO	0x37	0x2	UNC_C_LLC_VICTIMS.E_STATE	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0	null	0
+CBO	0x37	0x8	UNC_C_LLC_VICTIMS.MISS	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0	null	0
+CBO	0x37	0x1	UNC_C_LLC_VICTIMS.M_STATE	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0	null	0
+CBO	0x37	0x40	UNC_C_LLC_VICTIMS.NID	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0	CBoFilter[17:10]	0
+CBO	0x37	0x4	UNC_C_LLC_VICTIMS.S_STATE	Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.	0,1	0	null	0
+CBO	0x39	0x8	UNC_C_MISC.RFO_HIT_S	Miscellaneous events in the Cbo.	0,1	0	null	0
+CBO	0x39	0x1	UNC_C_MISC.RSPI_WAS_FSE	Miscellaneous events in the Cbo.	0,1	0	null	0
+CBO	0x39	0x4	UNC_C_MISC.STARTED	Miscellaneous events in the Cbo.	0,1	0	null	0
+CBO	0x39	0x2	UNC_C_MISC.WC_ALIASING	Miscellaneous events in the Cbo.	0,1	0	null	0
+CBO	0x1b	0x4	UNC_C_RING_AD_USED.DOWN_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1b	0x8	UNC_C_RING_AD_USED.DOWN_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1b	0x1	UNC_C_RING_AD_USED.UP_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1b	0x2	UNC_C_RING_AD_USED.UP_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1c	0x4	UNC_C_RING_AK_USED.DOWN_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1c	0x8	UNC_C_RING_AK_USED.DOWN_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1c	0x1	UNC_C_RING_AK_USED.UP_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1c	0x2	UNC_C_RING_AK_USED.UP_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1d	0x4	UNC_C_RING_BL_USED.DOWN_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1d	0x8	UNC_C_RING_BL_USED.DOWN_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1d	0x1	UNC_C_RING_BL_USED.UP_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x1d	0x2	UNC_C_RING_BL_USED.UP_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.	2,3	0	null	0
+CBO	0x5	0x2	UNC_C_RING_BOUNCES.AK_CORE	tbd	0,1	0	null	0
+CBO	0x5	0x4	UNC_C_RING_BOUNCES.BL_CORE	tbd	0,1	0	null	0
+CBO	0x5	0x8	UNC_C_RING_BOUNCES.IV_CORE	tbd	0,1	0	null	0
+CBO	0x1e	0xf	UNC_C_RING_IV_USED.ANY	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in JKT.  Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN.  To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.	2,3	0	null	0
+CBO	0x6	0x1	UNC_C_RING_SINK_STARVED.AD_CACHE	tbd	0,1	0	null	0
+CBO	0x6	0x2	UNC_C_RING_SINK_STARVED.AK_CORE	tbd	0,1	0	null	0
+CBO	0x6	0x4	UNC_C_RING_SINK_STARVED.BL_CORE	tbd	0,1	0	null	0
+CBO	0x6	0x8	UNC_C_RING_SINK_STARVED.IV_CORE	tbd	0,1	0	null	0
+CBO	0x7	0x0	UNC_C_RING_SRC_THRTL	tbd	0,1	0	null	0
+CBO	0x12	0x2	UNC_C_RxR_EXT_STARVED.IPQ	Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.	0,1	0	null	0
+CBO	0x12	0x1	UNC_C_RxR_EXT_STARVED.IRQ	Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.	0,1	0	null	0
+CBO	0x12	0x4	UNC_C_RxR_EXT_STARVED.ISMQ	Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.	0,1	0	null	0
+CBO	0x12	0x8	UNC_C_RxR_EXT_STARVED.ISMQ_BIDS	Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.	0,1	0	null	0
+CBO	0x13	0x4	UNC_C_RxR_INSERTS.IPQ	Counts number of allocations per cycle into the specified Ingress queue.	0,1	0	null	0
+CBO	0x13	0x1	UNC_C_RxR_INSERTS.IRQ	Counts number of allocations per cycle into the specified Ingress queue.	0,1	0	null	0
+CBO	0x13	0x2	UNC_C_RxR_INSERTS.IRQ_REJECTED	Counts number of allocations per cycle into the specified Ingress queue.	0,1	0	null	0
+CBO	0x13	0x10	UNC_C_RxR_INSERTS.VFIFO	Counts number of allocations per cycle into the specified Ingress queue.	0,1	0	null	0
+CBO	0x14	0x4	UNC_C_RxR_INT_STARVED.IPQ	Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.	0,1	0	null	0
+CBO	0x14	0x1	UNC_C_RxR_INT_STARVED.IRQ	Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.	0,1	0	null	0
+CBO	0x14	0x8	UNC_C_RxR_INT_STARVED.ISMQ	Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.	0,1	0	null	0
+CBO	0x31	0x4	UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT	Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.	0,1	0	null	0
+CBO	0x31	0x1	UNC_C_RxR_IPQ_RETRY.ANY	Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.	0,1	0	null	0
+CBO	0x31	0x2	UNC_C_RxR_IPQ_RETRY.FULL	Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.	0,1	0	null	0
+CBO	0x31	0x10	UNC_C_RxR_IPQ_RETRY.QPI_CREDITS	Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.	0,1	0	null	0
+CBO	0x32	0x4	UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT	tbd	0,1	0	null	0
+CBO	0x32	0x1	UNC_C_RxR_IRQ_RETRY.ANY	tbd	0,1	0	null	0
+CBO	0x32	0x2	UNC_C_RxR_IRQ_RETRY.FULL	tbd	0,1	0	null	0
+CBO	0x32	0x10	UNC_C_RxR_IRQ_RETRY.QPI_CREDITS	tbd	0,1	0	null	0
+CBO	0x32	0x8	UNC_C_RxR_IRQ_RETRY.RTID	tbd	0,1	0	null	0
+CBO	0x33	0x1	UNC_C_RxR_ISMQ_RETRY.ANY	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.	0,1	0	null	0
+CBO	0x33	0x2	UNC_C_RxR_ISMQ_RETRY.FULL	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.	0,1	0	null	0
+CBO	0x33	0x20	UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.	0,1	0	null	0
+CBO	0x33	0x10	UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.	0,1	0	null	0
+CBO	0x33	0x8	UNC_C_RxR_ISMQ_RETRY.RTID	Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.	0,1	0	null	0
+CBO	0x11	0x4	UNC_C_RxR_OCCUPANCY.IPQ	Counts number of entries in the specified Ingress queue in each cycle.	0	0	null	0
+CBO	0x11	0x1	UNC_C_RxR_OCCUPANCY.IRQ	Counts number of entries in the specified Ingress queue in each cycle.	0	0	null	0
+CBO	0x11	0x2	UNC_C_RxR_OCCUPANCY.IRQ_REJECTED	Counts number of entries in the specified Ingress queue in each cycle.	0	0	null	0
+CBO	0x11	0x10	UNC_C_RxR_OCCUPANCY.VFIFO	Counts number of entries in the specified Ingress queue in each cycle.	0	0	null	0
+CBO	0x35	0x4	UNC_C_TOR_INSERTS.EVICTION	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	null	0
+CBO	0x35	0xa	UNC_C_TOR_INSERTS.MISS_ALL	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	null	0
+CBO	0x35	0x3	UNC_C_TOR_INSERTS.MISS_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	CBoFilter[31:23]	0
+CBO	0x35	0x48	UNC_C_TOR_INSERTS.NID_ALL	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	CBoFilter[17:10]	0
+CBO	0x35	0x44	UNC_C_TOR_INSERTS.NID_EVICTION	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	CBoFilter[17:10]	0
+CBO	0x35	0x4a	UNC_C_TOR_INSERTS.NID_MISS_ALL	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	CBoFilter[17:10]	0
+CBO	0x35	0x43	UNC_C_TOR_INSERTS.NID_MISS_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	CBoFilter[31:23], CBoFilter[17:10]	0
+CBO	0x35	0x41	UNC_C_TOR_INSERTS.NID_OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	CBoFilter[31:23], CBoFilter[17:10]	0
+CBO	0x35	0x50	UNC_C_TOR_INSERTS.NID_WB	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	CBoFilter[17:10]	0
+CBO	0x35	0x1	UNC_C_TOR_INSERTS.OPCODE	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	CBoFilter[31:23]	0
+CBO	0x35	0x10	UNC_C_TOR_INSERTS.WB	Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).	0,1	0	null	0
+CBO	0x36	0x8	UNC_C_TOR_OCCUPANCY.ALL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	null	0
+CBO	0x36	0x4	UNC_C_TOR_OCCUPANCY.EVICTION	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	null	0
+CBO	0x36	0xa	UNC_C_TOR_OCCUPANCY.MISS_ALL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	null	0
+CBO	0x36	0x3	UNC_C_TOR_OCCUPANCY.MISS_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	CBoFilter[31:23]	0
+CBO	0x36	0x48	UNC_C_TOR_OCCUPANCY.NID_ALL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	CBoFilter[17:10]	0
+CBO	0x36	0x44	UNC_C_TOR_OCCUPANCY.NID_EVICTION	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	CBoFilter[17:10]	0
+CBO	0x36	0x4a	UNC_C_TOR_OCCUPANCY.NID_MISS_ALL	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	CBoFilter[17:10]	0
+CBO	0x36	0x43	UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	CBoFilter[31:23], CBoFilter[17:10]	0
+CBO	0x36	0x41	UNC_C_TOR_OCCUPANCY.NID_OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	CBoFilter[31:23], CBoFilter[17:10]	0
+CBO	0x36	0x1	UNC_C_TOR_OCCUPANCY.OPCODE	For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)	0	0	CBoFilter[31:23]	0
+CBO	0x4	0x0	UNC_C_TxR_ADS_USED	tbd	0,1	0	null	0
+CBO	0x2	0x1	UNC_C_TxR_INSERTS.AD_CACHE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.	0,1	0	null	0
+CBO	0x2	0x10	UNC_C_TxR_INSERTS.AD_CORE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.	0,1	0	null	0
+CBO	0x2	0x2	UNC_C_TxR_INSERTS.AK_CACHE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.	0,1	0	null	0
+CBO	0x2	0x20	UNC_C_TxR_INSERTS.AK_CORE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.	0,1	0	null	0
+CBO	0x2	0x4	UNC_C_TxR_INSERTS.BL_CACHE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.	0,1	0	null	0
+CBO	0x2	0x40	UNC_C_TxR_INSERTS.BL_CORE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.	0,1	0	null	0
+CBO	0x2	0x8	UNC_C_TxR_INSERTS.IV_CACHE	Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.	0,1	0	null	0
+CBO	0x3	0x2	UNC_C_TxR_STARVED.AK	Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.	0,1	0	null	0
+CBO	0x3	0x4	UNC_C_TxR_STARVED.BL	Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.	0,1	0	null	0
+PCU	0x0	0x0	UNC_P_CLOCKTICKS	The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.	0,1,2,3	0	null	0
+PCU	0x3	0x0	UNC_P_CORE0_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0	null	1
+PCU	0x4	0x0	UNC_P_CORE1_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0	null	1
+PCU	0x5	0x0	UNC_P_CORE2_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0	null	1
+PCU	0x6	0x0	UNC_P_CORE3_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0	null	1
+PCU	0x7	0x0	UNC_P_CORE4_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0	null	1
+PCU	0x8	0x0	UNC_P_CORE5_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0	null	1
+PCU	0x9	0x0	UNC_P_CORE6_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0	null	1
+PCU	0xa	0x0	UNC_P_CORE7_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions.  There is one event per core.	0,1,2,3	0	null	1
+PCU	0x1e	0x0	UNC_P_DEMOTIONS_CORE0	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x1f	0x0	UNC_P_DEMOTIONS_CORE1	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x20	0x0	UNC_P_DEMOTIONS_CORE2	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	null	0
+PCU	0x21	0x0	UNC_P_DEMOTIONS_CORE3	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x22	0x0	UNC_P_DEMOTIONS_CORE4	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x23	0x0	UNC_P_DEMOTIONS_CORE5	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x24	0x0	UNC_P_DEMOTIONS_CORE6	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0x25	0x0	UNC_P_DEMOTIONS_CORE7	Counts the number of times when a configurable cores had a C-state demotion	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0xb	0x0	UNC_P_FREQ_BAND0_CYCLES	Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.	0,1,2,3	0	PCUFilter[7:0]	0
+PCU	0xc	0x0	UNC_P_FREQ_BAND1_CYCLES	Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.	0,1,2,3	0	PCUFilter[15:8]	0
+PCU	0xd	0x0	UNC_P_FREQ_BAND2_CYCLES	Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.	0,1,2,3	0	PCUFilter[23:16]	0
+PCU	0xe	0x0	UNC_P_FREQ_BAND3_CYCLES	Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.	0,1,2,3	0	PCUFilter[31:24]	0
+PCU	0x7	0x0	UNC_P_FREQ_MAX_CURRENT_CYCLES	Counts the number of cycles when current is the upper limit on frequency.	0,1,2,3	0	null	0
+PCU	0x4	0x0	UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES	Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.	0,1,2,3	0	null	0
+PCU	0x6	0x0	UNC_P_FREQ_MAX_OS_CYCLES	Counts the number of cycles when the OS is the upper limit on frequency.	0,1,2,3	0	null	0
+PCU	0x5	0x0	UNC_P_FREQ_MAX_POWER_CYCLES	Counts the number of cycles when power is the upper limit on frequency.	0,1,2,3	0	null	0
+PCU	0x1	0x0	UNC_P_FREQ_MIN_IO_P_CYCLES	Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.	0,1,2,3	0	null	1
+PCU	0x2	0x0	UNC_P_FREQ_MIN_PERF_P_CYCLES	Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies.	0,1,2,3	0	null	1
+PCU	0x0	0x0	UNC_P_FREQ_TRANS_CYCLES	Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.	0,1,2,3	0	null	1
+PCU	0x2f	0x0	UNC_P_MEMORY_PHASE_SHEDDING_CYCLES	Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.	0,1,2,3	0	null	0
+PCU	0x80	0x40	UNC_P_POWER_STATE_OCCUPANCY.CORES_C0	This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.	0,1,2,3	0	null	0
+PCU	0x80	0x80	UNC_P_POWER_STATE_OCCUPANCY.CORES_C3	This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.	0,1,2,3	0	null	0
+PCU	0x80	0xc0	UNC_P_POWER_STATE_OCCUPANCY.CORES_C6	This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.	0,1,2,3	0	null	0
+PCU	0xa	0x0	UNC_P_PROCHOT_EXTERNAL_CYCLES	Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.	0,1,2,3	0	null	0
+PCU	0x9	0x0	UNC_P_PROCHOT_INTERNAL_CYCLES	Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.	0,1,2,3	0	null	0
+PCU	0xb	0x0	UNC_P_TOTAL_TRANSITION_CYCLES	Number of cycles spent performing core C state transitions across all cores.	0,1,2,3	0	null	1
+PCU	0x3	0x0	UNC_P_VOLT_TRANS_CYCLES_CHANGE	Counts the number of cycles when the system is changing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.  This event is calculated by or'ing together the increasing and decreasing events.	0,1,2,3	0	null	0
+PCU	0x2	0x0	UNC_P_VOLT_TRANS_CYCLES_DECREASE	Counts the number of cycles when the system is decreasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.	0,1,2,3	0	null	0
+PCU	0x1	0x0	UNC_P_VOLT_TRANS_CYCLES_INCREASE	Counts the number of cycles when the system is increasing voltage.  There is no filtering supported with this event.  One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition.	0,1,2,3	0	null	0
+PCU	0x32	0x0	UNC_P_VR_HOT_CYCLES	tbd	0,1,2,3	0	null	0
+UBOX	0x42	0x8	UNC_U_EVENT_MSG.DOORBELL_RCVD	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	null	0
+UBOX	0x42	0x10	UNC_U_EVENT_MSG.INT_PRIO	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	null	0
+UBOX	0x42	0x4	UNC_U_EVENT_MSG.IPI_RCVD	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	null	0
+UBOX	0x42	0x2	UNC_U_EVENT_MSG.MSI_RCVD	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	null	0
+UBOX	0x42	0x1	UNC_U_EVENT_MSG.VLW_RCVD	Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	null	0
+UBOX	0x41	0x2	UNC_U_FILTER_MATCH.DISABLE	Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	null	0
+UBOX	0x41	0x1	UNC_U_FILTER_MATCH.ENABLE	Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	UBoxFilter[3:0]	0
+UBOX	0x41	0x8	UNC_U_FILTER_MATCH.U2C_DISABLE	Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	null	0
+UBOX	0x41	0x4	UNC_U_FILTER_MATCH.U2C_ENABLE	Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.	0,1	0	UBoxFilter[3:0]	0
+UBOX	0x44	0x0	UNC_U_LOCK_CYCLES	Number of times an IDI Lock/SplitLock sequence was started	0,1	0	null	0
+UBOX	0x47	0x1	UNC_U_MSG_CHNL_SIZE_COUNT.4B	Number of transactions on the message channel filtered by request size.  This includes both reads and writes.	0,1	0	null	1
+UBOX	0x47	0x2	UNC_U_MSG_CHNL_SIZE_COUNT.8B	Number of transactions on the message channel filtered by request size.  This includes both reads and writes.	0,1	0	null	1
+UBOX	0x45	0x2	UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT	PHOLD cycles.  Filter from source CoreID.	0,1	0	null	1
+UBOX	0x45	0x1	UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK	PHOLD cycles.  Filter from source CoreID.	0,1	0	null	1
+UBOX	0x46	0x1	UNC_U_RACU_REQUESTS.COUNT	tbd	0,1	0	null	1
+UBOX	0x43	0x10	UNC_U_U2C_EVENTS.CMC	Events coming from Uncore can be sent to one or all cores	0,1	0	null	0
+UBOX	0x43	0x4	UNC_U_U2C_EVENTS.LIVELOCK	Events coming from Uncore can be sent to one or all cores	0,1	0	null	0
+UBOX	0x43	0x8	UNC_U_U2C_EVENTS.LTERROR	Events coming from Uncore can be sent to one or all cores	0,1	0	null	0
+UBOX	0x43	0x1	UNC_U_U2C_EVENTS.MONITOR_T0	Events coming from Uncore can be sent to one or all cores	0,1	0	null	0
+UBOX	0x43	0x2	UNC_U_U2C_EVENTS.MONITOR_T1	Events coming from Uncore can be sent to one or all cores	0,1	0	null	0
+UBOX	0x43	0x80	UNC_U_U2C_EVENTS.OTHER	Events coming from Uncore can be sent to one or all cores	0,1	0	null	0
+UBOX	0x43	0x40	UNC_U_U2C_EVENTS.TRAP	Events coming from Uncore can be sent to one or all cores	0,1	0	null	0
+UBOX	0x43	0x20	UNC_U_U2C_EVENTS.UMC	Events coming from Uncore can be sent to one or all cores	0,1	0	null	0
+QPI LL	0x14	0x0	UNC_Q_CLOCKTICKS	Counts the number of clocks in the QPI LL.  This clock runs at 1/8th the 'GT/s' speed of the QPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  JKT does not support dynamic link speeds, so this frequency is fixed.	0,1,2,3	0	null	0
+QPI LL	0x38	0x0	UNC_Q_CTO_COUNT	Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.	0,1,2,3	0	null	1
+QPI LL	0x13	0x2	UNC_Q_DIRECT2CORE.FAILURE_CREDITS	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.	0,1,2,3	0	null	0
+QPI LL	0x13	0x8	UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.	0,1,2,3	0	null	0
+QPI LL	0x13	0x4	UNC_Q_DIRECT2CORE.FAILURE_RBT	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.	0,1,2,3	0	null	0
+QPI LL	0x13	0x1	UNC_Q_DIRECT2CORE.SUCCESS	Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.	0,1,2,3	0	null	0
+QPI LL	0x12	0x0	UNC_Q_L1_POWER_CYCLES	Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.	0,1,2,3	0	null	0
+QPI LL	0x10	0x0	UNC_Q_RxL0P_POWER_CYCLES	Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.	0,1,2,3	0	null	0
+QPI LL	0xf	0x0	UNC_Q_RxL0_POWER_CYCLES	Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.	0,1,2,3	0	null	0
+QPI LL	0x9	0x0	UNC_Q_RxL_BYPASSED	Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.	0,1,2,3	0	null	0
+QPI LL	0x3	0x1	UNC_Q_RxL_CRC_ERRORS.LINK_INIT	Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).	0,1,2,3	0	null	0
+QPI LL	0x3	0x2	UNC_Q_RxL_CRC_ERRORS.NORMAL_OP	Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).	0,1,2,3	0	null	0
+QPI LL	0x1e	0x1	UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.	0,1,2,3	0	null	1
+QPI LL	0x1e	0x8	UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.	0,1,2,3	0	null	1
+QPI LL	0x1e	0x2	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.	0,1,2,3	0	null	1
+QPI LL	0x1e	0x4	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.	0,1,2,3	0	null	1
+QPI LL	0x1e	0x20	UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.	0,1,2,3	0	null	1
+QPI LL	0x1e	0x10	UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP	Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.	0,1,2,3	0	null	1
+QPI LL	0x1d	0x0	UNC_Q_RxL_CREDITS_CONSUMED_VNA	Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.	0,1,2,3	0	null	1
+QPI LL	0xa	0x0	UNC_Q_RxL_CYCLES_NE	Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.	0,1,2,3	0	null	0
+QPI LL	0x1	0x2	UNC_Q_RxL_FLITS_G0.DATA	Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.	0,1,2,3	0	null	0
+QPI LL	0x1	0x1	UNC_Q_RxL_FLITS_G0.IDLE	Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.	0,1,2,3	0	null	0
+QPI LL	0x1	0x4	UNC_Q_RxL_FLITS_G0.NON_DATA	Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.	0,1,2,3	0	null	0
+QPI LL	0x2	0x18	UNC_Q_RxL_FLITS_G1.DRS	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x2	0x8	UNC_Q_RxL_FLITS_G1.DRS_DATA	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x2	0x10	UNC_Q_RxL_FLITS_G1.DRS_NONDATA	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x2	0x6	UNC_Q_RxL_FLITS_G1.HOM	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x2	0x4	UNC_Q_RxL_FLITS_G1.HOM_NONREQ	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x2	0x2	UNC_Q_RxL_FLITS_G1.HOM_REQ	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x2	0x1	UNC_Q_RxL_FLITS_G1.SNP	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x3	0xc	UNC_Q_RxL_FLITS_G2.NCB	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x3	0x4	UNC_Q_RxL_FLITS_G2.NCB_DATA	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x3	0x8	UNC_Q_RxL_FLITS_G2.NCB_NONDATA	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x3	0x10	UNC_Q_RxL_FLITS_G2.NCS	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x3	0x1	UNC_Q_RxL_FLITS_G2.NDR_AD	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x3	0x2	UNC_Q_RxL_FLITS_G2.NDR_AK	Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x8	0x0	UNC_Q_RxL_INSERTS	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.	0,1,2,3	0	null	0
+QPI LL	0x9	0x0	UNC_Q_RxL_INSERTS_DRS	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.	0,1,2,3	0	null	1
+QPI LL	0xc	0x0	UNC_Q_RxL_INSERTS_HOM	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.	0,1,2,3	0	null	1
+QPI LL	0xa	0x0	UNC_Q_RxL_INSERTS_NCB	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.	0,1,2,3	0	null	1
+QPI LL	0xb	0x0	UNC_Q_RxL_INSERTS_NCS	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.	0,1,2,3	0	null	1
+QPI LL	0xe	0x0	UNC_Q_RxL_INSERTS_NDR	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.	0,1,2,3	0	null	1
+QPI LL	0xd	0x0	UNC_Q_RxL_INSERTS_SNP	Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.	0,1,2,3	0	null	1
+QPI LL	0xb	0x0	UNC_Q_RxL_OCCUPANCY	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.	0,1,2,3	0	null	0
+QPI LL	0x15	0x0	UNC_Q_RxL_OCCUPANCY_DRS	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.	0,1,2,3	0	null	1
+QPI LL	0x18	0x0	UNC_Q_RxL_OCCUPANCY_HOM	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.	0,1,2,3	0	null	1
+QPI LL	0x16	0x0	UNC_Q_RxL_OCCUPANCY_NCB	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.	0,1,2,3	0	null	1
+QPI LL	0x17	0x0	UNC_Q_RxL_OCCUPANCY_NCS	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.	0,1,2,3	0	null	1
+QPI LL	0x1a	0x0	UNC_Q_RxL_OCCUPANCY_NDR	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.	0,1,2,3	0	null	1
+QPI LL	0x19	0x0	UNC_Q_RxL_OCCUPANCY_SNP	Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.	0,1,2,3	0	null	1
+QPI LL	0x35	0x1	UNC_Q_RxL_STALLS.BGF_DRS	Number of stalls trying to send to R3QPI.	0,1,2,3	0	null	0
+QPI LL	0x35	0x8	UNC_Q_RxL_STALLS.BGF_HOM	Number of stalls trying to send to R3QPI.	0,1,2,3	0	null	0
+QPI LL	0x35	0x2	UNC_Q_RxL_STALLS.BGF_NCB	Number of stalls trying to send to R3QPI.	0,1,2,3	0	null	0
+QPI LL	0x35	0x4	UNC_Q_RxL_STALLS.BGF_NCS	Number of stalls trying to send to R3QPI.	0,1,2,3	0	null	0
+QPI LL	0x35	0x20	UNC_Q_RxL_STALLS.BGF_NDR	Number of stalls trying to send to R3QPI.	0,1,2,3	0	null	0
+QPI LL	0x35	0x10	UNC_Q_RxL_STALLS.BGF_SNP	Number of stalls trying to send to R3QPI.	0,1,2,3	0	null	0
+QPI LL	0x35	0x40	UNC_Q_RxL_STALLS.EGRESS_CREDITS	Number of stalls trying to send to R3QPI.	0,1,2,3	0	null	0
+QPI LL	0x35	0x80	UNC_Q_RxL_STALLS.GV	Number of stalls trying to send to R3QPI.	0,1,2,3	0	null	0
+QPI LL	0xd	0x0	UNC_Q_TxL0P_POWER_CYCLES	Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.	0,1,2,3	0	null	0
+QPI LL	0xc	0x0	UNC_Q_TxL0_POWER_CYCLES	Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.	0,1,2,3	0	null	0
+QPI LL	0x5	0x0	UNC_Q_TxL_BYPASSED	Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.	0,1,2,3	0	null	0
+QPI LL	0x2	0x2	UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL	Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.	0,1,2,3	0	null	0
+QPI LL	0x2	0x1	UNC_Q_TxL_CRC_NO_CREDITS.FULL	Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.	0,1,2,3	0	null	0
+QPI LL	0x6	0x0	UNC_Q_TxL_CYCLES_NE	Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.	0,1,2,3	0	null	0
+QPI LL	0x0	0x2	UNC_Q_TxL_FLITS_G0.DATA	Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.	0,1,2,3	0	null	0
+QPI LL	0x0	0x1	UNC_Q_TxL_FLITS_G0.IDLE	Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.	0,1,2,3	0	null	0
+QPI LL	0x0	0x4	UNC_Q_TxL_FLITS_G0.NON_DATA	Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.	0,1,2,3	0	null	0
+QPI LL	0x0	0x18	UNC_Q_TxL_FLITS_G1.DRS	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x0	0x8	UNC_Q_TxL_FLITS_G1.DRS_DATA	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x0	0x10	UNC_Q_TxL_FLITS_G1.DRS_NONDATA	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x0	0x6	UNC_Q_TxL_FLITS_G1.HOM	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x0	0x4	UNC_Q_TxL_FLITS_G1.HOM_NONREQ	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x0	0x2	UNC_Q_TxL_FLITS_G1.HOM_REQ	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x0	0x1	UNC_Q_TxL_FLITS_G1.SNP	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x1	0xc	UNC_Q_TxL_FLITS_G2.NCB	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x1	0x4	UNC_Q_TxL_FLITS_G2.NCB_DATA	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x1	0x8	UNC_Q_TxL_FLITS_G2.NCB_NONDATA	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x1	0x10	UNC_Q_TxL_FLITS_G2.NCS	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x1	0x1	UNC_Q_TxL_FLITS_G2.NDR_AD	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x1	0x2	UNC_Q_TxL_FLITS_G2.NDR_AK	Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.	0,1,2,3	0	null	1
+QPI LL	0x4	0x0	UNC_Q_TxL_INSERTS	Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.	0,1,2,3	0	null	0
+QPI LL	0x7	0x0	UNC_Q_TxL_OCCUPANCY	Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.	0,1,2,3	0	null	0
+QPI LL	0x1c	0x0	UNC_Q_VNA_CREDIT_RETURNS	Number of VNA credits returned.	0,1,2,3	0	null	1
+QPI LL	0x1b	0x0	UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY	Number of VNA credits in the Rx side that are waitng to be returned back across the link.	0,1,2,3	0	null	1
+R3QPI	0x1	0x0	UNC_R3_CLOCKTICKS	Counts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.	0,1,2	0	null	0
+R3QPI	0x20	0x8	UNC_R3_IIO_CREDITS_ACQUIRED.DRS	Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x20	0x10	UNC_R3_IIO_CREDITS_ACQUIRED.NCB	Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x20	0x20	UNC_R3_IIO_CREDITS_ACQUIRED.NCS	Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x21	0x8	UNC_R3_IIO_CREDITS_REJECT.DRS	Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x21	0x10	UNC_R3_IIO_CREDITS_REJECT.NCB	Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x21	0x20	UNC_R3_IIO_CREDITS_REJECT.NCS	Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x22	0x8	UNC_R3_IIO_CREDITS_USED.DRS	Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x22	0x10	UNC_R3_IIO_CREDITS_USED.NCB	Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x22	0x20	UNC_R3_IIO_CREDITS_USED.NCS	Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO.  There is one credit for each of these three message classes (three credits total).  NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions).  This event can only track one message class at a time.	0,1	0	null	0
+R3QPI	0x7	0x4	UNC_R3_RING_AD_USED.CCW_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x7	0x8	UNC_R3_RING_AD_USED.CCW_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x7	0x1	UNC_R3_RING_AD_USED.CW_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x7	0x2	UNC_R3_RING_AD_USED.CW_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x8	0x4	UNC_R3_RING_AK_USED.CCW_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.	0,1,2	0	null	0
+R3QPI	0x8	0x8	UNC_R3_RING_AK_USED.CCW_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.	0,1,2	0	null	0
+R3QPI	0x8	0x1	UNC_R3_RING_AK_USED.CW_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.	0,1,2	0	null	0
+R3QPI	0x8	0x2	UNC_R3_RING_AK_USED.CW_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.	0,1,2	0	null	0
+R3QPI	0x9	0x4	UNC_R3_RING_BL_USED.CCW_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x9	0x8	UNC_R3_RING_BL_USED.CCW_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x9	0x1	UNC_R3_RING_BL_USED.CW_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0x9	0x2	UNC_R3_RING_BL_USED.CW_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2	0	null	0
+R3QPI	0xa	0xf	UNC_R3_RING_IV_USED.ANY	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.	0,1,2	0	null	0
+R3QPI	0x12	0x1	UNC_R3_RxR_BYPASSED.AD	Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.	0,1	0	null	0
+R3QPI	0x10	0x8	UNC_R3_RxR_CYCLES_NE.DRS	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x10	0x1	UNC_R3_RxR_CYCLES_NE.HOM	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x10	0x10	UNC_R3_RxR_CYCLES_NE.NCB	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x10	0x20	UNC_R3_RxR_CYCLES_NE.NCS	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x10	0x4	UNC_R3_RxR_CYCLES_NE.NDR	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x10	0x2	UNC_R3_RxR_CYCLES_NE.SNP	Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x11	0x8	UNC_R3_RxR_INSERTS.DRS	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x11	0x1	UNC_R3_RxR_INSERTS.HOM	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x11	0x10	UNC_R3_RxR_INSERTS.NCB	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x11	0x20	UNC_R3_RxR_INSERTS.NCS	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x11	0x4	UNC_R3_RxR_INSERTS.NDR	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x11	0x2	UNC_R3_RxR_INSERTS.SNP	Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R3QPI	0x13	0x8	UNC_R3_RxR_OCCUPANCY.DRS	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.	0	0	null	0
+R3QPI	0x13	0x1	UNC_R3_RxR_OCCUPANCY.HOM	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.	0	0	null	0
+R3QPI	0x13	0x10	UNC_R3_RxR_OCCUPANCY.NCB	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.	0	0	null	0
+R3QPI	0x13	0x20	UNC_R3_RxR_OCCUPANCY.NCS	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.	0	0	null	0
+R3QPI	0x13	0x4	UNC_R3_RxR_OCCUPANCY.NDR	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.	0	0	null	0
+R3QPI	0x13	0x2	UNC_R3_RxR_OCCUPANCY.SNP	Accumulates the occupancy of a given QPI Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.	0	0	null	0
+R3QPI	0x37	0x8	UNC_R3_VN0_CREDITS_REJECT.DRS	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.	0,1	0	null	0
+R3QPI	0x37	0x1	UNC_R3_VN0_CREDITS_REJECT.HOM	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.	0,1	0	null	0
+R3QPI	0x37	0x10	UNC_R3_VN0_CREDITS_REJECT.NCB	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.	0,1	0	null	0
+R3QPI	0x37	0x20	UNC_R3_VN0_CREDITS_REJECT.NCS	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.	0,1	0	null	0
+R3QPI	0x37	0x4	UNC_R3_VN0_CREDITS_REJECT.NDR	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.	0,1	0	null	0
+R3QPI	0x37	0x2	UNC_R3_VN0_CREDITS_REJECT.SNP	Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.	0,1	0	null	0
+R3QPI	0x36	0x8	UNC_R3_VN0_CREDITS_USED.DRS	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.	0,1	0	null	0
+R3QPI	0x36	0x1	UNC_R3_VN0_CREDITS_USED.HOM	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.	0,1	0	null	0
+R3QPI	0x36	0x10	UNC_R3_VN0_CREDITS_USED.NCB	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.	0,1	0	null	0
+R3QPI	0x36	0x20	UNC_R3_VN0_CREDITS_USED.NCS	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.	0,1	0	null	0
+R3QPI	0x36	0x4	UNC_R3_VN0_CREDITS_USED.NDR	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.	0,1	0	null	0
+R3QPI	0x36	0x2	UNC_R3_VN0_CREDITS_USED.SNP	Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.	0,1	0	null	0
+R3QPI	0x33	0x0	UNC_R3_VNA_CREDITS_ACQUIRED	Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transfered).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transfered in a given message class using an qfclk event.	0,1	0	null	0
+R3QPI	0x34	0x8	UNC_R3_VNA_CREDITS_REJECT.DRS	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.	0,1	0	null	0
+R3QPI	0x34	0x1	UNC_R3_VNA_CREDITS_REJECT.HOM	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.	0,1	0	null	0
+R3QPI	0x34	0x10	UNC_R3_VNA_CREDITS_REJECT.NCB	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.	0,1	0	null	0
+R3QPI	0x34	0x20	UNC_R3_VNA_CREDITS_REJECT.NCS	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.	0,1	0	null	0
+R3QPI	0x34	0x4	UNC_R3_VNA_CREDITS_REJECT.NDR	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.	0,1	0	null	0
+R3QPI	0x34	0x2	UNC_R3_VNA_CREDITS_REJECT.SNP	Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.	0,1	0	null	0
+R3QPI	0x31	0x0	UNC_R3_VNA_CREDIT_CYCLES_OUT	Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel.  Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit.  Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth.	0,1	0	null	0
+R3QPI	0x32	0x0	UNC_R3_VNA_CREDIT_CYCLES_USED	Number of QPI uclk cycles with one or more VNA credits in use.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.	0,1	0	null	0
+R2PCIe	0x1	0x0	UNC_R2_CLOCKTICKS	Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.	0,1,2,3	0	null	0
+R2PCIe	0x33	0x8	UNC_R2_IIO_CREDITS_ACQUIRED.DRS	Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x33	0x10	UNC_R2_IIO_CREDITS_ACQUIRED.NCB	Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x33	0x20	UNC_R2_IIO_CREDITS_ACQUIRED.NCS	Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x34	0x8	UNC_R2_IIO_CREDITS_REJECT.DRS	Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x34	0x10	UNC_R2_IIO_CREDITS_REJECT.NCB	Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x34	0x20	UNC_R2_IIO_CREDITS_REJECT.NCS	Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x32	0x8	UNC_R2_IIO_CREDITS_USED.DRS	Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x32	0x10	UNC_R2_IIO_CREDITS_USED.NCB	Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x32	0x20	UNC_R2_IIO_CREDITS_USED.NCS	Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).	0,1	0	null	0
+R2PCIe	0x7	0x4	UNC_R2_RING_AD_USED.CCW_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x7	0x8	UNC_R2_RING_AD_USED.CCW_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x7	0x1	UNC_R2_RING_AD_USED.CW_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x7	0x2	UNC_R2_RING_AD_USED.CW_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x8	0x4	UNC_R2_RING_AK_USED.CCW_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x8	0x8	UNC_R2_RING_AK_USED.CCW_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x8	0x1	UNC_R2_RING_AK_USED.CW_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x8	0x2	UNC_R2_RING_AK_USED.CW_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x9	0x4	UNC_R2_RING_BL_USED.CCW_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x9	0x8	UNC_R2_RING_BL_USED.CCW_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x9	0x1	UNC_R2_RING_BL_USED.CW_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0x9	0x2	UNC_R2_RING_BL_USED.CW_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+R2PCIe	0xa	0xf	UNC_R2_RING_IV_USED.ANY	Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.	0,1,2,3	0	null	0
+R2PCIe	0x12	0x0	UNC_R2_RxR_AK_BOUNCES	Counts the number of times when a request destined for the AK ingress bounced.	0	0	null	0
+R2PCIe	0x10	0x8	UNC_R2_RxR_CYCLES_NE.DRS	Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R2PCIe	0x10	0x10	UNC_R2_RxR_CYCLES_NE.NCB	Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R2PCIe	0x10	0x20	UNC_R2_RxR_CYCLES_NE.NCS	Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.	0,1	0	null	0
+R2PCIe	0x25	0x1	UNC_R2_TxR_CYCLES_FULL.AD	Counts the number of cycles when the R2PCIe Egress buffer is full.	0	0	null	0
+R2PCIe	0x25	0x2	UNC_R2_TxR_CYCLES_FULL.AK	Counts the number of cycles when the R2PCIe Egress buffer is full.	0	0	null	0
+R2PCIe	0x25	0x4	UNC_R2_TxR_CYCLES_FULL.BL	Counts the number of cycles when the R2PCIe Egress buffer is full.	0	0	null	0
+R2PCIe	0x23	0x1	UNC_R2_TxR_CYCLES_NE.AD	Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.	0	0	null	0
+R2PCIe	0x23	0x2	UNC_R2_TxR_CYCLES_NE.AK	Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.	0	0	null	0
+R2PCIe	0x23	0x4	UNC_R2_TxR_CYCLES_NE.BL	Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.	0	0	null	0
+R2PCIe	0x26	0x1	UNC_R2_TxR_NACKS.AD	Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.	0,1	0	null	0
+R2PCIe	0x26	0x2	UNC_R2_TxR_NACKS.AK	Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.	0,1	0	null	0
+R2PCIe	0x26	0x4	UNC_R2_TxR_NACKS.BL	Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.	0,1	0	null	0
+HA	0x20	0x3	UNC_H_ADDR_OPC_MATCH.FILT	tbd	0,1,2,3	0	HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]	0
+HA	0x14	0x2	UNC_H_BYPASS_IMC.NOT_TAKEN	Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.	0,1,2,3	0	null	0
+HA	0x14	0x1	UNC_H_BYPASS_IMC.TAKEN	Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.	0,1,2,3	0	null	0
+HA	0x0	0x0	UNC_H_CLOCKTICKS	Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.	0,1,2,3	0	null	0
+HA	0xb	0x2	UNC_H_CONFLICT_CYCLES.CONFLICT	tbd	0,1,2,3	0	null	0
+HA	0xb	0x1	UNC_H_CONFLICT_CYCLES.NO_CONFLICT	tbd	0,1,2,3	0	null	0
+HA	0x11	0x0	UNC_H_DIRECT2CORE_COUNT	Number of Direct2Core messages sent	0,1,2,3	0	null	0
+HA	0x12	0x0	UNC_H_DIRECT2CORE_CYCLES_DISABLED	Number of cycles in which Direct2Core was disabled	0,1,2,3	0	null	0
+HA	0x13	0x0	UNC_H_DIRECT2CORE_TXN_OVERRIDE	Number of Reads where Direct2Core overridden	0,1,2,3	0	null	0
+HA	0xc	0x2	UNC_H_DIRECTORY_LOOKUP.NO_SNP	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.	0,1,2,3	0	null	0
+HA	0xc	0x1	UNC_H_DIRECTORY_LOOKUP.SNP	Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.	0,1,2,3	0	null	0
+HA	0xd	0x3	UNC_H_DIRECTORY_UPDATE.ANY	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0	null	0
+HA	0xd	0x2	UNC_H_DIRECTORY_UPDATE.CLEAR	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0	null	0
+HA	0xd	0x1	UNC_H_DIRECTORY_UPDATE.SET	Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.	0,1,2,3	0	null	0
+HA	0x22	0x1	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0	Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.	0,1,2,3	0	null	0
+HA	0x22	0x2	UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1	Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.	0,1,2,3	0	null	0
+HA	0x22	0x4	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0	Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.	0,1,2,3	0	null	0
+HA	0x22	0x8	UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1	Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.	0,1,2,3	0	null	0
+HA	0x1e	0x0	UNC_H_IMC_RETRY	tbd	0,1,2,3	0	null	0
+HA	0x1a	0xf	UNC_H_IMC_WRITES.ALL	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0	null	0
+HA	0x1a	0x1	UNC_H_IMC_WRITES.FULL	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0	null	0
+HA	0x1a	0x4	UNC_H_IMC_WRITES.FULL_ISOCH	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0	null	0
+HA	0x1a	0x2	UNC_H_IMC_WRITES.PARTIAL	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0	null	0
+HA	0x1a	0x8	UNC_H_IMC_WRITES.PARTIAL_ISOCH	Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.	0,1,2,3	0	null	0
+HA	0x1	0x3	UNC_H_REQUESTS.READS	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).	0,1,2,3	0	null	0
+HA	0x1	0xc	UNC_H_REQUESTS.WRITES	Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).	0,1,2,3	0	null	0
+HA	0x3e	0x4	UNC_H_RING_AD_USED.CCW_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3e	0x8	UNC_H_RING_AD_USED.CCW_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3e	0x1	UNC_H_RING_AD_USED.CW_EVEN	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3e	0x2	UNC_H_RING_AD_USED.CW_ODD	Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3f	0x4	UNC_H_RING_AK_USED.CCW_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3f	0x8	UNC_H_RING_AK_USED.CCW_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3f	0x1	UNC_H_RING_AK_USED.CW_EVEN	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x3f	0x2	UNC_H_RING_AK_USED.CW_ODD	Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x40	0x4	UNC_H_RING_BL_USED.CCW_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x40	0x8	UNC_H_RING_BL_USED.CCW_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x40	0x1	UNC_H_RING_BL_USED.CW_EVEN	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x40	0x2	UNC_H_RING_BL_USED.CW_ODD	Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.	0,1,2,3	0	null	0
+HA	0x15	0x1	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0	Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x15	0x2	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1	Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x15	0x4	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2	Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x15	0x8	UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3	Counts the number of cycles when there are no 'regular' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x16	0x1	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0	Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x16	0x2	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1	Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x16	0x4	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2	Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x16	0x8	UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3	Counts the number of cycles when there are no 'special' credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and 'special' requests such as ISOCH reads.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x1b	0x1	UNC_H_TAD_REQUESTS_G0.REGION0	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1b	0x2	UNC_H_TAD_REQUESTS_G0.REGION1	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1b	0x4	UNC_H_TAD_REQUESTS_G0.REGION2	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1b	0x8	UNC_H_TAD_REQUESTS_G0.REGION3	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1b	0x10	UNC_H_TAD_REQUESTS_G0.REGION4	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1b	0x20	UNC_H_TAD_REQUESTS_G0.REGION5	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1b	0x40	UNC_H_TAD_REQUESTS_G0.REGION6	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1b	0x80	UNC_H_TAD_REQUESTS_G0.REGION7	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1c	0x4	UNC_H_TAD_REQUESTS_G1.REGION10	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1c	0x8	UNC_H_TAD_REQUESTS_G1.REGION11	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1c	0x1	UNC_H_TAD_REQUESTS_G1.REGION8	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x1c	0x2	UNC_H_TAD_REQUESTS_G1.REGION9	Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for 'Monroe' systems that use the TAD to enable individual channels to enter self-refresh to save power.	0,1,2,3	0	null	0
+HA	0x6	0x3	UNC_H_TRACKER_INSERTS.ALL	Counts the number of allocations into the local HA tracker pool.  This can be used in conjunction with the occupancy accumulation event in order to calculate average latency.  One cannot filter between reads and writes.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.	0,1,2,3	0	null	0
+HA	0xf	0x1	UNC_H_TxR_AD.NDR	Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.	0,1,2,3	0	null	0
+HA	0xf	0x2	UNC_H_TxR_AD.SNP	Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.	0,1,2,3	0	null	0
+HA	0x2a	0x3	UNC_H_TxR_AD_CYCLES_FULL.ALL	AD Egress Full	0,1,2,3	0	null	0
+HA	0x2a	0x1	UNC_H_TxR_AD_CYCLES_FULL.SCHED0	AD Egress Full	0,1,2,3	0	null	0
+HA	0x2a	0x2	UNC_H_TxR_AD_CYCLES_FULL.SCHED1	AD Egress Full	0,1,2,3	0	null	0
+HA	0x29	0x3	UNC_H_TxR_AD_CYCLES_NE.ALL	AD Egress Not Empty	0,1,2,3	0	null	0
+HA	0x29	0x1	UNC_H_TxR_AD_CYCLES_NE.SCHED0	AD Egress Not Empty	0,1,2,3	0	null	0
+HA	0x29	0x2	UNC_H_TxR_AD_CYCLES_NE.SCHED1	AD Egress Not Empty	0,1,2,3	0	null	0
+HA	0x27	0x3	UNC_H_TxR_AD_INSERTS.ALL	AD Egress Allocations	0,1,2,3	0	null	0
+HA	0x27	0x1	UNC_H_TxR_AD_INSERTS.SCHED0	AD Egress Allocations	0,1,2,3	0	null	0
+HA	0x27	0x2	UNC_H_TxR_AD_INSERTS.SCHED1	AD Egress Allocations	0,1,2,3	0	null	0
+HA	0x28	0x3	UNC_H_TxR_AD_OCCUPANCY.ALL	AD Egress Occupancy	0,1,2,3	0	null	0
+HA	0x28	0x1	UNC_H_TxR_AD_OCCUPANCY.SCHED0	AD Egress Occupancy	0,1,2,3	0	null	0
+HA	0x28	0x2	UNC_H_TxR_AD_OCCUPANCY.SCHED1	AD Egress Occupancy	0,1,2,3	0	null	0
+HA	0x32	0x3	UNC_H_TxR_AK_CYCLES_FULL.ALL	AK Egress Full	0,1,2,3	0	null	0
+HA	0x32	0x1	UNC_H_TxR_AK_CYCLES_FULL.SCHED0	AK Egress Full	0,1,2,3	0	null	0
+HA	0x32	0x2	UNC_H_TxR_AK_CYCLES_FULL.SCHED1	AK Egress Full	0,1,2,3	0	null	0
+HA	0x31	0x3	UNC_H_TxR_AK_CYCLES_NE.ALL	AK Egress Not Empty	0,1,2,3	0	null	0
+HA	0x31	0x1	UNC_H_TxR_AK_CYCLES_NE.SCHED0	AK Egress Not Empty	0,1,2,3	0	null	0
+HA	0x31	0x2	UNC_H_TxR_AK_CYCLES_NE.SCHED1	AK Egress Not Empty	0,1,2,3	0	null	0
+HA	0x2f	0x3	UNC_H_TxR_AK_INSERTS.ALL	AK Egress Allocations	0,1,2,3	0	null	0
+HA	0x2f	0x1	UNC_H_TxR_AK_INSERTS.SCHED0	AK Egress Allocations	0,1,2,3	0	null	0
+HA	0x2f	0x2	UNC_H_TxR_AK_INSERTS.SCHED1	AK Egress Allocations	0,1,2,3	0	null	0
+HA	0xe	0x0	UNC_H_TxR_AK_NDR	Counts the number of outbound NDR transactions sent on the AK ring.  NDR stands for 'non-data response' and is generally used for completions that do not include data.  AK NDR is used for messages to the local socket.	0,1,2,3	0	null	0
+HA	0x30	0x3	UNC_H_TxR_AK_OCCUPANCY.ALL	AK Egress Occupancy	0,1,2,3	0	null	0
+HA	0x30	0x1	UNC_H_TxR_AK_OCCUPANCY.SCHED0	AK Egress Occupancy	0,1,2,3	0	null	0
+HA	0x30	0x2	UNC_H_TxR_AK_OCCUPANCY.SCHED1	AK Egress Occupancy	0,1,2,3	0	null	0
+HA	0x10	0x1	UNC_H_TxR_BL.DRS_CACHE	Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.	0,1,2,3	0	null	0
+HA	0x10	0x2	UNC_H_TxR_BL.DRS_CORE	Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.	0,1,2,3	0	null	0
+HA	0x10	0x4	UNC_H_TxR_BL.DRS_QPI	Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.	0,1,2,3	0	null	0
+HA	0x36	0x3	UNC_H_TxR_BL_CYCLES_FULL.ALL	BL Egress Full	0,1,2,3	0	null	0
+HA	0x36	0x1	UNC_H_TxR_BL_CYCLES_FULL.SCHED0	BL Egress Full	0,1,2,3	0	null	0
+HA	0x36	0x2	UNC_H_TxR_BL_CYCLES_FULL.SCHED1	BL Egress Full	0,1,2,3	0	null	0
+HA	0x35	0x3	UNC_H_TxR_BL_CYCLES_NE.ALL	BL Egress Not Empty	0,1,2,3	0	null	0
+HA	0x35	0x1	UNC_H_TxR_BL_CYCLES_NE.SCHED0	BL Egress Not Empty	0,1,2,3	0	null	0
+HA	0x35	0x2	UNC_H_TxR_BL_CYCLES_NE.SCHED1	BL Egress Not Empty	0,1,2,3	0	null	0
+HA	0x33	0x3	UNC_H_TxR_BL_INSERTS.ALL	BL Egress Allocations	0,1,2,3	0	null	0
+HA	0x33	0x1	UNC_H_TxR_BL_INSERTS.SCHED0	BL Egress Allocations	0,1,2,3	0	null	0
+HA	0x33	0x2	UNC_H_TxR_BL_INSERTS.SCHED1	BL Egress Allocations	0,1,2,3	0	null	0
+HA	0x34	0x3	UNC_H_TxR_BL_OCCUPANCY.ALL	BL Egress Occupancy	0,1,2,3	0	null	0
+HA	0x34	0x1	UNC_H_TxR_BL_OCCUPANCY.SCHED0	BL Egress Occupancy	0,1,2,3	0	null	0
+HA	0x34	0x2	UNC_H_TxR_BL_OCCUPANCY.SCHED1	BL Egress Occupancy	0,1,2,3	0	null	0
+HA	0x18	0x1	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0	Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x18	0x2	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1	Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x18	0x4	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2	Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x18	0x8	UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3	Counts the number of cycles when there are no 'regular' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x19	0x1	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0	Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x19	0x2	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1	Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x19	0x4	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2	Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+HA	0x19	0x8	UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3	Counts the number of cycles when there are no 'special' credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and 'special' requests such as ISOCH writes.  This count only tracks the 'special' credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.	0,1,2,3	0	null	0
+iMC	0x1	0x0	UNC_M_ACT_COUNT	Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.	0,1,2,3	0	null	0
+iMC	0x4	0xf	UNC_M_CAS_COUNT.ALL	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0	null	0
+iMC	0x4	0x3	UNC_M_CAS_COUNT.RD	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0	null	0
+iMC	0x4	0x1	UNC_M_CAS_COUNT.RD_REG	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0	null	0
+iMC	0x4	0x2	UNC_M_CAS_COUNT.RD_UNDERFILL	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0	null	0
+iMC	0x4	0xc	UNC_M_CAS_COUNT.WR	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0	null	0
+iMC	0x4	0x8	UNC_M_CAS_COUNT.WR_RMM	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0	null	0
+iMC	0x4	0x4	UNC_M_CAS_COUNT.WR_WMM	DRAM RD_CAS and WR_CAS Commands	0,1,2,3	0	null	0
+iMC	0x6	0x0	UNC_M_DRAM_PRE_ALL	Counts the number of times that the precharge all command was sent.	0,1,2,3	0	null	0
+iMC	0x5	0x4	UNC_M_DRAM_REFRESH.HIGH	Counts the number of refreshes issued.	0,1,2,3	0	null	0
+iMC	0x5	0x2	UNC_M_DRAM_REFRESH.PANIC	Counts the number of refreshes issued.	0,1,2,3	0	null	0
+iMC	0x9	0x0	UNC_M_ECC_CORRECTABLE_ERRORS	Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.	0,1,2,3	0	null	0
+iMC	0x7	0x8	UNC_M_MAJOR_MODES.ISOCH	Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.	0,1,2,3	0	null	0
+iMC	0x7	0x4	UNC_M_MAJOR_MODES.PARTIAL	Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.	0,1,2,3	0	null	0
+iMC	0x7	0x1	UNC_M_MAJOR_MODES.READ	Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.	0,1,2,3	0	null	0
+iMC	0x7	0x2	UNC_M_MAJOR_MODES.WRITE	Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.	0,1,2,3	0	null	0
+iMC	0x84	0x0	UNC_M_POWER_CHANNEL_DLLOFF	Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.	0,1,2,3	0	null	0
+iMC	0x85	0x0	UNC_M_POWER_CHANNEL_PPD	Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.	0,1,2,3	0	null	0
+iMC	0x83	0x1	UNC_M_POWER_CKE_CYCLES.RANK0	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0	null	0
+iMC	0x83	0x2	UNC_M_POWER_CKE_CYCLES.RANK1	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0	null	0
+iMC	0x83	0x4	UNC_M_POWER_CKE_CYCLES.RANK2	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0	null	0
+iMC	0x83	0x8	UNC_M_POWER_CKE_CYCLES.RANK3	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0	null	0
+iMC	0x83	0x10	UNC_M_POWER_CKE_CYCLES.RANK4	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0	null	0
+iMC	0x83	0x20	UNC_M_POWER_CKE_CYCLES.RANK5	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0	null	0
+iMC	0x83	0x40	UNC_M_POWER_CKE_CYCLES.RANK6	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0	null	0
+iMC	0x83	0x80	UNC_M_POWER_CKE_CYCLES.RANK7	Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).	0,1,2,3	0	null	0
+iMC	0x86	0x0	UNC_M_POWER_CRITICAL_THROTTLE_CYCLES	Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.	0,1,2,3	0	null	0
+iMC	0x43	0x0	UNC_M_POWER_SELF_REFRESH	Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.	0,1,2,3	0	null	0
+iMC	0x41	0x1	UNC_M_POWER_THROTTLE_CYCLES.RANK0	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0	null	0
+iMC	0x41	0x2	UNC_M_POWER_THROTTLE_CYCLES.RANK1	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0	null	0
+iMC	0x41	0x4	UNC_M_POWER_THROTTLE_CYCLES.RANK2	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0	null	0
+iMC	0x41	0x8	UNC_M_POWER_THROTTLE_CYCLES.RANK3	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0	null	0
+iMC	0x41	0x10	UNC_M_POWER_THROTTLE_CYCLES.RANK4	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0	null	0
+iMC	0x41	0x20	UNC_M_POWER_THROTTLE_CYCLES.RANK5	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0	null	0
+iMC	0x41	0x40	UNC_M_POWER_THROTTLE_CYCLES.RANK6	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0	null	0
+iMC	0x41	0x80	UNC_M_POWER_THROTTLE_CYCLES.RANK7	Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.	0,1,2,3	0	null	0
+iMC	0x8	0x1	UNC_M_PREEMPTION.RD_PREEMPT_RD	Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.	0,1,2,3	0	null	0
+iMC	0x8	0x2	UNC_M_PREEMPTION.RD_PREEMPT_WR	Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.	0,1,2,3	0	null	0
+iMC	0x2	0x2	UNC_M_PRE_COUNT.PAGE_CLOSE	Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	0	null	0
+iMC	0x2	0x1	UNC_M_PRE_COUNT.PAGE_MISS	Counts the number of DRAM Precharge commands sent on this channel.	0,1,2,3	0	null	0
+iMC	0x12	0x0	UNC_M_RPQ_CYCLES_FULL	Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.	0,1,2,3	0	null	0
+iMC	0x11	0x0	UNC_M_RPQ_CYCLES_NE	Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.	0,1,2,3	0	null	0
+iMC	0x10	0x0	UNC_M_RPQ_INSERTS	Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.	0,1,2,3	0	null	0
+iMC	0x80	0x0	UNC_M_RPQ_OCCUPANCY	Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.	0,1,2,3	0	null	0
+iMC	0x22	0x0	UNC_M_WPQ_CYCLES_FULL	Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.	0,1,2,3	0	null	0
+iMC	0x21	0x0	UNC_M_WPQ_CYCLES_NE	Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.	0,1,2,3	0	null	0
+iMC	0x20	0x0	UNC_M_WPQ_INSERTS	Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.	0,1,2,3	0	null	0
+iMC	0x81	0x0	UNC_M_WPQ_OCCUPANCY	Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.	0,1,2,3	0	null	0
+iMC	0x23	0x0	UNC_M_WPQ_READ_HIT	Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.	0,1,2,3	0	null	0
+iMC	0x24	0x0	UNC_M_WPQ_WRITE_HIT	Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.	0,1,2,3	0	null	0
+UBOX	0x0	0x0	UNC_U_CLOCKTICKS	tbd	0	0	null	0
+iMC	0x0	0x0	UNC_M_CLOCKTICKS	Uncore Fixed Counter - uclks	0,1,2,3	0x0	null	0
+IRP	0x17	0x1	UNC_I_ADDRESS_MATCH.STALL_COUNT	Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.	0,1	0	null	0
+IRP	0x17	0x2	UNC_I_ADDRESS_MATCH.MERGE_COUNT	Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.	0,1	0	null	0
+IRP	0x14	0x1	UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY	Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.	0,1	0	null	0
+IRP	0x14	0x2	UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE	Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore.  These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data.  The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released.  Note that a single tickle can result in multiple decrements.	0,1	0	null	0
+IRP	0x13	0x1	UNC_I_CACHE_OWN_OCCUPANCY.ANY	Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.	0,1	0	null	0
+IRP	0x13	0x2	UNC_I_CACHE_OWN_OCCUPANCY.SOURCE	Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle.  This can be used with the write transaction count to calculate the average write latency in the uncore.  The occupancy increments when a write request is issued, and decrements when the data is returned.	0,1	0	null	0
+IRP	0x10	0x1	UNC_I_CACHE_READ_OCCUPANCY.ANY	Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.	0,1	0	null	0
+IRP	0x10	0x2	UNC_I_CACHE_READ_OCCUPANCY.SOURCE	Accumulates the number of reads that are outstanding in the uncore in each cycle.  This can be used with the read transaction count to calculate the average read latency in the uncore.  The occupancy increments when a read request is issued, and decrements when the data is returned.	0,1	0	null	0
+IRP	0x12	0x1	UNC_I_CACHE_TOTAL_OCCUPANCY.ANY	Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.	0,1	0	null	0
+IRP	0x12	0x2	UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE	Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.	0,1	0	null	0
+IRP	0x11	0x1	UNC_I_CACHE_WRITE_OCCUPANCY.ANY	Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.	0,1	0	null	0
+IRP	0x11	0x2	UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE	Accumulates the number of writes (and write prefetches)  that are outstanding in the uncore in each cycle.  This can be used with the transaction count event to calculate the average latency in the uncore.  The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.	0,1	0	null	0
+IRP	0x0	0x0	UNC_I_CLOCKTICKS	Number of clocks in the IRP.	0,1	0	null	0
+IRP	0xB	0x0	UNC_I_RxR_AK_CYCLES_FULL	Counts the number of cycles when the AK Ingress is full.  This queue is where the IRP receives responses from R2PCIe (the ring).	0,1	0	null	0
+IRP	0xA	0x0	UNC_I_RxR_AK_INSERTS	Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).	0,1	0	null	0
+IRP	0xC	0x0	UNC_I_RxR_AK_OCCUPANCY	Accumulates the occupancy of the AK Ingress in each cycles.  This queue is where the IRP receives responses from R2PCIe (the ring).	0,1	0	null	0
+IRP	0x4	0x0	UNC_I_RxR_BL_DRS_CYCLES_FULL	Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x1	0x0	UNC_I_RxR_BL_DRS_INSERTS	Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x7	0x0	UNC_I_RxR_BL_DRS_OCCUPANCY	Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x5	0x0	UNC_I_RxR_BL_NCB_CYCLES_FULL	Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x2	0x0	UNC_I_RxR_BL_NCB_INSERTS	Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x8	0x0	UNC_I_RxR_BL_NCB_OCCUPANCY	Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x6	0x0	UNC_I_RxR_BL_NCS_CYCLES_FULL	Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x3	0x0	UNC_I_RxR_BL_NCS_INSERTS	Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x9	0x0	UNC_I_RxR_BL_NCS_OCCUPANCY	Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.	0,1	0	null	0
+IRP	0x16	0x1	UNC_I_TICKLES.LOST_OWNERSHIP	Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.	0,1	0	null	0
+IRP	0x16	0x2	UNC_I_TICKLES.TOP_OF_QUEUE	Counts the number of tickles that are received.  This is for both explicit (from Cbo) and implicit (internal conflict) tickles.	0,1	0	null	0
+IRP	0x15	0x1	UNC_I_TRANSACTIONS.READS	Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.	0,1	0	null	0
+IRP	0x15	0x2	UNC_I_TRANSACTIONS.WRITES	Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.	0,1	0	null	0
+IRP	0x15	0x4	UNC_I_TRANSACTIONS.PD_PREFETCHES	Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.	0,1	0	null	0
+IRP	0x15	0x8	UNC_I_TRANSACTIONS.ORDERINGQ	Counts the number of 'Inbound' transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.	0,1	0	IRPFilter[4:0]	0
+IRP	0x18	0x0	UNC_I_TxR_AD_STALL_CREDIT_CYCLES	Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.	0,1	0	null	0
+IRP	0x19	0x0	UNC_I_TxR_BL_STALL_CREDIT_CYCLES	Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.	0,1	0	null	0
+IRP	0xE	0x0	UNC_I_TxR_DATA_INSERTS_NCB	Counts the number of requests issued to the switch (towards the devices).	0,1	0	null	0
+IRP	0xF	0x0	UNC_I_TxR_DATA_INSERTS_NCS	Counts the number of requests issued to the switch (towards the devices).	0,1	0	null	0
+IRP	0xD	0x0	UNC_I_TxR_REQUEST_OCCUPANCY	Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.	0,1	0	null	0
+IRP	0x1A	0x0	UNC_I_WRITE_ORDERING_STALL_CYCLES	Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized.	0,1	0	null	0
diff --git a/x86data/perfmon_data/NHM-EP/NehalemEP_core_V1.json b/x86data/perfmon_data/NHM-EP/NehalemEP_core_V1.json
new file mode 100644
index 0000000..0ab662c
--- /dev/null
+++ b/x86data/perfmon_data/NHM-EP/NehalemEP_core_V1.json
@@ -0,0 +1,8931 @@
+[

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.CYCLES_DIV_BUSY",

+    "BriefDescription": "Cycles the divider is busy",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.DIV",

+    "BriefDescription": "Divide Operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x2",

+    "EventName": "ARITH.MUL",

+    "BriefDescription": "Multiply operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x2",

+    "EventName": "BACLEAR.BAD_TARGET",

+    "BriefDescription": "BACLEAR asserted with bad target address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1",

+    "EventName": "BACLEAR.CLEAR",

+    "BriefDescription": "BACLEAR asserted, regardless of cause ",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA7",

+    "UMask": "0x1",

+    "EventName": "BACLEAR_FORCE_IQ",

+    "BriefDescription": "Instruction queue forced BACLEAR",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x1",

+    "EventName": "BPU_CLEARS.EARLY",

+    "BriefDescription": "Early Branch Prediciton Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x2",

+    "EventName": "BPU_CLEARS.LATE",

+    "BriefDescription": "Late Branch Prediction Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE5",

+    "UMask": "0x1",

+    "EventName": "BPU_MISSED_CALL_RET",

+    "BriefDescription": "Branch prediction unit missed call or return",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE0",

+    "UMask": "0x1",

+    "EventName": "BR_INST_DECODED",

+    "BriefDescription": "Branch instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7F",

+    "EventName": "BR_INST_EXEC.ANY",

+    "BriefDescription": "Branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x1",

+    "EventName": "BR_INST_EXEC.COND",

+    "BriefDescription": "Conditional branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x2",

+    "EventName": "BR_INST_EXEC.DIRECT",

+    "BriefDescription": "Unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x10",

+    "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Unconditional call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x20",

+    "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x4",

+    "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x30",

+    "EventName": "BR_INST_EXEC.NEAR_CALLS",

+    "BriefDescription": "Call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7",

+    "EventName": "BR_INST_EXEC.NON_CALLS",

+    "BriefDescription": "All non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x8",

+    "EventName": "BR_INST_EXEC.RETURN_NEAR",

+    "BriefDescription": "Indirect return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x40",

+    "EventName": "BR_INST_EXEC.TAKEN",

+    "BriefDescription": "Taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x1",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Retired conditional branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Retired near call instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",

+    "BriefDescription": "Retired near call instructions Ring 3 only(Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7F",

+    "EventName": "BR_MISP_EXEC.ANY",

+    "BriefDescription": "Mispredicted branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x1",

+    "EventName": "BR_MISP_EXEC.COND",

+    "BriefDescription": "Mispredicted conditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_EXEC.DIRECT",

+    "BriefDescription": "Mispredicted unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x10",

+    "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Mispredicted indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x30",

+    "EventName": "BR_MISP_EXEC.NEAR_CALLS",

+    "BriefDescription": "Mispredicted call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7",

+    "EventName": "BR_MISP_EXEC.NON_CALLS",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x8",

+    "EventName": "BR_MISP_EXEC.RETURN_NEAR",

+    "BriefDescription": "Mispredicted return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x40",

+    "EventName": "BR_MISP_EXEC.TAKEN",

+    "BriefDescription": "Mispredicted taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_RETIRED.NEAR_CALL",

+    "BriefDescription": "Mispredicted near retired calls (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x2",

+    "EventName": "CACHE_LOCK_CYCLES.L1D",

+    "BriefDescription": "Cycles L1D locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x1",

+    "EventName": "CACHE_LOCK_CYCLES.L1D_L2",

+    "BriefDescription": "Cycles L1D and L2 locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.REF",

+    "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x1",

+    "EventName": "CPU_CLK_UNHALTED.REF_P",

+    "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 2",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",

+    "BriefDescription": "Total CPU cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "2",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x1",

+    "EventName": "DTLB_LOAD_MISSES.ANY",

+    "BriefDescription": "DTLB load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.PDE_MISS",

+    "BriefDescription": "DTLB load miss caused by low part of address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x2",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB load miss page walks complete",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x1",

+    "EventName": "DTLB_MISSES.ANY",

+    "BriefDescription": "DTLB misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB first level misses but second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x2",

+    "EventName": "DTLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD5",

+    "UMask": "0x1",

+    "EventName": "ES_REG_RENAMES",

+    "BriefDescription": "ES segment renames",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x1",

+    "EventName": "FP_ASSIST.ALL",

+    "BriefDescription": "X87 Floating point assists (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x4",

+    "EventName": "FP_ASSIST.INPUT",

+    "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x2",

+    "EventName": "FP_ASSIST.OUTPUT",

+    "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x2",

+    "EventName": "FP_COMP_OPS_EXE.MMX",

+    "BriefDescription": "MMX Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",

+    "BriefDescription": "SSE* FP double precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x4",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP",

+    "BriefDescription": "SSE and SSE2 FP Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",

+    "BriefDescription": "SSE FP packed Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",

+    "BriefDescription": "SSE FP scalar Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",

+    "BriefDescription": "SSE* FP single precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x8",

+    "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",

+    "BriefDescription": "SSE2 integer Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x1",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Computational floating-point operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x3",

+    "EventName": "FP_MMX_TRANS.ANY",

+    "BriefDescription": "All Floating Point to and from MMX transitions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x1",

+    "EventName": "FP_MMX_TRANS.TO_FP",

+    "BriefDescription": "Transitions from MMX to Floating Point instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x2",

+    "EventName": "FP_MMX_TRANS.TO_MMX",

+    "BriefDescription": "Transitions from Floating Point to MMX instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0xF",

+    "EventName": "ILD_STALL.ANY",

+    "BriefDescription": "Any Instruction Length Decoder stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x4",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Instruction Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x1",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Length Change Prefix stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x2",

+    "EventName": "ILD_STALL.MRU",

+    "BriefDescription": "Stall cycles due to BPU MRU bypass",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x8",

+    "EventName": "ILD_STALL.REGEN",

+    "BriefDescription": "Regen stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x18",

+    "UMask": "0x1",

+    "EventName": "INST_DECODED.DEC0",

+    "BriefDescription": "Instructions that must be decoded by decoder 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x1E",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITE_CYCLES",

+    "BriefDescription": "Cycles instructions are written to the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x17",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITES",

+    "BriefDescription": "Instructions written to instruction queue.",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired (fixed counter)",

+    "Counter": "Fixed counter 1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x4",

+    "EventName": "INST_RETIRED.MMX",

+    "BriefDescription": "Retired MMX instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x2",

+    "EventName": "INST_RETIRED.X87",

+    "BriefDescription": "Retired floating-point operations (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6C",

+    "UMask": "0x1",

+    "EventName": "IO_TRANSACTIONS",

+    "BriefDescription": "I/O transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x1",

+    "EventName": "ITLB_FLUSH",

+    "BriefDescription": "ITLB flushes",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISS_RETIRED",

+    "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x1",

+    "EventName": "ITLB_MISSES.ANY",

+    "BriefDescription": "ITLB miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x2",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "ITLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x4",

+    "EventName": "L1D.M_EVICT",

+    "BriefDescription": "L1D cache lines replaced in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x2",

+    "EventName": "L1D.M_REPL",

+    "BriefDescription": "L1D cache lines allocated in the M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x8",

+    "EventName": "L1D.M_SNOOP_EVICT",

+    "BriefDescription": "L1D snoop eviction of cache lines in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x1",

+    "EventName": "L1D.REPL",

+    "BriefDescription": "L1 data cache lines allocated",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x43",

+    "UMask": "0x1",

+    "EventName": "L1D_ALL_REF.ANY",

+    "BriefDescription": "All references to the L1 data cache",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x43",

+    "UMask": "0x2",

+    "EventName": "L1D_ALL_REF.CACHEABLE",

+    "BriefDescription": "L1 data cacheable reads and writes",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0x4",

+    "EventName": "L1D_CACHE_LD.E_STATE",

+    "BriefDescription": "L1 data cache read in E state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_LD.I_STATE",

+    "BriefDescription": "L1 data cache read in I state (misses)",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0x8",

+    "EventName": "L1D_CACHE_LD.M_STATE",

+    "BriefDescription": "L1 data cache read in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0xF",

+    "EventName": "L1D_CACHE_LD.MESI",

+    "BriefDescription": "L1 data cache reads",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0x2",

+    "EventName": "L1D_CACHE_LD.S_STATE",

+    "BriefDescription": "L1 data cache read in S state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x42",

+    "UMask": "0x4",

+    "EventName": "L1D_CACHE_LOCK.E_STATE",

+    "BriefDescription": "L1 data cache load locks in E state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x42",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_LOCK.HIT",

+    "BriefDescription": "L1 data cache load lock hits",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x42",

+    "UMask": "0x8",

+    "EventName": "L1D_CACHE_LOCK.M_STATE",

+    "BriefDescription": "L1 data cache load locks in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x42",

+    "UMask": "0x2",

+    "EventName": "L1D_CACHE_LOCK.S_STATE",

+    "BriefDescription": "L1 data cache load locks in S state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x53",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_LOCK_FB_HIT",

+    "BriefDescription": "L1D load lock accepted in fill buffer",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x52",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",

+    "BriefDescription": "L1D prefetch load lock accepted in fill buffer",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x41",

+    "UMask": "0x4",

+    "EventName": "L1D_CACHE_ST.E_STATE",

+    "BriefDescription": "L1 data cache stores in E state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x41",

+    "UMask": "0x8",

+    "EventName": "L1D_CACHE_ST.M_STATE",

+    "BriefDescription": "L1 data cache stores in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x41",

+    "UMask": "0x2",

+    "EventName": "L1D_CACHE_ST.S_STATE",

+    "BriefDescription": "L1 data cache stores in S state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x2",

+    "EventName": "L1D_PREFETCH.MISS",

+    "BriefDescription": "L1D hardware prefetch misses",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x1",

+    "EventName": "L1D_PREFETCH.REQUESTS",

+    "BriefDescription": "L1D hardware prefetch requests",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x4",

+    "EventName": "L1D_PREFETCH.TRIGGERS",

+    "BriefDescription": "L1D hardware prefetch requests triggered",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x4",

+    "EventName": "L1D_WB_L2.E_STATE",

+    "BriefDescription": "L1 writebacks to L2 in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x1",

+    "EventName": "L1D_WB_L2.I_STATE",

+    "BriefDescription": "L1 writebacks to L2 in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x8",

+    "EventName": "L1D_WB_L2.M_STATE",

+    "BriefDescription": "L1 writebacks to L2 in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0xF",

+    "EventName": "L1D_WB_L2.MESI",

+    "BriefDescription": "All L1 writebacks to L2",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x2",

+    "EventName": "L1D_WB_L2.S_STATE",

+    "BriefDescription": "L1 writebacks to L2 in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x4",

+    "EventName": "L1I.CYCLES_STALLED",

+    "BriefDescription": "L1I instruction fetch stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x1",

+    "EventName": "L1I.HITS",

+    "BriefDescription": "L1I instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x2",

+    "EventName": "L1I.MISSES",

+    "BriefDescription": "L1I instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x3",

+    "EventName": "L1I.READS",

+    "BriefDescription": "L1I Instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xFF",

+    "EventName": "L2_DATA_RQSTS.ANY",

+    "BriefDescription": "All L2 data requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x4",

+    "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",

+    "BriefDescription": "L2 data demand loads in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x1",

+    "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",

+    "BriefDescription": "L2 data demand loads in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x8",

+    "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",

+    "BriefDescription": "L2 data demand loads in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF",

+    "EventName": "L2_DATA_RQSTS.DEMAND.MESI",

+    "BriefDescription": "L2 data demand requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x2",

+    "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",

+    "BriefDescription": "L2 data demand loads in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x40",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",

+    "BriefDescription": "L2 data prefetches in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x10",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",

+    "BriefDescription": "L2 data prefetches in the I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x80",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",

+    "BriefDescription": "L2 data prefetches in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF0",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",

+    "BriefDescription": "All L2 data prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x20",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",

+    "BriefDescription": "L2 data prefetches in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x7",

+    "EventName": "L2_LINES_IN.ANY",

+    "BriefDescription": "L2 lines alloacated",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_IN.E_STATE",

+    "BriefDescription": "L2 lines allocated in the E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_IN.S_STATE",

+    "BriefDescription": "L2 lines allocated in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0xF",

+    "EventName": "L2_LINES_OUT.ANY",

+    "BriefDescription": "L2 lines evicted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x1",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "L2 lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",

+    "BriefDescription": "L2 lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x8",

+    "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.IFETCH_HIT",

+    "BriefDescription": "L2 instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.IFETCH_MISS",

+    "BriefDescription": "L2 instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.IFETCHES",

+    "BriefDescription": "L2 instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x1",

+    "EventName": "L2_RQSTS.LD_HIT",

+    "BriefDescription": "L2 load hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x2",

+    "EventName": "L2_RQSTS.LD_MISS",

+    "BriefDescription": "L2 load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3",

+    "EventName": "L2_RQSTS.LOADS",

+    "BriefDescription": "L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xAA",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All L2 misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PREFETCH_HIT",

+    "BriefDescription": "L2 prefetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PREFETCH_MISS",

+    "BriefDescription": "L2 prefetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.PREFETCHES",

+    "BriefDescription": "All L2 prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x4",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "L2 RFO hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x8",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "L2 RFO misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC",

+    "EventName": "L2_RQSTS.RFOS",

+    "BriefDescription": "L2 RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANSACTIONS.ANY",

+    "BriefDescription": "All L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANSACTIONS.FILL",

+    "BriefDescription": "L2 fill transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x4",

+    "EventName": "L2_TRANSACTIONS.IFETCH",

+    "BriefDescription": "L2 instruction fetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANSACTIONS.L1D_WB",

+    "BriefDescription": "L1D writeback to L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x1",

+    "EventName": "L2_TRANSACTIONS.LOAD",

+    "BriefDescription": "L2 Load transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x8",

+    "EventName": "L2_TRANSACTIONS.PREFETCH",

+    "BriefDescription": "L2 prefetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x2",

+    "EventName": "L2_TRANSACTIONS.RFO",

+    "BriefDescription": "L2 RFO transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANSACTIONS.WB",

+    "BriefDescription": "L2 writeback to LLC transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x40",

+    "EventName": "L2_WRITE.LOCK.E_STATE",

+    "BriefDescription": "L2 demand lock RFOs in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE0",

+    "EventName": "L2_WRITE.LOCK.HIT",

+    "BriefDescription": "All demand L2 lock RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x10",

+    "EventName": "L2_WRITE.LOCK.I_STATE",

+    "BriefDescription": "L2 demand lock RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x80",

+    "EventName": "L2_WRITE.LOCK.M_STATE",

+    "BriefDescription": "L2 demand lock RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF0",

+    "EventName": "L2_WRITE.LOCK.MESI",

+    "BriefDescription": "All demand L2 lock RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x20",

+    "EventName": "L2_WRITE.LOCK.S_STATE",

+    "BriefDescription": "L2 demand lock RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE",

+    "EventName": "L2_WRITE.RFO.HIT",

+    "BriefDescription": "All L2 demand store RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x1",

+    "EventName": "L2_WRITE.RFO.I_STATE",

+    "BriefDescription": "L2 demand store RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x8",

+    "EventName": "L2_WRITE.RFO.M_STATE",

+    "BriefDescription": "L2 demand store RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF",

+    "EventName": "L2_WRITE.RFO.MESI",

+    "BriefDescription": "All L2 demand store RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x2",

+    "EventName": "L2_WRITE.RFO.S_STATE",

+    "BriefDescription": "L2 demand store RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x82",

+    "UMask": "0x1",

+    "EventName": "LARGE_ITLB.HIT",

+    "BriefDescription": "Large ITLB hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x7",

+    "EventName": "LOAD_DISPATCH.ANY",

+    "BriefDescription": "All loads dispatched",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x4",

+    "EventName": "LOAD_DISPATCH.MOB",

+    "BriefDescription": "Loads dispatched from the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x1",

+    "EventName": "LOAD_DISPATCH.RS",

+    "BriefDescription": "Loads dispatched that bypass the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x2",

+    "EventName": "LOAD_DISPATCH.RS_DELAYED",

+    "BriefDescription": "Loads dispatched from stage 305",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x1",

+    "EventName": "LOAD_HIT_PRE",

+    "BriefDescription": "Load operations conflicting with software prefetches",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Longest latency cache miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Longest latency cache reference",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.ACTIVE",

+    "BriefDescription": "Cycles when uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.INACTIVE",

+    "BriefDescription": "Cycles no uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x20",

+    "UMask": "0x1",

+    "EventName": "LSD_OVERFLOW",

+    "BriefDescription": "Loops that can't stream from the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x1",

+    "EventName": "MACHINE_CLEARS.CYCLES",

+    "BriefDescription": "Cycles machine clear asserted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x2",

+    "EventName": "MACHINE_CLEARS.MEM_ORDER",

+    "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x4",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-Modifying Code detected",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.DECODED",

+    "BriefDescription": "Instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.FUSIONS_DECODED",

+    "BriefDescription": "Macro-fused instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x1",

+    "EventName": "MEM_INST_RETIRED.LOADS",

+    "BriefDescription": "Instructions retired which contains a load (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x2",

+    "EventName": "MEM_INST_RETIRED.STORES",

+    "BriefDescription": "Instructions retired which contains a store (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x80",

+    "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x1",

+    "EventName": "MEM_LOAD_RETIRED.L1D_HIT",

+    "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x2",

+    "EventName": "MEM_LOAD_RETIRED.L2_HIT",

+    "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_RETIRED.LLC_MISS",

+    "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x4",

+    "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",

+    "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x8",

+    "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",

+    "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC",

+    "UMask": "0x1",

+    "EventName": "MEM_STORE_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x20",

+    "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x2",

+    "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",

+    "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x8",

+    "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",

+    "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x10",

+    "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",

+    "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x80",

+    "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",

+    "BriefDescription": "Load instructions retired IO (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "4000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x40",

+    "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",

+    "BriefDescription": "Offcore L1 data cache writebacks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_SQ_FULL",

+    "BriefDescription": "Offcore requests blocked due to Super Queue full",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x7",

+    "UMask": "0x1",

+    "EventName": "PARTIAL_ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies due to partial address aliasing",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0xF",

+    "EventName": "RAT_STALLS.ANY",

+    "BriefDescription": "All RAT stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x1",

+    "EventName": "RAT_STALLS.FLAGS",

+    "BriefDescription": "Flag stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x2",

+    "EventName": "RAT_STALLS.REGISTERS",

+    "BriefDescription": "Partial register stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x4",

+    "EventName": "RAT_STALLS.ROB_READ_PORT",

+    "BriefDescription": "ROB read port stalls cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x8",

+    "EventName": "RAT_STALLS.SCOREBOARD",

+    "BriefDescription": "Scoreboard stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x1",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x20",

+    "EventName": "RESOURCE_STALLS.FPCW",

+    "BriefDescription": "FPU control word write stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x2",

+    "EventName": "RESOURCE_STALLS.LOAD",

+    "BriefDescription": "Load buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x40",

+    "EventName": "RESOURCE_STALLS.MXCSR",

+    "BriefDescription": "MXCSR rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x80",

+    "EventName": "RESOURCE_STALLS.OTHER",

+    "BriefDescription": "Other Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB_FULL",

+    "BriefDescription": "ROB full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x4",

+    "EventName": "RESOURCE_STALLS.RS_FULL",

+    "BriefDescription": "Reservation Station full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x8",

+    "EventName": "RESOURCE_STALLS.STORE",

+    "BriefDescription": "Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4",

+    "UMask": "0x7",

+    "EventName": "SB_DRAIN.ANY",

+    "BriefDescription": "All Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD4",

+    "UMask": "0x1",

+    "EventName": "SEG_RENAME_STALLS",

+    "BriefDescription": "Segment rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_128.PACK",

+    "BriefDescription": "128 bit SIMD integer pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_128.PACKED_ARITH",

+    "BriefDescription": "128 bit SIMD integer arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_128.PACKED_LOGICAL",

+    "BriefDescription": "128 bit SIMD integer logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_128.PACKED_MPY",

+    "BriefDescription": "128 bit SIMD integer multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_128.PACKED_SHIFT",

+    "BriefDescription": "128 bit SIMD integer shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_128.SHUFFLE_MOVE",

+    "BriefDescription": "128 bit SIMD integer shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_128.UNPACK",

+    "BriefDescription": "128 bit SIMD integer unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_64.PACK",

+    "BriefDescription": "SIMD integer 64 bit pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_64.PACKED_ARITH",

+    "BriefDescription": "SIMD integer 64 bit arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_64.PACKED_LOGICAL",

+    "BriefDescription": "SIMD integer 64 bit logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_64.PACKED_MPY",

+    "BriefDescription": "SIMD integer 64 bit packed multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_64.PACKED_SHIFT",

+    "BriefDescription": "SIMD integer 64 bit shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_64.SHUFFLE_MOVE",

+    "BriefDescription": "SIMD integer 64 bit shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_64.UNPACK",

+    "BriefDescription": "SIMD integer 64 bit unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x1",

+    "EventName": "SNOOP_RESPONSE.HIT",

+    "BriefDescription": "Thread responded HIT to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x2",

+    "EventName": "SNOOP_RESPONSE.HITE",

+    "BriefDescription": "Thread responded HITE to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x4",

+    "EventName": "SNOOP_RESPONSE.HITM",

+    "BriefDescription": "Thread responded HITM to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF6",

+    "UMask": "0x1",

+    "EventName": "SQ_FULL_STALL_CYCLES",

+    "BriefDescription": "Super Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x10",

+    "EventName": "SQ_MISC.SPLIT_LOCK",

+    "BriefDescription": "Super Queue lock splits across a cache line",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x4",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",

+    "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x1",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",

+    "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x8",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",

+    "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x2",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",

+    "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x10",

+    "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",

+    "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x4",

+    "EventName": "STORE_BLOCKS.AT_RET",

+    "BriefDescription": "Loads delayed with at-Retirement block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x8",

+    "EventName": "STORE_BLOCKS.L1D_BLOCK",

+    "BriefDescription": "Cacheable loads delayed with L1D block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x19",

+    "UMask": "0x1",

+    "EventName": "TWO_UOP_INSTS_DECODED",

+    "BriefDescription": "Two Uop instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xDB",

+    "UMask": "0x1",

+    "EventName": "UOP_UNFUSION",

+    "BriefDescription": "Uop unfusions due to FP exceptions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x4",

+    "EventName": "UOPS_DECODED.ESP_FOLDING",

+    "BriefDescription": "Stack pointer instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x8",

+    "EventName": "UOPS_DECODED.ESP_SYNC",

+    "BriefDescription": "Stack pointer sync operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x2",

+    "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",

+    "BriefDescription": "Uops decoded by Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x1",

+    "EventName": "UOPS_DECODED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops are decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",

+    "BriefDescription": "Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",

+    "BriefDescription": "Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1",

+    "EventName": "UOPS_EXECUTED.PORT0",

+    "BriefDescription": "Uops executed on port 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015",

+    "BriefDescription": "Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x2",

+    "EventName": "UOPS_EXECUTED.PORT1",

+    "BriefDescription": "Uops executed on port 1",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x4",

+    "EventName": "UOPS_EXECUTED.PORT2_CORE",

+    "BriefDescription": "Uops executed on port 2 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED.PORT234_CORE",

+    "BriefDescription": "Uops issued on ports 2, 3 or 4",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x8",

+    "EventName": "UOPS_EXECUTED.PORT3_CORE",

+    "BriefDescription": "Uops executed on port 3 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED.PORT4_CORE",

+    "BriefDescription": "Uops executed on port 4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED.PORT5",

+    "BriefDescription": "Uops executed on port 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued on any thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",

+    "BriefDescription": "Cycles Uops were issued on either thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x2",

+    "EventName": "UOPS_ISSUED.FUSED",

+    "BriefDescription": "Fused Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops are being retired",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ANY",

+    "BriefDescription": "Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x4",

+    "EventName": "UOPS_RETIRED.MACRO_FUSED",

+    "BriefDescription": "Macro-fused Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x2",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles Uops are not retiring (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",

+    "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",

+    "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "100",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x400",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",

+    "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "1000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",

+    "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",

+    "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",

+    "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x800",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",

+    "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "500",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",

+    "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",

+    "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "3",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",

+    "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",

+    "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x1000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",

+    "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "200",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",

+    "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",

+    "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",

+    "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x2000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  }

+,

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x111",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x211",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x411",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x144",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x244",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x444",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7FFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM",

+    "BriefDescription": "Offcore requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x60FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS",

+    "BriefDescription": "Offcore requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION",

+    "BriefDescription": "All offcore requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFFFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO",

+    "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x80FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE",

+    "BriefDescription": "Offcore requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x47FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM",

+    "BriefDescription": "Offcore requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x40FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE",

+    "BriefDescription": "Offcore requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x18FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x38FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x10FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x20FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x122",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x222",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x422",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_DRAM",

+    "BriefDescription": "Offcore writebacks to any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS",

+    "BriefDescription": "Offcore writebacks that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION",

+    "BriefDescription": "All offcore writebacks",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO",

+    "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x108",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x408",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE",

+    "BriefDescription": "Offcore writebacks to the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM",

+    "BriefDescription": "Offcore writebacks to the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE",

+    "BriefDescription": "Offcore writebacks to a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore writebacks that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore writebacks that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM",

+    "BriefDescription": "Offcore writebacks to a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore code or data read requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore code or data read requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x177",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x277",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x477",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = any cache_dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM",

+    "BriefDescription": "Offcore request = all data, response = any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS",

+    "BriefDescription": "Offcore request = all data, response = any LLC miss",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION",

+    "BriefDescription": "Offcore request = all data, response = any location",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x133",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x233",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x433",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE",

+    "BriefDescription": "Offcore request = all data, response = local cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = local cache or dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE",

+    "BriefDescription": "Offcore request = all data, response = remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = remote cache or dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand data requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore demand data requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x103",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x203",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x403",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand data requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand data requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION",

+    "BriefDescription": "All offcore demand data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x101",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x201",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x401",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore demand code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x104",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x204",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x404",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore demand RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x102",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x202",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x402",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS",

+    "BriefDescription": "Offcore other requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION",

+    "BriefDescription": "All offcore other requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO",

+    "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x180",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x280",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x480",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE",

+    "BriefDescription": "Offcore other requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore other requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore other requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F30",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch data requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch data requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF30",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x130",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x230",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x430",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x730",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4730",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x110",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x210",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x410",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x140",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x240",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x440",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x120",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x220",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x420",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x170",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x270",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x470",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/NHM-EP/NehalemEP_core_V1.tsv b/x86data/perfmon_data/NHM-EP/NehalemEP_core_V1.tsv
new file mode 100644
index 0000000..4684bb8
--- /dev/null
+++ b/x86data/perfmon_data/NHM-EP/NehalemEP_core_V1.tsv
@@ -0,0 +1,292 @@
+# Performance Monitoring Events for Intel Core i7 and i5 Processors Based on the Nehalem-EP Microarchitecture - V1
+# 12/13/2013 11:01:42 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0x14	0x1	ARITH.CYCLES_DIV_BUSY	Cycles the divider is busy	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x14	0x1	ARITH.DIV	Divide Operations executed	0,1,2,3	2000000	0	0	1	1	0	1	0	
+0x14	0x2	ARITH.MUL	Multiply operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x2	BACLEAR.BAD_TARGET	BACLEAR asserted with bad target address	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x1	BACLEAR.CLEAR	BACLEAR asserted, regardless of cause 	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA7	0x1	BACLEAR_FORCE_IQ	Instruction queue forced BACLEAR	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x1	BPU_CLEARS.EARLY	Early Branch Prediciton Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x2	BPU_CLEARS.LATE	Late Branch Prediction Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE5	0x1	BPU_MISSED_CALL_RET	Branch prediction unit missed call or return	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE0	0x1	BR_INST_DECODED	Branch instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x88	0x7F	BR_INST_EXEC.ANY	Branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x1	BR_INST_EXEC.COND	Conditional branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x2	BR_INST_EXEC.DIRECT	Unconditional branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x10	BR_INST_EXEC.DIRECT_NEAR_CALL	Unconditional call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x20	BR_INST_EXEC.INDIRECT_NEAR_CALL	Indirect call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x4	BR_INST_EXEC.INDIRECT_NON_CALL	Indirect non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x30	BR_INST_EXEC.NEAR_CALLS	Call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x7	BR_INST_EXEC.NON_CALLS	All non call branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x8	BR_INST_EXEC.RETURN_NEAR	Indirect return branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x40	BR_INST_EXEC.TAKEN	Taken branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x1	BR_INST_RETIRED.CONDITIONAL	Retired conditional branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL	Retired near call instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL_R3	Retired near call instructions Ring 3 only(Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x89	0x7F	BR_MISP_EXEC.ANY	Mispredicted branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x1	BR_MISP_EXEC.COND	Mispredicted conditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x2	BR_MISP_EXEC.DIRECT	Mispredicted unconditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x10	BR_MISP_EXEC.DIRECT_NEAR_CALL	Mispredicted non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x20	BR_MISP_EXEC.INDIRECT_NEAR_CALL	Mispredicted indirect call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x4	BR_MISP_EXEC.INDIRECT_NON_CALL	Mispredicted indirect non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x30	BR_MISP_EXEC.NEAR_CALLS	Mispredicted call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x7	BR_MISP_EXEC.NON_CALLS	Mispredicted non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x8	BR_MISP_EXEC.RETURN_NEAR	Mispredicted return branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x40	BR_MISP_EXEC.TAKEN	Mispredicted taken branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC5	0x2	BR_MISP_RETIRED.NEAR_CALL	Mispredicted near retired calls (Precise Event)	0,1,2,3	2000	0	0	0	0	0	0	1	
+0x63	0x2	CACHE_LOCK_CYCLES.L1D	Cycles L1D locked	0,1	2000000	0	0	0	0	0	0	0	
+0x63	0x1	CACHE_LOCK_CYCLES.L1D_L2	Cycles L1D and L2 locked	0,1	2000000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.REF	Reference cycles when thread is not halted (fixed counter)	Fixed counter 3	2000000	0	0	0	0	0	0	0	
+0x3C	0x1	CPU_CLK_UNHALTED.REF_P	Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.THREAD	Cycles when thread is not halted (fixed counter)	Fixed counter 2	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.THREAD_P	Cycles when thread is not halted (programmable counter)	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.TOTAL_CYCLES	Total CPU cycles	0,1,2,3	2000000	0	0	2	1	0	0	0	
+0x8	0x1	DTLB_LOAD_MISSES.ANY	DTLB load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x20	DTLB_LOAD_MISSES.PDE_MISS	DTLB load miss caused by low part of address	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x10	DTLB_LOAD_MISSES.STLB_HIT	DTLB second level hit	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x8	0x2	DTLB_LOAD_MISSES.WALK_COMPLETED	DTLB load miss page walks complete	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x1	DTLB_MISSES.ANY	DTLB misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x10	DTLB_MISSES.STLB_HIT	DTLB first level misses but second level hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x2	DTLB_MISSES.WALK_COMPLETED	DTLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD5	0x1	ES_REG_RENAMES	ES segment renames	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF7	0x1	FP_ASSIST.ALL	X87 Floating point assists (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x4	FP_ASSIST.INPUT	X87 Floating poiint assists for invalid input value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x2	FP_ASSIST.OUTPUT	X87 Floating point assists for invalid output value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x10	0x2	FP_COMP_OPS_EXE.MMX	MMX Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x80	FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION	SSE* FP double precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x4	FP_COMP_OPS_EXE.SSE_FP	SSE and SSE2 FP Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x10	FP_COMP_OPS_EXE.SSE_FP_PACKED	SSE FP packed Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x20	FP_COMP_OPS_EXE.SSE_FP_SCALAR	SSE FP scalar Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x40	FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION	SSE* FP single precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x8	FP_COMP_OPS_EXE.SSE2_INTEGER	SSE2 integer Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x1	FP_COMP_OPS_EXE.X87	Computational floating-point operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x3	FP_MMX_TRANS.ANY	All Floating Point to and from MMX transitions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x1	FP_MMX_TRANS.TO_FP	Transitions from MMX to Floating Point instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x2	FP_MMX_TRANS.TO_MMX	Transitions from Floating Point to MMX instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0xF	ILD_STALL.ANY	Any Instruction Length Decoder stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x4	ILD_STALL.IQ_FULL	Instruction Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x1	ILD_STALL.LCP	Length Change Prefix stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x2	ILD_STALL.MRU	Stall cycles due to BPU MRU bypass	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x8	ILD_STALL.REGEN	Regen stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x18	0x1	INST_DECODED.DEC0	Instructions that must be decoded by decoder 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x1E	0x1	INST_QUEUE_WRITE_CYCLES	Cycles instructions are written to the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x17	0x1	INST_QUEUE_WRITES	Instructions written to instruction queue.	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x0	0x0	INST_RETIRED.ANY	Instructions retired (fixed counter)	Fixed counter 1	2000000	0	0	0	0	0	0	0	
+0xC0	0x1	INST_RETIRED.ANY_P	Instructions retired (Programmable counter and Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x4	INST_RETIRED.MMX	Retired MMX instructions (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x1	INST_RETIRED.TOTAL_CYCLES	Total cycles (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC0	0x2	INST_RETIRED.X87	Retired floating-point operations (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0x6C	0x1	IO_TRANSACTIONS	I/O transactions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xAE	0x1	ITLB_FLUSH	ITLB flushes	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC8	0x20	ITLB_MISS_RETIRED	Retired instructions that missed the ITLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x85	0x1	ITLB_MISSES.ANY	ITLB miss	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x2	ITLB_MISSES.WALK_COMPLETED	ITLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x51	0x4	L1D.M_EVICT	L1D cache lines replaced in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x2	L1D.M_REPL	L1D cache lines allocated in the M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x8	L1D.M_SNOOP_EVICT	L1D snoop eviction of cache lines in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x1	L1D.REPL	L1 data cache lines allocated	0,1	2000000	0	0	0	0	0	0	0	
+0x43	0x1	L1D_ALL_REF.ANY	All references to the L1 data cache	0,1	2000000	0	0	0	0	0	0	0	
+0x43	0x2	L1D_ALL_REF.CACHEABLE	L1 data cacheable reads and writes	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0x4	L1D_CACHE_LD.E_STATE	L1 data cache read in E state	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0x1	L1D_CACHE_LD.I_STATE	L1 data cache read in I state (misses)	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0x8	L1D_CACHE_LD.M_STATE	L1 data cache read in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0xF	L1D_CACHE_LD.MESI	L1 data cache reads	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0x2	L1D_CACHE_LD.S_STATE	L1 data cache read in S state	0,1	2000000	0	0	0	0	0	0	0	
+0x42	0x4	L1D_CACHE_LOCK.E_STATE	L1 data cache load locks in E state	0,1	2000000	0	0	0	0	0	0	0	
+0x42	0x1	L1D_CACHE_LOCK.HIT	L1 data cache load lock hits	0,1	2000000	0	0	0	0	0	0	0	
+0x42	0x8	L1D_CACHE_LOCK.M_STATE	L1 data cache load locks in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x42	0x2	L1D_CACHE_LOCK.S_STATE	L1 data cache load locks in S state	0,1	2000000	0	0	0	0	0	0	0	
+0x53	0x1	L1D_CACHE_LOCK_FB_HIT	L1D load lock accepted in fill buffer	0,1	2000000	0	0	0	0	0	0	0	
+0x52	0x1	L1D_CACHE_PREFETCH_LOCK_FB_HIT	L1D prefetch load lock accepted in fill buffer	0,1	2000000	0	0	0	0	0	0	0	
+0x41	0x4	L1D_CACHE_ST.E_STATE	L1 data cache stores in E state	0,1	2000000	0	0	0	0	0	0	0	
+0x41	0x8	L1D_CACHE_ST.M_STATE	L1 data cache stores in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x41	0x2	L1D_CACHE_ST.S_STATE	L1 data cache stores in S state	0,1	2000000	0	0	0	0	0	0	0	
+0x4E	0x2	L1D_PREFETCH.MISS	L1D hardware prefetch misses	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x1	L1D_PREFETCH.REQUESTS	L1D hardware prefetch requests	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x4	L1D_PREFETCH.TRIGGERS	L1D hardware prefetch requests triggered	0,1	200000	0	0	0	0	0	0	0	
+0x28	0x4	L1D_WB_L2.E_STATE	L1 writebacks to L2 in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x1	L1D_WB_L2.I_STATE	L1 writebacks to L2 in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x8	L1D_WB_L2.M_STATE	L1 writebacks to L2 in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0xF	L1D_WB_L2.MESI	All L1 writebacks to L2	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x2	L1D_WB_L2.S_STATE	L1 writebacks to L2 in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x80	0x4	L1I.CYCLES_STALLED	L1I instruction fetch stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x1	L1I.HITS	L1I instruction fetch hits	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x2	L1I.MISSES	L1I instruction fetch misses	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x3	L1I.READS	L1I Instruction fetches	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x26	0xFF	L2_DATA_RQSTS.ANY	All L2 data requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x4	L2_DATA_RQSTS.DEMAND.E_STATE	L2 data demand loads in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x1	L2_DATA_RQSTS.DEMAND.I_STATE	L2 data demand loads in I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x8	L2_DATA_RQSTS.DEMAND.M_STATE	L2 data demand loads in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF	L2_DATA_RQSTS.DEMAND.MESI	L2 data demand requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x2	L2_DATA_RQSTS.DEMAND.S_STATE	L2 data demand loads in S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x40	L2_DATA_RQSTS.PREFETCH.E_STATE	L2 data prefetches in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x10	L2_DATA_RQSTS.PREFETCH.I_STATE	L2 data prefetches in the I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x80	L2_DATA_RQSTS.PREFETCH.M_STATE	L2 data prefetches in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF0	L2_DATA_RQSTS.PREFETCH.MESI	All L2 data prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x20	L2_DATA_RQSTS.PREFETCH.S_STATE	L2 data prefetches in the S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF1	0x7	L2_LINES_IN.ANY	L2 lines alloacated	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x4	L2_LINES_IN.E_STATE	L2 lines allocated in the E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x2	L2_LINES_IN.S_STATE	L2 lines allocated in the S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0xF	L2_LINES_OUT.ANY	L2 lines evicted	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x1	L2_LINES_OUT.DEMAND_CLEAN	L2 lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x2	L2_LINES_OUT.DEMAND_DIRTY	L2 modified lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x4	L2_LINES_OUT.PREFETCH_CLEAN	L2 lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x8	L2_LINES_OUT.PREFETCH_DIRTY	L2 modified lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x24	0x10	L2_RQSTS.IFETCH_HIT	L2 instruction fetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x20	L2_RQSTS.IFETCH_MISS	L2 instruction fetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x30	L2_RQSTS.IFETCHES	L2 instruction fetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x1	L2_RQSTS.LD_HIT	L2 load hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x2	L2_RQSTS.LD_MISS	L2 load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x3	L2_RQSTS.LOADS	L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xAA	L2_RQSTS.MISS	All L2 misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x40	L2_RQSTS.PREFETCH_HIT	L2 prefetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x80	L2_RQSTS.PREFETCH_MISS	L2 prefetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC0	L2_RQSTS.PREFETCHES	All L2 prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x4	L2_RQSTS.RFO_HIT	L2 RFO hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x8	L2_RQSTS.RFO_MISS	L2 RFO misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC	L2_RQSTS.RFOS	L2 RFO requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x80	L2_TRANSACTIONS.ANY	All L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x20	L2_TRANSACTIONS.FILL	L2 fill transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x4	L2_TRANSACTIONS.IFETCH	L2 instruction fetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x10	L2_TRANSACTIONS.L1D_WB	L1D writeback to L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x1	L2_TRANSACTIONS.LOAD	L2 Load transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x8	L2_TRANSACTIONS.PREFETCH	L2 prefetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x2	L2_TRANSACTIONS.RFO	L2 RFO transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x40	L2_TRANSACTIONS.WB	L2 writeback to LLC transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x27	0x40	L2_WRITE.LOCK.E_STATE	L2 demand lock RFOs in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE0	L2_WRITE.LOCK.HIT	All demand L2 lock RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x10	L2_WRITE.LOCK.I_STATE	L2 demand lock RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x80	L2_WRITE.LOCK.M_STATE	L2 demand lock RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF0	L2_WRITE.LOCK.MESI	All demand L2 lock RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x20	L2_WRITE.LOCK.S_STATE	L2 demand lock RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE	L2_WRITE.RFO.HIT	All L2 demand store RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x1	L2_WRITE.RFO.I_STATE	L2 demand store RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x8	L2_WRITE.RFO.M_STATE	L2 demand store RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF	L2_WRITE.RFO.MESI	All L2 demand store RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x2	L2_WRITE.RFO.S_STATE	L2 demand store RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x82	0x1	LARGE_ITLB.HIT	Large ITLB hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x13	0x7	LOAD_DISPATCH.ANY	All loads dispatched	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x4	LOAD_DISPATCH.MOB	Loads dispatched from the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x1	LOAD_DISPATCH.RS	Loads dispatched that bypass the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x2	LOAD_DISPATCH.RS_DELAYED	Loads dispatched from stage 305	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4C	0x1	LOAD_HIT_PRE	Load operations conflicting with software prefetches	0,1	200000	0	0	0	0	0	0	0	
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Longest latency cache miss	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Longest latency cache reference	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xA8	0x1	LSD.ACTIVE	Cycles when uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xA8	0x1	LSD.INACTIVE	Cycles no uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0x20	0x1	LSD_OVERFLOW	Loops that can't stream from the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC3	0x1	MACHINE_CLEARS.CYCLES	Cycles machine clear asserted	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x2	MACHINE_CLEARS.MEM_ORDER	Execution pipeline restart due to Memory ordering conflicts	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x4	MACHINE_CLEARS.SMC	Self-Modifying Code detected	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xD0	0x1	MACRO_INSTS.DECODED	Instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA6	0x1	MACRO_INSTS.FUSIONS_DECODED	Macro-fused instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB	0x1	MEM_INST_RETIRED.LOADS	Instructions retired which contains a load (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xB	0x2	MEM_INST_RETIRED.STORES	Instructions retired which contains a store (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x80	MEM_LOAD_RETIRED.DTLB_MISS	Retired loads that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x40	MEM_LOAD_RETIRED.HIT_LFB	Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x1	MEM_LOAD_RETIRED.L1D_HIT	Retired loads that hit the L1 data cache (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x2	MEM_LOAD_RETIRED.L2_HIT	Retired loads that hit the L2 cache (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x10	MEM_LOAD_RETIRED.LLC_MISS	Retired loads that miss the LLC cache (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xCB	0x4	MEM_LOAD_RETIRED.LLC_UNSHARED_HIT	Retired loads that hit valid versions in the LLC cache (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xCB	0x8	MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM	Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xC	0x1	MEM_STORE_RETIRED.DTLB_MISS	Retired stores that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xF	0x20	MEM_UNCORE_RETIRED.LOCAL_DRAM	Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xF	0x2	MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM	Load instructions retired that HIT modified data in sibling core (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xF	0x8	MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT	Load instructions retired remote cache HIT data source (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF	0x10	MEM_UNCORE_RETIRED.REMOTE_DRAM	Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xF	0x80	MEM_UNCORE_RETIRED.UNCACHEABLE	Load instructions retired IO (Precise Event)	0,1,2,3	4000	0	0	0	0	0	0	1	
+0xB0	0x40	OFFCORE_REQUESTS.L1D_WRITEBACK	Offcore L1 data cache writebacks	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB2	0x1	OFFCORE_REQUESTS_SQ_FULL	Offcore requests blocked due to Super Queue full	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x7	0x1	PARTIAL_ADDRESS_ALIAS	False dependencies due to partial address aliasing	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD2	0xF	RAT_STALLS.ANY	All RAT stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x1	RAT_STALLS.FLAGS	Flag stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x2	RAT_STALLS.REGISTERS	Partial register stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x4	RAT_STALLS.ROB_READ_PORT	ROB read port stalls cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x8	RAT_STALLS.SCOREBOARD	Scoreboard stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x1	RESOURCE_STALLS.ANY	Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x20	RESOURCE_STALLS.FPCW	FPU control word write stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x2	RESOURCE_STALLS.LOAD	Load buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x40	RESOURCE_STALLS.MXCSR	MXCSR rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x80	RESOURCE_STALLS.OTHER	Other Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x10	RESOURCE_STALLS.ROB_FULL	ROB full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x4	RESOURCE_STALLS.RS_FULL	Reservation Station full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x8	RESOURCE_STALLS.STORE	Store buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4	0x7	SB_DRAIN.ANY	All Store buffer stall cycles	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD4	0x1	SEG_RENAME_STALLS	Segment rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x12	0x4	SIMD_INT_128.PACK	128 bit SIMD integer pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x20	SIMD_INT_128.PACKED_ARITH	128 bit SIMD integer arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x10	SIMD_INT_128.PACKED_LOGICAL	128 bit SIMD integer logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x1	SIMD_INT_128.PACKED_MPY	128 bit SIMD integer multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x2	SIMD_INT_128.PACKED_SHIFT	128 bit SIMD integer shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x40	SIMD_INT_128.SHUFFLE_MOVE	128 bit SIMD integer shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x8	SIMD_INT_128.UNPACK	128 bit SIMD integer unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x4	SIMD_INT_64.PACK	SIMD integer 64 bit pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x20	SIMD_INT_64.PACKED_ARITH	SIMD integer 64 bit arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x10	SIMD_INT_64.PACKED_LOGICAL	SIMD integer 64 bit logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x1	SIMD_INT_64.PACKED_MPY	SIMD integer 64 bit packed multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x2	SIMD_INT_64.PACKED_SHIFT	SIMD integer 64 bit shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x40	SIMD_INT_64.SHUFFLE_MOVE	SIMD integer 64 bit shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x8	SIMD_INT_64.UNPACK	SIMD integer 64 bit unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xB8	0x1	SNOOP_RESPONSE.HIT	Thread responded HIT to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x2	SNOOP_RESPONSE.HITE	Thread responded HITE to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x4	SNOOP_RESPONSE.HITM	Thread responded HITM to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF6	0x1	SQ_FULL_STALL_CYCLES	Super Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF4	0x10	SQ_MISC.SPLIT_LOCK	Super Queue lock splits across a cache line	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC7	0x4	SSEX_UOPS_RETIRED.PACKED_DOUBLE	SIMD Packed-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x1	SSEX_UOPS_RETIRED.PACKED_SINGLE	SIMD Packed-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x8	SSEX_UOPS_RETIRED.SCALAR_DOUBLE	SIMD Scalar-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x2	SSEX_UOPS_RETIRED.SCALAR_SINGLE	SIMD Scalar-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x10	SSEX_UOPS_RETIRED.VECTOR_INTEGER	SIMD Vector Integer Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x6	0x4	STORE_BLOCKS.AT_RET	Loads delayed with at-Retirement block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x6	0x8	STORE_BLOCKS.L1D_BLOCK	Cacheable loads delayed with L1D block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x19	0x1	TWO_UOP_INSTS_DECODED	Two Uop instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xDB	0x1	UOP_UNFUSION	Uop unfusions due to FP exceptions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x4	UOPS_DECODED.ESP_FOLDING	Stack pointer instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x8	UOPS_DECODED.ESP_SYNC	Stack pointer sync operations	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x2	UOPS_DECODED.MS_CYCLES_ACTIVE	Uops decoded by Microcode Sequencer	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xD1	0x1	UOPS_DECODED.STALL_CYCLES	Cycles no Uops are decoded	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES	Cycles Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5	Cycles Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_COUNT	Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	1	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5	Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	1	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_CYCLES	Cycles no Uops issued on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5	Cycles no Uops issued on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1	UOPS_EXECUTED.PORT0	Uops executed on port 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015	Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015_STALL_CYCLES	Cycles no Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x2	UOPS_EXECUTED.PORT1	Uops executed on port 1	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x4	UOPS_EXECUTED.PORT2_CORE	Uops executed on port 2 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x80	UOPS_EXECUTED.PORT234_CORE	Uops issued on ports 2, 3 or 4	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x8	UOPS_EXECUTED.PORT3_CORE	Uops executed on port 3 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x10	UOPS_EXECUTED.PORT4_CORE	Uops executed on port 4 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x20	UOPS_EXECUTED.PORT5	Uops executed on port 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.ANY	Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles no Uops were issued on any thread	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xE	0x1	UOPS_ISSUED.CYCLES_ALL_THREADS	Cycles Uops were issued on either thread	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xE	0x2	UOPS_ISSUED.FUSED	Fused Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.STALL_CYCLES	Cycles no Uops were issued	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xC2	0x1	UOPS_RETIRED.ACTIVE_CYCLES	Cycles Uops are being retired	0,1,2,3	2000000	0	0	1	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.ANY	Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x4	UOPS_RETIRED.MACRO_FUSED	Macro-fused Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x2	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.STALL_CYCLES	Cycles Uops are not retiring (Precise Event)	0,1,2,3	2000000	0	0	1	1	0	0	1	
+0xC2	0x1	UOPS_RETIRED.TOTAL_CYCLES	Total cycles using precise uop retired event (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0	Memory instructions retired above 0 clocks (Precise Event)	3	2000000	0x3F6	0x0	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024	Memory instructions retired above 1024 clocks (Precise Event)	3	100	0x3F6	0x400	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128	Memory instructions retired above 128 clocks (Precise Event)	3	1000	0x3F6	0x80	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16	Memory instructions retired above 16 clocks (Precise Event)	3	10000	0x3F6	0x10	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384	Memory instructions retired above 16384 clocks (Precise Event)	3	5	0x3F6	0x4000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048	Memory instructions retired above 2048 clocks (Precise Event)	3	50	0x3F6	0x800	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256	Memory instructions retired above 256 clocks (Precise Event)	3	500	0x3F6	0x100	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32	Memory instructions retired above 32 clocks (Precise Event)	3	5000	0x3F6	0x20	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768	Memory instructions retired above 32768 clocks (Precise Event)	3	3	0x3F6	0x8000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4	Memory instructions retired above 4 clocks (Precise Event)	3	50000	0x3F6	0x4	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096	Memory instructions retired above 4096 clocks (Precise Event)	3	20	0x3F6	0x1000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512	Memory instructions retired above 512 clocks (Precise Event)	3	200	0x3F6	0x200	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64	Memory instructions retired above 64 clocks (Precise Event)	3	2000	0x3F6	0x40	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8	Memory instructions retired above 8 clocks (Precise Event)	3	20000	0x3F6	0x8	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192	Memory instructions retired above 8192 clocks (Precise Event)	3	10	0x3F6	0x2000	0	0	0	0	2	
diff --git a/x86data/perfmon_data/NHM-EP/NehalemEP_offcore_V1.tsv b/x86data/perfmon_data/NHM-EP/NehalemEP_offcore_V1.tsv
new file mode 100644
index 0000000..3076c25
--- /dev/null
+++ b/x86data/perfmon_data/NHM-EP/NehalemEP_offcore_V1.tsv
@@ -0,0 +1,273 @@
+# Performance Monitoring Events for Intel Core i7 and i5 Processors Based on the Nehalem-EP Microarchitecture - V1
+# 12/13/2013 11:01:42 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM	Offcore data reads satisfied by any cache or DRAM	2	100000	0x1A6	0x7F11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM	Offcore data reads satisfied by any DRAM	2	100000	0x1A6	0x6011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS	Offcore data reads that missed the LLC	2	100000	0x1A6	0xF811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION	All offcore data reads	2	100000	0x1A6	0xFF11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO	Offcore data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE	Offcore data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x111	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x211	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x411	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE	Offcore data reads satisfied by the LLC	2	100000	0x1A6	0x711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM	Offcore data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM	Offcore data reads satisfied by the local DRAM	2	100000	0x1A6	0x4011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE	Offcore data reads satisfied by a remote cache	2	100000	0x1A6	0x1811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM	Offcore data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT	Offcore data reads that HIT in a remote cache	2	100000	0x1A6	0x1011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM	Offcore data reads that HITM in a remote cache	2	100000	0x1A6	0x811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM	Offcore data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM	Offcore code reads satisfied by any cache or DRAM	2	100000	0x1A6	0x7F44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM	Offcore code reads satisfied by any DRAM	2	100000	0x1A6	0x6044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS	Offcore code reads that missed the LLC	2	100000	0x1A6	0xF844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION	All offcore code reads	2	100000	0x1A6	0xFF44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO	Offcore code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x144	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x244	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x444	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE	Offcore code reads satisfied by the LLC	2	100000	0x1A6	0x744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM	Offcore code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM	Offcore code reads satisfied by the local DRAM	2	100000	0x1A6	0x4044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE	Offcore code reads satisfied by a remote cache	2	100000	0x1A6	0x1844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM	Offcore code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT	Offcore code reads that HIT in a remote cache	2	100000	0x1A6	0x1044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM	Offcore code reads that HITM in a remote cache	2	100000	0x1A6	0x844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM	Offcore code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM	Offcore requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7FFF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM	Offcore requests satisfied by any DRAM	2	100000	0x1A6	0x60FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS	Offcore requests that missed the LLC	2	100000	0x1A6	0xF8FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION	All offcore requests	2	100000	0x1A6	0xFFFF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO	Offcore requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x80FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE	Offcore requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x1FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT	Offcore requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x2FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM	Offcore requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x4FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE	Offcore requests satisfied by the LLC	2	100000	0x1A6	0x7FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM	Offcore requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x47FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM	Offcore requests satisfied by the local DRAM	2	100000	0x1A6	0x40FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE	Offcore requests satisfied by a remote cache	2	100000	0x1A6	0x18FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM	Offcore requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x38FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT	Offcore requests that HIT in a remote cache	2	100000	0x1A6	0x10FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM	Offcore requests that HITM in a remote cache	2	100000	0x1A6	0x8FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM	Offcore requests satisfied by a remote DRAM	2	100000	0x1A6	0x20FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM	Offcore RFO requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM	Offcore RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS	Offcore RFO requests that missed the LLC	2	100000	0x1A6	0xF822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION	All offcore RFO requests	2	100000	0x1A6	0xFF22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO	Offcore RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE	Offcore RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x122	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x222	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x422	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE	Offcore RFO requests satisfied by the LLC	2	100000	0x1A6	0x722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM	Offcore RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM	Offcore RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE	Offcore RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM	Offcore RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT	Offcore RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM	Offcore RFO requests that HITM in a remote cache	2	100000	0x1A6	0x822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM	Offcore RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM	Offcore writebacks to any cache or DRAM.	2	100000	0x1A6	0x7F08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_DRAM	Offcore writebacks to any DRAM	2	100000	0x1A6	0x6008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS	Offcore writebacks that missed the LLC	2	100000	0x1A6	0xF808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION	All offcore writebacks	2	100000	0x1A6	0xFF08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO	Offcore writebacks to the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE	Offcore writebacks to the LLC and not found in a sibling core	2	100000	0x1A6	0x108	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM	Offcore writebacks to the LLC  and HITM in a sibling core	2	100000	0x1A6	0x408	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE	Offcore writebacks to the LLC	2	100000	0x1A6	0x708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM	Offcore writebacks to the LLC or local DRAM	2	100000	0x1A6	0x4708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM	Offcore writebacks to the local DRAM	2	100000	0x1A6	0x4008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE	Offcore writebacks to a remote cache	2	100000	0x1A6	0x1808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM	Offcore writebacks to a remote cache or remote DRAM	2	100000	0x1A6	0x3808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT	Offcore writebacks that HIT in a remote cache	2	100000	0x1A6	0x1008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM	Offcore writebacks that HITM in a remote cache	2	100000	0x1A6	0x808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM	Offcore writebacks to a remote DRAM	2	100000	0x1A6	0x2008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM	Offcore code or data read requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM	Offcore code or data read requests satisfied by any DRAM	2	100000	0x1A6	0x6077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS	Offcore code or data read requests that missed the LLC	2	100000	0x1A6	0xF877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION	All offcore code or data read requests	2	100000	0x1A6	0xFF77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO	Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore code or data read requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x177	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore code or data read requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x277	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x477	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE	Offcore code or data read requests satisfied by the LLC	2	100000	0x1A6	0x777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM	Offcore code or data read requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM	Offcore code or data read requests satisfied by the local DRAM	2	100000	0x1A6	0x4077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE	Offcore code or data read requests satisfied by a remote cache	2	100000	0x1A6	0x1877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM	Offcore code or data read requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT	Offcore code or data read requests that HIT in a remote cache	2	100000	0x1A6	0x1077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM	Offcore code or data read requests that HITM in a remote cache	2	100000	0x1A6	0x877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM	Offcore code or data read requests satisfied by a remote DRAM	2	100000	0x1A6	0x2077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM	Offcore request = all data, response = any cache_dram	2	100000	0x1A6	0x7F33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM	Offcore request = all data, response = any DRAM	2	100000	0x1A6	0x6033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS	Offcore request = all data, response = any LLC miss	2	100000	0x1A6	0xF833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION	Offcore request = all data, response = any location	2	100000	0x1A6	0xFF33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO	Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE	Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x133	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT	Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x233	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM	Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x433	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE	Offcore request = all data, response = local cache	2	100000	0x1A6	0x733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM	Offcore request = all data, response = local cache or dram	2	100000	0x1A6	0x4733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM	Offcore data reads, RFO's and prefetches statisfied by the local DRAM.	2	100000	0x1A6	0x4033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE	Offcore request = all data, response = remote cache	2	100000	0x1A6	0x1833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM	Offcore request = all data, response = remote cache or dram	2	100000	0x1A6	0x3833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT	Offcore data reads, RFO's and prefetches that HIT in a remote cache 	2	100000	0x1A6	0x1033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM	Offcore data reads, RFO's and prefetches that HITM in a remote cache	2	100000	0x1A6	0x833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM	Offcore data reads, RFO's and prefetches statisfied by the remote DRAM	2	100000	0x1A6	0x2033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM	Offcore demand data requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM	Offcore demand data requests satisfied by any DRAM	2	100000	0x1A6	0x6003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS	Offcore demand data requests that missed the LLC	2	100000	0x1A6	0xF803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION	All offcore demand data requests	2	100000	0x1A6	0xFF03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO	Offcore demand data requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE	Offcore demand data requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x103	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore demand data requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x203	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore demand data requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x403	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE	Offcore demand data requests satisfied by the LLC	2	100000	0x1A6	0x703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM	Offcore demand data requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM	Offcore demand data requests satisfied by the local DRAM	2	100000	0x1A6	0x4003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE	Offcore demand data requests satisfied by a remote cache	2	100000	0x1A6	0x1803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM	Offcore demand data requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT	Offcore demand data requests that HIT in a remote cache	2	100000	0x1A6	0x1003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM	Offcore demand data requests that HITM in a remote cache	2	100000	0x1A6	0x803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM	Offcore demand data requests satisfied by a remote DRAM	2	100000	0x1A6	0x2003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM	Offcore demand data reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM	Offcore demand data reads satisfied by any DRAM	2	100000	0x1A6	0x6001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS	Offcore demand data reads that missed the LLC	2	100000	0x1A6	0xF801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION	All offcore demand data reads	2	100000	0x1A6	0xFF01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO	Offcore demand data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE	Offcore demand data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x101	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT	Offcore demand data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x201	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM	Offcore demand data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x401	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE	Offcore demand data reads satisfied by the LLC	2	100000	0x1A6	0x701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM	Offcore demand data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM	Offcore demand data reads satisfied by the local DRAM	2	100000	0x1A6	0x4001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE	Offcore demand data reads satisfied by a remote cache	2	100000	0x1A6	0x1801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM	Offcore demand data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT	Offcore demand data reads that HIT in a remote cache	2	100000	0x1A6	0x1001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM	Offcore demand data reads that HITM in a remote cache	2	100000	0x1A6	0x801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM	Offcore demand data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM	Offcore demand code reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM	Offcore demand code reads satisfied by any DRAM	2	100000	0x1A6	0x6004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS	Offcore demand code reads that missed the LLC	2	100000	0x1A6	0xF804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION	All offcore demand code reads	2	100000	0x1A6	0xFF04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO	Offcore demand code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore demand code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x104	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore demand code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x204	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore demand code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x404	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE	Offcore demand code reads satisfied by the LLC	2	100000	0x1A6	0x704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM	Offcore demand code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM	Offcore demand code reads satisfied by the local DRAM	2	100000	0x1A6	0x4004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE	Offcore demand code reads satisfied by a remote cache	2	100000	0x1A6	0x1804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM	Offcore demand code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT	Offcore demand code reads that HIT in a remote cache	2	100000	0x1A6	0x1004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM	Offcore demand code reads that HITM in a remote cache	2	100000	0x1A6	0x804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM	Offcore demand code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM	Offcore demand RFO requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM	Offcore demand RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS	Offcore demand RFO requests that missed the LLC	2	100000	0x1A6	0xF802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION	All offcore demand RFO requests	2	100000	0x1A6	0xFF02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO	Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE	Offcore demand RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x102	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x202	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x402	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE	Offcore demand RFO requests satisfied by the LLC	2	100000	0x1A6	0x702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM	Offcore demand RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM	Offcore demand RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE	Offcore demand RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM	Offcore demand RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT	Offcore demand RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM	Offcore demand RFO requests that HITM in a remote cache	2	100000	0x1A6	0x802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM	Offcore demand RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM	Offcore other requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_DRAM	Offcore other requests satisfied by any DRAM	2	100000	0x1A6	0x6080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS	Offcore other requests that missed the LLC	2	100000	0x1A6	0xF880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION	All offcore other requests	2	100000	0x1A6	0xFF80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO	Offcore other requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE	Offcore other requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x180	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT	Offcore other requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x280	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM	Offcore other requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x480	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE	Offcore other requests satisfied by the LLC	2	100000	0x1A6	0x780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM	Offcore other requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE	Offcore other requests satisfied by a remote cache	2	100000	0x1A6	0x1880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM	Offcore other requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT	Offcore other requests that HIT in a remote cache	2	100000	0x1A6	0x1080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM	Offcore other requests that HITM in a remote cache	2	100000	0x1A6	0x880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM	Offcore other requests satisfied by a remote DRAM	2	100000	0x1A6	0x2080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM	Offcore prefetch data requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F30	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM	Offcore prefetch data requests satisfied by any DRAM	2	100000	0x1A6	0x6030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS	Offcore prefetch data requests that missed the LLC	2	100000	0x1A6	0xF830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION	All offcore prefetch data requests	2	100000	0x1A6	0xFF30	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO	Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE	Offcore prefetch data requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x130	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x230	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x430	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE	Offcore prefetch data requests satisfied by the LLC	2	100000	0x1A6	0x730	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM	Offcore prefetch data requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4730	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM	Offcore prefetch data requests satisfied by the local DRAM	2	100000	0x1A6	0x4030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE	Offcore prefetch data requests satisfied by a remote cache	2	100000	0x1A6	0x1830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM	Offcore prefetch data requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT	Offcore prefetch data requests that HIT in a remote cache	2	100000	0x1A6	0x1030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM	Offcore prefetch data requests that HITM in a remote cache	2	100000	0x1A6	0x830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM	Offcore prefetch data requests satisfied by a remote DRAM	2	100000	0x1A6	0x2030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM	Offcore prefetch data reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM	Offcore prefetch data reads satisfied by any DRAM	2	100000	0x1A6	0x6010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS	Offcore prefetch data reads that missed the LLC	2	100000	0x1A6	0xF810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION	All offcore prefetch data reads	2	100000	0x1A6	0xFF10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO	Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE	Offcore prefetch data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x110	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x210	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x410	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE	Offcore prefetch data reads satisfied by the LLC	2	100000	0x1A6	0x710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM	Offcore prefetch data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM	Offcore prefetch data reads satisfied by the local DRAM	2	100000	0x1A6	0x4010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE	Offcore prefetch data reads satisfied by a remote cache	2	100000	0x1A6	0x1810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM	Offcore prefetch data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT	Offcore prefetch data reads that HIT in a remote cache	2	100000	0x1A6	0x1010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM	Offcore prefetch data reads that HITM in a remote cache	2	100000	0x1A6	0x810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM	Offcore prefetch data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM	Offcore prefetch code reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM	Offcore prefetch code reads satisfied by any DRAM	2	100000	0x1A6	0x6040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS	Offcore prefetch code reads that missed the LLC	2	100000	0x1A6	0xF840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION	All offcore prefetch code reads	2	100000	0x1A6	0xFF40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO	Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore prefetch code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x140	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x240	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x440	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE	Offcore prefetch code reads satisfied by the LLC	2	100000	0x1A6	0x740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM	Offcore prefetch code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM	Offcore prefetch code reads satisfied by the local DRAM	2	100000	0x1A6	0x4040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE	Offcore prefetch code reads satisfied by a remote cache	2	100000	0x1A6	0x1840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM	Offcore prefetch code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT	Offcore prefetch code reads that HIT in a remote cache	2	100000	0x1A6	0x1040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM	Offcore prefetch code reads that HITM in a remote cache	2	100000	0x1A6	0x840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM	Offcore prefetch code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM	Offcore prefetch RFO requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM	Offcore prefetch RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS	Offcore prefetch RFO requests that missed the LLC	2	100000	0x1A6	0xF820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION	All offcore prefetch RFO requests	2	100000	0x1A6	0xFF20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO	Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE	Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x120	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x220	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x420	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE	Offcore prefetch RFO requests satisfied by the LLC	2	100000	0x1A6	0x720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM	Offcore prefetch RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM	Offcore prefetch RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE	Offcore prefetch RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM	Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT	Offcore prefetch RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM	Offcore prefetch RFO requests that HITM in a remote cache	2	100000	0x1A6	0x820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM	Offcore prefetch RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM	Offcore prefetch requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM	Offcore prefetch requests satisfied by any DRAM	2	100000	0x1A6	0x6070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS	Offcore prefetch requests that missed the LLC	2	100000	0x1A6	0xF870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION	All offcore prefetch requests	2	100000	0x1A6	0xFF70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO	Offcore prefetch requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE	Offcore prefetch requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x170	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x270	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x470	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE	Offcore prefetch requests satisfied by the LLC	2	100000	0x1A6	0x770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM	Offcore prefetch requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM	Offcore prefetch requests satisfied by the local DRAM	2	100000	0x1A6	0x4070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE	Offcore prefetch requests satisfied by a remote cache	2	100000	0x1A6	0x1870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM	Offcore prefetch requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT	Offcore prefetch requests that HIT in a remote cache	2	100000	0x1A6	0x1070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM	Offcore prefetch requests that HITM in a remote cache	2	100000	0x1A6	0x870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM	Offcore prefetch requests satisfied by a remote DRAM	2	100000	0x1A6	0x2070	0	0	0	0	0	
diff --git a/x86data/perfmon_data/NHM-EX/NehalemEX_core_V1.json b/x86data/perfmon_data/NHM-EX/NehalemEX_core_V1.json
new file mode 100644
index 0000000..439aaf6
--- /dev/null
+++ b/x86data/perfmon_data/NHM-EX/NehalemEX_core_V1.json
@@ -0,0 +1,8866 @@
+[

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.CYCLES_DIV_BUSY",

+    "BriefDescription": "Cycles the divider is busy",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.DIV",

+    "BriefDescription": "Divide Operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x2",

+    "EventName": "ARITH.MUL",

+    "BriefDescription": "Multiply operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x2",

+    "EventName": "BACLEAR.BAD_TARGET",

+    "BriefDescription": "BACLEAR asserted with bad target address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1",

+    "EventName": "BACLEAR.CLEAR",

+    "BriefDescription": "BACLEAR asserted, regardless of cause ",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA7",

+    "UMask": "0x1",

+    "EventName": "BACLEAR_FORCE_IQ",

+    "BriefDescription": "Instruction queue forced BACLEAR",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x1",

+    "EventName": "BPU_CLEARS.EARLY",

+    "BriefDescription": "Early Branch Prediciton Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x2",

+    "EventName": "BPU_CLEARS.LATE",

+    "BriefDescription": "Late Branch Prediction Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE5",

+    "UMask": "0x1",

+    "EventName": "BPU_MISSED_CALL_RET",

+    "BriefDescription": "Branch prediction unit missed call or return",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE0",

+    "UMask": "0x1",

+    "EventName": "BR_INST_DECODED",

+    "BriefDescription": "Branch instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7F",

+    "EventName": "BR_INST_EXEC.ANY",

+    "BriefDescription": "Branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x1",

+    "EventName": "BR_INST_EXEC.COND",

+    "BriefDescription": "Conditional branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x2",

+    "EventName": "BR_INST_EXEC.DIRECT",

+    "BriefDescription": "Unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x10",

+    "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Unconditional call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x20",

+    "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x4",

+    "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x30",

+    "EventName": "BR_INST_EXEC.NEAR_CALLS",

+    "BriefDescription": "Call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7",

+    "EventName": "BR_INST_EXEC.NON_CALLS",

+    "BriefDescription": "All non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x8",

+    "EventName": "BR_INST_EXEC.RETURN_NEAR",

+    "BriefDescription": "Indirect return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x40",

+    "EventName": "BR_INST_EXEC.TAKEN",

+    "BriefDescription": "Taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x1",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Retired conditional branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Retired near call instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",

+    "BriefDescription": "Retired near call instructions Ring 3 only(Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7F",

+    "EventName": "BR_MISP_EXEC.ANY",

+    "BriefDescription": "Mispredicted branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x1",

+    "EventName": "BR_MISP_EXEC.COND",

+    "BriefDescription": "Mispredicted conditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_EXEC.DIRECT",

+    "BriefDescription": "Mispredicted unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x10",

+    "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Mispredicted indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x30",

+    "EventName": "BR_MISP_EXEC.NEAR_CALLS",

+    "BriefDescription": "Mispredicted call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7",

+    "EventName": "BR_MISP_EXEC.NON_CALLS",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x8",

+    "EventName": "BR_MISP_EXEC.RETURN_NEAR",

+    "BriefDescription": "Mispredicted return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x40",

+    "EventName": "BR_MISP_EXEC.TAKEN",

+    "BriefDescription": "Mispredicted taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_RETIRED.NEAR_CALL",

+    "BriefDescription": "Mispredicted near retired calls (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x2",

+    "EventName": "CACHE_LOCK_CYCLES.L1D",

+    "BriefDescription": "Cycles L1D locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x1",

+    "EventName": "CACHE_LOCK_CYCLES.L1D_L2",

+    "BriefDescription": "Cycles L1D and L2 locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.REF",

+    "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x1",

+    "EventName": "CPU_CLK_UNHALTED.REF_P",

+    "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 2",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",

+    "BriefDescription": "Total CPU cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "2",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x1",

+    "EventName": "DTLB_LOAD_MISSES.ANY",

+    "BriefDescription": "DTLB load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.PDE_MISS",

+    "BriefDescription": "DTLB load miss caused by low part of address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x2",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB load miss page walks complete",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x1",

+    "EventName": "DTLB_MISSES.ANY",

+    "BriefDescription": "DTLB misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB first level misses but second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x2",

+    "EventName": "DTLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD5",

+    "UMask": "0x1",

+    "EventName": "ES_REG_RENAMES",

+    "BriefDescription": "ES segment renames",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x1",

+    "EventName": "FP_ASSIST.ALL",

+    "BriefDescription": "X87 Floating point assists (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x4",

+    "EventName": "FP_ASSIST.INPUT",

+    "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x2",

+    "EventName": "FP_ASSIST.OUTPUT",

+    "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x2",

+    "EventName": "FP_COMP_OPS_EXE.MMX",

+    "BriefDescription": "MMX Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",

+    "BriefDescription": "SSE* FP double precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x4",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP",

+    "BriefDescription": "SSE and SSE2 FP Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",

+    "BriefDescription": "SSE FP packed Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",

+    "BriefDescription": "SSE FP scalar Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",

+    "BriefDescription": "SSE* FP single precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x8",

+    "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",

+    "BriefDescription": "SSE2 integer Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x1",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Computational floating-point operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x3",

+    "EventName": "FP_MMX_TRANS.ANY",

+    "BriefDescription": "All Floating Point to and from MMX transitions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x1",

+    "EventName": "FP_MMX_TRANS.TO_FP",

+    "BriefDescription": "Transitions from MMX to Floating Point instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x2",

+    "EventName": "FP_MMX_TRANS.TO_MMX",

+    "BriefDescription": "Transitions from Floating Point to MMX instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0xF",

+    "EventName": "ILD_STALL.ANY",

+    "BriefDescription": "Any Instruction Length Decoder stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x4",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Instruction Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x1",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Length Change Prefix stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x2",

+    "EventName": "ILD_STALL.MRU",

+    "BriefDescription": "Stall cycles due to BPU MRU bypass",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x8",

+    "EventName": "ILD_STALL.REGEN",

+    "BriefDescription": "Regen stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x18",

+    "UMask": "0x1",

+    "EventName": "INST_DECODED.DEC0",

+    "BriefDescription": "Instructions that must be decoded by decoder 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x1E",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITE_CYCLES",

+    "BriefDescription": "Cycles instructions are written to the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x17",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITES",

+    "BriefDescription": "Instructions written to instruction queue.",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired (fixed counter)",

+    "Counter": "Fixed counter 1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x4",

+    "EventName": "INST_RETIRED.MMX",

+    "BriefDescription": "Retired MMX instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x2",

+    "EventName": "INST_RETIRED.X87",

+    "BriefDescription": "Retired floating-point operations (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6C",

+    "UMask": "0x1",

+    "EventName": "IO_TRANSACTIONS",

+    "BriefDescription": "I/O transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x1",

+    "EventName": "ITLB_FLUSH",

+    "BriefDescription": "ITLB flushes",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISS_RETIRED",

+    "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x1",

+    "EventName": "ITLB_MISSES.ANY",

+    "BriefDescription": "ITLB miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x2",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "ITLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x4",

+    "EventName": "L1D.M_EVICT",

+    "BriefDescription": "L1D cache lines replaced in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x2",

+    "EventName": "L1D.M_REPL",

+    "BriefDescription": "L1D cache lines allocated in the M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x8",

+    "EventName": "L1D.M_SNOOP_EVICT",

+    "BriefDescription": "L1D snoop eviction of cache lines in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x1",

+    "EventName": "L1D.REPL",

+    "BriefDescription": "L1 data cache lines allocated",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x43",

+    "UMask": "0x1",

+    "EventName": "L1D_ALL_REF.ANY",

+    "BriefDescription": "All references to the L1 data cache",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x43",

+    "UMask": "0x2",

+    "EventName": "L1D_ALL_REF.CACHEABLE",

+    "BriefDescription": "L1 data cacheable reads and writes",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0x4",

+    "EventName": "L1D_CACHE_LD.E_STATE",

+    "BriefDescription": "L1 data cache read in E state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_LD.I_STATE",

+    "BriefDescription": "L1 data cache read in I state (misses)",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0x8",

+    "EventName": "L1D_CACHE_LD.M_STATE",

+    "BriefDescription": "L1 data cache read in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0xF",

+    "EventName": "L1D_CACHE_LD.MESI",

+    "BriefDescription": "L1 data cache reads",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x40",

+    "UMask": "0x2",

+    "EventName": "L1D_CACHE_LD.S_STATE",

+    "BriefDescription": "L1 data cache read in S state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x42",

+    "UMask": "0x4",

+    "EventName": "L1D_CACHE_LOCK.E_STATE",

+    "BriefDescription": "L1 data cache load locks in E state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x42",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_LOCK.HIT",

+    "BriefDescription": "L1 data cache load lock hits",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x42",

+    "UMask": "0x8",

+    "EventName": "L1D_CACHE_LOCK.M_STATE",

+    "BriefDescription": "L1 data cache load locks in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x42",

+    "UMask": "0x2",

+    "EventName": "L1D_CACHE_LOCK.S_STATE",

+    "BriefDescription": "L1 data cache load locks in S state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x53",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_LOCK_FB_HIT",

+    "BriefDescription": "L1D load lock accepted in fill buffer",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x52",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",

+    "BriefDescription": "L1D prefetch load lock accepted in fill buffer",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x41",

+    "UMask": "0x4",

+    "EventName": "L1D_CACHE_ST.E_STATE",

+    "BriefDescription": "L1 data cache stores in E state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x41",

+    "UMask": "0x8",

+    "EventName": "L1D_CACHE_ST.M_STATE",

+    "BriefDescription": "L1 data cache stores in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x41",

+    "UMask": "0x2",

+    "EventName": "L1D_CACHE_ST.S_STATE",

+    "BriefDescription": "L1 data cache stores in S state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x2",

+    "EventName": "L1D_PREFETCH.MISS",

+    "BriefDescription": "L1D hardware prefetch misses",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x1",

+    "EventName": "L1D_PREFETCH.REQUESTS",

+    "BriefDescription": "L1D hardware prefetch requests",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x4",

+    "EventName": "L1D_PREFETCH.TRIGGERS",

+    "BriefDescription": "L1D hardware prefetch requests triggered",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x4",

+    "EventName": "L1D_WB_L2.E_STATE",

+    "BriefDescription": "L1 writebacks to L2 in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x1",

+    "EventName": "L1D_WB_L2.I_STATE",

+    "BriefDescription": "L1 writebacks to L2 in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x8",

+    "EventName": "L1D_WB_L2.M_STATE",

+    "BriefDescription": "L1 writebacks to L2 in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0xF",

+    "EventName": "L1D_WB_L2.MESI",

+    "BriefDescription": "All L1 writebacks to L2",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x2",

+    "EventName": "L1D_WB_L2.S_STATE",

+    "BriefDescription": "L1 writebacks to L2 in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x4",

+    "EventName": "L1I.CYCLES_STALLED",

+    "BriefDescription": "L1I instruction fetch stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x1",

+    "EventName": "L1I.HITS",

+    "BriefDescription": "L1I instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x2",

+    "EventName": "L1I.MISSES",

+    "BriefDescription": "L1I instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x3",

+    "EventName": "L1I.READS",

+    "BriefDescription": "L1I Instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xFF",

+    "EventName": "L2_DATA_RQSTS.ANY",

+    "BriefDescription": "All L2 data requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x4",

+    "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",

+    "BriefDescription": "L2 data demand loads in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x1",

+    "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",

+    "BriefDescription": "L2 data demand loads in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x8",

+    "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",

+    "BriefDescription": "L2 data demand loads in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF",

+    "EventName": "L2_DATA_RQSTS.DEMAND.MESI",

+    "BriefDescription": "L2 data demand requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x2",

+    "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",

+    "BriefDescription": "L2 data demand loads in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x40",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",

+    "BriefDescription": "L2 data prefetches in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x10",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",

+    "BriefDescription": "L2 data prefetches in the I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x80",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",

+    "BriefDescription": "L2 data prefetches in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF0",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",

+    "BriefDescription": "All L2 data prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x20",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",

+    "BriefDescription": "L2 data prefetches in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x7",

+    "EventName": "L2_LINES_IN.ANY",

+    "BriefDescription": "L2 lines alloacated",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_IN.E_STATE",

+    "BriefDescription": "L2 lines allocated in the E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_IN.S_STATE",

+    "BriefDescription": "L2 lines allocated in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0xF",

+    "EventName": "L2_LINES_OUT.ANY",

+    "BriefDescription": "L2 lines evicted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x1",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "L2 lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",

+    "BriefDescription": "L2 lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x8",

+    "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.IFETCH_HIT",

+    "BriefDescription": "L2 instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.IFETCH_MISS",

+    "BriefDescription": "L2 instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.IFETCHES",

+    "BriefDescription": "L2 instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x1",

+    "EventName": "L2_RQSTS.LD_HIT",

+    "BriefDescription": "L2 load hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x2",

+    "EventName": "L2_RQSTS.LD_MISS",

+    "BriefDescription": "L2 load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3",

+    "EventName": "L2_RQSTS.LOADS",

+    "BriefDescription": "L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xAA",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All L2 misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PREFETCH_HIT",

+    "BriefDescription": "L2 prefetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PREFETCH_MISS",

+    "BriefDescription": "L2 prefetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.PREFETCHES",

+    "BriefDescription": "All L2 prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x4",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "L2 RFO hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x8",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "L2 RFO misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC",

+    "EventName": "L2_RQSTS.RFOS",

+    "BriefDescription": "L2 RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANSACTIONS.ANY",

+    "BriefDescription": "All L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANSACTIONS.FILL",

+    "BriefDescription": "L2 fill transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x4",

+    "EventName": "L2_TRANSACTIONS.IFETCH",

+    "BriefDescription": "L2 instruction fetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANSACTIONS.L1D_WB",

+    "BriefDescription": "L1D writeback to L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x1",

+    "EventName": "L2_TRANSACTIONS.LOAD",

+    "BriefDescription": "L2 Load transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x8",

+    "EventName": "L2_TRANSACTIONS.PREFETCH",

+    "BriefDescription": "L2 prefetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x2",

+    "EventName": "L2_TRANSACTIONS.RFO",

+    "BriefDescription": "L2 RFO transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANSACTIONS.WB",

+    "BriefDescription": "L2 writeback to LLC transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x40",

+    "EventName": "L2_WRITE.LOCK.E_STATE",

+    "BriefDescription": "L2 demand lock RFOs in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE0",

+    "EventName": "L2_WRITE.LOCK.HIT",

+    "BriefDescription": "All demand L2 lock RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x10",

+    "EventName": "L2_WRITE.LOCK.I_STATE",

+    "BriefDescription": "L2 demand lock RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x80",

+    "EventName": "L2_WRITE.LOCK.M_STATE",

+    "BriefDescription": "L2 demand lock RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF0",

+    "EventName": "L2_WRITE.LOCK.MESI",

+    "BriefDescription": "All demand L2 lock RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x20",

+    "EventName": "L2_WRITE.LOCK.S_STATE",

+    "BriefDescription": "L2 demand lock RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE",

+    "EventName": "L2_WRITE.RFO.HIT",

+    "BriefDescription": "All L2 demand store RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x1",

+    "EventName": "L2_WRITE.RFO.I_STATE",

+    "BriefDescription": "L2 demand store RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x8",

+    "EventName": "L2_WRITE.RFO.M_STATE",

+    "BriefDescription": "L2 demand store RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF",

+    "EventName": "L2_WRITE.RFO.MESI",

+    "BriefDescription": "All L2 demand store RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x2",

+    "EventName": "L2_WRITE.RFO.S_STATE",

+    "BriefDescription": "L2 demand store RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x82",

+    "UMask": "0x1",

+    "EventName": "LARGE_ITLB.HIT",

+    "BriefDescription": "Large ITLB hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x7",

+    "EventName": "LOAD_DISPATCH.ANY",

+    "BriefDescription": "All loads dispatched",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x4",

+    "EventName": "LOAD_DISPATCH.MOB",

+    "BriefDescription": "Loads dispatched from the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x1",

+    "EventName": "LOAD_DISPATCH.RS",

+    "BriefDescription": "Loads dispatched that bypass the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x2",

+    "EventName": "LOAD_DISPATCH.RS_DELAYED",

+    "BriefDescription": "Loads dispatched from stage 305",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x1",

+    "EventName": "LOAD_HIT_PRE",

+    "BriefDescription": "Load operations conflicting with software prefetches",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Longest latency cache miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Longest latency cache reference",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.ACTIVE",

+    "BriefDescription": "Cycles when uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.INACTIVE",

+    "BriefDescription": "Cycles no uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x20",

+    "UMask": "0x1",

+    "EventName": "LSD_OVERFLOW",

+    "BriefDescription": "Loops that can't stream from the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x1",

+    "EventName": "MACHINE_CLEARS.CYCLES",

+    "BriefDescription": "Cycles machine clear asserted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x2",

+    "EventName": "MACHINE_CLEARS.MEM_ORDER",

+    "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x4",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-Modifying Code detected",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.DECODED",

+    "BriefDescription": "Instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.FUSIONS_DECODED",

+    "BriefDescription": "Macro-fused instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x1",

+    "EventName": "MEM_INST_RETIRED.LOADS",

+    "BriefDescription": "Instructions retired which contains a load (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x2",

+    "EventName": "MEM_INST_RETIRED.STORES",

+    "BriefDescription": "Instructions retired which contains a store (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x80",

+    "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x1",

+    "EventName": "MEM_LOAD_RETIRED.L1D_HIT",

+    "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x2",

+    "EventName": "MEM_LOAD_RETIRED.L2_HIT",

+    "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_RETIRED.LLC_MISS",

+    "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x4",

+    "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",

+    "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x8",

+    "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",

+    "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC",

+    "UMask": "0x1",

+    "EventName": "MEM_STORE_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x40",

+    "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",

+    "BriefDescription": "Offcore L1 data cache writebacks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_SQ_FULL",

+    "BriefDescription": "Offcore requests blocked due to Super Queue full",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x7",

+    "UMask": "0x1",

+    "EventName": "PARTIAL_ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies due to partial address aliasing",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0xF",

+    "EventName": "RAT_STALLS.ANY",

+    "BriefDescription": "All RAT stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x1",

+    "EventName": "RAT_STALLS.FLAGS",

+    "BriefDescription": "Flag stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x2",

+    "EventName": "RAT_STALLS.REGISTERS",

+    "BriefDescription": "Partial register stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x4",

+    "EventName": "RAT_STALLS.ROB_READ_PORT",

+    "BriefDescription": "ROB read port stalls cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x8",

+    "EventName": "RAT_STALLS.SCOREBOARD",

+    "BriefDescription": "Scoreboard stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x1",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x20",

+    "EventName": "RESOURCE_STALLS.FPCW",

+    "BriefDescription": "FPU control word write stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x2",

+    "EventName": "RESOURCE_STALLS.LOAD",

+    "BriefDescription": "Load buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x40",

+    "EventName": "RESOURCE_STALLS.MXCSR",

+    "BriefDescription": "MXCSR rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x80",

+    "EventName": "RESOURCE_STALLS.OTHER",

+    "BriefDescription": "Other Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB_FULL",

+    "BriefDescription": "ROB full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x4",

+    "EventName": "RESOURCE_STALLS.RS_FULL",

+    "BriefDescription": "Reservation Station full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x8",

+    "EventName": "RESOURCE_STALLS.STORE",

+    "BriefDescription": "Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4",

+    "UMask": "0x7",

+    "EventName": "SB_DRAIN.ANY",

+    "BriefDescription": "All Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD4",

+    "UMask": "0x1",

+    "EventName": "SEG_RENAME_STALLS",

+    "BriefDescription": "Segment rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_128.PACK",

+    "BriefDescription": "128 bit SIMD integer pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_128.PACKED_ARITH",

+    "BriefDescription": "128 bit SIMD integer arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_128.PACKED_LOGICAL",

+    "BriefDescription": "128 bit SIMD integer logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_128.PACKED_MPY",

+    "BriefDescription": "128 bit SIMD integer multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_128.PACKED_SHIFT",

+    "BriefDescription": "128 bit SIMD integer shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_128.SHUFFLE_MOVE",

+    "BriefDescription": "128 bit SIMD integer shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_128.UNPACK",

+    "BriefDescription": "128 bit SIMD integer unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_64.PACK",

+    "BriefDescription": "SIMD integer 64 bit pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_64.PACKED_ARITH",

+    "BriefDescription": "SIMD integer 64 bit arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_64.PACKED_LOGICAL",

+    "BriefDescription": "SIMD integer 64 bit logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_64.PACKED_MPY",

+    "BriefDescription": "SIMD integer 64 bit packed multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_64.PACKED_SHIFT",

+    "BriefDescription": "SIMD integer 64 bit shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_64.SHUFFLE_MOVE",

+    "BriefDescription": "SIMD integer 64 bit shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_64.UNPACK",

+    "BriefDescription": "SIMD integer 64 bit unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x1",

+    "EventName": "SNOOP_RESPONSE.HIT",

+    "BriefDescription": "Thread responded HIT to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x2",

+    "EventName": "SNOOP_RESPONSE.HITE",

+    "BriefDescription": "Thread responded HITE to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x4",

+    "EventName": "SNOOP_RESPONSE.HITM",

+    "BriefDescription": "Thread responded HITM to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF6",

+    "UMask": "0x1",

+    "EventName": "SQ_FULL_STALL_CYCLES",

+    "BriefDescription": "Super Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x10",

+    "EventName": "SQ_MISC.SPLIT_LOCK",

+    "BriefDescription": "Super Queue lock splits across a cache line",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x4",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",

+    "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x1",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",

+    "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x8",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",

+    "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x2",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",

+    "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x10",

+    "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",

+    "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x4",

+    "EventName": "STORE_BLOCKS.AT_RET",

+    "BriefDescription": "Loads delayed with at-Retirement block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x8",

+    "EventName": "STORE_BLOCKS.L1D_BLOCK",

+    "BriefDescription": "Cacheable loads delayed with L1D block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x19",

+    "UMask": "0x1",

+    "EventName": "TWO_UOP_INSTS_DECODED",

+    "BriefDescription": "Two Uop instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xDB",

+    "UMask": "0x1",

+    "EventName": "UOP_UNFUSION",

+    "BriefDescription": "Uop unfusions due to FP exceptions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x4",

+    "EventName": "UOPS_DECODED.ESP_FOLDING",

+    "BriefDescription": "Stack pointer instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x8",

+    "EventName": "UOPS_DECODED.ESP_SYNC",

+    "BriefDescription": "Stack pointer sync operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x2",

+    "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",

+    "BriefDescription": "Uops decoded by Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x1",

+    "EventName": "UOPS_DECODED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops are decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",

+    "BriefDescription": "Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",

+    "BriefDescription": "Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1",

+    "EventName": "UOPS_EXECUTED.PORT0",

+    "BriefDescription": "Uops executed on port 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015",

+    "BriefDescription": "Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x2",

+    "EventName": "UOPS_EXECUTED.PORT1",

+    "BriefDescription": "Uops executed on port 1",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x4",

+    "EventName": "UOPS_EXECUTED.PORT2_CORE",

+    "BriefDescription": "Uops executed on port 2 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED.PORT234_CORE",

+    "BriefDescription": "Uops issued on ports 2, 3 or 4",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x8",

+    "EventName": "UOPS_EXECUTED.PORT3_CORE",

+    "BriefDescription": "Uops executed on port 3 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED.PORT4_CORE",

+    "BriefDescription": "Uops executed on port 4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED.PORT5",

+    "BriefDescription": "Uops executed on port 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued on any thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",

+    "BriefDescription": "Cycles Uops were issued on either thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x2",

+    "EventName": "UOPS_ISSUED.FUSED",

+    "BriefDescription": "Fused Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops are being retired",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ANY",

+    "BriefDescription": "Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x4",

+    "EventName": "UOPS_RETIRED.MACRO_FUSED",

+    "BriefDescription": "Macro-fused Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x2",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles Uops are not retiring (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",

+    "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",

+    "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "100",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x400",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",

+    "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "1000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",

+    "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",

+    "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",

+    "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x800",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",

+    "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "500",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",

+    "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",

+    "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "3",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",

+    "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",

+    "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x1000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",

+    "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "200",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",

+    "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",

+    "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",

+    "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x2000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x111",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x211",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x411",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x144",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x244",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x444",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7FFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM",

+    "BriefDescription": "Offcore requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x60FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS",

+    "BriefDescription": "Offcore requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION",

+    "BriefDescription": "All offcore requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFFFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO",

+    "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x80FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE",

+    "BriefDescription": "Offcore requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x47FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM",

+    "BriefDescription": "Offcore requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x40FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE",

+    "BriefDescription": "Offcore requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x18FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x38FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x10FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x20FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x122",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x222",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x422",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_DRAM",

+    "BriefDescription": "Offcore writebacks to any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS",

+    "BriefDescription": "Offcore writebacks that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION",

+    "BriefDescription": "All offcore writebacks",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO",

+    "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x108",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x408",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE",

+    "BriefDescription": "Offcore writebacks to the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM",

+    "BriefDescription": "Offcore writebacks to the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE",

+    "BriefDescription": "Offcore writebacks to a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore writebacks that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore writebacks that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM",

+    "BriefDescription": "Offcore writebacks to a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore code or data read requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore code or data read requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x177",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x277",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x477",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = any cache_dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM",

+    "BriefDescription": "Offcore request = all data, response = any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS",

+    "BriefDescription": "Offcore request = all data, response = any LLC miss",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION",

+    "BriefDescription": "Offcore request = all data, response = any location",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x133",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x233",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x433",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE",

+    "BriefDescription": "Offcore request = all data, response = local cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = local cache or dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE",

+    "BriefDescription": "Offcore request = all data, response = remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = remote cache or dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand data requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore demand data requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x103",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x203",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x403",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand data requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand data requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION",

+    "BriefDescription": "All offcore demand data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x101",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x201",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x401",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore demand code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x104",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x204",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x404",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore demand RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x102",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x202",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x402",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS",

+    "BriefDescription": "Offcore other requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION",

+    "BriefDescription": "All offcore other requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO",

+    "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x180",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x280",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x480",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE",

+    "BriefDescription": "Offcore other requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore other requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore other requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F30",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch data requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch data requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF30",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x130",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x230",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x430",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x730",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4730",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x110",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x210",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x410",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x140",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x240",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x440",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x120",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x220",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x420",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x170",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x270",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x470",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/NHM-EX/NehalemEX_core_V1.tsv b/x86data/perfmon_data/NHM-EX/NehalemEX_core_V1.tsv
new file mode 100644
index 0000000..b606107
--- /dev/null
+++ b/x86data/perfmon_data/NHM-EX/NehalemEX_core_V1.tsv
@@ -0,0 +1,287 @@
+# Performance Monitoring Events for Intel Xeon Processor Processors Based on the Nehalem-EX Microarchitecture - V1
+# 12/13/2013 10:48:04 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0x14	0x1	ARITH.CYCLES_DIV_BUSY	Cycles the divider is busy	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x14	0x1	ARITH.DIV	Divide Operations executed	0,1,2,3	2000000	0	0	1	1	0	1	0	
+0x14	0x2	ARITH.MUL	Multiply operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x2	BACLEAR.BAD_TARGET	BACLEAR asserted with bad target address	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x1	BACLEAR.CLEAR	BACLEAR asserted, regardless of cause 	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA7	0x1	BACLEAR_FORCE_IQ	Instruction queue forced BACLEAR	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x1	BPU_CLEARS.EARLY	Early Branch Prediciton Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x2	BPU_CLEARS.LATE	Late Branch Prediction Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE5	0x1	BPU_MISSED_CALL_RET	Branch prediction unit missed call or return	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE0	0x1	BR_INST_DECODED	Branch instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x88	0x7F	BR_INST_EXEC.ANY	Branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x1	BR_INST_EXEC.COND	Conditional branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x2	BR_INST_EXEC.DIRECT	Unconditional branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x10	BR_INST_EXEC.DIRECT_NEAR_CALL	Unconditional call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x20	BR_INST_EXEC.INDIRECT_NEAR_CALL	Indirect call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x4	BR_INST_EXEC.INDIRECT_NON_CALL	Indirect non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x30	BR_INST_EXEC.NEAR_CALLS	Call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x7	BR_INST_EXEC.NON_CALLS	All non call branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x8	BR_INST_EXEC.RETURN_NEAR	Indirect return branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x40	BR_INST_EXEC.TAKEN	Taken branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x1	BR_INST_RETIRED.CONDITIONAL	Retired conditional branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL	Retired near call instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL_R3	Retired near call instructions Ring 3 only(Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x89	0x7F	BR_MISP_EXEC.ANY	Mispredicted branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x1	BR_MISP_EXEC.COND	Mispredicted conditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x2	BR_MISP_EXEC.DIRECT	Mispredicted unconditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x10	BR_MISP_EXEC.DIRECT_NEAR_CALL	Mispredicted non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x20	BR_MISP_EXEC.INDIRECT_NEAR_CALL	Mispredicted indirect call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x4	BR_MISP_EXEC.INDIRECT_NON_CALL	Mispredicted indirect non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x30	BR_MISP_EXEC.NEAR_CALLS	Mispredicted call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x7	BR_MISP_EXEC.NON_CALLS	Mispredicted non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x8	BR_MISP_EXEC.RETURN_NEAR	Mispredicted return branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x40	BR_MISP_EXEC.TAKEN	Mispredicted taken branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC5	0x2	BR_MISP_RETIRED.NEAR_CALL	Mispredicted near retired calls (Precise Event)	0,1,2,3	2000	0	0	0	0	0	0	1	
+0x63	0x2	CACHE_LOCK_CYCLES.L1D	Cycles L1D locked	0,1	2000000	0	0	0	0	0	0	0	
+0x63	0x1	CACHE_LOCK_CYCLES.L1D_L2	Cycles L1D and L2 locked	0,1	2000000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.REF	Reference cycles when thread is not halted (fixed counter)	Fixed counter 3	2000000	0	0	0	0	0	0	0	
+0x3C	0x1	CPU_CLK_UNHALTED.REF_P	Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.THREAD	Cycles when thread is not halted (fixed counter)	Fixed counter 2	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.THREAD_P	Cycles when thread is not halted (programmable counter)	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.TOTAL_CYCLES	Total CPU cycles	0,1,2,3	2000000	0	0	2	1	0	0	0	
+0x8	0x1	DTLB_LOAD_MISSES.ANY	DTLB load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x20	DTLB_LOAD_MISSES.PDE_MISS	DTLB load miss caused by low part of address	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x10	DTLB_LOAD_MISSES.STLB_HIT	DTLB second level hit	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x8	0x2	DTLB_LOAD_MISSES.WALK_COMPLETED	DTLB load miss page walks complete	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x1	DTLB_MISSES.ANY	DTLB misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x10	DTLB_MISSES.STLB_HIT	DTLB first level misses but second level hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x2	DTLB_MISSES.WALK_COMPLETED	DTLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD5	0x1	ES_REG_RENAMES	ES segment renames	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF7	0x1	FP_ASSIST.ALL	X87 Floating point assists (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x4	FP_ASSIST.INPUT	X87 Floating poiint assists for invalid input value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x2	FP_ASSIST.OUTPUT	X87 Floating point assists for invalid output value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x10	0x2	FP_COMP_OPS_EXE.MMX	MMX Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x80	FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION	SSE* FP double precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x4	FP_COMP_OPS_EXE.SSE_FP	SSE and SSE2 FP Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x10	FP_COMP_OPS_EXE.SSE_FP_PACKED	SSE FP packed Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x20	FP_COMP_OPS_EXE.SSE_FP_SCALAR	SSE FP scalar Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x40	FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION	SSE* FP single precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x8	FP_COMP_OPS_EXE.SSE2_INTEGER	SSE2 integer Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x1	FP_COMP_OPS_EXE.X87	Computational floating-point operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x3	FP_MMX_TRANS.ANY	All Floating Point to and from MMX transitions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x1	FP_MMX_TRANS.TO_FP	Transitions from MMX to Floating Point instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x2	FP_MMX_TRANS.TO_MMX	Transitions from Floating Point to MMX instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0xF	ILD_STALL.ANY	Any Instruction Length Decoder stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x4	ILD_STALL.IQ_FULL	Instruction Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x1	ILD_STALL.LCP	Length Change Prefix stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x2	ILD_STALL.MRU	Stall cycles due to BPU MRU bypass	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x8	ILD_STALL.REGEN	Regen stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x18	0x1	INST_DECODED.DEC0	Instructions that must be decoded by decoder 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x1E	0x1	INST_QUEUE_WRITE_CYCLES	Cycles instructions are written to the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x17	0x1	INST_QUEUE_WRITES	Instructions written to instruction queue.	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x0	0x0	INST_RETIRED.ANY	Instructions retired (fixed counter)	Fixed counter 1	2000000	0	0	0	0	0	0	0	
+0xC0	0x1	INST_RETIRED.ANY_P	Instructions retired (Programmable counter and Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x4	INST_RETIRED.MMX	Retired MMX instructions (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x1	INST_RETIRED.TOTAL_CYCLES	Total cycles (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC0	0x2	INST_RETIRED.X87	Retired floating-point operations (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0x6C	0x1	IO_TRANSACTIONS	I/O transactions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xAE	0x1	ITLB_FLUSH	ITLB flushes	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC8	0x20	ITLB_MISS_RETIRED	Retired instructions that missed the ITLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x85	0x1	ITLB_MISSES.ANY	ITLB miss	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x2	ITLB_MISSES.WALK_COMPLETED	ITLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x51	0x4	L1D.M_EVICT	L1D cache lines replaced in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x2	L1D.M_REPL	L1D cache lines allocated in the M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x8	L1D.M_SNOOP_EVICT	L1D snoop eviction of cache lines in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x1	L1D.REPL	L1 data cache lines allocated	0,1	2000000	0	0	0	0	0	0	0	
+0x43	0x1	L1D_ALL_REF.ANY	All references to the L1 data cache	0,1	2000000	0	0	0	0	0	0	0	
+0x43	0x2	L1D_ALL_REF.CACHEABLE	L1 data cacheable reads and writes	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0x4	L1D_CACHE_LD.E_STATE	L1 data cache read in E state	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0x1	L1D_CACHE_LD.I_STATE	L1 data cache read in I state (misses)	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0x8	L1D_CACHE_LD.M_STATE	L1 data cache read in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0xF	L1D_CACHE_LD.MESI	L1 data cache reads	0,1	2000000	0	0	0	0	0	0	0	
+0x40	0x2	L1D_CACHE_LD.S_STATE	L1 data cache read in S state	0,1	2000000	0	0	0	0	0	0	0	
+0x42	0x4	L1D_CACHE_LOCK.E_STATE	L1 data cache load locks in E state	0,1	2000000	0	0	0	0	0	0	0	
+0x42	0x1	L1D_CACHE_LOCK.HIT	L1 data cache load lock hits	0,1	2000000	0	0	0	0	0	0	0	
+0x42	0x8	L1D_CACHE_LOCK.M_STATE	L1 data cache load locks in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x42	0x2	L1D_CACHE_LOCK.S_STATE	L1 data cache load locks in S state	0,1	2000000	0	0	0	0	0	0	0	
+0x53	0x1	L1D_CACHE_LOCK_FB_HIT	L1D load lock accepted in fill buffer	0,1	2000000	0	0	0	0	0	0	0	
+0x52	0x1	L1D_CACHE_PREFETCH_LOCK_FB_HIT	L1D prefetch load lock accepted in fill buffer	0,1	2000000	0	0	0	0	0	0	0	
+0x41	0x4	L1D_CACHE_ST.E_STATE	L1 data cache stores in E state	0,1	2000000	0	0	0	0	0	0	0	
+0x41	0x8	L1D_CACHE_ST.M_STATE	L1 data cache stores in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x41	0x2	L1D_CACHE_ST.S_STATE	L1 data cache stores in S state	0,1	2000000	0	0	0	0	0	0	0	
+0x4E	0x2	L1D_PREFETCH.MISS	L1D hardware prefetch misses	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x1	L1D_PREFETCH.REQUESTS	L1D hardware prefetch requests	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x4	L1D_PREFETCH.TRIGGERS	L1D hardware prefetch requests triggered	0,1	200000	0	0	0	0	0	0	0	
+0x28	0x4	L1D_WB_L2.E_STATE	L1 writebacks to L2 in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x1	L1D_WB_L2.I_STATE	L1 writebacks to L2 in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x8	L1D_WB_L2.M_STATE	L1 writebacks to L2 in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0xF	L1D_WB_L2.MESI	All L1 writebacks to L2	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x2	L1D_WB_L2.S_STATE	L1 writebacks to L2 in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x80	0x4	L1I.CYCLES_STALLED	L1I instruction fetch stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x1	L1I.HITS	L1I instruction fetch hits	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x2	L1I.MISSES	L1I instruction fetch misses	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x3	L1I.READS	L1I Instruction fetches	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x26	0xFF	L2_DATA_RQSTS.ANY	All L2 data requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x4	L2_DATA_RQSTS.DEMAND.E_STATE	L2 data demand loads in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x1	L2_DATA_RQSTS.DEMAND.I_STATE	L2 data demand loads in I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x8	L2_DATA_RQSTS.DEMAND.M_STATE	L2 data demand loads in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF	L2_DATA_RQSTS.DEMAND.MESI	L2 data demand requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x2	L2_DATA_RQSTS.DEMAND.S_STATE	L2 data demand loads in S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x40	L2_DATA_RQSTS.PREFETCH.E_STATE	L2 data prefetches in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x10	L2_DATA_RQSTS.PREFETCH.I_STATE	L2 data prefetches in the I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x80	L2_DATA_RQSTS.PREFETCH.M_STATE	L2 data prefetches in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF0	L2_DATA_RQSTS.PREFETCH.MESI	All L2 data prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x20	L2_DATA_RQSTS.PREFETCH.S_STATE	L2 data prefetches in the S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF1	0x7	L2_LINES_IN.ANY	L2 lines alloacated	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x4	L2_LINES_IN.E_STATE	L2 lines allocated in the E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x2	L2_LINES_IN.S_STATE	L2 lines allocated in the S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0xF	L2_LINES_OUT.ANY	L2 lines evicted	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x1	L2_LINES_OUT.DEMAND_CLEAN	L2 lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x2	L2_LINES_OUT.DEMAND_DIRTY	L2 modified lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x4	L2_LINES_OUT.PREFETCH_CLEAN	L2 lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x8	L2_LINES_OUT.PREFETCH_DIRTY	L2 modified lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x24	0x10	L2_RQSTS.IFETCH_HIT	L2 instruction fetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x20	L2_RQSTS.IFETCH_MISS	L2 instruction fetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x30	L2_RQSTS.IFETCHES	L2 instruction fetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x1	L2_RQSTS.LD_HIT	L2 load hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x2	L2_RQSTS.LD_MISS	L2 load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x3	L2_RQSTS.LOADS	L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xAA	L2_RQSTS.MISS	All L2 misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x40	L2_RQSTS.PREFETCH_HIT	L2 prefetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x80	L2_RQSTS.PREFETCH_MISS	L2 prefetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC0	L2_RQSTS.PREFETCHES	All L2 prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x4	L2_RQSTS.RFO_HIT	L2 RFO hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x8	L2_RQSTS.RFO_MISS	L2 RFO misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC	L2_RQSTS.RFOS	L2 RFO requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x80	L2_TRANSACTIONS.ANY	All L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x20	L2_TRANSACTIONS.FILL	L2 fill transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x4	L2_TRANSACTIONS.IFETCH	L2 instruction fetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x10	L2_TRANSACTIONS.L1D_WB	L1D writeback to L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x1	L2_TRANSACTIONS.LOAD	L2 Load transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x8	L2_TRANSACTIONS.PREFETCH	L2 prefetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x2	L2_TRANSACTIONS.RFO	L2 RFO transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x40	L2_TRANSACTIONS.WB	L2 writeback to LLC transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x27	0x40	L2_WRITE.LOCK.E_STATE	L2 demand lock RFOs in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE0	L2_WRITE.LOCK.HIT	All demand L2 lock RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x10	L2_WRITE.LOCK.I_STATE	L2 demand lock RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x80	L2_WRITE.LOCK.M_STATE	L2 demand lock RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF0	L2_WRITE.LOCK.MESI	All demand L2 lock RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x20	L2_WRITE.LOCK.S_STATE	L2 demand lock RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE	L2_WRITE.RFO.HIT	All L2 demand store RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x1	L2_WRITE.RFO.I_STATE	L2 demand store RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x8	L2_WRITE.RFO.M_STATE	L2 demand store RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF	L2_WRITE.RFO.MESI	All L2 demand store RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x2	L2_WRITE.RFO.S_STATE	L2 demand store RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x82	0x1	LARGE_ITLB.HIT	Large ITLB hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x13	0x7	LOAD_DISPATCH.ANY	All loads dispatched	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x4	LOAD_DISPATCH.MOB	Loads dispatched from the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x1	LOAD_DISPATCH.RS	Loads dispatched that bypass the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x2	LOAD_DISPATCH.RS_DELAYED	Loads dispatched from stage 305	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4C	0x1	LOAD_HIT_PRE	Load operations conflicting with software prefetches	0,1	200000	0	0	0	0	0	0	0	
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Longest latency cache miss	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Longest latency cache reference	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xA8	0x1	LSD.ACTIVE	Cycles when uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xA8	0x1	LSD.INACTIVE	Cycles no uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0x20	0x1	LSD_OVERFLOW	Loops that can't stream from the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC3	0x1	MACHINE_CLEARS.CYCLES	Cycles machine clear asserted	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x2	MACHINE_CLEARS.MEM_ORDER	Execution pipeline restart due to Memory ordering conflicts	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x4	MACHINE_CLEARS.SMC	Self-Modifying Code detected	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xD0	0x1	MACRO_INSTS.DECODED	Instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA6	0x1	MACRO_INSTS.FUSIONS_DECODED	Macro-fused instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB	0x1	MEM_INST_RETIRED.LOADS	Instructions retired which contains a load (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xB	0x2	MEM_INST_RETIRED.STORES	Instructions retired which contains a store (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x80	MEM_LOAD_RETIRED.DTLB_MISS	Retired loads that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x40	MEM_LOAD_RETIRED.HIT_LFB	Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x1	MEM_LOAD_RETIRED.L1D_HIT	Retired loads that hit the L1 data cache (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x2	MEM_LOAD_RETIRED.L2_HIT	Retired loads that hit the L2 cache (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x10	MEM_LOAD_RETIRED.LLC_MISS	Retired loads that miss the LLC cache (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xCB	0x4	MEM_LOAD_RETIRED.LLC_UNSHARED_HIT	Retired loads that hit valid versions in the LLC cache (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xCB	0x8	MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM	Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xC	0x1	MEM_STORE_RETIRED.DTLB_MISS	Retired stores that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xB0	0x40	OFFCORE_REQUESTS.L1D_WRITEBACK	Offcore L1 data cache writebacks	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB2	0x1	OFFCORE_REQUESTS_SQ_FULL	Offcore requests blocked due to Super Queue full	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x7	0x1	PARTIAL_ADDRESS_ALIAS	False dependencies due to partial address aliasing	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD2	0xF	RAT_STALLS.ANY	All RAT stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x1	RAT_STALLS.FLAGS	Flag stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x2	RAT_STALLS.REGISTERS	Partial register stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x4	RAT_STALLS.ROB_READ_PORT	ROB read port stalls cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x8	RAT_STALLS.SCOREBOARD	Scoreboard stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x1	RESOURCE_STALLS.ANY	Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x20	RESOURCE_STALLS.FPCW	FPU control word write stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x2	RESOURCE_STALLS.LOAD	Load buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x40	RESOURCE_STALLS.MXCSR	MXCSR rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x80	RESOURCE_STALLS.OTHER	Other Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x10	RESOURCE_STALLS.ROB_FULL	ROB full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x4	RESOURCE_STALLS.RS_FULL	Reservation Station full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x8	RESOURCE_STALLS.STORE	Store buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4	0x7	SB_DRAIN.ANY	All Store buffer stall cycles	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD4	0x1	SEG_RENAME_STALLS	Segment rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x12	0x4	SIMD_INT_128.PACK	128 bit SIMD integer pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x20	SIMD_INT_128.PACKED_ARITH	128 bit SIMD integer arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x10	SIMD_INT_128.PACKED_LOGICAL	128 bit SIMD integer logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x1	SIMD_INT_128.PACKED_MPY	128 bit SIMD integer multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x2	SIMD_INT_128.PACKED_SHIFT	128 bit SIMD integer shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x40	SIMD_INT_128.SHUFFLE_MOVE	128 bit SIMD integer shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x8	SIMD_INT_128.UNPACK	128 bit SIMD integer unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x4	SIMD_INT_64.PACK	SIMD integer 64 bit pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x20	SIMD_INT_64.PACKED_ARITH	SIMD integer 64 bit arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x10	SIMD_INT_64.PACKED_LOGICAL	SIMD integer 64 bit logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x1	SIMD_INT_64.PACKED_MPY	SIMD integer 64 bit packed multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x2	SIMD_INT_64.PACKED_SHIFT	SIMD integer 64 bit shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x40	SIMD_INT_64.SHUFFLE_MOVE	SIMD integer 64 bit shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x8	SIMD_INT_64.UNPACK	SIMD integer 64 bit unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xB8	0x1	SNOOP_RESPONSE.HIT	Thread responded HIT to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x2	SNOOP_RESPONSE.HITE	Thread responded HITE to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x4	SNOOP_RESPONSE.HITM	Thread responded HITM to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF6	0x1	SQ_FULL_STALL_CYCLES	Super Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF4	0x10	SQ_MISC.SPLIT_LOCK	Super Queue lock splits across a cache line	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC7	0x4	SSEX_UOPS_RETIRED.PACKED_DOUBLE	SIMD Packed-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x1	SSEX_UOPS_RETIRED.PACKED_SINGLE	SIMD Packed-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x8	SSEX_UOPS_RETIRED.SCALAR_DOUBLE	SIMD Scalar-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x2	SSEX_UOPS_RETIRED.SCALAR_SINGLE	SIMD Scalar-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x10	SSEX_UOPS_RETIRED.VECTOR_INTEGER	SIMD Vector Integer Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x6	0x4	STORE_BLOCKS.AT_RET	Loads delayed with at-Retirement block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x6	0x8	STORE_BLOCKS.L1D_BLOCK	Cacheable loads delayed with L1D block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x19	0x1	TWO_UOP_INSTS_DECODED	Two Uop instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xDB	0x1	UOP_UNFUSION	Uop unfusions due to FP exceptions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x4	UOPS_DECODED.ESP_FOLDING	Stack pointer instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x8	UOPS_DECODED.ESP_SYNC	Stack pointer sync operations	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x2	UOPS_DECODED.MS_CYCLES_ACTIVE	Uops decoded by Microcode Sequencer	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xD1	0x1	UOPS_DECODED.STALL_CYCLES	Cycles no Uops are decoded	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES	Cycles Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5	Cycles Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_COUNT	Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	1	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5	Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	1	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_CYCLES	Cycles no Uops issued on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5	Cycles no Uops issued on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1	UOPS_EXECUTED.PORT0	Uops executed on port 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015	Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015_STALL_CYCLES	Cycles no Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x2	UOPS_EXECUTED.PORT1	Uops executed on port 1	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x4	UOPS_EXECUTED.PORT2_CORE	Uops executed on port 2 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x80	UOPS_EXECUTED.PORT234_CORE	Uops issued on ports 2, 3 or 4	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x8	UOPS_EXECUTED.PORT3_CORE	Uops executed on port 3 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x10	UOPS_EXECUTED.PORT4_CORE	Uops executed on port 4 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x20	UOPS_EXECUTED.PORT5	Uops executed on port 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.ANY	Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles no Uops were issued on any thread	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xE	0x1	UOPS_ISSUED.CYCLES_ALL_THREADS	Cycles Uops were issued on either thread	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xE	0x2	UOPS_ISSUED.FUSED	Fused Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.STALL_CYCLES	Cycles no Uops were issued	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xC2	0x1	UOPS_RETIRED.ACTIVE_CYCLES	Cycles Uops are being retired	0,1,2,3	2000000	0	0	1	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.ANY	Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x4	UOPS_RETIRED.MACRO_FUSED	Macro-fused Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x2	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.STALL_CYCLES	Cycles Uops are not retiring (Precise Event)	0,1,2,3	2000000	0	0	1	1	0	0	1	
+0xC2	0x1	UOPS_RETIRED.TOTAL_CYCLES	Total cycles using precise uop retired event (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0	Memory instructions retired above 0 clocks (Precise Event)	3	2000000	0x3F6	0x0	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024	Memory instructions retired above 1024 clocks (Precise Event)	3	100	0x3F6	0x400	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128	Memory instructions retired above 128 clocks (Precise Event)	3	1000	0x3F6	0x80	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16	Memory instructions retired above 16 clocks (Precise Event)	3	10000	0x3F6	0x10	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384	Memory instructions retired above 16384 clocks (Precise Event)	3	5	0x3F6	0x4000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048	Memory instructions retired above 2048 clocks (Precise Event)	3	50	0x3F6	0x800	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256	Memory instructions retired above 256 clocks (Precise Event)	3	500	0x3F6	0x100	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32	Memory instructions retired above 32 clocks (Precise Event)	3	5000	0x3F6	0x20	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768	Memory instructions retired above 32768 clocks (Precise Event)	3	3	0x3F6	0x8000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4	Memory instructions retired above 4 clocks (Precise Event)	3	50000	0x3F6	0x4	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096	Memory instructions retired above 4096 clocks (Precise Event)	3	20	0x3F6	0x1000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512	Memory instructions retired above 512 clocks (Precise Event)	3	200	0x3F6	0x200	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64	Memory instructions retired above 64 clocks (Precise Event)	3	2000	0x3F6	0x40	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8	Memory instructions retired above 8 clocks (Precise Event)	3	20000	0x3F6	0x8	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192	Memory instructions retired above 8192 clocks (Precise Event)	3	10	0x3F6	0x2000	0	0	0	0	2	
diff --git a/x86data/perfmon_data/NHM-EX/NehalemEX_offcore_V1.tsv b/x86data/perfmon_data/NHM-EX/NehalemEX_offcore_V1.tsv
new file mode 100644
index 0000000..bbe9227
--- /dev/null
+++ b/x86data/perfmon_data/NHM-EX/NehalemEX_offcore_V1.tsv
@@ -0,0 +1,273 @@
+# Performance Monitoring Events for Intel Xeon Processor Processors Based on the Nehalem-EX Microarchitecture - V1
+# 12/13/2013 10:48:04 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM	Offcore data reads satisfied by any cache or DRAM	2	100000	0x1A6	0x7F11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM	Offcore data reads satisfied by any DRAM	2	100000	0x1A6	0x6011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS	Offcore data reads that missed the LLC	2	100000	0x1A6	0xF811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION	All offcore data reads	2	100000	0x1A6	0xFF11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO	Offcore data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE	Offcore data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x111	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x211	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x411	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE	Offcore data reads satisfied by the LLC	2	100000	0x1A6	0x711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM	Offcore data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM	Offcore data reads satisfied by the local DRAM	2	100000	0x1A6	0x4011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE	Offcore data reads satisfied by a remote cache	2	100000	0x1A6	0x1811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM	Offcore data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT	Offcore data reads that HIT in a remote cache	2	100000	0x1A6	0x1011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM	Offcore data reads that HITM in a remote cache	2	100000	0x1A6	0x811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM	Offcore data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM	Offcore code reads satisfied by any cache or DRAM	2	100000	0x1A6	0x7F44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM	Offcore code reads satisfied by any DRAM	2	100000	0x1A6	0x6044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS	Offcore code reads that missed the LLC	2	100000	0x1A6	0xF844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION	All offcore code reads	2	100000	0x1A6	0xFF44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO	Offcore code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x144	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x244	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x444	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE	Offcore code reads satisfied by the LLC	2	100000	0x1A6	0x744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM	Offcore code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM	Offcore code reads satisfied by the local DRAM	2	100000	0x1A6	0x4044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE	Offcore code reads satisfied by a remote cache	2	100000	0x1A6	0x1844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM	Offcore code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT	Offcore code reads that HIT in a remote cache	2	100000	0x1A6	0x1044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM	Offcore code reads that HITM in a remote cache	2	100000	0x1A6	0x844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM	Offcore code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM	Offcore requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7FFF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM	Offcore requests satisfied by any DRAM	2	100000	0x1A6	0x60FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS	Offcore requests that missed the LLC	2	100000	0x1A6	0xF8FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION	All offcore requests	2	100000	0x1A6	0xFFFF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO	Offcore requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x80FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE	Offcore requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x1FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT	Offcore requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x2FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM	Offcore requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x4FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE	Offcore requests satisfied by the LLC	2	100000	0x1A6	0x7FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM	Offcore requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x47FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM	Offcore requests satisfied by the local DRAM	2	100000	0x1A6	0x40FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE	Offcore requests satisfied by a remote cache	2	100000	0x1A6	0x18FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM	Offcore requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x38FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT	Offcore requests that HIT in a remote cache	2	100000	0x1A6	0x10FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM	Offcore requests that HITM in a remote cache	2	100000	0x1A6	0x8FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM	Offcore requests satisfied by a remote DRAM	2	100000	0x1A6	0x20FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM	Offcore RFO requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM	Offcore RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS	Offcore RFO requests that missed the LLC	2	100000	0x1A6	0xF822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION	All offcore RFO requests	2	100000	0x1A6	0xFF22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO	Offcore RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE	Offcore RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x122	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x222	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x422	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE	Offcore RFO requests satisfied by the LLC	2	100000	0x1A6	0x722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM	Offcore RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM	Offcore RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE	Offcore RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM	Offcore RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT	Offcore RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM	Offcore RFO requests that HITM in a remote cache	2	100000	0x1A6	0x822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM	Offcore RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM	Offcore writebacks to any cache or DRAM.	2	100000	0x1A6	0x7F08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_DRAM	Offcore writebacks to any DRAM	2	100000	0x1A6	0x6008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS	Offcore writebacks that missed the LLC	2	100000	0x1A6	0xF808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION	All offcore writebacks	2	100000	0x1A6	0xFF08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO	Offcore writebacks to the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE	Offcore writebacks to the LLC and not found in a sibling core	2	100000	0x1A6	0x108	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM	Offcore writebacks to the LLC  and HITM in a sibling core	2	100000	0x1A6	0x408	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE	Offcore writebacks to the LLC	2	100000	0x1A6	0x708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM	Offcore writebacks to the LLC or local DRAM	2	100000	0x1A6	0x4708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM	Offcore writebacks to the local DRAM	2	100000	0x1A6	0x4008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE	Offcore writebacks to a remote cache	2	100000	0x1A6	0x1808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM	Offcore writebacks to a remote cache or remote DRAM	2	100000	0x1A6	0x3808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT	Offcore writebacks that HIT in a remote cache	2	100000	0x1A6	0x1008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM	Offcore writebacks that HITM in a remote cache	2	100000	0x1A6	0x808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM	Offcore writebacks to a remote DRAM	2	100000	0x1A6	0x2008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM	Offcore code or data read requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM	Offcore code or data read requests satisfied by any DRAM	2	100000	0x1A6	0x6077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS	Offcore code or data read requests that missed the LLC	2	100000	0x1A6	0xF877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION	All offcore code or data read requests	2	100000	0x1A6	0xFF77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO	Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore code or data read requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x177	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore code or data read requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x277	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x477	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE	Offcore code or data read requests satisfied by the LLC	2	100000	0x1A6	0x777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM	Offcore code or data read requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM	Offcore code or data read requests satisfied by the local DRAM	2	100000	0x1A6	0x4077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE	Offcore code or data read requests satisfied by a remote cache	2	100000	0x1A6	0x1877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM	Offcore code or data read requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT	Offcore code or data read requests that HIT in a remote cache	2	100000	0x1A6	0x1077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM	Offcore code or data read requests that HITM in a remote cache	2	100000	0x1A6	0x877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM	Offcore code or data read requests satisfied by a remote DRAM	2	100000	0x1A6	0x2077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM	Offcore request = all data, response = any cache_dram	2	100000	0x1A6	0x7F33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM	Offcore request = all data, response = any DRAM	2	100000	0x1A6	0x6033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS	Offcore request = all data, response = any LLC miss	2	100000	0x1A6	0xF833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION	Offcore request = all data, response = any location	2	100000	0x1A6	0xFF33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO	Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE	Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x133	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT	Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x233	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM	Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x433	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE	Offcore request = all data, response = local cache	2	100000	0x1A6	0x733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM	Offcore request = all data, response = local cache or dram	2	100000	0x1A6	0x4733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM	Offcore data reads, RFO's and prefetches statisfied by the local DRAM.	2	100000	0x1A6	0x4033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE	Offcore request = all data, response = remote cache	2	100000	0x1A6	0x1833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM	Offcore request = all data, response = remote cache or dram	2	100000	0x1A6	0x3833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT	Offcore data reads, RFO's and prefetches that HIT in a remote cache 	2	100000	0x1A6	0x1033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM	Offcore data reads, RFO's and prefetches that HITM in a remote cache	2	100000	0x1A6	0x833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM	Offcore data reads, RFO's and prefetches statisfied by the remote DRAM	2	100000	0x1A6	0x2033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM	Offcore demand data requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM	Offcore demand data requests satisfied by any DRAM	2	100000	0x1A6	0x6003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS	Offcore demand data requests that missed the LLC	2	100000	0x1A6	0xF803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION	All offcore demand data requests	2	100000	0x1A6	0xFF03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO	Offcore demand data requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE	Offcore demand data requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x103	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore demand data requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x203	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore demand data requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x403	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE	Offcore demand data requests satisfied by the LLC	2	100000	0x1A6	0x703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM	Offcore demand data requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM	Offcore demand data requests satisfied by the local DRAM	2	100000	0x1A6	0x4003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE	Offcore demand data requests satisfied by a remote cache	2	100000	0x1A6	0x1803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM	Offcore demand data requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT	Offcore demand data requests that HIT in a remote cache	2	100000	0x1A6	0x1003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM	Offcore demand data requests that HITM in a remote cache	2	100000	0x1A6	0x803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM	Offcore demand data requests satisfied by a remote DRAM	2	100000	0x1A6	0x2003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM	Offcore demand data reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM	Offcore demand data reads satisfied by any DRAM	2	100000	0x1A6	0x6001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS	Offcore demand data reads that missed the LLC	2	100000	0x1A6	0xF801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION	All offcore demand data reads	2	100000	0x1A6	0xFF01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO	Offcore demand data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE	Offcore demand data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x101	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT	Offcore demand data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x201	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM	Offcore demand data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x401	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE	Offcore demand data reads satisfied by the LLC	2	100000	0x1A6	0x701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM	Offcore demand data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM	Offcore demand data reads satisfied by the local DRAM	2	100000	0x1A6	0x4001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE	Offcore demand data reads satisfied by a remote cache	2	100000	0x1A6	0x1801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM	Offcore demand data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT	Offcore demand data reads that HIT in a remote cache	2	100000	0x1A6	0x1001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM	Offcore demand data reads that HITM in a remote cache	2	100000	0x1A6	0x801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM	Offcore demand data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM	Offcore demand code reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM	Offcore demand code reads satisfied by any DRAM	2	100000	0x1A6	0x6004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS	Offcore demand code reads that missed the LLC	2	100000	0x1A6	0xF804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION	All offcore demand code reads	2	100000	0x1A6	0xFF04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO	Offcore demand code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore demand code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x104	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore demand code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x204	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore demand code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x404	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE	Offcore demand code reads satisfied by the LLC	2	100000	0x1A6	0x704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM	Offcore demand code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM	Offcore demand code reads satisfied by the local DRAM	2	100000	0x1A6	0x4004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE	Offcore demand code reads satisfied by a remote cache	2	100000	0x1A6	0x1804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM	Offcore demand code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT	Offcore demand code reads that HIT in a remote cache	2	100000	0x1A6	0x1004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM	Offcore demand code reads that HITM in a remote cache	2	100000	0x1A6	0x804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM	Offcore demand code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM	Offcore demand RFO requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM	Offcore demand RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS	Offcore demand RFO requests that missed the LLC	2	100000	0x1A6	0xF802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION	All offcore demand RFO requests	2	100000	0x1A6	0xFF02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO	Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE	Offcore demand RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x102	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x202	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x402	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE	Offcore demand RFO requests satisfied by the LLC	2	100000	0x1A6	0x702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM	Offcore demand RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM	Offcore demand RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE	Offcore demand RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM	Offcore demand RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT	Offcore demand RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM	Offcore demand RFO requests that HITM in a remote cache	2	100000	0x1A6	0x802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM	Offcore demand RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM	Offcore other requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_DRAM	Offcore other requests satisfied by any DRAM	2	100000	0x1A6	0x6080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS	Offcore other requests that missed the LLC	2	100000	0x1A6	0xF880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION	All offcore other requests	2	100000	0x1A6	0xFF80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO	Offcore other requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE	Offcore other requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x180	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT	Offcore other requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x280	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM	Offcore other requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x480	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE	Offcore other requests satisfied by the LLC	2	100000	0x1A6	0x780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM	Offcore other requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE	Offcore other requests satisfied by a remote cache	2	100000	0x1A6	0x1880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM	Offcore other requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT	Offcore other requests that HIT in a remote cache	2	100000	0x1A6	0x1080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM	Offcore other requests that HITM in a remote cache	2	100000	0x1A6	0x880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM	Offcore other requests satisfied by a remote DRAM	2	100000	0x1A6	0x2080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM	Offcore prefetch data requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F30	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM	Offcore prefetch data requests satisfied by any DRAM	2	100000	0x1A6	0x6030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS	Offcore prefetch data requests that missed the LLC	2	100000	0x1A6	0xF830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION	All offcore prefetch data requests	2	100000	0x1A6	0xFF30	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO	Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE	Offcore prefetch data requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x130	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x230	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x430	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE	Offcore prefetch data requests satisfied by the LLC	2	100000	0x1A6	0x730	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM	Offcore prefetch data requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4730	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM	Offcore prefetch data requests satisfied by the local DRAM	2	100000	0x1A6	0x4030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE	Offcore prefetch data requests satisfied by a remote cache	2	100000	0x1A6	0x1830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM	Offcore prefetch data requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT	Offcore prefetch data requests that HIT in a remote cache	2	100000	0x1A6	0x1030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM	Offcore prefetch data requests that HITM in a remote cache	2	100000	0x1A6	0x830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM	Offcore prefetch data requests satisfied by a remote DRAM	2	100000	0x1A6	0x2030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM	Offcore prefetch data reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM	Offcore prefetch data reads satisfied by any DRAM	2	100000	0x1A6	0x6010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS	Offcore prefetch data reads that missed the LLC	2	100000	0x1A6	0xF810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION	All offcore prefetch data reads	2	100000	0x1A6	0xFF10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO	Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE	Offcore prefetch data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x110	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x210	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x410	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE	Offcore prefetch data reads satisfied by the LLC	2	100000	0x1A6	0x710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM	Offcore prefetch data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM	Offcore prefetch data reads satisfied by the local DRAM	2	100000	0x1A6	0x4010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE	Offcore prefetch data reads satisfied by a remote cache	2	100000	0x1A6	0x1810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM	Offcore prefetch data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT	Offcore prefetch data reads that HIT in a remote cache	2	100000	0x1A6	0x1010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM	Offcore prefetch data reads that HITM in a remote cache	2	100000	0x1A6	0x810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM	Offcore prefetch data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM	Offcore prefetch code reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM	Offcore prefetch code reads satisfied by any DRAM	2	100000	0x1A6	0x6040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS	Offcore prefetch code reads that missed the LLC	2	100000	0x1A6	0xF840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION	All offcore prefetch code reads	2	100000	0x1A6	0xFF40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO	Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore prefetch code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x140	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x240	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x440	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE	Offcore prefetch code reads satisfied by the LLC	2	100000	0x1A6	0x740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM	Offcore prefetch code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM	Offcore prefetch code reads satisfied by the local DRAM	2	100000	0x1A6	0x4040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE	Offcore prefetch code reads satisfied by a remote cache	2	100000	0x1A6	0x1840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM	Offcore prefetch code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT	Offcore prefetch code reads that HIT in a remote cache	2	100000	0x1A6	0x1040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM	Offcore prefetch code reads that HITM in a remote cache	2	100000	0x1A6	0x840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM	Offcore prefetch code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM	Offcore prefetch RFO requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM	Offcore prefetch RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS	Offcore prefetch RFO requests that missed the LLC	2	100000	0x1A6	0xF820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION	All offcore prefetch RFO requests	2	100000	0x1A6	0xFF20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO	Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE	Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x120	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x220	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x420	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE	Offcore prefetch RFO requests satisfied by the LLC	2	100000	0x1A6	0x720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM	Offcore prefetch RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM	Offcore prefetch RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE	Offcore prefetch RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM	Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT	Offcore prefetch RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM	Offcore prefetch RFO requests that HITM in a remote cache	2	100000	0x1A6	0x820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM	Offcore prefetch RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM	Offcore prefetch requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM	Offcore prefetch requests satisfied by any DRAM	2	100000	0x1A6	0x6070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS	Offcore prefetch requests that missed the LLC	2	100000	0x1A6	0xF870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION	All offcore prefetch requests	2	100000	0x1A6	0xFF70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO	Offcore prefetch requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE	Offcore prefetch requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x170	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x270	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x470	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE	Offcore prefetch requests satisfied by the LLC	2	100000	0x1A6	0x770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM	Offcore prefetch requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM	Offcore prefetch requests satisfied by the local DRAM	2	100000	0x1A6	0x4070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE	Offcore prefetch requests satisfied by a remote cache	2	100000	0x1A6	0x1870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM	Offcore prefetch requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT	Offcore prefetch requests that HIT in a remote cache	2	100000	0x1A6	0x1070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM	Offcore prefetch requests that HITM in a remote cache	2	100000	0x1A6	0x870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM	Offcore prefetch requests satisfied by a remote DRAM	2	100000	0x1A6	0x2070	0	0	0	0	0	
diff --git a/x86data/perfmon_data/SKL/Skylake_FP_ARITH_INST_V13.json b/x86data/perfmon_data/SKL/Skylake_FP_ARITH_INST_V13.json
new file mode 100644
index 0000000..c70f573
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_FP_ARITH_INST_V13.json
@@ -0,0 +1,50 @@
+[
+  {
+    "BitName": "SCALAR_DOUBLE",
+    "BitIndex": 0,
+    "FlopsMultiplier": 1,
+    "Description": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "SCALAR_SINGLE",
+    "BitIndex": 1,
+    "FlopsMultiplier": 1,
+    "Description": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "128BIT_PACKED_DOUBLE",
+    "BitIndex": 2,
+    "FlopsMultiplier": 2,
+    "Description": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "128BIT_PACKED_SINGLE",
+    "BitIndex": 3,
+    "FlopsMultiplier": 4,
+    "Description": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "256BIT_PACKED_DOUBLE",
+    "BitIndex": 4,
+    "FlopsMultiplier": 4,
+    "Description": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "256BIT_PACKED_SINGLE",
+    "BitIndex": 5,
+    "FlopsMultiplier": 8,
+    "Description": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element."
+  },
+  {
+    "BitName": "512BIT_PACKED_DOUBLE ",
+    "BitIndex": 6,
+    "FlopsMultiplier": 8,
+    "Description": "tbd"
+  },
+  {
+    "BitName": "512BIT_PACKED_SINGLE ",
+    "BitIndex": 7,
+    "FlopsMultiplier": 16,
+    "Description": "tbd"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SKL/Skylake_FP_ARITH_INST_V13.tsv b/x86data/perfmon_data/SKL/Skylake_FP_ARITH_INST_V13.tsv
new file mode 100644
index 0000000..ad83701
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_FP_ARITH_INST_V13.tsv
@@ -0,0 +1,12 @@
+# Performance Monitoring Events for the Next+1 Generation Intel Core Processors Based on the Skylake Microarchitecture - V13
+# 9/17/2015 11:13:42 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	FlopsMultiplier	Description
+SCALAR_DOUBLE	0	1	Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+SCALAR_SINGLE	1	1	Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+128BIT_PACKED_DOUBLE	2	2	Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+128BIT_PACKED_SINGLE	3	4	Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+256BIT_PACKED_DOUBLE	4	4	Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+256BIT_PACKED_SINGLE	5	8	Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
+512BIT_PACKED_DOUBLE 	6	8	tbd
+512BIT_PACKED_SINGLE 	7	16	tbd
diff --git a/x86data/perfmon_data/SKL/Skylake_core_V13.json b/x86data/perfmon_data/SKL/Skylake_core_V13.json
new file mode 100644
index 0000000..eeae6e0
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_core_V13.json
@@ -0,0 +1,15600 @@
+[

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired from execution.mem",

+    "PublicDescription": "Instructions retired from execution.mem",

+    "Counter": "Fixed counter 1",

+    "CounterHTOff": "Fixed counter 1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Core cycles when the thread is not in halt state",

+    "PublicDescription": "Core cycles when the thread is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Reference cycles when the core is not in halt state.",

+    "PublicDescription": "Reference cycles when the core is not in halt state.",

+    "Counter": "Fixed counter 3",

+    "CounterHTOff": "Fixed counter 3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x04",

+    "EventName": "ICACHE_16B.IFDATA_STALL",

+    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",

+    "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x83",

+    "UMask": "0x01",

+    "EventName": "ICACHE_64B.IFTAG_HIT",

+    "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",

+    "PublicDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x83",

+    "UMask": "0x02",

+    "EventName": "ICACHE_64B.IFTAG_MISS",

+    "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",

+    "PublicDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x83",

+    "UMask": "0x04",

+    "EventName": "ICACHE_64B.IFTAG_STALL",

+    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",

+    "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Thread cycles when thread is not in halt state",

+    "PublicDescription": "Thread cycles when thread is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x01",

+    "EventName": "BACLEARS.ANY",

+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x01",

+    "EventName": "ITLB.ITLB_FLUSH",

+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "PublicDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.UOPS",

+    "BriefDescription": "Number of Uops delivered by the LSD.",

+    "PublicDescription": "Number of Uops delivered by the LSD.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x01",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

+    "PublicDescription": "Stalls caused by changing prefix length of the instruction.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x20",

+    "EventName": "IDQ.MS_MITE_UOPS",

+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_CYCLES",

+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles MITE is delivering 4 Uops",

+    "PublicDescription": "Cycles MITE is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles MITE is delivering any Uop",

+    "PublicDescription": "Cycles MITE is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",

+    "PublicDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "PublicDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "PublicDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x02",

+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x01",

+    "EventName": "INT_MISC.RECOVERY_CYCLES",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x80",

+    "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",

+    "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",

+    "PublicDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x01",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource-related stall cycles",

+    "PublicDescription": "Resource-related stall cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x08",

+    "EventName": "RESOURCE_STALLS.SB",

+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "PublicDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "PublicDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x20",

+    "EventName": "UOPS_ISSUED.SLOW_LEA",

+    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x01",

+    "EventName": "TX_EXEC.MISC1",

+    "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",

+    "PublicDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x02",

+    "EventName": "TX_EXEC.MISC2",

+    "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",

+    "PublicDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x04",

+    "EventName": "TX_EXEC.MISC3",

+    "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",

+    "PublicDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x08",

+    "EventName": "TX_EXEC.MISC4",

+    "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",

+    "PublicDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5d",

+    "UMask": "0x10",

+    "EventName": "TX_EXEC.MISC5",

+    "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",

+    "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_CYCLES",

+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "PublicDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_END",

+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x01",

+    "EventName": "HLE_RETIRED.START",

+    "BriefDescription": "Number of times an HLE execution started.",

+    "PublicDescription": "Number of times an HLE execution started.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x02",

+    "EventName": "HLE_RETIRED.COMMIT",

+    "BriefDescription": "Number of times an HLE execution successfully committed",

+    "PublicDescription": "Number of times an HLE execution successfully committed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x04",

+    "EventName": "HLE_RETIRED.ABORTED",

+    "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",

+    "PublicDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x08",

+    "EventName": "HLE_RETIRED.ABORTED_MEM",

+    "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "PublicDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x10",

+    "EventName": "HLE_RETIRED.ABORTED_TIMER",

+    "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",

+    "PublicDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x20",

+    "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",

+    "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.). ",

+    "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.). ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x40",

+    "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",

+    "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",

+    "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x80",

+    "EventName": "HLE_RETIRED.ABORTED_EVENTS",

+    "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",

+    "PublicDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC9",

+    "UMask": "0x01",

+    "EventName": "RTM_RETIRED.START",

+    "BriefDescription": "Number of times an RTM execution started.",

+    "PublicDescription": "Number of times an RTM execution started.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC9",

+    "UMask": "0x02",

+    "EventName": "RTM_RETIRED.COMMIT",

+    "BriefDescription": "Number of times an RTM execution successfully committed",

+    "PublicDescription": "Number of times an RTM execution successfully committed",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC9",

+    "UMask": "0x04",

+    "EventName": "RTM_RETIRED.ABORTED",

+    "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",

+    "PublicDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC9",

+    "UMask": "0x08",

+    "EventName": "RTM_RETIRED.ABORTED_MEM",

+    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",

+    "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC9",

+    "UMask": "0x10",

+    "EventName": "RTM_RETIRED.ABORTED_TIMER",

+    "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",

+    "PublicDescription": "Number of times an RTM execution aborted due to uncommon conditions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC9",

+    "UMask": "0x20",

+    "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",

+    "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",

+    "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC9",

+    "UMask": "0x40",

+    "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",

+    "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",

+    "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC9",

+    "UMask": "0x80",

+    "EventName": "RTM_RETIRED.ABORTED_EVENTS",

+    "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",

+    "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.COUNT",

+    "BriefDescription": "Number of machine clears (nukes) of any type. ",

+    "PublicDescription": "Number of machine clears (nukes) of any type. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "PublicDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-modifying code (SMC) detected.",

+    "PublicDescription": "Self-modifying code (SMC) detected.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x01",

+    "EventName": "HW_INTERRUPTS.RECEIVED",

+    "BriefDescription": "Number of hardware interrupts received by the processor.",

+    "PublicDescription": "Number of hardware interrupts received by the processor.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",

+    "PublicDescription": "Number of instructions retired. General Counter   - architectural event",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.PREC_DIST",

+    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",

+    "Counter": "1",

+    "CounterHTOff": "1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x02",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used.",

+    "PublicDescription": "Retirement slots used.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops.",

+    "PublicDescription": "Cycles without actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Cycles with less than 10 actually retired uops.",

+    "PublicDescription": "Cycles with less than 10 actually retired uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "10",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x01",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Conditional branch instructions retired.",

+    "PublicDescription": "Conditional branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x02",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect near call instructions retired.",

+    "PublicDescription": "Direct and indirect near call instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All (macro) branch instructions retired.",

+    "PublicDescription": "All (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x08",

+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",

+    "BriefDescription": "Return instructions retired.",

+    "PublicDescription": "Return instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x10",

+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Not taken branch instructions retired.",

+    "PublicDescription": "Not taken branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x20",

+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "Taken branch instructions retired.",

+    "PublicDescription": "Taken branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x40",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Far branch instructions retired.",

+    "PublicDescription": "Far branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x04",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "All (macro) branch instructions retired. ",

+    "PublicDescription": "All (macro) branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x01",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional branch instructions retired.",

+    "PublicDescription": "Mispredicted conditional branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All mispredicted macro branch instructions retired.",

+    "PublicDescription": "All mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",

+    "PublicDescription": "number of near branch instructions retired that were mispredicted and taken.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x04",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "Mispredicted macro branch instructions retired. ",

+    "PublicDescription": "Mispredicted macro branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x01",

+    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

+    "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x02",

+    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

+    "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x04",

+    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

+    "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x08",

+    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

+    "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ",

+    "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x10",

+    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

+    "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x20",

+    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

+    "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x1E",

+    "EventName": "FP_ASSIST.ANY",

+    "BriefDescription": "Cycles with any input/output SSE or FP assist",

+    "PublicDescription": "Cycles with any input/output SSE or FP assist",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

+    "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.",

+    "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

+    "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.",

+    "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

+    "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.",

+    "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

+    "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.",

+    "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

+    "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.",

+    "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

+    "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.",

+    "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "1009",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

+    "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.",

+    "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "503",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

+    "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.",

+    "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "101",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x11",

+    "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",

+    "BriefDescription": "Retired load instructions that miss the STLB.",

+    "PublicDescription": "Retired load instructions that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x12",

+    "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",

+    "BriefDescription": "Retired store instructions that miss the STLB.",

+    "PublicDescription": "Retired store instructions that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x21",

+    "EventName": "MEM_INST_RETIRED.LOCK_LOADS",

+    "BriefDescription": "Retired load instructions with locked access.",

+    "PublicDescription": "Retired load instructions with locked access.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x41",

+    "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",

+    "BriefDescription": "Retired load instructions that split across a cacheline boundary.",

+    "PublicDescription": "Retired load instructions that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x42",

+    "EventName": "MEM_INST_RETIRED.SPLIT_STORES",

+    "BriefDescription": "Retired store instructions that split across a cacheline boundary.",

+    "PublicDescription": "Retired store instructions that split across a cacheline boundary.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x81",

+    "EventName": "MEM_INST_RETIRED.ALL_LOADS",

+    "BriefDescription": "All retired load instructions.",

+    "PublicDescription": "All retired load instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x82",

+    "EventName": "MEM_INST_RETIRED.ALL_STORES",

+    "BriefDescription": "All retired store instructions.",

+    "PublicDescription": "All retired store instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_RETIRED.L1_HIT",

+    "BriefDescription": "Retired load instructions with L1 cache hits as data sources",

+    "PublicDescription": "Retired load instructions with L1 cache hits as data sources",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_RETIRED.L2_HIT",

+    "BriefDescription": "Retired load instructions with L2 cache hits as data sources",

+    "PublicDescription": "Retired load instructions with L2 cache hits as data sources",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_RETIRED.L3_HIT",

+    "BriefDescription": "Retired load instructions with L3 cache hits as data sources",

+    "PublicDescription": "Retired load instructions with L3 cache hits as data sources",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_RETIRED.L1_MISS",

+    "BriefDescription": "Retired load instructions missed L1 cache as data sources",

+    "PublicDescription": "Retired load instructions missed L1 cache as data sources",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_RETIRED.L2_MISS",

+    "BriefDescription": "Retired load instructions missed L2 cache as data sources",

+    "PublicDescription": "Retired load instructions missed L2 cache as data sources",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x20",

+    "EventName": "MEM_LOAD_RETIRED.L3_MISS",

+    "BriefDescription": "Retired load instructions missed L3 cache as data sources",

+    "PublicDescription": "Retired load instructions missed L3 cache as data sources",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_RETIRED.FB_HIT",

+    "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",

+    "PublicDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",

+    "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",

+    "PublicDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",

+    "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",

+    "PublicDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",

+    "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",

+    "PublicDescription": "Retired load instructions which data sources were HitM responses from shared L3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",

+    "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",

+    "PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops required",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "1",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.DSB_MISS",

+    "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded insturction-cache) miss.",

+    "PublicDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded insturction-cache) miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x11",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.L1I_MISS",

+    "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",

+    "PublicDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x12",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.L2_MISS",

+    "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",

+    "PublicDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x13",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.ITLB_MISS",

+    "BriefDescription": "Retired Instructions who experienced iTLB true miss.",

+    "PublicDescription": "Retired Instructions who experienced iTLB true miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x14",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.STLB_MISS",

+    "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",

+    "PublicDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x15",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x400206",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x200206",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x400406",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.THREAD",

+    "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",

+    "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE",

+    "BriefDescription": "Number of uops executed on the core.",

+    "PublicDescription": "Number of uops executed on the core.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED.X87",

+    "BriefDescription": "Counts the number of x87 uops dispatched.",

+    "PublicDescription": "Counts the number of x87 uops dispatched.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.STALL_CYCLES",

+    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "PublicDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",

+    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",

+    "PublicDescription": "Cycles where at least 1 uop was executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 2 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 3 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",

+    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",

+    "PublicDescription": "Cycles where at least 4 uops were executed per-thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x01",

+    "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",

+    "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",

+    "PublicDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x02",

+    "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",

+    "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",

+    "PublicDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x04",

+    "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",

+    "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",

+    "PublicDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x08",

+    "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",

+    "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",

+    "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x10",

+    "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",

+    "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",

+    "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x40",

+    "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",

+    "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",

+    "PublicDescription": "Cycles where the Store Buffer was full and no outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are executed in port 0",

+    "PublicDescription": "Cycles per thread when uops are executed in port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are executed in port 1",

+    "PublicDescription": "Cycles per thread when uops are executed in port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x04",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when uops are executed in port 2",

+    "PublicDescription": "Cycles per thread when uops are executed in port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x08",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when uops are executed in port 3",

+    "PublicDescription": "Cycles per thread when uops are executed in port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x10",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are executed in port 4",

+    "PublicDescription": "Cycles per thread when uops are executed in port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x20",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are executed in port 5",

+    "PublicDescription": "Cycles per thread when uops are executed in port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_6",

+    "BriefDescription": "Cycles per thread when uops are executed in port 6",

+    "PublicDescription": "Cycles per thread when uops are executed in port 6",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_7",

+    "BriefDescription": "Cycles per thread when uops are executed in port 7",

+    "PublicDescription": "Cycles per thread when uops are executed in port 7",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",

+    "BriefDescription": "Total execution stalls.",

+    "PublicDescription": "Total execution stalls.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4F",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_PENDING",

+    "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",

+    "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x01",

+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Misses at all ITLB levels that cause page walks",

+    "PublicDescription": "Misses at all ITLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x10",

+    "EventName": "ITLB_MISSES.WALK_PENDING",

+    "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request.",

+    "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISSES.STLB_HIT",

+    "BriefDescription": "Intruction fetch requests that miss the ITLB and hit the STLB.",

+    "PublicDescription": "Intruction fetch requests that miss the ITLB and hit the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x01",

+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Load misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Load misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",

+    "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load.",

+    "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "Loads that miss the DTLB and hit the STLB.",

+    "PublicDescription": "Loads that miss the DTLB and hit the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x01",

+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.WALK_PENDING",

+    "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store.",

+    "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x20",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",

+    "BriefDescription": "Stores that miss the DTLB and hit the STLB.",

+    "PublicDescription": "Stores that miss the DTLB and hit the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x01",

+    "EventName": "TLB_FLUSH.DTLB_THREAD",

+    "BriefDescription": "DTLB flush attempts of the thread-specific entries",

+    "PublicDescription": "DTLB flush attempts of the thread-specific entries",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x20",

+    "EventName": "TLB_FLUSH.STLB_ANY",

+    "BriefDescription": "STLB flush attempts",

+    "PublicDescription": "STLB flush attempts",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x08",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",

+    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "8",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x0C",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",

+    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "12",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x01",

+    "EventName": "L1D.REPLACEMENT",

+    "BriefDescription": "L1D data line replacements",

+    "PublicDescription": "L1D data line replacements",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x01",

+    "EventName": "TX_MEM.ABORT_CONFLICT",

+    "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",

+    "PublicDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x02",

+    "EventName": "TX_MEM.ABORT_CAPACITY",

+    "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",

+    "PublicDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x04",

+    "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",

+    "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",

+    "PublicDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x08",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x10",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x20",

+    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",

+    "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",

+    "PublicDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x54",

+    "UMask": "0x40",

+    "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",

+    "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",

+    "PublicDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING",

+    "BriefDescription": "L1D miss oustandings duration in cycles",

+    "PublicDescription": "L1D miss oustandings duration in cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.FB_FULL",

+    "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e",

+    "PublicDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",

+    "BriefDescription": "Cycles with L1D load Misses outstanding.",

+    "PublicDescription": "Cycles with L1D load Misses outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x01",

+    "EventName": "LOAD_HIT_PRE.SW_PF",

+    "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",

+    "PublicDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x02",

+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1D is locked",

+    "PublicDescription": "Cycles when L1D is locked",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "LD_BLOCKS.STORE_FORWARD",

+    "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded .",

+    "PublicDescription": "loads blocked by overlapping with store buffer that cannot be forwarded .",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS.NO_SR",

+    "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",

+    "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies in MOB due to partial compare on address.",

+    "PublicDescription": "False dependencies in MOB due to partial compare on address.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests sent to uncore",

+    "PublicDescription": "Demand Data Read requests sent to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

+    "BriefDescription": "Cacheable and noncachaeble code read requests",

+    "PublicDescription": "Cacheable and noncachaeble code read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",

+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "PublicDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",

+    "BriefDescription": "Demand and prefetch data reads",

+    "PublicDescription": "Demand and prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x10",

+    "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests who miss L3 cache",

+    "PublicDescription": "Demand Data Read requests who miss L3 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x80",

+    "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",

+    "BriefDescription": "Any memory transaction that reached the SQ.",

+    "PublicDescription": "Any memory transaction that reached the SQ.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",

+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "PublicDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",

+    "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle. ",

+    "PublicDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x10",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",

+    "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests who miss L3 cache in the superQ every cycle.",

+    "PublicDescription": "Counts number of Offcore outstanding Demand Data Read requests who miss L3 cache in the superQ every cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",

+    "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",

+    "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",

+    "PublicDescription": "Offcore requests buffer cannot take more entries for this thread core.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",

+    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",

+    "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",

+    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",

+    "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x10",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",

+    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",

+    "PublicDescription": "Cycles while memory subsystem has an outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "16",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x14",

+    "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",

+    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "20",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANS.L2_WB",

+    "BriefDescription": "L2 writebacks that access L2 cache",

+    "PublicDescription": "L2 writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Core-originated cacheable demand requests missed L3",

+    "PublicDescription": "Core-originated cacheable demand requests missed L3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Core-originated cacheable demand requests that refer to L3",

+    "PublicDescription": "Core-originated cacheable demand requests that refer to L3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE",

+    "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",

+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",

+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",

+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x21",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",

+    "BriefDescription": "Demand Data Read miss L2, no rejects",

+    "PublicDescription": "Demand Data Read miss L2, no rejects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x41",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",

+    "BriefDescription": "Demand Data Read requests that hit L2 cache",

+    "PublicDescription": "Demand Data Read requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE1",

+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests",

+    "PublicDescription": "Demand Data Read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE2",

+    "EventName": "L2_RQSTS.ALL_RFO",

+    "BriefDescription": "RFO requests to L2 cache",

+    "PublicDescription": "RFO requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xE4",

+    "EventName": "L2_RQSTS.ALL_CODE_RD",

+    "BriefDescription": "L2 code requests",

+    "PublicDescription": "L2 code requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xF8",

+    "EventName": "L2_RQSTS.ALL_PF",

+    "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",

+    "PublicDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x38",

+    "EventName": "L2_RQSTS.PF_MISS",

+    "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",

+    "PublicDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xd8",

+    "EventName": "L2_RQSTS.PF_HIT",

+    "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",

+    "PublicDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x42",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "RFO requests that hit L2 cache",

+    "PublicDescription": "RFO requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x22",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "RFO requests that miss L2 cache",

+    "PublicDescription": "RFO requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x44",

+    "EventName": "L2_RQSTS.CODE_RD_HIT",

+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",

+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x24",

+    "EventName": "L2_RQSTS.CODE_RD_MISS",

+    "BriefDescription": "L2 cache misses when fetching instructions",

+    "PublicDescription": "L2 cache misses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x27",

+    "EventName": "L2_RQSTS.ALL_DEMAND_MISS",

+    "BriefDescription": "Demand requests that miss L2 cache",

+    "PublicDescription": "Demand requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xe7",

+    "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",

+    "BriefDescription": "Demand requests to L2 cache",

+    "PublicDescription": "Demand requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3F",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All requests that miss L2 cache",

+    "PublicDescription": "All requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "PublicDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_SWITCHES",

+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x0E",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",

+    "PublicDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x0E",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",

+    "PublicDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x0E",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",

+    "PublicDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x1F",

+    "EventName": "L2_LINES_IN.ALL",

+    "BriefDescription": "L2 cache lines filling L2",

+    "PublicDescription": "L2 cache lines filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",

+    "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",

+    "PublicDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",

+    "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",

+    "PublicDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x01",

+    "EventName": "ARITH.DIVIDER_ACTIVE",

+    "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",

+    "PublicDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",

+    "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",

+    "PublicDescription": "Cycles while L3 cache miss demand load is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",

+    "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",

+    "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_ACTIVE",

+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_4_UOPS",

+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x3F",

+    "EventName": "OTHER_ASSISTS.ANY",

+    "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",

+    "PublicDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x10",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ",

+    "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x10",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",

+    "BriefDescription": "Cycles with at least 6 Demand Data Read requests who miss L3 cache in the superQ",

+    "PublicDescription": "Cycles with at least 6 Demand Data Read requests who miss L3 cache in the superQ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x400806",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x401006",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x402006",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x404006",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x408006",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x410006",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x420006",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x100206",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC6",

+    "UMask": "0x01",

+    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",

+    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",

+    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F7",

+    "MSRValue": "0x300206",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",

+    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",

+    "PublicDescription": "Cycles when at least one PMH is busy with a page walk for a store.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",

+    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load.",

+    "PublicDescription": "Cycles when at least one PMH is busy with a page walk for a load.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x02",

+    "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",

+    "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",

+    "PublicDescription": "This event counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register.\r\nFor more information, refer to ?Mixing Intel AVX and Intel SSE Code? section of the Optimization Guide.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",

+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x01",

+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",

+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",

+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",

+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",

+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",

+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",

+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",

+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3ffc008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x203c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x103c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x007c008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc4008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0044008000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0408000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000408000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000408000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400408000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200408000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100408000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080408000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040408000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc01c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20001c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10001c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04001c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts any other requests that hit in the L3 and the snoops sent to sibling cores return clean response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02001c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01001c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00801c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00401c8000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0108000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000108000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000108000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400108000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200108000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100108000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080108000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040108000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0088000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000088000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000088000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400088000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200088000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100088000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080088000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040088000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0048000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000048000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000048000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400048000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200048000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100048000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080048000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040048000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040028000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",

+    "BriefDescription": "Counts any other requests that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000018000 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3ffc000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x203c000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x103c000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x007c000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc4000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0044000800 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0400800 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000400800 ",

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+    "Invert": "0",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

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+    "MSRIndex": "0x1a6,0x1a7",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

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+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400400800 ",

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+    "EdgeDetect": "0",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200400800 ",

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+    "EdgeDetect": "0",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400800 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

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+    "MSRValue": "0x0080400800 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040400800 ",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc01c0800 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20001c0800 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10001c0800 ",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts streaming stores that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

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+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts streaming stores that hit in the L3 and the snoops sent to sibling cores return clean response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts streaming stores that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01001c0800 ",

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+    "EdgeDetect": "0",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

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+    "EdgeDetect": "0",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

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+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00401c0800 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0100800 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000100800 ",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000100800 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400100800 ",

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+    "EdgeDetect": "0",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200100800 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100100800 ",

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+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080100800 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040100800 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0080800 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000080800 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

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+    "L1_Hit_Indication": "0",

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+    "Offcore": "1"

+  },

+  {

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+    "UMask": "0x01",

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+  },

+  {

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+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HIT_NO_FWD",

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+  },

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+    "UMask": "0x01",

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+  },

+  {

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+    "UMask": "0x01",

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+  },

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+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NONE",

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+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",

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+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",

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+  {

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+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NON_DRAM",

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+  {

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+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HITM",

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+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD",

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+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

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+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x007c000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc4000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0044000100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0400100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000400100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000400100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400400100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200400100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080400100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040400100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc01c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20001c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10001c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04001c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02001c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01001c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00801c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00401c0100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0100100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000100100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000100100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400100100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200100100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100100100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080100100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040100100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0080100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000080100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000080100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400080100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200080100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100080100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080080100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040080100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0040100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000040100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000040100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400040100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200040100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100040100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080040100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040040100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040020100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010100 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3ffc000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x203c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x103c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x007c000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc4000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0044000080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0400080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000400080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000400080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400400080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200400080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080400080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040400080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc01c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20001c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10001c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04001c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops sent to sibling cores return clean response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02001c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01001c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00801c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00401c0080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0100080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000100080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000100080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400100080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200100080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100100080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080100080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040100080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0080080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000080080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000080080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400080080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200080080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100080080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080080080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040080080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0040080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000040080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000040080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400040080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200040080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100040080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080040080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040040080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040020080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010080 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3ffc000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x203c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x103c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x007c000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc4000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0044000004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0400004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000400004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000400004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400400004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200400004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080400004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040400004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc01c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20001c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10001c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04001c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops sent to sibling cores return clean response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02001c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01001c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00801c0004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00401c0004 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0100004 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000100004 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000100004 ",

+    "TakenAlone": "0",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400100004 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200100004 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100100004 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080100004 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040100004 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

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+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0080004 ",

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+    "EdgeDetect": "0",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

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+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000080004 ",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

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+    "MSRValue": "0x1000080004 ",

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+    "EdgeDetect": "0",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

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+    "MSRValue": "0x0200080004 ",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100080004 ",

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+    "EdgeDetect": "0",

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+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080080004 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040080004 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0040004 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000040004 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000040004 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400040004 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200040004 ",

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+    "CounterMask": "0",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100040004 ",

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+    "CounterMask": "0",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080040004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040040004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040020004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010004 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3ffc000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x203c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x103c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x007c000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc4000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0044000002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0400002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000400002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000400002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400400002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200400002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080400002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040400002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc01c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20001c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10001c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04001c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops sent to sibling cores return clean response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02001c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01001c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00801c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00401c0002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0100002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000100002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000100002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400100002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200100002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100100002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080100002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040100002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0080002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000080002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000080002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400080002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200080002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100080002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080080002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040080002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0040002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000040002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000040002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400040002 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200040002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100040002 ",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080040002 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040040002 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0020002 ",

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+    "AnyThread": "0",

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+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020002 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020002 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020002 ",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020002 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040020002 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010002 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3ffc000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x203c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x103c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x043c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x023c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x013c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00bc000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x007c000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc4000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2004000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1004000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0404000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0204000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0104000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0084000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0044000001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0400001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000400001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000400001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400400001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200400001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100400001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080400001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040400001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc01c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x20001c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10001c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x04001c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x02001c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",

+    "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x01001c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00801c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00401c0001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0100001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000100001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000100001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400100001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200100001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100100001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080100001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040100001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0080001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000080001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000080001 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400080001 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

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+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200080001 ",

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+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100080001 ",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

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+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080080001 ",

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+    "CounterMask": "0",

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+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040080001 ",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0040001 ",

+    "TakenAlone": "0",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000040001 ",

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+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000040001 ",

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+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400040001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200040001 ",

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+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100040001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080040001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040040001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3fc0020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2000020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0100020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0040020001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts demand data reads that have any response type.",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010001 ",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Data_LA": "0",

+    "L1_Hit_Indication": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SKL/Skylake_core_V13.tsv b/x86data/perfmon_data/SKL/Skylake_core_V13.tsv
new file mode 100644
index 0000000..4ee3bf5
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_core_V13.tsv
@@ -0,0 +1,258 @@
+# Performance Monitoring Events for the Next+1 Generation Intel Core Processors Based on the Skylake Microarchitecture - V13
+# 9/17/2015 11:13:39 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.mem	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x80	0x04	ICACHE_16B.IFDATA_STALL	Cycles where a code fetch is stalled due to L1 instruction cache miss.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x83	0x01	ICACHE_64B.IFTAG_HIT	Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x83	0x02	ICACHE_64B.IFTAG_MISS	Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x83	0x04	ICACHE_64B.IFTAG_STALL	Cycles where a code fetch is stalled due to L1 instruction cache tag miss.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xE6	0x01	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xAE	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0	null
+0xA8	0x01	LSD.UOPS	Number of Uops delivered by the LSD.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0D	0x01	INT_MISC.RECOVERY_CYCLES	Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0D	0x80	INT_MISC.CLEAR_RESTEER_CYCLES	Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x20	UOPS_ISSUED.SLOW_LEA	Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	0	0	0	0	null
+0x5d	0x01	TX_EXEC.MISC1	Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x02	TX_EXEC.MISC2	Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x04	TX_EXEC.MISC3	Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x08	TX_EXEC.MISC4	Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5d	0x10	TX_EXEC.MISC5	Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	1	0	0	0	null
+0xC8	0x01	HLE_RETIRED.START	Number of times an HLE execution started.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC8	0x02	HLE_RETIRED.COMMIT	Number of times an HLE execution successfully committed	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC8	0x04	HLE_RETIRED.ABORTED	Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xC8	0x08	HLE_RETIRED.ABORTED_MEM	Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC8	0x10	HLE_RETIRED.ABORTED_TIMER	Number of times an HLE execution aborted due to hardware timer expiration.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC8	0x20	HLE_RETIRED.ABORTED_UNFRIENDLY	Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.). 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC8	0x40	HLE_RETIRED.ABORTED_MEMTYPE	Number of times an HLE execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC8	0x80	HLE_RETIRED.ABORTED_EVENTS	Number of times an HLE execution aborted due to unfriendly events (such as interrupts).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC9	0x01	RTM_RETIRED.START	Number of times an RTM execution started.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC9	0x02	RTM_RETIRED.COMMIT	Number of times an RTM execution successfully committed	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC9	0x04	RTM_RETIRED.ABORTED	Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0	null
+0xC9	0x08	RTM_RETIRED.ABORTED_MEM	Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC9	0x10	RTM_RETIRED.ABORTED_TIMER	Number of times an RTM execution aborted due to uncommon conditions.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC9	0x20	RTM_RETIRED.ABORTED_UNFRIENDLY	Number of times an RTM execution aborted due to HLE-unfriendly instructions	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC9	0x40	RTM_RETIRED.ABORTED_MEMTYPE	Number of times an RTM execution aborted due to incompatible memory type	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC9	0x80	RTM_RETIRED.ABORTED_EVENTS	Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0	null
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xCB	0x01	HW_INTERRUPTS.RECEIVED	Number of hardware interrupts received by the processor.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC0	0x01	INST_RETIRED.PREC_DIST	Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution	1	1	2000003	0	0	0	0	0	0	0	2	0	0	null
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	10	1	0	0	0	0	0	null
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0	null
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0	null
+0xC5	0x20	BR_MISP_RETIRED.NEAR_TAKEN	number of near branch instructions retired that were mispredicted and taken.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0	null
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. 	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0	null
+0xC7	0x01	FP_ARITH_INST_RETIRED.SCALAR_DOUBLE	Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x02	FP_ARITH_INST_RETIRED.SCALAR_SINGLE	Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x04	FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE	Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x08	FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE	Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x10	FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE	Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xC7	0x20	FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE	Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	0	0	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Counts loads when the latency from first dispatch to completion is greater than 4 cycles.	0,1,2,3	0,1,2,3	100003	0x3F6	0x4	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Counts loads when the latency from first dispatch to completion is greater than 8 cycles.	0,1,2,3	0,1,2,3	50021	0x3F6	0x8	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Counts loads when the latency from first dispatch to completion is greater than 16 cycles.	0,1,2,3	0,1,2,3	20011	0x3F6	0x10	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Counts loads when the latency from first dispatch to completion is greater than 32 cycles.	0,1,2,3	0,1,2,3	100007	0x3F6	0x20	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Counts loads when the latency from first dispatch to completion is greater than 64 cycles.	0,1,2,3	0,1,2,3	2003	0x3F6	0x40	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Counts loads when the latency from first dispatch to completion is greater than 128 cycles.	0,1,2,3	0,1,2,3	1009	0x3F6	0x80	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Counts loads when the latency from first dispatch to completion is greater than 256 cycles.	0,1,2,3	0,1,2,3	503	0x3F6	0x100	1	0	0	0	0	2	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Counts loads when the latency from first dispatch to completion is greater than 512 cycles.	0,1,2,3	0,1,2,3	101	0x3F6	0x200	1	0	0	0	0	2	0	0	null
+0xD0	0x11	MEM_INST_RETIRED.STLB_MISS_LOADS	Retired load instructions that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD0	0x12	MEM_INST_RETIRED.STLB_MISS_STORES	Retired store instructions that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	null
+0xD0	0x21	MEM_INST_RETIRED.LOCK_LOADS	Retired load instructions with locked access.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null
+0xD0	0x41	MEM_INST_RETIRED.SPLIT_LOADS	Retired load instructions that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD0	0x42	MEM_INST_RETIRED.SPLIT_STORES	Retired store instructions that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	1	null
+0xD0	0x81	MEM_INST_RETIRED.ALL_LOADS	All retired load instructions.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	null
+0xD0	0x82	MEM_INST_RETIRED.ALL_STORES	All retired store instructions.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	1	null
+0xD1	0x01	MEM_LOAD_RETIRED.L1_HIT	Retired load instructions with L1 cache hits as data sources	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x02	MEM_LOAD_RETIRED.L2_HIT	Retired load instructions with L2 cache hits as data sources	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x04	MEM_LOAD_RETIRED.L3_HIT	Retired load instructions with L3 cache hits as data sources	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x08	MEM_LOAD_RETIRED.L1_MISS	Retired load instructions missed L1 cache as data sources	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x10	MEM_LOAD_RETIRED.L2_MISS	Retired load instructions missed L2 cache as data sources	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x20	MEM_LOAD_RETIRED.L3_MISS	Retired load instructions missed L3 cache as data sources	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null
+0xD1	0x40	MEM_LOAD_RETIRED.FB_HIT	Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	1	0	null
+0xD2	0x01	MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS	Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null
+0xD2	0x02	MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT	Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null
+0xD2	0x04	MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM	Retired load instructions which data sources were HitM responses from shared L3	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	1	0	null
+0xD2	0x08	MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE	Retired load instructions which data sources were hits in L3 without snoops required	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	1	0	null
+0xC6	0x01	FRONTEND_RETIRED.DSB_MISS	Retired Instructions who experienced decode stream buffer (DSB - the decoded insturction-cache) miss.	0,1,2,3	0,1,2,3	100007	0x3F7	0x11	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.L1I_MISS	Retired Instructions who experienced Instruction L1 Cache true miss.	0,1,2,3	0,1,2,3	100007	0x3F7	0x12	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.L2_MISS	Retired Instructions who experienced Instruction L2 Cache true miss.	0,1,2,3	0,1,2,3	100007	0x3F7	0x13	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.ITLB_MISS	Retired Instructions who experienced iTLB true miss.	0,1,2,3	0,1,2,3	100007	0x3F7	0x14	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.STLB_MISS	Retired Instructions who experienced STLB (2nd level TLB) true miss.	0,1,2,3	0,1,2,3	100007	0x3F7	0x15	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_2	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x400206	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2	Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x200206	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_4	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x400406	1	0	0	0	0	1	0	0	null
+0xB1	0x01	UOPS_EXECUTED.THREAD	Counts the number of uops to be executed per-thread each cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE	Number of uops executed on the core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xB1	0x10	UOPS_EXECUTED.X87	Counts the number of x87 uops dispatched.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.STALL_CYCLES	Counts number of cycles no uops were dispatched to be executed on this thread.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC	Cycles where at least 1 uop was executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC	Cycles where at least 2 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC	Cycles where at least 3 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC	Cycles where at least 4 uops were executed per-thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xA6	0x01	EXE_ACTIVITY.EXE_BOUND_0_PORTS	Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA6	0x02	EXE_ACTIVITY.1_PORTS_UTIL	Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA6	0x04	EXE_ACTIVITY.2_PORTS_UTIL	Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA6	0x08	EXE_ACTIVITY.3_PORTS_UTIL	Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA6	0x10	EXE_ACTIVITY.4_PORTS_UTIL	Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA6	0x40	EXE_ACTIVITY.BOUND_ON_STORES	Cycles where the Store Buffer was full and no outstanding load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are executed in port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are executed in port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x04	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when uops are executed in port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x08	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when uops are executed in port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x10	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are executed in port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x20	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are executed in port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_6	Cycles per thread when uops are executed in port 6	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_7	Cycles per thread when uops are executed in port 7	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.STALLS_TOTAL	Total execution stalls.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0x4F	0x10	EPT.WALK_PENDING	Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x10	ITLB_MISSES.WALK_PENDING	Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x85	0x20	ITLB_MISSES.STLB_HIT	Intruction fetch requests that miss the ITLB and hit the STLB.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x01	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Load misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x10	DTLB_LOAD_MISSES.WALK_PENDING	Counts 1 per cycle for each PMH that is busy with a page walk for a load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x20	DTLB_LOAD_MISSES.STLB_HIT	Loads that miss the DTLB and hit the STLB.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x10	DTLB_STORE_MISSES.WALK_PENDING	Counts 1 per cycle for each PMH that is busy with a page walk for a store.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x20	DTLB_STORE_MISSES.STLB_HIT	Stores that miss the DTLB and hit the STLB.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xBD	0x01	TLB_FLUSH.DTLB_THREAD	DTLB flush attempts of the thread-specific entries	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0	null
+0xBD	0x20	TLB_FLUSH.STLB_ANY	STLB flush attempts	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0	null
+0xA3	0x08	CYCLE_ACTIVITY.CYCLES_L1D_MISS	Cycles while L1 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	8	0	0	0	0	0	0	null
+0xA3	0x0C	CYCLE_ACTIVITY.STALLS_L1D_MISS	Execution stalls while L1 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	12	0	0	0	0	0	0	null
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x01	TX_MEM.ABORT_CONFLICT	Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x02	TX_MEM.ABORT_CAPACITY	Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x04	TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK	Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x08	TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY	Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x10	TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH	Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x20	TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT	Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x54	0x40	TX_MEM.HLE_ELISION_BUFFER_FULL	Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x4C	0x01	LOAD_HIT_PRE.SW_PF	Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	loads blocked by overlapping with store buffer that cannot be forwarded .	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x03	0x08	LD_BLOCKS.NO_SR	The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare on address.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB0	0x10	OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD	Demand Data Read requests who miss L3 cache	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB0	0x80	OFFCORE_REQUESTS.ALL_REQUESTS	Any memory transaction that reached the SQ.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD	Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x10	OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD	Counts number of Offcore outstanding Demand Data Read requests who miss L3 cache in the superQ every cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xB2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Offcore requests buffer cannot take more entries for this thread core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_MISS	Cycles while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_MISS	Execution stalls while L2 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	5	0	0	0	0	0	0	null
+0xA3	0x10	CYCLE_ACTIVITY.CYCLES_MEM_ANY	Cycles while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	16	0	0	0	0	0	0	null
+0xA3	0x14	CYCLE_ACTIVITY.STALLS_MEM_ANY	Execution stalls while memory subsystem has an outstanding load.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	20	0	0	0	0	0	0	null
+0xF0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to L3	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE	Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x3C	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other thread is halted.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x21	L2_RQSTS.DEMAND_DATA_RD_MISS	Demand Data Read miss L2, no rejects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x41	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE1	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE2	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xE4	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xF8	L2_RQSTS.ALL_PF	Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x38	L2_RQSTS.PF_MISS	Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xd8	L2_RQSTS.PF_HIT	Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x42	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x22	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x44	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x24	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x27	L2_RQSTS.ALL_DEMAND_MISS	Demand requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xe7	L2_RQSTS.ALL_DEMAND_REFERENCES	Demand requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0x3F	L2_RQSTS.MISS	All requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null
+0x85	0x0E	ITLB_MISSES.WALK_COMPLETED	Code miss in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x08	0x0E	DTLB_LOAD_MISSES.WALK_COMPLETED	Load miss in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x49	0x0E	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all TLB levels causes a page walk that completes. (All page sizes)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0xF1	0x1F	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x02	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD	Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO	Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x14	0x01	ARITH.DIVIDER_ACTIVE	Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_L3_MISS	Cycles while L3 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_L3_MISS	Execution stalls while L3 cache miss demand load is outstanding.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xC1	0x3F	OTHER_ASSISTS.ANY	Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0	null
+0x60	0x10	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD	Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0x60	0x10	OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6	Cycles with at least 6 Demand Data Read requests who miss L3 cache in the superQ	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_8	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x400806	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_16	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x401006	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_32	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x402006	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_64	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x404006	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_128	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x408006	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_256	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall	0,1,2,3	0,1,2,3	100007	0x3F7	0x410006	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_512	Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x420006	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1	Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x100206	1	0	0	0	0	1	0	0	null
+0xC6	0x01	FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3	Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.	0,1,2,3	0,1,2,3	100007	0x3F7	0x300206	1	0	0	0	0	1	0	0	null
+0x49	0x10	DTLB_STORE_MISSES.WALK_ACTIVE	Cycles when at least one PMH is busy with a page walk for a store.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	0	0	0	0	null
+0x08	0x10	DTLB_LOAD_MISSES.WALK_ACTIVE	Cycles when at least one PMH is busy with a page walk for a load.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	0	0	0	0	null
+0x0E	0x02	UOPS_ISSUED.VECTOR_WIDTH_MISMATCH	Uops inserted at issue-stage in order to preserve upper bits of vector registers.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0x0D	0x01	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/SKL/Skylake_matrix_V13.json b/x86data/perfmon_data/SKL/Skylake_matrix_V13.json
new file mode 100644
index 0000000..e07dbe5
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_matrix_V13.json
@@ -0,0 +1,513 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand data reads"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand data writes (RFOs)"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L3_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L3_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "STREAMING_STORES",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000800",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts streaming stores"
+  },
+  {
+    "MATRIX_REQUEST": "OTHER",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any other requests"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "ANY_RESPONSE",
+    "MATRIX_VALUE": "0x0000010000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "have any response type."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SPL_HIT",
+    "MATRIX_VALUE": "0x0040020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_NONE",
+    "MATRIX_VALUE": "0x0080020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x0100020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0200020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x0400020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_HITM",
+    "MATRIX_VALUE": "0x1000020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x2000020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "SUPPLIER_NONE.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3fc0020000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_M.SPL_HIT",
+    "MATRIX_VALUE": "0x0040040000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_M.SNOOP_NONE",
+    "MATRIX_VALUE": "0x0080040000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_M.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x0100040000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_M.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0200040000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_M.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x0400040000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_M.SNOOP_HITM",
+    "MATRIX_VALUE": "0x1000040000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_M.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x2000040000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_M.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3fc0040000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_E.SPL_HIT",
+    "MATRIX_VALUE": "0x0040080000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_E.SNOOP_NONE",
+    "MATRIX_VALUE": "0x0080080000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_E.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x0100080000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_E.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0200080000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_E.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x0400080000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_E.SNOOP_HITM",
+    "MATRIX_VALUE": "0x1000080000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_E.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x2000080000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_E.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3fc0080000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_S.SPL_HIT",
+    "MATRIX_VALUE": "0x0040100000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_S.SNOOP_NONE",
+    "MATRIX_VALUE": "0x0080100000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_S.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x0100100000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_S.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0200100000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_S.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x0400100000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_S.SNOOP_HITM",
+    "MATRIX_VALUE": "0x1000100000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_S.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x2000100000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT_S.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3fc0100000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SPL_HIT",
+    "MATRIX_VALUE": "0x00401c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_NONE",
+    "MATRIX_VALUE": "0x00801c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x01001c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_MISS",
+    "MATRIX_VALUE": "0x02001c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoops sent to sibling cores return clean response."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x04001c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded."
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_HITM",
+    "MATRIX_VALUE": "0x10001c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x20001c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_HIT.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3fc01c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.SPL_HIT",
+    "MATRIX_VALUE": "0x0040400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.SNOOP_NONE",
+    "MATRIX_VALUE": "0x0080400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x0100400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0200400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x0400400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.SNOOP_HIT_WITH_FWD",
+    "MATRIX_VALUE": "0x0800400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.SNOOP_HITM",
+    "MATRIX_VALUE": "0x1000400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x2000400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L4_HIT_LOCAL_L4.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3fc0400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SPL_HIT",
+    "MATRIX_VALUE": "0x0044000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_NONE",
+    "MATRIX_VALUE": "0x0084000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x0104000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0204000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x0404000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_HITM",
+    "MATRIX_VALUE": "0x1004000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x2004000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS_LOCAL_DRAM.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3fc4000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SPL_HIT",
+    "MATRIX_VALUE": "0x007c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_NONE",
+    "MATRIX_VALUE": "0x00bc000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_NOT_NEEDED",
+    "MATRIX_VALUE": "0x013c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_MISS",
+    "MATRIX_VALUE": "0x023c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_HIT_NO_FWD",
+    "MATRIX_VALUE": "0x043c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_HITM",
+    "MATRIX_VALUE": "0x103c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.SNOOP_NON_DRAM",
+    "MATRIX_VALUE": "0x203c000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L3_MISS.ANY_SNOOP",
+    "MATRIX_VALUE": "0x3ffc000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "tbd"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SKL/Skylake_matrix_V13.tsv b/x86data/perfmon_data/SKL/Skylake_matrix_V13.tsv
new file mode 100644
index 0000000..0f666bf
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_matrix_V13.tsv
@@ -0,0 +1,77 @@
+# Performance Monitoring Events for the Next+1 Generation Intel Core Processors Based on the Skylake Microarchitecture - V13
+# 9/17/2015 11:13:39 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand data reads
+DEMAND_RFO	Null	0x0002	0,1	Counts all demand data writes (RFOs)
+DEMAND_CODE_RD	Null	0x0004	0,1	Counts all demand code reads
+PF_L3_DATA_RD	Null	0x0080	0,1	Counts all prefetch (that bring data to LLC only) data reads
+PF_L3_RFO	Null	0x0100	0,1	Counts all prefetch (that bring data to LLC only) RFOs
+STREAMING_STORES	Null	0x0800	0,1	Counts streaming stores
+OTHER	Null	0x8000	0,1	Counts any other requests
+Null	ANY_RESPONSE	0x000001	0,1	have any response type.
+Null	SUPPLIER_NONE.SPL_HIT	0x004002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_NONE	0x008002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_NOT_NEEDED	0x010002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_MISS	0x020002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_HIT_NO_FWD	0x040002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_HITM	0x100002	0,1	tbd
+Null	SUPPLIER_NONE.SNOOP_NON_DRAM	0x200002	0,1	tbd
+Null	SUPPLIER_NONE.ANY_SNOOP	0x3fc002	0,1	tbd
+Null	L3_HIT_M.SPL_HIT	0x004004	0,1	tbd
+Null	L3_HIT_M.SNOOP_NONE	0x008004	0,1	tbd
+Null	L3_HIT_M.SNOOP_NOT_NEEDED	0x010004	0,1	tbd
+Null	L3_HIT_M.SNOOP_MISS	0x020004	0,1	tbd
+Null	L3_HIT_M.SNOOP_HIT_NO_FWD	0x040004	0,1	tbd
+Null	L3_HIT_M.SNOOP_HITM	0x100004	0,1	tbd
+Null	L3_HIT_M.SNOOP_NON_DRAM	0x200004	0,1	tbd
+Null	L3_HIT_M.ANY_SNOOP	0x3fc004	0,1	tbd
+Null	L3_HIT_E.SPL_HIT	0x004008	0,1	tbd
+Null	L3_HIT_E.SNOOP_NONE	0x008008	0,1	tbd
+Null	L3_HIT_E.SNOOP_NOT_NEEDED	0x010008	0,1	tbd
+Null	L3_HIT_E.SNOOP_MISS	0x020008	0,1	tbd
+Null	L3_HIT_E.SNOOP_HIT_NO_FWD	0x040008	0,1	tbd
+Null	L3_HIT_E.SNOOP_HITM	0x100008	0,1	tbd
+Null	L3_HIT_E.SNOOP_NON_DRAM	0x200008	0,1	tbd
+Null	L3_HIT_E.ANY_SNOOP	0x3fc008	0,1	tbd
+Null	L3_HIT_S.SPL_HIT	0x004010	0,1	tbd
+Null	L3_HIT_S.SNOOP_NONE	0x008010	0,1	tbd
+Null	L3_HIT_S.SNOOP_NOT_NEEDED	0x010010	0,1	tbd
+Null	L3_HIT_S.SNOOP_MISS	0x020010	0,1	tbd
+Null	L3_HIT_S.SNOOP_HIT_NO_FWD	0x040010	0,1	tbd
+Null	L3_HIT_S.SNOOP_HITM	0x100010	0,1	tbd
+Null	L3_HIT_S.SNOOP_NON_DRAM	0x200010	0,1	tbd
+Null	L3_HIT_S.ANY_SNOOP	0x3fc010	0,1	tbd
+Null	L3_HIT.SPL_HIT	0x00401c	0,1	tbd
+Null	L3_HIT.SNOOP_NONE	0x00801c	0,1	tbd
+Null	L3_HIT.SNOOP_NOT_NEEDED	0x01001c	0,1	hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.
+Null	L3_HIT.SNOOP_MISS	0x02001c	0,1	hit in the L3 and the snoops sent to sibling cores return clean response.
+Null	L3_HIT.SNOOP_HIT_NO_FWD	0x04001c	0,1	hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
+Null	L3_HIT.SNOOP_HITM	0x10001c	0,1	tbd
+Null	L3_HIT.SNOOP_NON_DRAM	0x20001c	0,1	tbd
+Null	L3_HIT.ANY_SNOOP	0x3fc01c	0,1	tbd
+Null	L4_HIT_LOCAL_L4.SPL_HIT	0x004040	0,1	tbd
+Null	L4_HIT_LOCAL_L4.SNOOP_NONE	0x008040	0,1	tbd
+Null	L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED	0x010040	0,1	tbd
+Null	L4_HIT_LOCAL_L4.SNOOP_MISS	0x020040	0,1	tbd
+Null	L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD	0x040040	0,1	tbd
+Null	L4_HIT_LOCAL_L4.SNOOP_HIT_WITH_FWD	0x080040	0,1	tbd
+Null	L4_HIT_LOCAL_L4.SNOOP_HITM	0x100040	0,1	tbd
+Null	L4_HIT_LOCAL_L4.SNOOP_NON_DRAM	0x200040	0,1	tbd
+Null	L4_HIT_LOCAL_L4.ANY_SNOOP	0x3fc040	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SPL_HIT	0x004400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_NONE	0x008400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	0x010400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_MISS	0x020400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	0x040400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_HITM	0x100400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	0x200400	0,1	tbd
+Null	L3_MISS_LOCAL_DRAM.ANY_SNOOP	0x3fc400	0,1	tbd
+Null	L3_MISS.SPL_HIT	0x007c00	0,1	tbd
+Null	L3_MISS.SNOOP_NONE	0x00bc00	0,1	tbd
+Null	L3_MISS.SNOOP_NOT_NEEDED	0x013c00	0,1	tbd
+Null	L3_MISS.SNOOP_MISS	0x023c00	0,1	tbd
+Null	L3_MISS.SNOOP_HIT_NO_FWD	0x043c00	0,1	tbd
+Null	L3_MISS.SNOOP_HITM	0x103c00	0,1	tbd
+Null	L3_MISS.SNOOP_NON_DRAM	0x203c00	0,1	tbd
+Null	L3_MISS.ANY_SNOOP	0x3ffc00	0,1	tbd
diff --git a/x86data/perfmon_data/SKL/Skylake_matrix_bit_definitions_V13.json b/x86data/perfmon_data/SKL/Skylake_matrix_bit_definitions_V13.json
new file mode 100644
index 0000000..bf1d36b
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_matrix_bit_definitions_V13.json
@@ -0,0 +1,177 @@
+[
+  {
+    "BitName": "DEMAND_DATA_RD",
+    "BitIndex": "0",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_RFO",
+    "BitIndex": "1",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_CODE_RD",
+    "BitIndex": "2",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_DATA_RD",
+    "BitIndex": "7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L3_RFO",
+    "BitIndex": "8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "STREAMING_STORES",
+    "BitIndex": "11",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "OTHER",
+    "BitIndex": "15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_RESPONSE",
+    "BitIndex": "16",
+    "Type": "2",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SUPPLIER_NONE",
+    "BitIndex": "17",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_M",
+    "BitIndex": "18",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_E",
+    "BitIndex": "19",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT_S",
+    "BitIndex": "20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_HIT",
+    "BitIndex": "18,19,20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L4_HIT_LOCAL_L4",
+    "BitIndex": "22",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_LOCAL_DRAM",
+    "BitIndex": "26",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS",
+    "BitIndex": "26,27,28,29",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SPL_HIT",
+    "BitIndex": "30",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NONE",
+    "BitIndex": "31",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NOT_NEEDED",
+    "BitIndex": "32",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_MISS",
+    "BitIndex": "33",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_NO_FWD",
+    "BitIndex": "34",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_WITH_FWD",
+    "BitIndex": "35",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "18,19,20,21"
+  },
+  {
+    "BitName": "SNOOP_HITM",
+    "BitIndex": "36",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NON_DRAM",
+    "BitIndex": "37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_SNOOP",
+    "BitIndex": "30,31,32,33,34,35,36,37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SKL/Skylake_matrix_bit_definitions_V13.tsv b/x86data/perfmon_data/SKL/Skylake_matrix_bit_definitions_V13.tsv
new file mode 100644
index 0000000..136b92b
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_matrix_bit_definitions_V13.tsv
@@ -0,0 +1,29 @@
+# Performance Monitoring Events for the Next+1 Generation Intel Core Processors Based on the Skylake Microarchitecture - V13
+# 9/17/2015 11:13:42 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	Type	MATRIX_REG	BitsNotCombinedWith
+DEMAND_DATA_RD	0	1	0,1	Null
+DEMAND_RFO	1	1	0,1	Null
+DEMAND_CODE_RD	2	1	0,1	Null
+PF_L3_DATA_RD	7	1	0,1	Null
+PF_L3_RFO	8	1	0,1	Null
+STREAMING_STORES	11	1	0,1	Null
+OTHER	15	1	0,1	Null
+ANY_RESPONSE	16	2	0,1	Null
+SUPPLIER_NONE	17	3	0,1	Null
+L3_HIT_M	18	3	0,1	Null
+L3_HIT_E	19	3	0,1	Null
+L3_HIT_S	20	3	0,1	Null
+L3_HIT	18,19,20	3	0,1	Null
+L4_HIT_LOCAL_L4	22	3	0,1	Null
+L3_MISS_LOCAL_DRAM	26	3	0,1	Null
+L3_MISS	26,27,28,29	3	0,1	Null
+SPL_HIT	30	4	0,1	Null
+SNOOP_NONE	31	4	0,1	Null
+SNOOP_NOT_NEEDED	32	4	0,1	Null
+SNOOP_MISS	33	4	0,1	Null
+SNOOP_HIT_NO_FWD	34	4	0,1	Null
+SNOOP_HIT_WITH_FWD	35	4	0,1	18,19,20,21
+SNOOP_HITM	36	4	0,1	Null
+SNOOP_NON_DRAM	37	4	0,1	Null
+ANY_SNOOP	30,31,32,33,34,35,36,37	4	0,1	Null
diff --git a/x86data/perfmon_data/SKL/Skylake_offcore_V13.tsv b/x86data/perfmon_data/SKL/Skylake_offcore_V13.tsv
new file mode 100644
index 0000000..d373fa4
--- /dev/null
+++ b/x86data/perfmon_data/SKL/Skylake_offcore_V13.tsv
@@ -0,0 +1,459 @@
+# Performance Monitoring Events for the Next+1 Generation Intel Core Processors Based on the Skylake Microarchitecture - V13
+# 9/17/2015 11:13:42 AM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Data_LA	L1_Hit_Indication	Errata
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3ffc008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x203c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x103c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x007c008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc4008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0044008000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0408000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000408000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000408000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400408000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200408000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100408000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080408000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040408000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc01c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20001c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10001c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD	Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04001c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS	Counts any other requests that hit in the L3 and the snoops sent to sibling cores return clean response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02001c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED	Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01001c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00801c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00401c8000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0108000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000108000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000108000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400108000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200108000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100108000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080108000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040108000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0088000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000088000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000088000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400088000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200088000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100088000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080088000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040088000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0048000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000048000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000048000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400048000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200048000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100048000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080048000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040048000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040028000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.OTHER.ANY_RESPONSE	Counts any other requests that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000018000 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3ffc000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x203c000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x103c000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x007c000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc4000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0044000800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0400800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000400800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000400800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400400800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200400800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080400800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040400800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc01c0800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20001c0800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10001c0800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HIT_NO_FWD	Counts streaming stores that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04001c0800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_MISS	Counts streaming stores that hit in the L3 and the snoops sent to sibling cores return clean response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02001c0800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NOT_NEEDED	Counts streaming stores that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01001c0800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00801c0800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00401c0800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0100800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000100800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000100800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400100800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200100800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100100800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080100800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040100800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0080800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000080800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000080800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400080800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200080800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100080800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080080800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040080800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0040800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000040800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000040800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400040800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200040800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100040800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080040800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040040800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0020800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040020800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE	Counts streaming stores that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010800 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3ffc000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x203c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x103c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x007c000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc4000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0044000100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0400100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000400100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000400100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400400100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200400100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080400100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040400100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc01c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20001c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10001c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04001c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02001c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01001c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00801c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00401c0100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0100100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000100100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000100100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400100100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200100100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100100100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080100100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040100100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0080100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000080100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000080100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400080100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200080100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100080100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080080100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040080100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0040100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000040100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000040100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400040100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200040100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100040100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080040100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040040100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040020100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) RFOs that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010100 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3ffc000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x203c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x103c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x007c000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc4000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0044000080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0400080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000400080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000400080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400400080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200400080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080400080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040400080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc01c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20001c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10001c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04001c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops sent to sibling cores return clean response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02001c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01001c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00801c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00401c0080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0100080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000100080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000100080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400100080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200100080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100100080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080100080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040100080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0080080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000080080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000080080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400080080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200080080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100080080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080080080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040080080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0040080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000040080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000040080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400040080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200040080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100040080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080040080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040040080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040020080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE	Counts all prefetch (that bring data to LLC only) data reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010080 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3ffc000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x203c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x103c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x007c000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc4000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0044000004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0400004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000400004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000400004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400400004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200400004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080400004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040400004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc01c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20001c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10001c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04001c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS	Counts all demand code reads that hit in the L3 and the snoops sent to sibling cores return clean response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02001c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01001c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00801c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00401c0004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0100004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000100004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000100004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400100004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200100004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100100004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080100004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040100004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0080004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000080004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000080004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400080004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200080004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100080004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080080004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040080004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0040004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000040004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000040004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400040004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200040004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100040004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080040004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040040004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040020004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE	Counts all demand code reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010004 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3ffc000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x203c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x103c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x007c000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc4000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0044000002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0400002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000400002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000400002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400400002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200400002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080400002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040400002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc01c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20001c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10001c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD	Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04001c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS	Counts all demand data writes (RFOs) that hit in the L3 and the snoops sent to sibling cores return clean response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02001c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED	Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01001c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00801c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00401c0002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0100002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000100002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000100002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400100002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200100002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100100002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080100002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040100002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0080002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000080002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000080002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400080002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200080002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100080002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080080002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040080002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0040002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000040002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000040002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400040002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200040002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100040002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080040002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040040002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0020002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040020002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE	Counts all demand data writes (RFOs) that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010002 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3ffc000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x203c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x103c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x043c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x023c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x013c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00bc000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x007c000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc4000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2004000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1004000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0404000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0204000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0104000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0084000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0044000001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0400001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000400001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000400001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400400001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200400001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100400001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080400001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040400001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc01c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x20001c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x10001c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD	Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x04001c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS	Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x02001c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED	Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x01001c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00801c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x00401c0001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0100001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000100001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000100001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400100001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200100001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100100001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080100001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040100001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0080001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000080001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000080001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400080001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200080001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100080001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080080001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040080001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0040001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000040001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000040001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400040001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200040001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100040001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080040001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040040001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x3fc0020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x2000020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x1000020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0400020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0200020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0100020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0080020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT	tbd	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0040020001 	0	0	0	0	0	0	0	0	null
+0xB7, 0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand data reads that have any response type.	0,1,2,3	0,1,2,3	100003	0x1a6,0x1a7	0x0000010001 	0	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/SLM/Silvermont_core_V10.json b/x86data/perfmon_data/SLM/Silvermont_core_V10.json
new file mode 100644
index 0000000..ff93128
--- /dev/null
+++ b/x86data/perfmon_data/SLM/Silvermont_core_V10.json
@@ -0,0 +1,2415 @@
+[

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Counts the number of branch instructions retired...",

+    "PublicDescription": "ALL_BRANCHES counts the number of any branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x7E",

+    "EventName": "BR_INST_RETIRED.JCC",

+    "BriefDescription": "Counts the number of JCC branch instructions retired",

+    "PublicDescription": "JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0xFE",

+    "EventName": "BR_INST_RETIRED.TAKEN_JCC",

+    "BriefDescription": "Counts the number of taken JCC branch instructions retired",

+    "PublicDescription": "TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0xF9",

+    "EventName": "BR_INST_RETIRED.CALL",

+    "BriefDescription": "Counts the number of near CALL branch instructions retired",

+    "PublicDescription": "CALL counts the number of near CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0xFD",

+    "EventName": "BR_INST_RETIRED.REL_CALL",

+    "BriefDescription": "Counts the number of near relative CALL branch instructions retired",

+    "PublicDescription": "REL_CALL counts the number of near relative CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0xFB",

+    "EventName": "BR_INST_RETIRED.IND_CALL",

+    "BriefDescription": "Counts the number of near indirect CALL branch instructions retired",

+    "PublicDescription": "IND_CALL counts the number of near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0xF7",

+    "EventName": "BR_INST_RETIRED.RETURN",

+    "BriefDescription": "Counts the number of near RET branch instructions retired",

+    "PublicDescription": "RETURN counts the number of near RET branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0xEB",

+    "EventName": "BR_INST_RETIRED.NON_RETURN_IND",

+    "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired",

+    "PublicDescription": "NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0xBF",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Counts the number of far branch instructions retired",

+    "PublicDescription": "FAR counts the number of far branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Counts the number of mispredicted branch instructions retired",

+    "PublicDescription": "ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.  ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x7E",

+    "EventName": "BR_MISP_RETIRED.JCC",

+    "BriefDescription": "Counts the number of mispredicted JCC branch instructions retired",

+    "PublicDescription": "JCC counts the number of mispredicted conditional branches (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.  ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0xFE",

+    "EventName": "BR_MISP_RETIRED.TAKEN_JCC",

+    "BriefDescription": "Counts the number of mispredicted taken JCC branch instructions retired",

+    "PublicDescription": "TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.  ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0xFB",

+    "EventName": "BR_MISP_RETIRED.IND_CALL",

+    "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired",

+    "PublicDescription": "IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.  ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0xF7",

+    "EventName": "BR_MISP_RETIRED.RETURN",

+    "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired",

+    "PublicDescription": "RETURN counts the number of mispredicted near RET branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.  ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0xEB",

+    "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",

+    "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired",

+    "PublicDescription": "NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.  ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.MS",

+    "BriefDescription": "MSROM micro-ops retired",

+    "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x10",

+    "EventName": "UOPS_RETIRED.ALL",

+    "BriefDescription": "Micro-ops retired",

+    "PublicDescription": "This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-Modifying Code detected",

+    "PublicDescription": "This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Stalls due to Memory ordering",

+    "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.FP_ASSIST",

+    "BriefDescription": "Stalls due to FP assists",

+    "PublicDescription": "This event counts the number of times that pipeline stalled due to FP operations needing assists. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x08",

+    "EventName": "MACHINE_CLEARS.ALL",

+    "BriefDescription": "Counts all machine clears",

+    "PublicDescription": "Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path.  All instructions \"older\" than this one will be allowed to finish.  This instruction and all \"younger\" instructions must be cleared, since they must not be allowed to complete.  Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine.  This means all older instructions are retired, and all pending stores (from older instructions) are completed.  Then the new path of instructions from the front end are allowed to start into the machine.  There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault).  All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST).  However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x01",

+    "EventName": "NO_ALLOC_CYCLES.ROB_FULL",

+    "BriefDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)",

+    "PublicDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x04",

+    "EventName": "NO_ALLOC_CYCLES.MISPREDICTS",

+    "BriefDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted ",

+    "PublicDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x20",

+    "EventName": "NO_ALLOC_CYCLES.RAT_STALL",

+    "BriefDescription": "Counts the number of cycles when no uops are allocated and a RATstall is asserted.",

+    "PublicDescription": "Counts the number of cycles when no uops are allocated and a RATstall is asserted.  ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x50",

+    "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED",

+    "BriefDescription": "Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.  The Silvermont implementation for this event is identical to NO_ALLOC_CYCLES.IQ_EMPTY.  This is a good approximation for NO_ALLOC_CYCLES.NOT_DELIVERED.",

+    "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance.  Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources.  When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x3F",

+    "EventName": "NO_ALLOC_CYCLES.ALL",

+    "BriefDescription": "Counts the number of cycles when no uops are allocated for any reason.",

+    "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x01",

+    "EventName": "RS_FULL_STALL.MEC",

+    "BriefDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M",

+    "PublicDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x1F",

+    "EventName": "RS_FULL_STALL.ALL",

+    "BriefDescription": "Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.",

+    "PublicDescription": "Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Instructions retired",

+    "PublicDescription": "This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "CYCLES_DIV_BUSY.ALL",

+    "BriefDescription": "Cycles the divider is busy.  Does not imply a stall waiting for the divider.",

+    "PublicDescription": "Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty.  The divide instruction is one of the longest latency instructions in the machine.  Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Fixed Counter: Counts the number of instructions retired",

+    "PublicDescription": "This event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.  Background: Modern microprocessors employ extensive pipelining and speculative techniques.  Since sometimes an instruction is started but never completed, the notion of \"retirement\" is introduced.  A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires.  This counter measures the number of completed instructions.  The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.",

+    "Counter": "Fixed counter 1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.CORE",

+    "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",

+    "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.",

+    "Counter": "Fixed counter 2",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",

+    "PublicDescription": "Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.",

+    "Counter": "Fixed counter 3",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.CORE_P",

+    "BriefDescription": "Core cycles when core is not halted",

+    "PublicDescription": "This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_UNHALTED.REF",

+    "BriefDescription": "Reference cycles when core is not halted",

+    "PublicDescription": "This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x30",

+    "UMask": "0x00",

+    "EventName": "L2_REJECT_XQ.ALL",

+    "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",

+    "PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims) ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x31",

+    "UMask": "0x00",

+    "EventName": "CORE_REJECT_L2Q.ALL",

+    "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",

+    "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.)",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "L2 cache requests from this core",

+    "PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "L2 cache request misses",

+    "PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x03",

+    "EventName": "ICACHE.ACCESSES",

+    "BriefDescription": "Instruction fetches",

+    "PublicDescription": "This event counts all instruction fetches, including uncacheable fetches. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x01",

+    "EventName": "ICACHE.HIT",

+    "BriefDescription": "Instruction fetches from Icache",

+    "PublicDescription": "This event counts all instruction fetches from the instruction cache. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x02",

+    "EventName": "ICACHE.MISSES",

+    "BriefDescription": "Icache miss",

+    "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x86",

+    "UMask": "0x04",

+    "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",

+    "BriefDescription": "Counts the number of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.",

+    "PublicDescription": "Counts the number of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x01",

+    "EventName": "BACLEARS.ALL",

+    "BriefDescription": "Counts the number of baclears",

+    "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.ANY event counts the number of baclears for any type of branch.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x08",

+    "EventName": "BACLEARS.RETURN",

+    "BriefDescription": "Counts the number of RETURN baclears",

+    "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.RETURN event counts the number of RETURN baclears.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x10",

+    "EventName": "BACLEARS.COND",

+    "BriefDescription": "Counts the number of JCC baclears",

+    "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE7",

+    "UMask": "0x01",

+    "EventName": "MS_DECODED.MS_ENTRY",

+    "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative count.",

+    "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE9",

+    "UMask": "0x01",

+    "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",

+    "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction",

+    "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x01",

+    "EventName": "REHABQ.LD_BLOCK_ST_FORWARD",

+    "BriefDescription": "Loads blocked due to store forward restriction",

+    "PublicDescription": "This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY",

+    "BriefDescription": "Loads blocked due to store data not ready",

+    "PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x04",

+    "EventName": "REHABQ.ST_SPLITS",

+    "BriefDescription": "Store uops that split cache line boundary",

+    "PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "REHABQ.LD_SPLITS",

+    "BriefDescription": "Load uops that split cache line boundary",

+    "PublicDescription": "This event counts the number of retire loads that experienced cache line boundary splits ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x10",

+    "EventName": "REHABQ.LOCK",

+    "BriefDescription": "Uops with lock semantics",

+    "PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0). ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x20",

+    "EventName": "REHABQ.STA_FULL",

+    "BriefDescription": "Store address buffer full",

+    "PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x40",

+    "EventName": "REHABQ.ANY_LD",

+    "BriefDescription": "Any reissued load uops",

+    "PublicDescription": "This event counts the number of load uops reissued from Rehabq ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x80",

+    "EventName": "REHABQ.ANY_ST",

+    "BriefDescription": "Any reissued store uops",

+    "PublicDescription": "This event counts the number of store uops reissued from Rehabq ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x04",

+    "UMask": "0x01",

+    "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS",

+    "BriefDescription": "Loads missed L1",

+    "PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x04",

+    "UMask": "0x02",

+    "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",

+    "BriefDescription": "Loads hit L2",

+    "PublicDescription": "This event counts the number of load ops retired that hit in the L2",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x04",

+    "UMask": "0x04",

+    "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",

+    "BriefDescription": "Loads missed L2",

+    "PublicDescription": "This event counts the number of load ops retired that miss in the L2",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x04",

+    "UMask": "0x08",

+    "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",

+    "BriefDescription": "Loads missed DTLB",

+    "PublicDescription": "This event counts the number of load ops retired that had DTLB miss. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x04",

+    "UMask": "0x10",

+    "EventName": "MEM_UOPS_RETIRED.UTLB_MISS",

+    "BriefDescription": "Loads missed UTLB",

+    "PublicDescription": "This event counts the number of load ops retired that had UTLB miss. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x04",

+    "UMask": "0x20",

+    "EventName": "MEM_UOPS_RETIRED.HITM",

+    "BriefDescription": "Cross core or cross module hitm",

+    "PublicDescription": "This event counts the number of load ops retired that got data from the other core or from the other module. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x04",

+    "UMask": "0x40",

+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

+    "BriefDescription": "All Loads",

+    "PublicDescription": "This event counts the number of load ops retired ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x04",

+    "UMask": "0x80",

+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

+    "BriefDescription": "All Stores",

+    "PublicDescription": "This event counts the number of store ops retired ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "PAGE_WALKS.D_SIDE_WALKS",

+    "BriefDescription": "D-side page-walks",

+    "PublicDescription": "This event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "PAGE_WALKS.D_SIDE_CYCLES",

+    "BriefDescription": "Duration of D-side page-walks in core cycles",

+    "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "PAGE_WALKS.I_SIDE_WALKS",

+    "BriefDescription": "I-side page-walks",

+    "PublicDescription": "This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "PAGE_WALKS.I_SIDE_CYCLES",

+    "BriefDescription": "Duration of I-side page-walks in core cycles",

+    "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks. ",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x03",

+    "EventName": "PAGE_WALKS.WALKS",

+    "BriefDescription": "Total page walks that are completed (I-side and D-side)",

+    "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x03",

+    "EventName": "PAGE_WALKS.CYCLES",

+    "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)",

+    "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE",

+    "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY",

+    "BriefDescription": "Counts any code reads (demand & prefetch)  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts any code reads (demand & prefetch)  that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000000044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts any code reads (demand & prefetch)  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400000044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts any code reads (demand & prefetch)  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200000044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts any code reads (demand & prefetch)  that have any response type",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY",

+    "BriefDescription": "Counts any rfo reads (demand & prefetch)  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts any rfo reads (demand & prefetch)  that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000000022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts any rfo reads (demand & prefetch)  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400000022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts any rfo reads (demand & prefetch)  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200000022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts any rfo reads (demand & prefetch)  that have any response type",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY",

+    "BriefDescription": "Counts any data read (demand & prefetch)  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680003091",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts any data read (demand & prefetch)  that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000003091",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts any data read (demand & prefetch)  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400003091",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts any data read (demand & prefetch)  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200003091",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts any data read (demand & prefetch)  that have any response type",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000013091",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY",

+    "BriefDescription": "Counts streaming store  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680004800",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000008008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400008008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts any request that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200008008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",

+    "BriefDescription": "Counts any request that have any response type",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000018008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY",

+    "BriefDescription": "Counts DCU hardware prefetcher data read  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680002000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts DCU hardware prefetcher data read  that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000002000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts DCU hardware prefetcher data read  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400002000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts DCU hardware prefetcher data read  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200002000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts DCU hardware prefetcher data read  that have any response type",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000012000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY",

+    "BriefDescription": "Countsof demand RFO requests to write to partial cache lines  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000100",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY",

+    "BriefDescription": "Counts demand reads of partial cache lines (including UC and WC)  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY",

+    "BriefDescription": "Counts code reads generated by L2 prefetchers  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts code reads generated by L2 prefetchers  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400000040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts code reads generated by L2 prefetchers  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200000040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY",

+    "BriefDescription": "Counts RFO requests generated by L2 prefetchers  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts RFO requests generated by L2 prefetchers  that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000000020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts RFO requests generated by L2 prefetchers  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400000020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts RFO requests generated by L2 prefetchers  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200000020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY",

+    "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers  that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000000010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400000010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200000010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY",

+    "BriefDescription": "Counts writeback (modified to exclusive)  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts writeback (modified to exclusive)  that miss L2 with no details on snoop-related information",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0080000008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",

+    "BriefDescription": "Counts demand and DCU prefetch instruction cacheline cycles of outstanding offcore requests",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6",

+    "MSRValue": "0x4000000004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY",

+    "BriefDescription": "Counts demand and DCU prefetch instruction cacheline  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand and DCU prefetch instruction cacheline  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400000004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts demand and DCU prefetch instruction cacheline  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200000004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts demand and DCU prefetch instruction cacheline  that have any response type",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",

+    "BriefDescription": "Counts demand and DCU prefetch RFOs cycles of outstanding offcore requests",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6",

+    "MSRValue": "0x4000000002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY",

+    "BriefDescription": "Counts demand and DCU prefetch RFOs  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand and DCU prefetch RFOs  that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000000002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand and DCU prefetch RFOs  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400000002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts demand and DCU prefetch RFOs  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200000002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",

+    "BriefDescription": "Counts demand and DCU prefetch data read cycles of outstanding offcore requests",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6",

+    "MSRValue": "0x4000000001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY",

+    "BriefDescription": "Counts demand and DCU prefetch data read  that miss L2",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1680000001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand and DCU prefetch data read  that hit in the other module where modified copies were found in other core's L1 cache",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000000001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand and DCU prefetch data read  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0400000001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS",

+    "BriefDescription": "Counts demand and DCU prefetch data read  that miss L2 with a snoop miss response",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0200000001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x01,0x02",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts demand and DCU prefetch data read  that have any response type",

+    "PublicDescription": "tbd",

+    "Counter": "0,1",

+    "PEBScounters": "0",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x0000010001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SLM/Silvermont_core_V10.tsv b/x86data/perfmon_data/SLM/Silvermont_core_V10.tsv
new file mode 100644
index 0000000..278a052
--- /dev/null
+++ b/x86data/perfmon_data/SLM/Silvermont_core_V10.tsv
@@ -0,0 +1,75 @@
+# Performance Monitoring Events for Intel Atom Processors Based on the Silvermont Microarchitecture - V10
+# 7/7/2015 1:13:11 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	PEBScounters	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Errata
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	Counts the number of branch instructions retired...	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC4	0x7E	BR_INST_RETIRED.JCC	Counts the number of JCC branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC4	0xFE	BR_INST_RETIRED.TAKEN_JCC	Counts the number of taken JCC branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC4	0xF9	BR_INST_RETIRED.CALL	Counts the number of near CALL branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC4	0xFD	BR_INST_RETIRED.REL_CALL	Counts the number of near relative CALL branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC4	0xFB	BR_INST_RETIRED.IND_CALL	Counts the number of near indirect CALL branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC4	0xF7	BR_INST_RETIRED.RETURN	Counts the number of near RET branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC4	0xEB	BR_INST_RETIRED.NON_RETURN_IND	Counts the number of near indirect JMP and near indirect CALL branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC4	0xBF	BR_INST_RETIRED.FAR_BRANCH	Counts the number of far branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	Counts the number of mispredicted branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC5	0x7E	BR_MISP_RETIRED.JCC	Counts the number of mispredicted JCC branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC5	0xFE	BR_MISP_RETIRED.TAKEN_JCC	Counts the number of mispredicted taken JCC branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC5	0xFB	BR_MISP_RETIRED.IND_CALL	Counts the number of mispredicted near indirect CALL branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC5	0xF7	BR_MISP_RETIRED.RETURN	Counts the number of mispredicted near RET branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC5	0xEB	BR_MISP_RETIRED.NON_RETURN_IND	Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired	0,1	0	200003	0	0	0	0	0	0	1	null
+0xC2	0x01	UOPS_RETIRED.MS	MSROM micro-ops retired	0,1	0	2000003	0	0	0	0	0	0	0	null
+0xC2	0x10	UOPS_RETIRED.ALL	Micro-ops retired	0,1	0	2000003	0	0	0	0	0	0	0	null
+0xC3	0x01	MACHINE_CLEARS.SMC	Self-Modifying Code detected	0,1	0	200003	0	0	0	0	0	0	0	null
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Stalls due to Memory ordering	0,1	0	200003	0	0	0	0	0	0	0	null
+0xC3	0x04	MACHINE_CLEARS.FP_ASSIST	Stalls due to FP assists	0,1	0	200003	0	0	0	0	0	0	0	null
+0xC3	0x08	MACHINE_CLEARS.ALL	Counts all machine clears	0,1	0	200003	0	0	0	0	0	0	0	null
+0xCA	0x01	NO_ALLOC_CYCLES.ROB_FULL	Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)	0,1	0	200003	0	0	0	0	0	0	0	null
+0xCA	0x04	NO_ALLOC_CYCLES.MISPREDICTS	Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted 	0,1	0	200003	0	0	0	0	0	0	0	null
+0xCA	0x20	NO_ALLOC_CYCLES.RAT_STALL	Counts the number of cycles when no uops are allocated and a RATstall is asserted.	0,1	0	200003	0	0	0	0	0	0	0	null
+0xCA	0x50	NO_ALLOC_CYCLES.NOT_DELIVERED	Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.  The Silvermont implementation for this event is identical to NO_ALLOC_CYCLES.IQ_EMPTY.  This is a good approximation for NO_ALLOC_CYCLES.NOT_DELIVERED.	0,1	0	200003	0	0	0	0	0	0	0	null
+0xCA	0x3F	NO_ALLOC_CYCLES.ALL	Counts the number of cycles when no uops are allocated for any reason.	0,1	0	200003	0	0	0	0	0	0	0	null
+0xCB	0x01	RS_FULL_STALL.MEC	Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M	0,1	0	200003	0	0	0	0	0	0	0	null
+0xCB	0x1F	RS_FULL_STALL.ALL	Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.	0,1	0	200003	0	0	0	0	0	0	0	null
+0xC0	0x00	INST_RETIRED.ANY_P	Instructions retired	0,1	0	2000003	0	0	0	0	0	0	0	null
+0xCD	0x01	CYCLES_DIV_BUSY.ALL	Cycles the divider is busy.  Does not imply a stall waiting for the divider.	0,1	0	2000003	0	0	0	0	0	0	0	null
+0x00	0x01	INST_RETIRED.ANY	Fixed Counter: Counts the number of instructions retired	Fixed counter 1	0	2000003	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.CORE	Fixed Counter: Counts the number of unhalted core clock cycles	Fixed counter 2	0	2000003	0	0	0	0	0	0	0	null
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Fixed Counter: Counts the number of unhalted reference clock cycles	Fixed counter 3	0	2000003	0	0	0	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.CORE_P	Core cycles when core is not halted	0,1	0	2000003	0	0	0	0	0	0	0	null
+0x3C	0x01	CPU_CLK_UNHALTED.REF	Reference cycles when core is not halted	0,1	0	2000003	0	0	0	0	0	0	0	null
+0x30	0x00	L2_REJECT_XQ.ALL	Counts the number of request from the L2 that were not accepted into the XQ	0,1	0	200003	0	0	0	0	0	0	0	null
+0x31	0x00	CORE_REJECT_L2Q.ALL	Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.	0,1	0	200003	0	0	0	0	0	0	0	null
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	L2 cache requests from this core	0,1	0	200003	0	0	0	0	0	0	0	null
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	L2 cache request misses	0,1	0	200003	0	0	0	0	0	0	0	null
+0x80	0x03	ICACHE.ACCESSES	Instruction fetches	0,1	0	200003	0	0	0	0	0	0	0	null
+0x80	0x01	ICACHE.HIT	Instruction fetches from Icache	0,1	0	200003	0	0	0	0	0	0	0	null
+0x80	0x02	ICACHE.MISSES	Icache miss	0,1	0	200003	0	0	0	0	0	0	0	null
+0x86	0x04	FETCH_STALL.ICACHE_FILL_PENDING_CYCLES	Counts the number of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.	0,1	0	200003	0	0	0	0	0	0	0	null
+0xE6	0x01	BACLEARS.ALL	Counts the number of baclears	0,1	0	200003	0	0	0	0	0	0	0	null
+0xE6	0x08	BACLEARS.RETURN	Counts the number of RETURN baclears	0,1	0	200003	0	0	0	0	0	0	0	null
+0xE6	0x10	BACLEARS.COND	Counts the number of JCC baclears	0,1	0	200003	0	0	0	0	0	0	0	null
+0xE7	0x01	MS_DECODED.MS_ENTRY	Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative count.	0,1	0	200003	0	0	0	0	0	0	0	null
+0xE9	0x01	DECODE_RESTRICTION.PREDECODE_WRONG	Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction	0,1	0	200003	0	0	0	0	0	0	0	null
+0x03	0x01	REHABQ.LD_BLOCK_ST_FORWARD	Loads blocked due to store forward restriction	0,1	0	200003	0	0	0	0	0	0	1	null
+0x03	0x02	REHABQ.LD_BLOCK_STD_NOTREADY	Loads blocked due to store data not ready	0,1	0	200003	0	0	0	0	0	0	0	null
+0x03	0x04	REHABQ.ST_SPLITS	Store uops that split cache line boundary	0,1	0	200003	0	0	0	0	0	0	0	null
+0x03	0x08	REHABQ.LD_SPLITS	Load uops that split cache line boundary	0,1	0	200003	0	0	0	0	0	0	1	null
+0x03	0x10	REHABQ.LOCK	Uops with lock semantics	0,1	0	200003	0	0	0	0	0	0	0	null
+0x03	0x20	REHABQ.STA_FULL	Store address buffer full	0,1	0	200003	0	0	0	0	0	0	0	null
+0x03	0x40	REHABQ.ANY_LD	Any reissued load uops	0,1	0	200003	0	0	0	0	0	0	0	null
+0x03	0x80	REHABQ.ANY_ST	Any reissued store uops	0,1	0	200003	0	0	0	0	0	0	0	null
+0x04	0x01	MEM_UOPS_RETIRED.L1_MISS_LOADS	Loads missed L1	0,1	0	200003	0	0	0	0	0	0	0	null
+0x04	0x02	MEM_UOPS_RETIRED.L2_HIT_LOADS	Loads hit L2	0,1	0	200003	0	0	0	0	0	0	1	null
+0x04	0x04	MEM_UOPS_RETIRED.L2_MISS_LOADS	Loads missed L2	0,1	0	100007	0	0	0	0	0	0	1	null
+0x04	0x08	MEM_UOPS_RETIRED.DTLB_MISS_LOADS	Loads missed DTLB	0,1	0	200003	0	0	0	0	0	0	1	null
+0x04	0x10	MEM_UOPS_RETIRED.UTLB_MISS	Loads missed UTLB	0,1	0	200003	0	0	0	0	0	0	0	null
+0x04	0x20	MEM_UOPS_RETIRED.HITM	Cross core or cross module hitm	0,1	0	200003	0	0	0	0	0	0	1	null
+0x04	0x40	MEM_UOPS_RETIRED.ALL_LOADS	All Loads	0,1	0	200003	0	0	0	0	0	0	0	null
+0x04	0x80	MEM_UOPS_RETIRED.ALL_STORES	All Stores	0,1	0	200003	0	0	0	0	0	0	0	null
+0x05	0x01	PAGE_WALKS.D_SIDE_WALKS	D-side page-walks	0,1	0	100003	0	0	0	0	0	1	0	null
+0x05	0x01	PAGE_WALKS.D_SIDE_CYCLES	Duration of D-side page-walks in core cycles	0,1	0	200003	0	0	0	0	0	0	0	null
+0x05	0x02	PAGE_WALKS.I_SIDE_WALKS	I-side page-walks	0,1	0	100003	0	0	0	0	0	1	0	null
+0x05	0x02	PAGE_WALKS.I_SIDE_CYCLES	Duration of I-side page-walks in core cycles	0,1	0	200003	0	0	0	0	0	0	0	null
+0x05	0x03	PAGE_WALKS.WALKS	Total page walks that are completed (I-side and D-side)	0,1	0	100003	0	0	0	0	0	1	0	null
+0x05	0x03	PAGE_WALKS.CYCLES	Total cycles for all the page walks. (I-side and D-side)	0,1	0	200003	0	0	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE	Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction	0,1	0	100007	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/SLM/Silvermont_matrix_V10.json b/x86data/perfmon_data/SLM/Silvermont_matrix_V10.json
new file mode 100644
index 0000000..34aa187
--- /dev/null
+++ b/x86data/perfmon_data/SLM/Silvermont_matrix_V10.json
@@ -0,0 +1,191 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand and DCU prefetch data read"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand and DCU prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand and DCU prefetch instruction cacheline"
+  },
+  {
+    "MATRIX_REQUEST": "COREWB",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000008",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts writeback (modified to exclusive)"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000010",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts data cacheline reads generated by L2 prefetchers"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000020",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts RFO requests generated by L2 prefetchers"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000040",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts code reads generated by L2 prefetchers"
+  },
+  {
+    "MATRIX_REQUEST": "PARTIAL_READS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand reads of partial cache lines (including UC and WC)"
+  },
+  {
+    "MATRIX_REQUEST": "PARTIAL_WRITES",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Countsof demand RFO requests to write to partial cache lines"
+  },
+  {
+    "MATRIX_REQUEST": "UC_CODE_READS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000200",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts UC instruction fetch"
+  },
+  {
+    "MATRIX_REQUEST": "BUS_LOCKS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000400",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Bus lock and split lock"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L1_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000002000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts DCU hardware prefetcher data read"
+  },
+  {
+    "MATRIX_REQUEST": "ANY_REQUEST",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008008",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any request"
+  },
+  {
+    "MATRIX_REQUEST": "STREAMING_STORES",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000004800",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts streaming store"
+  },
+  {
+    "MATRIX_REQUEST": "ANY_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000003091",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any data read (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ANY_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000022",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any rfo reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ANY_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000044",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any code reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ANY_READS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x00000032f7",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any data/code/rfo reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ANY_PF_L2",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000070",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any prefetch read"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "ANY_RESPONSE",
+    "MATRIX_VALUE": "0x0000010000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "have any response type"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L2_MISS.NO_SNOOP_NEEDED",
+    "MATRIX_VALUE": "0x0080000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss L2 with no details on snoop-related information"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L2_MISS.SNOOP_MISS",
+    "MATRIX_VALUE": "0x0200000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss L2 with a snoop miss response"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L2_MISS.HIT_OTHER_CORE_NO_FWD",
+    "MATRIX_VALUE": "0x0400000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L2_MISS.HITM_OTHER_CORE",
+    "MATRIX_VALUE": "0x1000000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the other module where modified copies were found in other core's L1 cache"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L2_MISS.NON_DRAM",
+    "MATRIX_VALUE": "0x2000000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss L2 and the target was non-DRAM system address"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "L2_MISS.ANY",
+    "MATRIX_VALUE": "0x1680000000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss L2"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "OUTSTANDING",
+    "MATRIX_VALUE": "0x4000000000",
+    "MATRIX_REGISTER": "0",
+    "DESCRIPTION": "cycles of outstanding offcore requests"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SLM/Silvermont_matrix_V10.tsv b/x86data/perfmon_data/SLM/Silvermont_matrix_V10.tsv
new file mode 100644
index 0000000..0ddf44f
--- /dev/null
+++ b/x86data/perfmon_data/SLM/Silvermont_matrix_V10.tsv
@@ -0,0 +1,31 @@
+# Performance Monitoring Events for Intel Atom Processors Based on the Silvermont Microarchitecture - V10
+# 7/7/2015 1:13:11 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand and DCU prefetch data read
+DEMAND_RFO	Null	0x0002	0,1	Counts demand and DCU prefetch RFOs
+DEMAND_CODE_RD	Null	0x0004	0,1	Counts demand and DCU prefetch instruction cacheline
+COREWB	Null	0x0008	0,1	Counts writeback (modified to exclusive)
+PF_L2_DATA_RD	Null	0x0010	0,1	Counts data cacheline reads generated by L2 prefetchers
+PF_L2_RFO	Null	0x0020	0,1	Counts RFO requests generated by L2 prefetchers
+PF_L2_CODE_RD	Null	0x0040	0,1	Counts code reads generated by L2 prefetchers
+PARTIAL_READS	Null	0x0080	0,1	Counts demand reads of partial cache lines (including UC and WC)
+PARTIAL_WRITES	Null	0x0100	0,1	Countsof demand RFO requests to write to partial cache lines
+UC_CODE_READS	Null	0x0200	0,1	Counts UC instruction fetch
+BUS_LOCKS	Null	0x0400	0,1	Bus lock and split lock
+PF_L1_DATA_RD	Null	0x2000	0,1	Counts DCU hardware prefetcher data read
+ANY_REQUEST	Null	0x8008	0,1	Counts any request
+STREAMING_STORES	Null	0x4800	0,1	Counts streaming store
+ANY_DATA_RD	Null	0x3091	0,1	Counts any data read (demand & prefetch)
+ANY_RFO	Null	0x0022	0,1	Counts any rfo reads (demand & prefetch)
+ANY_CODE_RD	Null	0x0044	0,1	Counts any code reads (demand & prefetch)
+ANY_READS	Null	0x32f7	0,1	Counts any data/code/rfo reads (demand & prefetch)
+ANY_PF_L2	Null	0x0070	0,1	Counts any prefetch read
+Null	ANY_RESPONSE	0x000001	0,1	have any response type
+Null	L2_MISS.NO_SNOOP_NEEDED	0x008000	0,1	miss L2 with no details on snoop-related information
+Null	L2_MISS.SNOOP_MISS	0x020000	0,1	miss L2 with a snoop miss response
+Null	L2_MISS.HIT_OTHER_CORE_NO_FWD	0x040000	0,1	miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
+Null	L2_MISS.HITM_OTHER_CORE	0x100000	0,1	hit in the other module where modified copies were found in other core's L1 cache
+Null	L2_MISS.NON_DRAM	0x200000	0,1	miss L2 and the target was non-DRAM system address
+Null	L2_MISS.ANY	0x168000	0,1	miss L2
+Null	OUTSTANDING	0x400000	0	cycles of outstanding offcore requests
diff --git a/x86data/perfmon_data/SLM/Silvermont_offcore_V10.tsv b/x86data/perfmon_data/SLM/Silvermont_offcore_V10.tsv
new file mode 100644
index 0000000..b936ce9
--- /dev/null
+++ b/x86data/perfmon_data/SLM/Silvermont_offcore_V10.tsv
@@ -0,0 +1,60 @@
+# Performance Monitoring Events for Intel Atom Processors Based on the Silvermont Microarchitecture - V10
+# 7/7/2015 1:13:12 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	PEBScounters	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Errata
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY	Counts any code reads (demand & prefetch)  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000044	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE	Counts any code reads (demand & prefetch)  that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000000044	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts any code reads (demand & prefetch)  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400000044	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS	Counts any code reads (demand & prefetch)  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200000044	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE	Counts any code reads (demand & prefetch)  that have any response type	0,1	0	100007	0x1a6,0x1a7	0x0000010044	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY	Counts any rfo reads (demand & prefetch)  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000022	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE	Counts any rfo reads (demand & prefetch)  that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000000022	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts any rfo reads (demand & prefetch)  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400000022	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS	Counts any rfo reads (demand & prefetch)  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200000022	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE	Counts any rfo reads (demand & prefetch)  that have any response type	0,1	0	100007	0x1a6,0x1a7	0x0000010022	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY	Counts any data read (demand & prefetch)  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680003091	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE	Counts any data read (demand & prefetch)  that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000003091	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts any data read (demand & prefetch)  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400003091	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS	Counts any data read (demand & prefetch)  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200003091	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE	Counts any data read (demand & prefetch)  that have any response type	0,1	0	100007	0x1a6,0x1a7	0x0000013091	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY	Counts streaming store  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680004800	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE	Counts any request that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000008008	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400008008	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS	Counts any request that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200008008	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE	Counts any request that have any response type	0,1	0	100007	0x1a6,0x1a7	0x0000018008	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY	Counts DCU hardware prefetcher data read  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680002000	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE	Counts DCU hardware prefetcher data read  that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000002000	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts DCU hardware prefetcher data read  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400002000	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS	Counts DCU hardware prefetcher data read  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200002000	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE	Counts DCU hardware prefetcher data read  that have any response type	0,1	0	100007	0x1a6,0x1a7	0x0000012000	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY	Countsof demand RFO requests to write to partial cache lines  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000100	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY	Counts demand reads of partial cache lines (including UC and WC)  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000080	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY	Counts code reads generated by L2 prefetchers  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000040	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts code reads generated by L2 prefetchers  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400000040	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS	Counts code reads generated by L2 prefetchers  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200000040	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY	Counts RFO requests generated by L2 prefetchers  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000020	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE	Counts RFO requests generated by L2 prefetchers  that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000000020	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts RFO requests generated by L2 prefetchers  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400000020	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS	Counts RFO requests generated by L2 prefetchers  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200000020	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY	Counts data cacheline reads generated by L2 prefetchers  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000010	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE	Counts data cacheline reads generated by L2 prefetchers  that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000000010	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts data cacheline reads generated by L2 prefetchers  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400000010	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS	Counts data cacheline reads generated by L2 prefetchers  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200000010	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.COREWB.L2_MISS.ANY	Counts writeback (modified to exclusive)  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000008	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED	Counts writeback (modified to exclusive)  that miss L2 with no details on snoop-related information	0,1	0	100007	0x1a6,0x1a7	0x0080000008	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING	Counts demand and DCU prefetch instruction cacheline cycles of outstanding offcore requests	0,1	0	100007	0x1a6	0x4000000004	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY	Counts demand and DCU prefetch instruction cacheline  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000004	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts demand and DCU prefetch instruction cacheline  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400000004	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS	Counts demand and DCU prefetch instruction cacheline  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200000004	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE	Counts demand and DCU prefetch instruction cacheline  that have any response type	0,1	0	100007	0x1a6,0x1a7	0x0000010004	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING	Counts demand and DCU prefetch RFOs cycles of outstanding offcore requests	0,1	0	100007	0x1a6	0x4000000002	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY	Counts demand and DCU prefetch RFOs  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000002	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE	Counts demand and DCU prefetch RFOs  that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000000002	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts demand and DCU prefetch RFOs  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400000002	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS	Counts demand and DCU prefetch RFOs  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200000002	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING	Counts demand and DCU prefetch data read cycles of outstanding offcore requests	0,1	0	100007	0x1a6	0x4000000001	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY	Counts demand and DCU prefetch data read  that miss L2	0,1	0	100007	0x1a6,0x1a7	0x1680000001	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE	Counts demand and DCU prefetch data read  that hit in the other module where modified copies were found in other core's L1 cache	0,1	0	100007	0x1a6,0x1a7	0x1000000001	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts demand and DCU prefetch data read  that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	0	100007	0x1a6,0x1a7	0x0400000001	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS	Counts demand and DCU prefetch data read  that miss L2 with a snoop miss response	0,1	0	100007	0x1a6,0x1a7	0x0200000001	0	0	0	0	0	null
+0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand and DCU prefetch data read  that have any response type	0,1	0	100007	0x1a6,0x1a7	0x0000010001	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/SNB/SandyBridge_core_V12.json b/x86data/perfmon_data/SNB/SandyBridge_core_V12.json
new file mode 100644
index 0000000..368b5a7
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_core_V12.json
@@ -0,0 +1,8444 @@
+[

+  {

+    "EventCode": "0x00",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired from execution.",

+    "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. ",

+    "Counter": "Fixed counter 1",

+    "CounterHTOff": "Fixed counter 1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Core cycles when the thread is not in halt state.",

+    "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x03",

+    "EventName": "CPU_CLK_UNHALTED.REF_TSC",

+    "BriefDescription": "Reference cycles when the core is not in halt state.",

+    "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ",

+    "Counter": "Fixed counter 3",

+    "CounterHTOff": "Fixed counter 3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x41",

+    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken macro-conditional branches",

+    "PublicDescription": "Not taken macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x81",

+    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired macro-conditional branches",

+    "PublicDescription": "Taken speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x82",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",

+    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x84",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x88",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x90",

+    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired direct near calls",

+    "PublicDescription": "Taken speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xA0",

+    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired indirect calls",

+    "PublicDescription": "Taken speculative and retired indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC1",

+    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired macro-conditional branches",

+    "PublicDescription": "Speculative and retired macro-conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC2",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",

+    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC4",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "PublicDescription": "Speculative and retired indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xC8",

+    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",

+    "BriefDescription": "Speculative and retired indirect return branches.",

+    "PublicDescription": "Speculative and retired indirect return branches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xD0",

+    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired direct near calls",

+    "PublicDescription": "Speculative and retired direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x41",

+    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",

+    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x81",

+    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",

+    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x84",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x88",

+    "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x90",

+    "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted direct near calls",

+    "PublicDescription": "Taken speculative and retired mispredicted direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xA0",

+    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",

+    "BriefDescription": "Taken speculative and retired mispredicted indirect calls",

+    "PublicDescription": "Taken speculative and retired mispredicted indirect calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC1",

+    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xC4",

+    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",

+    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",

+    "PublicDescription": "Mispredicted indirect branches excluding calls and returns",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xD0",

+    "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",

+    "BriefDescription": "Speculative and retired mispredicted direct near calls",

+    "PublicDescription": "Speculative and retired mispredicted direct near calls",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Thread cycles when thread is not in halt state",

+    "PublicDescription": "Thread cycles when thread is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x01",

+    "EventName": "ITLB.ITLB_FLUSH",

+    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "PublicDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x01",

+    "EventName": "ICACHE.HIT",

+    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x02",

+    "EventName": "ICACHE.MISSES",

+    "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",

+    "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.UOPS",

+    "BriefDescription": "Number of Uops delivered by the LSD. ",

+    "PublicDescription": "Number of Uops delivered by the LSD. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_ACTIVE",

+    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x01",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

+    "PublicDescription": "Stalls caused by changing prefix length of the instruction.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x04",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Stall cycles because IQ is full",

+    "PublicDescription": "Stall cycles because IQ is full",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x17",

+    "UMask": "0x01",

+    "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",

+    "BriefDescription": "Valid instructions written to IQ per cycle",

+    "PublicDescription": "Valid instructions written to IQ per cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x02",

+    "EventName": "IDQ.EMPTY",

+    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "PublicDescription": "Instruction Decode Queue (IDQ) empty cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_UOPS",

+    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x20",

+    "EventName": "IDQ.MS_MITE_UOPS",

+    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

+    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",

+    "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "PublicDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "PublicDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x01",

+    "EventName": "DSB2MITE_SWITCHES.COUNT",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

+    "PublicDescription": "Decode Stream Buffer (DSB)-to-MITE switches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAB",

+    "UMask": "0x02",

+    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

+    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",

+    "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAC",

+    "UMask": "0x02",

+    "EventName": "DSB_FILL.OTHER_CANCEL",

+    "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit",

+    "PublicDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAC",

+    "UMask": "0x08",

+    "EventName": "DSB_FILL.EXCEED_DSB_LINES",

+    "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

+    "PublicDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x40",

+    "EventName": "INT_MISC.RAT_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x59",

+    "UMask": "0x20",

+    "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",

+    "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",

+    "PublicDescription": "Increments the number of flags-merge uops in flight each cycle.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x59",

+    "UMask": "0x40",

+    "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",

+    "BriefDescription": "Cycles with at least one slow LEA uop being allocated",

+    "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x59",

+    "UMask": "0x80",

+    "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",

+    "BriefDescription": "Multiply packed/scalar single precision uops allocated",

+    "PublicDescription": "Multiply packed/scalar single precision uops allocated",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x01",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource-related stall cycles",

+    "PublicDescription": "Resource-related stall cycles",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x02",

+    "EventName": "RESOURCE_STALLS.LB",

+    "BriefDescription": "Counts the cycles of stall due to lack of load buffers.",

+    "PublicDescription": "Counts the cycles of stall due to lack of load buffers.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x04",

+    "EventName": "RESOURCE_STALLS.RS",

+    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",

+    "PublicDescription": "Cycles stalled due to no eligible RS entry available.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x08",

+    "EventName": "RESOURCE_STALLS.SB",

+    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "PublicDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB",

+    "BriefDescription": "Cycles stalled due to re-order buffer full.",

+    "PublicDescription": "Cycles stalled due to re-order buffer full.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5B",

+    "UMask": "0x40",

+    "EventName": "RESOURCE_STALLS2.BOB_FULL",

+    "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it",

+    "PublicDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",

+    "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0E",

+    "UMask": "0x01",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_CYCLES",

+    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "PublicDescription": "Cycles when Reservation Station (RS) is empty for the thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0",

+    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

+    "PublicDescription": "Unhalted core cycles when the thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x01",

+    "EventName": "CPL_CYCLES.RING0_TRANS",

+    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "PublicDescription": "Number of intervals between processor halts while thread is in ring 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5C",

+    "UMask": "0x02",

+    "EventName": "CPL_CYCLES.RING123",

+    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "PublicDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x20",

+    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",

+    "BriefDescription": "Count cases of saving new LBR",

+    "PublicDescription": "Count cases of saving new LBR",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x02",

+    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

+    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

+    "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x04",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-modifying code (SMC) detected.",

+    "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x20",

+    "EventName": "MACHINE_CLEARS.MASKMOV",

+    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ",

+    "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x00",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",

+    "PublicDescription": "Number of instructions retired. General Counter   - architectural event",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.ALL",

+    "BriefDescription": "Actually retired uops. ",

+    "PublicDescription": "This event counts the number of micro-ops retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x02",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used. ",

+    "PublicDescription": "This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops. ",

+    "PublicDescription": "Cycles without actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Cycles with less than 10 actually retired uops. ",

+    "PublicDescription": "Cycles with less than 10 actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "10",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x01",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Conditional branch instructions retired. ",

+    "PublicDescription": "Conditional branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x02",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect near call instructions retired. ",

+    "PublicDescription": "Direct and indirect near call instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x00",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All (macro) branch instructions retired.",

+    "PublicDescription": "All (macro) branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x08",

+    "EventName": "BR_INST_RETIRED.NEAR_RETURN",

+    "BriefDescription": "Return instructions retired. ",

+    "PublicDescription": "Return instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x10",

+    "EventName": "BR_INST_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Not taken branch instructions retired. ",

+    "PublicDescription": "Not taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x20",

+    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",

+    "BriefDescription": "Taken branch instructions retired. ",

+    "PublicDescription": "Taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x40",

+    "EventName": "BR_INST_RETIRED.FAR_BRANCH",

+    "BriefDescription": "Far branch instructions retired. ",

+    "PublicDescription": "Far branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x04",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",

+    "PublicDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x01",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional branch instructions retired. ",

+    "PublicDescription": "Mispredicted conditional branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x02",

+    "EventName": "BR_MISP_RETIRED.NEAR_CALL",

+    "BriefDescription": "Direct and indirect mispredicted near call instructions retired. ",

+    "PublicDescription": "Direct and indirect mispredicted near call instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x00",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "All mispredicted macro branch instructions retired.",

+    "PublicDescription": "All mispredicted macro branch instructions retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x10",

+    "EventName": "BR_MISP_RETIRED.NOT_TAKEN",

+    "BriefDescription": "Mispredicted not taken branch instructions retired. ",

+    "PublicDescription": "Mispredicted not taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_RETIRED.TAKEN",

+    "BriefDescription": "Mispredicted taken branch instructions retired. ",

+    "PublicDescription": "Mispredicted taken branch instructions retired. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x04",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",

+    "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",

+    "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "400009",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x02",

+    "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",

+    "BriefDescription": "Retired instructions experiencing ITLB misses. ",

+    "PublicDescription": "Retired instructions experiencing ITLB misses. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x08",

+    "EventName": "OTHER_ASSISTS.AVX_STORE",

+    "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

+    "PublicDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x10",

+    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

+    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "PublicDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC1",

+    "UMask": "0x20",

+    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

+    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "PublicDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x02",

+    "EventName": "FP_ASSIST.X87_OUTPUT",

+    "BriefDescription": "Number of X87 assists due to output value.",

+    "PublicDescription": "Number of X87 assists due to output value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x04",

+    "EventName": "FP_ASSIST.X87_INPUT",

+    "BriefDescription": "Number of X87 assists due to input value.",

+    "PublicDescription": "Number of X87 assists due to input value.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x08",

+    "EventName": "FP_ASSIST.SIMD_OUTPUT",

+    "BriefDescription": "Number of SIMD FP assists due to Output values",

+    "PublicDescription": "Number of SIMD FP assists due to Output values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x10",

+    "EventName": "FP_ASSIST.SIMD_INPUT",

+    "BriefDescription": "Number of SIMD FP assists due to input values",

+    "PublicDescription": "Number of SIMD FP assists due to input values",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

+    "BriefDescription": "Loads with latency value being above 4 ",

+    "PublicDescription": "Loads with latency value being above 4 ",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

+    "BriefDescription": "Loads with latency value being above 8",

+    "PublicDescription": "Loads with latency value being above 8",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

+    "BriefDescription": "Loads with latency value being above 16",

+    "PublicDescription": "Loads with latency value being above 16",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

+    "BriefDescription": "Loads with latency value being above 32",

+    "PublicDescription": "Loads with latency value being above 32",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

+    "BriefDescription": "Loads with latency value being above 64",

+    "PublicDescription": "Loads with latency value being above 64",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2003",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

+    "BriefDescription": "Loads with latency value being above 128",

+    "PublicDescription": "Loads with latency value being above 128",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "1009",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

+    "BriefDescription": "Loads with latency value being above 256",

+    "PublicDescription": "Loads with latency value being above 256",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "503",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x01",

+    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

+    "BriefDescription": "Loads with latency value being above 512",

+    "PublicDescription": "Loads with latency value being above 512",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "101",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCD",

+    "UMask": "0x02",

+    "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",

+    "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS)",

+    "PublicDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS)",

+    "Counter": "3",

+    "CounterHTOff": "3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "1",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x11",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",

+    "BriefDescription": "Retired load uops that miss the STLB.",

+    "PublicDescription": "Retired load uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x12",

+    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",

+    "BriefDescription": "Retired store uops that miss the STLB.",

+    "PublicDescription": "Retired store uops that miss the STLB.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x21",

+    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",

+    "BriefDescription": "Retired load uops with locked access.",

+    "PublicDescription": "Retired load uops with locked access.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x41",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",

+    "BriefDescription": "Retired load uops that split across a cacheline boundary.",

+    "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x42",

+    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",

+    "BriefDescription": "Retired store uops that split across a cacheline boundary.",

+    "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x81",

+    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

+    "BriefDescription": "All retired load uops.",

+    "PublicDescription": "This event counts the number of load uops retired",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x82",

+    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

+    "BriefDescription": "All retired store uops.",

+    "PublicDescription": "This event counts the number of store uops retired.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",

+    "BriefDescription": "Retired load uops with L1 cache hits as data sources. ",

+    "PublicDescription": "Retired load uops with L1 cache hits as data sources. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

+    "BriefDescription": "Retired load uops with L2 cache hits as data sources. ",

+    "PublicDescription": "Retired load uops with L2 cache hits as data sources. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",

+    "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ",

+    "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "50021",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",

+    "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x01",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",

+    "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",

+    "PublicDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",

+    "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ",

+    "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified state.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x04",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",

+    "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ",

+    "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "20011",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x08",

+    "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",

+    "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",

+    "PublicDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD4",

+    "UMask": "0x02",

+    "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS",

+    "BriefDescription": "Retired load uops with unknown information as data source in cache serviced the load. ",

+    "PublicDescription": "This event counts retired demand loads that missed the  last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x01",

+    "EventName": "ARITH.FPU_DIV_ACTIVE",

+    "BriefDescription": "Cycles when divider is busy executing divide operations",

+    "PublicDescription": "Cycles when divider is busy executing divide operations",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x01",

+    "EventName": "ARITH.FPU_DIV",

+    "BriefDescription": "Divide operations executed",

+    "PublicDescription": "This event counts the number of the divide operations executed.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x01",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

+    "PublicDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",

+    "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

+    "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x11",

+    "UMask": "0x01",

+    "EventName": "SIMD_FP_256.PACKED_SINGLE",

+    "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

+    "PublicDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x11",

+    "UMask": "0x02",

+    "EventName": "SIMD_FP_256.PACKED_DOUBLE",

+    "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

+    "PublicDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED.THREAD",

+    "BriefDescription": "Uops dispatched per thread",

+    "PublicDescription": "Uops dispatched per thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED.CORE",

+    "BriefDescription": "Uops dispatched from any thread",

+    "PublicDescription": "Uops dispatched from any thread",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 0",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 1",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 4",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",

+    "BriefDescription": "Cycles per thread when uops are dispatched to port 5",

+    "PublicDescription": "Cycles per thread when uops are dispatched to port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x04",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",

+    "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",

+    "PublicDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x02",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",

+    "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",

+    "PublicDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x01",

+    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",

+    "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",

+    "PublicDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x06",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",

+    "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",

+    "PublicDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA3",

+    "UMask": "0x05",

+    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",

+    "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",

+    "PublicDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "5",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4F",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",

+    "PublicDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x01",

+    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Misses at all ITLB levels that cause page walks",

+    "PublicDescription": "Misses at all ITLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x02",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Misses in all ITLB levels that cause completed page walks",

+    "PublicDescription": "Misses in all ITLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x04",

+    "EventName": "ITLB_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x10",

+    "EventName": "ITLB_MISSES.STLB_HIT",

+    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x01",

+    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Load misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Load misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x02",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Load misses at all DTLB levels that cause completed page walks",

+    "PublicDescription": "Load misses at all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x04",

+    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x08",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",

+    "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x01",

+    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",

+    "BriefDescription": "Store misses in all DTLB levels that cause page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x02",

+    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",

+    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x04",

+    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",

+    "BriefDescription": "Cycles when PMH is busy with page walks",

+    "PublicDescription": "Cycles when PMH is busy with page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_STORE_MISSES.STLB_HIT",

+    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x01",

+    "EventName": "TLB_FLUSH.DTLB_THREAD",

+    "BriefDescription": "DTLB flush attempts of the thread-specific entries",

+    "PublicDescription": "DTLB flush attempts of the thread-specific entries",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBD",

+    "UMask": "0x20",

+    "EventName": "TLB_FLUSH.STLB_ANY",

+    "BriefDescription": "STLB flush attempts",

+    "PublicDescription": "STLB flush attempts",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100007",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBE",

+    "UMask": "0x01",

+    "EventName": "PAGE_WALKS.LLC_MISS",

+    "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND",

+    "PublicDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x01",

+    "EventName": "L1D.REPLACEMENT",

+    "BriefDescription": "L1D data line replacements",

+    "PublicDescription": "This event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.  ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x02",

+    "EventName": "L1D.ALLOCATED_IN_M",

+    "BriefDescription": "Allocated L1D data cache lines in M state",

+    "PublicDescription": "Allocated L1D data cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x04",

+    "EventName": "L1D.EVICTION",

+    "BriefDescription": "L1D data cache lines in M state evicted due to replacement",

+    "PublicDescription": "L1D data cache lines in M state evicted due to replacement",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x08",

+    "EventName": "L1D.ALL_M_REPLACEMENT",

+    "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement",

+    "PublicDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING",

+    "BriefDescription": "L1D miss oustandings duration in cycles",

+    "PublicDescription": "L1D miss oustandings duration in cycles",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",

+    "BriefDescription": "Cycles with L1D load Misses outstanding. ",

+    "PublicDescription": "Cycles with L1D load Misses outstanding. ",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x01",

+    "EventName": "LOAD_HIT_PRE.SW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x02",

+    "EventName": "LOAD_HIT_PRE.HW_PF",

+    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "PublicDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x02",

+    "EventName": "HW_PRE_REQ.DL1_MISS",

+    "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for ",

+    "PublicDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x01",

+    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "PublicDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x02",

+    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",

+    "BriefDescription": "Cycles when L1D is locked",

+    "PublicDescription": "Cycles when L1D is locked",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS.DATA_UNKNOWN",

+    "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data",

+    "PublicDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x02",

+    "EventName": "LD_BLOCKS.STORE_FORWARD",

+    "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",

+    "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS.NO_SR",

+    "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "PublicDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x03",

+    "UMask": "0x10",

+    "EventName": "LD_BLOCKS.ALL_BLOCK",

+    "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)",

+    "PublicDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x01",

+    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies in MOB due to partial compare",

+    "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline.  The enhanced address check typically has a performance penalty of 5 cycles.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x07",

+    "UMask": "0x08",

+    "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",

+    "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",

+    "PublicDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x01",

+    "EventName": "MISALIGN_MEM_REF.LOADS",

+    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split load uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x05",

+    "UMask": "0x02",

+    "EventName": "MISALIGN_MEM_REF.STORES",

+    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "PublicDescription": "Speculative cache line split STA uops dispatched to L1 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB6",

+    "UMask": "0x01",

+    "EventName": "AGU_BYPASS_CANCEL.COUNT",

+    "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an",

+    "PublicDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",

+    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "PublicDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

+    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

+    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests sent to uncore",

+    "PublicDescription": "Demand Data Read requests sent to uncore",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x02",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

+    "BriefDescription": "Cacheable and noncachaeble code read requests",

+    "PublicDescription": "Cacheable and noncachaeble code read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",

+    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "PublicDescription": "Demand RFO requests including regular RFOs, locks, ItoM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x08",

+    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",

+    "BriefDescription": "Demand and prefetch data reads",

+    "PublicDescription": "Demand and prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",

+    "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",

+    "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x01",

+    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",

+    "BriefDescription": "Demand Data Read requests that hit L2 cache",

+    "PublicDescription": "Demand Data Read requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x04",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "RFO requests that hit L2 cache",

+    "PublicDescription": "RFO requests that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x08",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "RFO requests that miss L2 cache",

+    "PublicDescription": "RFO requests that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.CODE_RD_HIT",

+    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",

+    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.CODE_RD_MISS",

+    "BriefDescription": "L2 cache misses when fetching instructions",

+    "PublicDescription": "L2 cache misses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PF_HIT",

+    "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",

+    "PublicDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PF_MISS",

+    "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",

+    "PublicDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x01",

+    "EventName": "L2_STORE_LOCK_RQSTS.MISS",

+    "BriefDescription": "RFOs that miss cache lines",

+    "PublicDescription": "RFOs that miss cache lines",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x04",

+    "EventName": "L2_STORE_LOCK_RQSTS.HIT_E",

+    "BriefDescription": "RFOs that hit cache lines in E state",

+    "PublicDescription": "RFOs that hit cache lines in E state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x08",

+    "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",

+    "BriefDescription": "RFOs that hit cache lines in M state",

+    "PublicDescription": "RFOs that hit cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x0F",

+    "EventName": "L2_STORE_LOCK_RQSTS.ALL",

+    "BriefDescription": "RFOs that access cache lines in any state",

+    "PublicDescription": "RFOs that access cache lines in any state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x01",

+    "EventName": "L2_L1D_WB_RQSTS.MISS",

+    "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",

+    "PublicDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x02",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_S",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in S state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x04",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_E",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x08",

+    "EventName": "L2_L1D_WB_RQSTS.HIT_M",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x0F",

+    "EventName": "L2_L1D_WB_RQSTS.ALL",

+    "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",

+    "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x01",

+    "EventName": "L2_TRANS.DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests that access L2 cache",

+    "PublicDescription": "Demand Data Read requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x02",

+    "EventName": "L2_TRANS.RFO",

+    "BriefDescription": "RFO requests that access L2 cache",

+    "PublicDescription": "RFO requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x04",

+    "EventName": "L2_TRANS.CODE_RD",

+    "BriefDescription": "L2 cache accesses when fetching instructions",

+    "PublicDescription": "L2 cache accesses when fetching instructions",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x08",

+    "EventName": "L2_TRANS.ALL_PF",

+    "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",

+    "PublicDescription": "L2 or LLC HW prefetches that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANS.L1D_WB",

+    "BriefDescription": "L1D writebacks that access L2 cache",

+    "PublicDescription": "L1D writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANS.L2_FILL",

+    "BriefDescription": "L2 fill requests that access L2 cache",

+    "PublicDescription": "L2 fill requests that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANS.L2_WB",

+    "BriefDescription": "L2 writebacks that access L2 cache",

+    "PublicDescription": "L2 writebacks that access L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANS.ALL_REQUESTS",

+    "BriefDescription": "Transactions accessing L2 pipe",

+    "PublicDescription": "Transactions accessing L2 pipe",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_IN.I",

+    "BriefDescription": "L2 cache lines in I state filling L2",

+    "PublicDescription": "L2 cache lines in I state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_IN.S",

+    "BriefDescription": "L2 cache lines in S state filling L2",

+    "PublicDescription": "L2 cache lines in S state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_IN.E",

+    "BriefDescription": "L2 cache lines in E state filling L2",

+    "PublicDescription": "L2 cache lines in E state filling L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x07",

+    "EventName": "L2_LINES_IN.ALL",

+    "BriefDescription": "L2 cache lines filling L2",

+    "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x01",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by demand",

+    "PublicDescription": "Clean L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x02",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by demand",

+    "PublicDescription": "Dirty L2 cache lines evicted by demand",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x04",

+    "EventName": "L2_LINES_OUT.PF_CLEAN",

+    "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",

+    "PublicDescription": "Clean L2 cache lines evicted by L2 prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x08",

+    "EventName": "L2_LINES_OUT.PF_DIRTY",

+    "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",

+    "PublicDescription": "Dirty L2 cache lines evicted by L2 prefetch",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x0A",

+    "EventName": "L2_LINES_OUT.DIRTY_ALL",

+    "BriefDescription": "Dirty L2 cache lines filling the L2",

+    "PublicDescription": "Dirty L2 cache lines filling the L2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Core-originated cacheable demand requests missed LLC",

+    "PublicDescription": "Core-originated cacheable demand requests missed LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",

+    "PublicDescription": "Core-originated cacheable demand requests that refer to LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x10",

+    "EventName": "SQ_MISC.SPLIT_LOCK",

+    "BriefDescription": "Split locks in SQ",

+    "PublicDescription": "Split locks in SQ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",

+    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",

+    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",

+    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x01",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 0",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 0",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x02",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 1",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 1",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x40",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 4",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 4",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x80",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",

+    "BriefDescription": "Cycles per core when uops are dispatched to port 5",

+    "PublicDescription": "Cycles per core when uops are dispatched to port 5",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x04",

+    "EventName": "IDQ.MITE_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x08",

+    "EventName": "IDQ.DSB_CYCLES",

+    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x0C",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",

+    "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",

+    "PublicDescription": "Cycles per thread when load or STA uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x30",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",

+    "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",

+    "PublicDescription": "Cycles per thread when load or STA uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_CYCLES",

+    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x10",

+    "EventName": "IDQ.MS_DSB_OCCUR",

+    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x0C",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",

+    "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2",

+    "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 2",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA1",

+    "UMask": "0x30",

+    "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",

+    "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",

+    "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x01",

+    "EventName": "INST_RETIRED.PREC_DIST",

+    "BriefDescription": "Instructions retired. (Precise Event - PEBS)",

+    "PublicDescription": "Instructions retired. (Precise Event - PEBS)",

+    "Counter": "1",

+    "CounterHTOff": "1",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "1",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x03",

+    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

+    "BriefDescription": "Demand Data Read requests",

+    "PublicDescription": "Demand Data Read requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x0C",

+    "EventName": "L2_RQSTS.ALL_RFO",

+    "BriefDescription": "RFO requests to L2 cache",

+    "PublicDescription": "RFO requests to L2 cache",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.ALL_CODE_RD",

+    "BriefDescription": "L2 code requests",

+    "PublicDescription": "L2 code requests",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.ALL_PF",

+    "BriefDescription": "Requests from L2 hardware prefetchers",

+    "PublicDescription": "Requests from L2 hardware prefetchers",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xBF",

+    "UMask": "0x05",

+    "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",

+    "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports",

+    "PublicDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5B",

+    "UMask": "0x0F",

+    "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",

+    "BriefDescription": "Resource stalls2 control structures full for physical registers",

+    "PublicDescription": "Resource stalls2 control structures full for physical registers",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 2 uops delivered by the front end",

+    "PublicDescription": "Cycles with less than 2 uops delivered by the front end",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles with less than 3 uops delivered by the front end",

+    "PublicDescription": "Cycles with less than 3 uops delivered by the front end",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5B",

+    "UMask": "0x0C",

+    "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",

+    "BriefDescription": "Cycles with either free list is empty",

+    "PublicDescription": "Cycles with either free list is empty",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x0E",

+    "EventName": "RESOURCE_STALLS.MEM_RS",

+    "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized",

+    "PublicDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0xF0",

+    "EventName": "RESOURCE_STALLS.OOO_RSRC",

+    "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER",

+    "PublicDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5B",

+    "UMask": "0x4F",

+    "EventName": "RESOURCE_STALLS2.OOO_RSRC",

+    "BriefDescription": "Resource stalls out of order resources full",

+    "PublicDescription": "Resource stalls out of order resources full",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x0A",

+    "EventName": "RESOURCE_STALLS.LB_SB",

+    "BriefDescription": "Resource stalls due to load or store buffers all being in use",

+    "PublicDescription": "Resource stalls due to load or store buffers all being in use",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES",

+    "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x59",

+    "UMask": "0x20",

+    "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",

+    "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch",

+    "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",

+    "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",

+    "PublicDescription": "Cycles when 1 or more uops were delivered to the by the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_STALLS_COUNT",

+    "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "PublicDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x18",

+    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "PublicDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",

+    "BriefDescription": "Cycles MITE is delivering 4 Uops",

+    "PublicDescription": "Cycles MITE is delivering 4 Uops",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x24",

+    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",

+    "BriefDescription": "Cycles MITE is delivering any Uop",

+    "PublicDescription": "Cycles MITE is delivering any Uop",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAC",

+    "UMask": "0x0A",

+    "EventName": "DSB_FILL.ALL_CANCEL",

+    "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit",

+    "PublicDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCA",

+    "UMask": "0x1E",

+    "EventName": "FP_ASSIST.ANY",

+    "BriefDescription": "Cycles with any input/output SSE or FP assist",

+    "PublicDescription": "Cycles with any input/output SSE or FP assist",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1F",

+    "EventName": "BACLEARS.ANY",

+    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x04",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",

+    "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x9C",

+    "UMask": "0x01",

+    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

+    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0xFF",

+    "EventName": "BR_INST_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired  branches",

+    "PublicDescription": "Speculative and retired  branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0xFF",

+    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",

+    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",

+    "PublicDescription": "Speculative and retired mispredicted macro conditional branches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "200003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x3c",

+    "EventName": "IDQ.MITE_ALL_UOPS",

+    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "PublicDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x01",

+    "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles without actually retired uops. ",

+    "PublicDescription": "Cycles without actually retired uops. ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x01",

+    "EventName": "LSD.CYCLES_4_UOPS",

+    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xc3",

+    "UMask": "0x01",

+    "EventName": "MACHINE_CLEARS.COUNT",

+    "BriefDescription": "Number of machine clears (nukes) of any type.",

+    "PublicDescription": "Number of machine clears (nukes) of any type.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5E",

+    "UMask": "0x01",

+    "EventName": "RS_EVENTS.EMPTY_END",

+    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x79",

+    "UMask": "0x30",

+    "EventName": "IDQ.MS_SWITCHES",

+    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x00",

+    "UMask": "0x02",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "Fixed counter 2",

+    "CounterHTOff": "Fixed counter 2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x00",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",

+    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x01",

+    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",

+    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0D",

+    "UMask": "0x03",

+    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",

+    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6",

+    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "6",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",

+    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",

+    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "2",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",

+    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "3",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",

+    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "4",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x02",

+    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",

+    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x01",

+    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",

+    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",

+    "Counter": "2",

+    "CounterHTOff": "2",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x48",

+    "UMask": "0x02",

+    "EventName": "L1D_PEND_MISS.FB_FULL",

+    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3,4,5,6,7",

+    "SampleAfterValue": "2000003",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "TakenAlone": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400244",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",

+    "PublicDescription": "Counts all demand & prefetch data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400091",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch code reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0240",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0240",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0240",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0240",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0240",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all prefetch code reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all prefetch code reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400240",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch data reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all prefetch data reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all prefetch data reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400090",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch RFOs that hit in the LLC",

+    "PublicDescription": "Counts all prefetch RFOs that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0120",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0120",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0120",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0120",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0120",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all prefetch RFOs that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all prefetch RFOs that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400120",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c03f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3004003f7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",

+    "PublicDescription": "Counts all demand & prefetch RFOs that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",

+    "BriefDescription": "tbd",

+    "PublicDescription": "tbd",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10008",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads that hit in the LLC",

+    "PublicDescription": "Counts all demand code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",

+    "PublicDescription": "Counts demand code reads that miss the LLC and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data reads that hit in the LLC",

+    "PublicDescription": "Counts all demand data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",

+    "PublicDescription": "Counts demand data reads that miss the LLC and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",

+    "PublicDescription": "Counts all demand data writes (RFOs) that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",

+    "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram",

+    "PublicDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",

+    "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "PublicDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x18000",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",

+    "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "PublicDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x803c8000",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",

+    "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",

+    "PublicDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2380408000",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram",

+    "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400020",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x3f803c0100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x4003c0100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10003c0100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1003c0100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS",

+    "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "PublicDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x2003c0100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",

+    "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram",

+    "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x300400100",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",

+    "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address ",

+    "PublicDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10400",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",

+    "BriefDescription": "Counts non-temporal stores",

+    "PublicDescription": "Counts non-temporal stores",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10800",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand data reads ",

+    "PublicDescription": "Counts all demand data reads ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010001",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand rfo's ",

+    "PublicDescription": "Counts all demand rfo's ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand code reads",

+    "PublicDescription": "Counts all demand code reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch data reads",

+    "PublicDescription": "Counts all demand & prefetch data reads",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x000105B3",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",

+    "BriefDescription": "Counts all demand & prefetch prefetch RFOs ",

+    "PublicDescription": "Counts all demand & prefetch prefetch RFOs ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x00010122",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",

+    "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) ",

+    "PublicDescription": "Counts all data/code/rfo references (demand & prefetch) ",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x000107F7",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x01",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",

+    "BriefDescription": "Counts LLC replacements",

+    "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC  where the data is returned from local DRAM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x6004001b3",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",

+    "BriefDescription": " REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1f80408fff",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE",

+    "BriefDescription": " REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE",

+    "PublicDescription": " REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10433",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",

+    "BriefDescription": " REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",

+    "PublicDescription": " REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x17004001b3",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",

+    "BriefDescription": " REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "PublicDescription": " REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1f80400004",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM",

+    "BriefDescription": " REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM",

+    "PublicDescription": " REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1000040002",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",

+    "BriefDescription": " REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "PublicDescription": " REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1f80400010",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE",

+    "BriefDescription": " REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE",

+    "PublicDescription": " REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",

+    "BriefDescription": " REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "PublicDescription": " REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1f80400040",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE",

+    "BriefDescription": " REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE",

+    "PublicDescription": " REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",

+    "BriefDescription": " REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "PublicDescription": " REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1f80400080",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE",

+    "BriefDescription": " REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE",

+    "PublicDescription": " REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x10200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7, 0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",

+    "BriefDescription": " REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "PublicDescription": " REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

+    "Counter": "0,1,2,3",

+    "CounterHTOff": "0,1,2,3",

+    "SampleAfterValue": "100003",

+    "MSRIndex": "0x1a6,0x1a7",

+    "MSRValue": "0x1f80400200",

+    "TakenAlone": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "PRECISE_STORE": "0",

+    "Errata": "null",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SNB/SandyBridge_core_V12.tsv b/x86data/perfmon_data/SNB/SandyBridge_core_V12.tsv
new file mode 100644
index 0000000..e2779b0
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_core_V12.tsv
@@ -0,0 +1,288 @@
+# Performance Monitoring Events for the Second Generation Intel Core Processors Based on the Sandy Bridge Microarchitecture - V12
+# 8/16/2015 8:57:19 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
+0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state.	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	null
+0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 3	Fixed counter 3	2000003	0	0	0	0	0	0	0	0	0	null
+0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x88	BR_MISP_EXEC.TAKEN_RETURN_NEAR	Taken speculative and retired mispredicted indirect branches with return mnemonic	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0x90	BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired mispredicted direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xD0	BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired mispredicted direct near calls	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAE	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x80	0x02	ICACHE.MISSES	Instruction cache, streaming buffer and victim cache misses	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xA8	0x01	LSD.UOPS	Number of Uops delivered by the LSD. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x87	0x04	ILD_STALL.IQ_FULL	Stall cycles because IQ is full	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x17	0x01	INSTS_WRITTEN_TO_IQ.INSTS	Valid instructions written to IQ per cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled 	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	null
+0xAB	0x01	DSB2MITE_SWITCHES.COUNT	Decode Stream Buffer (DSB)-to-MITE switches	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAC	0x02	DSB_FILL.OTHER_CANCEL	Cases of cancelling valid DSB fill not because of exceeding way limit	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xAC	0x08	DSB_FILL.EXCEED_DSB_LINES	Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0D	0x40	INT_MISC.RAT_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x59	0x20	PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP	Increments the number of flags-merge uops in flight each cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x59	0x40	PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW	Cycles with at least one slow LEA uop being allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x59	0x80	PARTIAL_RAT_STALLS.MUL_SINGLE_UOP	Multiply packed/scalar single precision uops allocated	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x02	RESOURCE_STALLS.LB	Counts the cycles of stall due to lack of load buffers.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5B	0x40	RESOURCE_STALLS2.BOB_FULL	Cycles when Allocator is stalled if BOB is full and new branch needs it	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0x0E	0x01	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	1	0	0	1	0	0	null
+0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	null
+0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used. 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	null
+0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	null
+0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. (Precise Event - PEBS)	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	null
+0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x02	BR_MISP_RETIRED.NEAR_CALL	Direct and indirect mispredicted near call instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	null
+0xC5	0x10	BR_MISP_RETIRED.NOT_TAKEN	Mispredicted not taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x20	BR_MISP_RETIRED.TAKEN	Mispredicted taken branch instructions retired. 	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	null
+0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. (Precise Event - PEBS)	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	null
+0xC1	0x02	OTHER_ASSISTS.ITLB_MISS_RETIRED	Retired instructions experiencing ITLB misses. 	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x08	OTHER_ASSISTS.AVX_STORE	Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x10	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xC1	0x20	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4 	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32	3	3	100007	0x3F6	0x20	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	null
+0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	null
+0xCD	0x02	MEM_TRANS_RETIRED.PRECISE_STORE	Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS)	3	3	2000003	0	0	1	0	0	0	0	2	1	null
+0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access.	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	null
+0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary.	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources. 	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD1	0x04	MEM_LOAD_UOPS_RETIRED.LLC_HIT	Retired load uops which data sources were data hits in LLC without snoops required. 	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	0	null
+0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD2	0x01	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x02	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x04	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared LLC. 	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	null
+0xD2	0x08	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in LLC without snoops required. 	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	null
+0xD4	0x02	MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS	Retired load uops with unknown information as data source in cache serviced the load. 	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	null
+0x14	0x01	ARITH.FPU_DIV_ACTIVE	Cycles when divider is busy executing divide operations	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x14	0x01	ARITH.FPU_DIV	Divide operations executed	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	null
+0x10	0x01	FP_COMP_OPS_EXE.X87	Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x10	FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE	Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x20	FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE	Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x40	FP_COMP_OPS_EXE.SSE_PACKED_SINGLE	Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x10	0x80	FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE	Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x11	0x01	SIMD_FP_256.PACKED_SINGLE	number of GSSE-256 Computational FP single precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x11	0x02	SIMD_FP_256.PACKED_DOUBLE	number of AVX-256 Computational FP double precision uops issued this cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x01	UOPS_DISPATCHED.THREAD	Uops dispatched per thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB1	0x02	UOPS_DISPATCHED.CORE	Uops dispatched from any thread	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are dispatched to port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are dispatched to port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are dispatched to port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are dispatched to port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_DISPATCH	Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	null
+0xA3	0x02	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.	2	2	2000003	0	0	0	2	0	0	0	0	0	null
+0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xA3	0x06	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.	2	2	2000003	0	0	0	6	0	0	0	0	0	null
+0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	null
+0x4F	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x02	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x85	0x04	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x85	0x10	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x01	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Load misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED	Load misses at all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x08	0x04	DTLB_LOAD_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x08	0x10	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x49	0x04	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x49	0x10	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xBD	0x01	TLB_FLUSH.DTLB_THREAD	DTLB flush attempts of the thread-specific entries	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xBD	0x20	TLB_FLUSH.STLB_ANY	STLB flush attempts	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	null
+0xBE	0x01	PAGE_WALKS.LLC_MISS	Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x51	0x01	L1D.REPLACEMENT	L1D data line replacements	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x51	0x02	L1D.ALLOCATED_IN_M	Allocated L1D data cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x51	0x04	L1D.EVICTION	L1D data cache lines in M state evicted due to replacement	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x51	0x08	L1D.ALL_M_REPLACEMENT	Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles	2	2	2000003	0	0	0	0	0	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding. 	2	2	2000003	0	0	0	1	0	0	0	0	0	null
+0x4C	0x01	LOAD_HIT_PRE.SW_PF	Not software-prefetch load dispatches that hit FB allocated for software prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4C	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x4E	0x02	HW_PRE_REQ.DL1_MISS	Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for 	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x03	0x01	LD_BLOCKS.DATA_UNKNOWN	Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x03	0x02	LD_BLOCKS.STORE_FORWARD	Cases when loads get true Block-on-Store blocking code preventing store forwarding	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x03	0x08	LD_BLOCKS.NO_SR	This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x03	0x10	LD_BLOCKS.ALL_BLOCK	Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x07	0x08	LD_BLOCKS_PARTIAL.ALL_STA_BLOCK	This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xB6	0x01	AGU_BYPASS_CANCEL.COUNT	This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xB0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xB2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Cases when offcore requests buffer cannot take more entries for core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x24	0x01	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x04	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x08	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x10	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x20	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x40	L2_RQSTS.PF_HIT	Requests from the L2 hardware prefetchers that hit L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x80	L2_RQSTS.PF_MISS	Requests from the L2 hardware prefetchers that miss L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x01	L2_STORE_LOCK_RQSTS.MISS	RFOs that miss cache lines	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x04	L2_STORE_LOCK_RQSTS.HIT_E	RFOs that hit cache lines in E state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x08	L2_STORE_LOCK_RQSTS.HIT_M	RFOs that hit cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x27	0x0F	L2_STORE_LOCK_RQSTS.ALL	RFOs that access cache lines in any state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x01	L2_L1D_WB_RQSTS.MISS	Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x02	L2_L1D_WB_RQSTS.HIT_S	Not rejected writebacks from L1D to L2 cache lines in S state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x04	L2_L1D_WB_RQSTS.HIT_E	Not rejected writebacks from L1D to L2 cache lines in E state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x08	L2_L1D_WB_RQSTS.HIT_M	Not rejected writebacks from L1D to L2 cache lines in M state	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x28	0x0F	L2_L1D_WB_RQSTS.ALL	Not rejected writebacks from L1D to L2 cache lines in any state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x08	L2_TRANS.ALL_PF	L2 or LLC HW prefetches that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x01	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x02	L2_LINES_OUT.DEMAND_DIRTY	Dirty L2 cache lines evicted by demand	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x04	L2_LINES_OUT.PF_CLEAN	Clean L2 cache lines evicted by L2 prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x08	L2_LINES_OUT.PF_DIRTY	Dirty L2 cache lines evicted by L2 prefetch	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF2	0x0A	L2_LINES_OUT.DIRTY_ALL	Dirty L2 cache lines filling the L2	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed LLC	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to LLC	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0xF4	0x10	SQ_MISC.SPLIT_LOCK	Split locks in SQ	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x3C	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	null
+0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3). 	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	null
+0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0_CORE	Cycles per core when uops are dispatched to port 0	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1_CORE	Cycles per core when uops are dispatched to port 1	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4_CORE	Cycles per core when uops are dispatched to port 4	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5_CORE	Cycles per core when uops are dispatched to port 5	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when load or STA uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when load or STA uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2_CORE	Cycles per core when load or STA uops are dispatched to port 2	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3_CORE	Cycles per core when load or STA uops are dispatched to port 3	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0xC0	0x01	INST_RETIRED.PREC_DIST	Instructions retired. (Precise Event - PEBS)	1	1	2000003	0	0	1	0	0	0	0	2	0	null
+0x24	0x03	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x0C	L2_RQSTS.ALL_RFO	RFO requests to L2 cache	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0x30	L2_RQSTS.ALL_CODE_RD	L2 code requests	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x24	0xC0	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0xBF	0x05	L1D_BLOCKS.BANK_CONFLICT_CYCLES	Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	0	0	0	null
+0x5B	0x0F	RESOURCE_STALLS2.ALL_PRF_CONTROL	Resource stalls2 control structures full for physical registers	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	null
+0x5B	0x0C	RESOURCE_STALLS2.ALL_FL_EMPTY	Cycles with either free list is empty	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x0E	RESOURCE_STALLS.MEM_RS	Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0xF0	RESOURCE_STALLS.OOO_RSRC	Resource stalls due to Rob being full, FCSW, MXCSR and OTHER	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x5B	0x4F	RESOURCE_STALLS2.OOO_RSRC	Resource stalls out of order resources full	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xA2	0x0A	RESOURCE_STALLS.LB_SB	Resource stalls due to load or store buffers all being in use	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x59	0x20	PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES	Performance sensitive flags-merging uops added by Sandy Bridge u-arch	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE	Cycles when 1 or more uops were delivered to the by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	1	0	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_STALLS_COUNT	Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xAC	0x0A	DSB_FILL.ALL_CANCEL	Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	null
+0xE6	0x1F	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	null
+0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO	Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	null
+0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	null
+0xC2	0x01	UOPS_RETIRED.CORE_STALL_CYCLES	Cycles without actually retired uops. 	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	null
+0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0xc3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	null
+0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	1	0	0	null
+0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	null
+0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	1	0	0	0	null
+0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	null
+0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	null
+0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	6	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	2	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	3	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	null
+0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	1	0	0	0	0	null
+0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core	2	2	2000003	0	0	0	1	0	1	0	0	0	null
+0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/SNB/SandyBridge_matrix_V12.json b/x86data/perfmon_data/SNB/SandyBridge_matrix_V12.json
new file mode 100644
index 0000000..d625e9a
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_matrix_V12.json
@@ -0,0 +1,191 @@
+[
+  {
+    "MATRIX_REQUEST": "DEMAND_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000001",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts demand data reads"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000002",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand data writes (RFOs)"
+  },
+  {
+    "MATRIX_REQUEST": "DEMAND_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000004",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand code reads"
+  },
+  {
+    "MATRIX_REQUEST": "COREWB",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000008",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts core writebacks due to L2 evictions or L1 writeback requests"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000010",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to L2) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000020",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to L2) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_L2_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000040",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000080",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) data reads"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000100",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch (that bring data to LLC only) RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "PF_LLC_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000200",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch (that bring data to LLC only) code reads"
+  },
+  {
+    "MATRIX_REQUEST": "OTHER",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts any other requests"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000090",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000120",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_PF_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000240",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_DATA_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000091",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch data reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_RFO",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000122",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch RFOs"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_CODE_RD",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000000244",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all demand & prefetch code reads"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_READS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x00000003f7",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all data/code/rfo reads (demand & prefetch)"
+  },
+  {
+    "MATRIX_REQUEST": "ALL_REQUESTS",
+    "MATRIX_RESPONSE": "Null",
+    "MATRIX_VALUE": "0x0000008fff",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "Counts all requests"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3f803c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.NO_SNOOP_NEEDED",
+    "MATRIX_VALUE": "0x01003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.SNOOP_MISS",
+    "MATRIX_VALUE": "0x02003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoops sent to sibling cores return clean response"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+    "MATRIX_VALUE": "0x04003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_HIT.HITM_OTHER_CORE",
+    "MATRIX_VALUE": "0x10003c0000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_RESPONSE",
+    "MATRIX_VALUE": "0x3fffc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss in the LLC"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.LOCAL_DRAM",
+    "MATRIX_VALUE": "0x0600400000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the LLC and the data returned from local dram"
+  },
+  {
+    "MATRIX_REQUEST": "Null",
+    "MATRIX_RESPONSE": "LLC_MISS.ANY_DRAM",
+    "MATRIX_VALUE": "0x067fc00000",
+    "MATRIX_REGISTER": "0,1",
+    "DESCRIPTION": "miss the LLC and the data returned from local or remote dram"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SNB/SandyBridge_matrix_V12.tsv b/x86data/perfmon_data/SNB/SandyBridge_matrix_V12.tsv
new file mode 100644
index 0000000..824bc9d
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_matrix_V12.tsv
@@ -0,0 +1,31 @@
+# Performance Monitoring Events for the Second Generation Intel Core Processors Based on the Sandy Bridge Microarchitecture - V12
+# 7/28/2015 3:10:24 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
+DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand data reads
+DEMAND_RFO	Null	0x0002	0,1	Counts all demand data writes (RFOs)
+DEMAND_CODE_RD	Null	0x0004	0,1	Counts all demand code reads
+COREWB	Null	0x0008	0,1	Counts core writebacks due to L2 evictions or L1 writeback requests
+PF_L2_DATA_RD	Null	0x0010	0,1	Counts prefetch (that bring data to L2) data reads
+PF_L2_RFO	Null	0x0020	0,1	Counts all prefetch (that bring data to L2) RFOs
+PF_L2_CODE_RD	Null	0x0040	0,1	Counts all prefetch (that bring data to LLC only) code reads
+PF_LLC_DATA_RD	Null	0x0080	0,1	Counts all prefetch (that bring data to LLC only) data reads
+PF_LLC_RFO	Null	0x0100	0,1	Counts all prefetch (that bring data to LLC only) RFOs
+PF_LLC_CODE_RD	Null	0x0200	0,1	Counts prefetch (that bring data to LLC only) code reads
+OTHER	Null	0x8000	0,1	Counts any other requests
+ALL_PF_DATA_RD	Null	0x0090	0,1	Counts all prefetch data reads
+ALL_PF_RFO	Null	0x0120	0,1	Counts prefetch RFOs
+ALL_PF_CODE_RD	Null	0x0240	0,1	Counts all prefetch code reads
+ALL_DATA_RD	Null	0x0091	0,1	Counts all demand & prefetch data reads
+ALL_RFO	Null	0x0122	0,1	Counts all demand & prefetch RFOs
+ALL_CODE_RD	Null	0x0244	0,1	Counts all demand & prefetch code reads
+ALL_READS	Null	0x03f7	0,1	Counts all data/code/rfo reads (demand & prefetch)
+ALL_REQUESTS	Null	0x8fff	0,1	Counts all requests
+Null	LLC_HIT.ANY_RESPONSE	0x3f803c	0,1	hit in the LLC
+Null	LLC_HIT.NO_SNOOP_NEEDED	0x01003c	0,1	hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
+Null	LLC_HIT.SNOOP_MISS	0x02003c	0,1	hit in the LLC and the snoops sent to sibling cores return clean response
+Null	LLC_HIT.HIT_OTHER_CORE_NO_FWD	0x04003c	0,1	hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
+Null	LLC_HIT.HITM_OTHER_CORE	0x10003c	0,1	hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
+Null	LLC_MISS.ANY_RESPONSE	0x3fffc0	0,1	miss in the LLC
+Null	LLC_MISS.LOCAL_DRAM	0x060040	0,1	miss the LLC and the data returned from local dram
+Null	LLC_MISS.ANY_DRAM	0x067fc0	0,1	miss the LLC and the data returned from local or remote dram
diff --git a/x86data/perfmon_data/SNB/SandyBridge_matrix_bit_definitions_V12.json b/x86data/perfmon_data/SNB/SandyBridge_matrix_bit_definitions_V12.json
new file mode 100644
index 0000000..42f185d
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_matrix_bit_definitions_V12.json
@@ -0,0 +1,254 @@
+[
+  {
+    "BitName": "DEMAND_DATA_RD",
+    "BitIndex": "0",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_RFO",
+    "BitIndex": "1",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "DEMAND_CODE_RD",
+    "BitIndex": "2",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "COREWB",
+    "BitIndex": "3",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_DATA_RD",
+    "BitIndex": "4",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_RFO",
+    "BitIndex": "5",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_L2_CODE_RD",
+    "BitIndex": "6",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_DATA_RD",
+    "BitIndex": "7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_RFO",
+    "BitIndex": "8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "PF_LLC_CODE_RD",
+    "BitIndex": "9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "OTHER",
+    "BitIndex": "15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_DATA_RD",
+    "BitIndex": "4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_RFO",
+    "BitIndex": "5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_PF_CODE_RD",
+    "BitIndex": "6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_DATA_RD",
+    "BitIndex": "0,4,7",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_RFO",
+    "BitIndex": "1,5,8",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_CODE_RD",
+    "BitIndex": "2,6,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_READS",
+    "BitIndex": "0,1,2,4,5,6,7,8,9",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ALL_REQUESTS",
+    "BitIndex": "0,1,2,3,4,5,6,7,8,9,10,11,15",
+    "Type": "1",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_RESPONSE",
+    "BitIndex": "16",
+    "Type": "2",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SUPPLIER_NONE",
+    "BitIndex": "17",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_M",
+    "BitIndex": "18",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_E",
+    "BitIndex": "19",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_S",
+    "BitIndex": "20",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT_F",
+    "BitIndex": "21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "LLC_HIT",
+    "BitIndex": "18,19,20,21",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_LOCAL_DRAM",
+    "BitIndex": "22",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "L3_MISS_REMOTE_DRAM",
+    "BitIndex": "22,23,24,25,26,27,28,29,30",
+    "Type": "3",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NONE",
+    "BitIndex": "31",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NOT_NEEDED",
+    "BitIndex": "32",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_MISS",
+    "BitIndex": "33",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_NO_FWD",
+    "BitIndex": "34",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_HIT_WITH_FWD",
+    "BitIndex": "35",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "18,19,20,21"
+  },
+  {
+    "BitName": "SNOOP_HITM",
+    "BitIndex": "36",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "SNOOP_NON_DRAM",
+    "BitIndex": "37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  },
+  {
+    "BitName": "ANY_SNOOP",
+    "BitIndex": "31,32,33,34,35,36,37",
+    "Type": "4",
+    "MATRIX_REG": "0,1",
+    "BitsNotCombinedWith": "Null"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SNB/SandyBridge_matrix_bit_definitions_V12.tsv b/x86data/perfmon_data/SNB/SandyBridge_matrix_bit_definitions_V12.tsv
new file mode 100644
index 0000000..f0af84f
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_matrix_bit_definitions_V12.tsv
@@ -0,0 +1,40 @@
+# Performance Monitoring Events for the Second Generation Intel Core Processors Based on the Sandy Bridge Microarchitecture - V12
+# 7/28/2015 3:10:25 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+BitName	BitIndex	Type	MATRIX_REG	BitsNotCombinedWith
+DEMAND_DATA_RD	0	1	0,1	Null
+DEMAND_RFO	1	1	0,1	Null
+DEMAND_CODE_RD	2	1	0,1	Null
+COREWB	3	1	0,1	Null
+PF_L2_DATA_RD	4	1	0,1	Null
+PF_L2_RFO	5	1	0,1	Null
+PF_L2_CODE_RD	6	1	0,1	Null
+PF_LLC_DATA_RD	7	1	0,1	Null
+PF_LLC_RFO	8	1	0,1	Null
+PF_LLC_CODE_RD	9	1	0,1	Null
+OTHER	15	1	0,1	Null
+ALL_PF_DATA_RD	4,7	1	0,1	Null
+ALL_PF_RFO	5,8	1	0,1	Null
+ALL_PF_CODE_RD	6,9	1	0,1	Null
+ALL_DATA_RD	0,4,7	1	0,1	Null
+ALL_RFO	1,5,8	1	0,1	Null
+ALL_CODE_RD	2,6,9	1	0,1	Null
+ALL_READS	0,1,2,4,5,6,7,8,9	1	0,1	Null
+ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	0,1	Null
+ANY_RESPONSE	16	2	0,1	Null
+SUPPLIER_NONE	17	3	0,1	Null
+LLC_HIT_M	18	3	0,1	Null
+LLC_HIT_E	19	3	0,1	Null
+LLC_HIT_S	20	3	0,1	Null
+LLC_HIT_F	21	3	0,1	Null
+LLC_HIT	18,19,20,21	3	0,1	Null
+L3_MISS_LOCAL_DRAM	22	3	0,1	Null
+L3_MISS_REMOTE_DRAM	22,23,24,25,26,27,28,29,30	3	0,1	Null
+SNOOP_NONE	31	4	0,1	Null
+SNOOP_NOT_NEEDED	32	4	0,1	Null
+SNOOP_MISS	33	4	0,1	Null
+SNOOP_HIT_NO_FWD	34	4	0,1	Null
+SNOOP_HIT_WITH_FWD	35	4	0,1	18,19,20,21
+SNOOP_HITM	36	4	0,1	Null
+SNOOP_NON_DRAM	37	4	0,1	Null
+ANY_SNOOP	31,32,33,34,35,36,37	4	0,1	Null
diff --git a/x86data/perfmon_data/SNB/SandyBridge_offcore_V12.tsv b/x86data/perfmon_data/SNB/SandyBridge_offcore_V12.tsv
new file mode 100644
index 0000000..1a06343
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_offcore_V12.tsv
@@ -0,0 +1,246 @@
+# Performance Monitoring Events for the Second Generation Intel Core Processors Based on the Sandy Bridge Microarchitecture - V12
+# 7/28/2015 3:10:24 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS_0	Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM_0	Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400244	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand & prefetch data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM_0	Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400091	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0240	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0240	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0240	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0240	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0240	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM_0	Counts all prefetch code reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400240	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM_0	Counts all prefetch data reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400090	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch RFOs that hit in the LLC	0	0	100003	0x1a6	0x3f803c0120	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0120	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0120	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0120	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS_0	Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0120	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM_0	Counts all prefetch RFOs that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400120	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE_0	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC	0	0	100003	0x1a6	0x3f803c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE_0	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED_0	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS_0	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c03f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM_0	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x3004003f7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCE.ANY_RESPONSE_0	Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC 	0	0	100003	0x1a6	0x103F7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE_0	Counts all demand & prefetch RFOs that hit in the LLC	0	0	100003	0x1a6	0x3f803c0122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE_0	Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS_0	Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM_0	Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_0	Counts all writebacks from the core to the LLC	0	0	100003	0x1a6	0x10008	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS_0	Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM_0	Counts demand code reads that miss the LLC and the data returned from dram	0	0	100003	0x1a6	0x300400004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all demand data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM_0	Counts demand data reads that miss the LLC and the data returned from dram	0	0	100003	0x1a6	0x300400001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE_0	Counts all demand data writes (RFOs) that hit in the LLC	0	0	100003	0x1a6	0x3f803c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_0	Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED_0	Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS_0	Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM_0	Counts demand data writes (RFOs) that miss the LLC and the data returned from dram	0	0	100003	0x1a6	0x300400002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.OTHER.ANY_RESPONSE_0	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches	0	0	100003	0x1a6	0x18000	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.OTHER.LRU_HINTS_0	Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches	0	0	100003	0x1a6	0x803c8000	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC_0	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses	0	0	100003	0x1a6	0x2380408000	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to L2) code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM_0	Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400040	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to L2) data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM_0	Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram	0	0	100003	0x1a6	0x300400010	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to L2) RFOs that hit in the LLC	0	0	100003	0x1a6	0x3f803c0020	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0020	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0020	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0020	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0020	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM_0	Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400020	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM_0	Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400200	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC	0	0	100003	0x1a6	0x3f803c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM_0	Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400080	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE_0	Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC	0	0	100003	0x1a6	0x3f803c0100	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0	Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0	0	100003	0x1a6	0x4003c0100	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE_0	Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0	0	100003	0x1a6	0x10003c0100	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED_0	Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0	0	100003	0x1a6	0x1003c0100	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS_0	Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response	0	0	100003	0x1a6	0x2003c0100	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM_0	Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram	0	0	100003	0x1a6	0x300400100	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_0	Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address 	0	0	100003	0x1a6	0x10400	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_0	Counts non-temporal stores	0	0	100003	0x1a6	0x10800	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand & prefetch code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand & prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS_1	Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM_1	Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400244	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand & prefetch data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM_1	Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400091	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0240	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0240	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0240	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0240	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0240	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM_1	Counts all prefetch code reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400240	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM_1	Counts all prefetch data reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400090	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch RFOs that hit in the LLC	3	3	100003	0x1a7	0x3f803c0120	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0120	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0120	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0120	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS_1	Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0120	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM_1	Counts all prefetch RFOs that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400120	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE_1	Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC	3	3	100003	0x1a7	0x3f803c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE_1	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED_1	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS_1	Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c03f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM_1	Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x3004003f7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCE_ANY.ANY_RESPONSE_1	Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC 	3	3	100003	0x1a7	0x103F7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE_1	Counts all demand & prefetch RFOs that hit in the LLC	3	3	100003	0x1a7	0x3f803c0122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE_1	Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS_1	Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM_1	Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_1	tbd	3	3	100003	0x1a7	0x10008	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS_1	Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM_1	Counts demand code reads that miss the LLC and the data returned from dram	3	3	100003	0x1a7	0x300400004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all demand data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM_1	Counts demand data reads that miss the LLC and the data returned from dram	3	3	100003	0x1a7	0x300400001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE_1	Counts all demand data writes (RFOs) that hit in the LLC	3	3	100003	0x1a7	0x3f803c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_1	Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED_1	Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS_1	Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM_1	Counts demand data writes (RFOs) that miss the LLC and the data returned from dram	3	3	100003	0x1a7	0x300400002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.ANY_RESPONSE_1	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches	3	3	100003	0x1a7	0x18000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.LRU_HINTS_1	Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches	3	3	100003	0x1a7	0x803c8000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC_1	Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses	3	3	100003	0x1a7	0x2380408000	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to L2) code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM_1	Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400040	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to L2) data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM_1	Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram	3	3	100003	0x1a7	0x300400010	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to L2) RFOs that hit in the LLC	3	3	100003	0x1a7	0x3f803c0020	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0020	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0020	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0020	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0020	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM_1	Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400020	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM_1	Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400200	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC	3	3	100003	0x1a7	0x3f803c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM_1	Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400080	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE_1	Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC	3	3	100003	0x1a7	0x3f803c0100	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1	Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded	3	3	100003	0x1a7	0x4003c0100	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE_1	Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	3	3	100003	0x1a7	0x10003c0100	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED_1	Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	3	3	100003	0x1a7	0x1003c0100	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS_1	Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response	3	3	100003	0x1a7	0x2003c0100	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM_1	Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram	3	3	100003	0x1a7	0x300400100	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_1	Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address 	3	3	100003	0x1a7	0x10400	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_1	Counts non-temporal stores	3	3	100003	0x1a7	0x10800	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE_0	Counts all demand data reads 	0	0	100003	0x1A6	0x00010001	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE_0	Counts all demand rfo's 	0	0	100003	0x1A6	0x00010002	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE_0	Counts all demand code reads	0	0	100003	0x1A6	0x00010004	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE_0	Counts all demand & prefetch data reads	0	0	100003	0x1A6	0x000105B3	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE_0	Counts all demand & prefetch prefetch RFOs 	0	0	100003	0x1A6	0x00010122	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE_0	Counts all data/code/rfo references (demand & prefetch) 	0	0	100003	0x1A6	0x000107F7	0	0	0	0	0	0	0	null
+0xB7	0x01	OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM_0	Counts LLC replacements	0	0	100003	0x1A6	0x6004001b3	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE_1	Counts all demand data reads 	3	3	100003	0x1A7	0x00010001	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE_1	Counts all demand rfo's 	3	3	100003	0x1A7	0x00010002	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE_1	Counts all demand code reads	3	3	100003	0x1A7	0x00010004	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE_1	Counts all demand & prefetch data reads	3	3	100003	0x1A7	0x000105B3	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE_1	Counts all demand & prefetch prefetch RFOs 	3	3	100003	0x1A7	0x00010122	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE_1	Counts all data/code/rfo references (demand & prefetch) 	3	3	100003	0x1A7	0x000107F7	0	0	0	0	0	0	0	null
+0xBB	0x01	OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM_1	Counts LLC replacements	3	3	100003	0x1A7	0x6004001b3	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM_0	 REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	0	0	100003	0x1A6	0x1f80408fff	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM_1	 REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	3	3	100003	0x1A7	0x1f80408fff	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE_0	 REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE	0	0	100003	0x1A6	0x10433	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE_1	 REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE	3	3	100003	0x1A7	0x10433	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT_0	 REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT	0	0	100003	0x1A6	0x17004001b3	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT_1	 REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT	3	3	100003	0x1A7	0x17004001b3	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM_0	 REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	0	0	100003	0x1A6	0x1f80400004	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM_1	 REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	3	3	100003	0x1A7	0x1f80400004	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM_0	 REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM	0	0	100003	0x1A6	0x1000040002	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM_1	 REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM	3	3	100003	0x1A7	0x1000040002	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM_0	 REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	0	0	100003	0x1A6	0x1f80400010	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM_1	 REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	3	3	100003	0x1A7	0x1f80400010	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE_0	 REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE	0	0	100003	0x1A6	0x10040	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE_1	 REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE	3	3	100003	0x1A7	0x10040	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM_0	 REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	0	0	100003	0x1A6	0x1f80400040	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM_1	 REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	3	3	100003	0x1A7	0x1f80400040	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE_0	 REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE	0	0	100003	0x1A6	0x10080	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE_1	 REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE	3	3	100003	0x1A7	0x10080	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM_0	 REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	0	0	100003	0x1A6	0x1f80400080	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM_1	 REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	3	3	100003	0x1A7	0x1f80400080	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE_0	 REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE	0	0	100003	0x1A6	0x10200	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE_1	 REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE	3	3	100003	0x1A7	0x10200	0	0	0	0	0	0	0	null
+0xB7	0x1	OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM_0	 REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	0	0	100003	0x1A6	0x1f80400200	0	0	0	0	0	0	0	null
+0xBB	0x1	OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM_1	 REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM	3	3	100003	0x1A7	0x1f80400200	0	0	0	0	0	0	0	null
diff --git a/x86data/perfmon_data/SNB/SandyBridge_uncore_V12.json b/x86data/perfmon_data/SNB/SandyBridge_uncore_V12.json
new file mode 100644
index 0000000..a3cef94
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_uncore_V12.json
@@ -0,0 +1,314 @@
+[
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x01",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS",
+    "BriefDescription": "A snoop misses in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x02",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL",
+    "BriefDescription": "A snoop invalidates a non-modified line in some processor core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x04",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT",
+    "BriefDescription": "A snoop hits a non-modified line in some processor core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x08",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM",
+    "BriefDescription": "A snoop hits a modified line in some processor core.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x10",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M",
+    "BriefDescription": "A snoop invalidates a modified line in some processor core",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x20",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER",
+    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x40",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER",
+    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x22",
+    "UMask": "0x80",
+    "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER",
+    "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x01",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.M",
+    "BriefDescription": "LLC lookup request that access cache and found line in M-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x02",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.E",
+    "BriefDescription": "LLC lookup request that access cache and found line in E-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x04",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.S",
+    "BriefDescription": "LLC lookup request that access cache and found line in S-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x08",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.I",
+    "BriefDescription": "LLC lookup request that access cache and found line in I-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x10",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER",
+    "BriefDescription": "Filter on processor core initiated cacheable read requests.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x20",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER",
+    "BriefDescription": "Filter on processor core initiated cacheable write requests.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x40",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER",
+    "BriefDescription": "Filter on external snoop requests.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x80",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER",
+    "BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+    "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x81",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+    "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x81",
+    "UMask": "0x20",
+    "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
+    "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x81",
+    "UMask": "0x80",
+    "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
+    "BriefDescription": "Counts the number of LLC evictions allocated.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x83",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
+    "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x84",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+    "BriefDescription": "Number of requests allocated in Coherency Tracker.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
+    "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "1",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x80",
+    "UMask": "0x01",
+    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
+    "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
+    "PublicDescription": "tbd",
+    "Counter": "0,1",
+    "CounterMask": "10",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "ARB",
+    "EventCode": "0x0",
+    "UMask": "0x01",
+    "EventName": "UNC_CLOCK.SOCKET",
+    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
+    "PublicDescription": "tbd",
+    "Counter": "Fixed",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  },
+  {
+    "Unit": "CBO",
+    "EventCode": "0x34",
+    "UMask": "0x06",
+    "EventName": "UNC_CBO_CACHE_LOOKUP.ES",
+    "BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.",
+    "PublicDescription": "tbd",
+    "Counter": "0",
+    "CounterMask": "0",
+    "Invert": "0",
+    "EdgeDetect": "0"
+  }
+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/SNB/SandyBridge_uncore_V12.tsv b/x86data/perfmon_data/SNB/SandyBridge_uncore_V12.tsv
new file mode 100644
index 0000000..6bfdc3f
--- /dev/null
+++ b/x86data/perfmon_data/SNB/SandyBridge_uncore_V12.tsv
@@ -0,0 +1,30 @@
+# Performance Monitoring Events for the Second Generation Intel Core Processors Based on the Sandy Bridge Microarchitecture - V12
+# 7/28/2015 3:10:24 PM
+# Copyright (c) 2007 - 2014 Intel Corporation. All rights reserved.
+Unit	EventCode	UMask	EventName	Description	Counter	CounterMask	Invert	EdgeDetect
+CBO	0x22	0x01	UNC_CBO_XSNP_RESPONSE.MISS	A snoop misses in some processor core.	0,1	0	0	0
+CBO	0x22	0x02	UNC_CBO_XSNP_RESPONSE.INVAL	A snoop invalidates a non-modified line in some processor core	0,1	0	0	0
+CBO	0x22	0x04	UNC_CBO_XSNP_RESPONSE.HIT	A snoop hits a non-modified line in some processor core	0,1	0	0	0
+CBO	0x22	0x08	UNC_CBO_XSNP_RESPONSE.HITM	A snoop hits a modified line in some processor core.	0,1	0	0	0
+CBO	0x22	0x10	UNC_CBO_XSNP_RESPONSE.INVAL_M	A snoop invalidates a modified line in some processor core	0,1	0	0	0
+CBO	0x22	0x20	UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER	Filter on cross-core snoops initiated by this Cbox due to external snoop request.	0,1	0	0	0
+CBO	0x22	0x40	UNC_CBO_XSNP_RESPONSE.XCORE_FILTER	Filter on cross-core snoops initiated by this Cbox due to processor core memory request.	0,1	0	0	0
+CBO	0x22	0x80	UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER	Filter on cross-core snoops initiated by this Cbox due to LLC eviction.	0,1	0	0	0
+CBO	0x34	0x01	UNC_CBO_CACHE_LOOKUP.M	LLC lookup request that access cache and found line in M-state.	0,1	0	0	0
+CBO	0x34	0x02	UNC_CBO_CACHE_LOOKUP.E	LLC lookup request that access cache and found line in E-state.	0,1	0	0	0
+CBO	0x34	0x04	UNC_CBO_CACHE_LOOKUP.S	LLC lookup request that access cache and found line in S-state.	0,1	0	0	0
+CBO	0x34	0x08	UNC_CBO_CACHE_LOOKUP.I	LLC lookup request that access cache and found line in I-state.	0,1	0	0	0
+CBO	0x34	0x10	UNC_CBO_CACHE_LOOKUP.READ_FILTER	Filter on processor core initiated cacheable read requests.	0,1	0	0	0
+CBO	0x34	0x20	UNC_CBO_CACHE_LOOKUP.WRITE_FILTER	Filter on processor core initiated cacheable write requests.	0,1	0	0	0
+CBO	0x34	0x40	UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER	Filter on external snoop requests.	0,1	0	0	0
+CBO	0x34	0x80	UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER	Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.	0,1	0	0	0
+ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.ALL	Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.	0	0	0	0
+ARB	0x81	0x01	UNC_ARB_TRK_REQUESTS.ALL	Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.	0,1	0	0	0
+ARB	0x81	0x20	UNC_ARB_TRK_REQUESTS.WRITES	Counts the number of allocated write entries, include full, partial, and LLC evictions.	0,1	0	0	0
+ARB	0x81	0x80	UNC_ARB_TRK_REQUESTS.EVICTIONS	Counts the number of LLC evictions allocated.	0,1	0	0	0
+ARB	0x83	0x01	UNC_ARB_COH_TRK_OCCUPANCY.ALL	Cycles weighted by number of requests pending in Coherency Tracker.	0	0	0	0
+ARB	0x84	0x01	UNC_ARB_COH_TRK_REQUESTS.ALL	Number of requests allocated in Coherency Tracker.	0,1	0	0	0
+ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST	Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.	0,1	1	0	0
+ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL	Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.	0,1	10	0	0
+ARB	0x0	0x01	UNC_CLOCK.SOCKET	This 48-bit fixed counter counts the UCLK cycles	Fixed	0	0	0
+CBO	0x34	0x06	UNC_CBO_CACHE_LOOKUP.ES	LLC lookup request that access cache and found line in E-state or S-state.	0	0	0	0
diff --git a/x86data/perfmon_data/TMAM_Metrics.csv b/x86data/perfmon_data/TMAM_Metrics.csv
new file mode 100644
index 0000000..3c820a4
--- /dev/null
+++ b/x86data/perfmon_data/TMAM_Metrics.csv
@@ -0,0 +1,77 @@
+TMAM,Version,3.01,,,Core,,,,,,,,,,,,
+,,,,,,Server,,Server,,Server,,Server,,,,,
+Key,Level1,Level2,Level3,Level4,SKL,BDX,BDW/BDW-DE,HSX,HSW,IVT,IVB,JKT/SNB-EP,SNB,Locate-with,Count Domain,Metric Description,Threshold
+FE,Frontend_Bound,,,,,,,,,,,,IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS,SKL ? FRONTEND_RETIRED.LATENCY_GE_8_PS : N/A,Slots,"This category represents slots fraction where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend, a branch predictor predicts the next address to fetch, cache-lines are fetched from the memory subsystem, parsed into instructions, and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example, stalls due to instruction-cache misses would be categorized under Frontend Bound.",> 0.2
+FE,,Frontend_Latency,,,,,#Pipeline_Width * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS,,,,,,#Pipeline_Width * #Frontend_Latency_Cycles / SLOTS,SKL ? FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_32_PS : RS_EVENTS.EMPTY_END,Slots,"This metric represents slots fraction the CPU was stalled due to Frontend latency issues.  For example, instruction-cache misses, iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases, the Frontend eventually delivers no uops for some period.",> 0.15 & P
+FE,,,ICache_Misses,,ICACHE_16B.IFDATA_STALL / CLKS,,,,ICACHE.IFDATA_STALL  / CLKS,,ICACHE.IFETCH_STALL / CLKS - ITLB_Misses,,N/A,SKL ? FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS : N/A,Clocks,This metric represents cycles fraction the CPU was stalled due to instruction cache misses.,> 0.05 & P
+FE,,,ITLB_Misses,,ICACHE_64B.IFTAG_STALL / CLKS,,,,,,,,#ITLB_Miss_Cycles / CLKS,SKL ? FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS : ITLB_MISSES.WALK_COMPLETED,Clocks,This metric represents cycles fraction the CPU was stalled due to instruction TLB misses.,> 0.05 & P
+FE,,,Branch_Resteers,,INT_MISC.CLEAR_RESTEER_CYCLES / CLKS,,,,,,,,#Avg_RS_Empty_Period_Clears * ( BR_MISP_RETIRED.ALL_BRANCHES_PS + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CLKS,BR_MISP_RETIRED.ALL_BRANCHES_PS,Clocks,"This metric represents cycles fraction the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path, following all sorts of miss-predicted branches. For example, branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",> 0.05 & P; $issueB; ~overlap
+FE,,,DSB_Switches,,,,,,,,,,DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS,SKL ? FRONTEND_RETIRED.DSB_MISS_PS : N/A,Clocks,"This metric represents cycles fraction the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache, introduced with the Sandy Bridge microarchitecture) pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties. This metric estimates when such penalty can be exposed. Optimizing for better DSB hit rate may be considered.",> 0.05 & P
+FE,,,MS_Switches,,,,,,,,,,#MS_Switches_Cost * IDQ.MS_SWITCHES / CLKS,IDQ.MS_SWITCHES,Clocks,"This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB or MITE pipelines. Certain operations cannot be handled natively by the execution pipeline, and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID, or uncommon conditions like Floating Point Assists when dealing with Denormals.",> 0.05 & P; $issueMS
+FE,,Frontend_Bandwidth,,,,,,,,,,,Frontend_Bound - Frontend_Latency,SKL ? FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS : N/A,Slots,"This metric represents slots fraction the CPU was stalled due to Frontend bandwidth issues.  For example, inefficiencies at the instruction decoders, or code restrictions for caching in the DSB (decoded uops cache) are categorized under Frontend Bandwidth. In such cases, the Frontend typically delivers non-optimal amount of uops to the Backend (less than four).",> 0.1 & (IPC > 2.0) & P
+BAD,Bad_Speculation,,,,,,,,,,,,( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + #Pipeline_Width * #Recovery_Cycles ) / SLOTS,INT_MISC.RECOVERY_CYCLES,Slots,"This category represents slots fraction wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example, wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",> 0.1; $issueB
+BAD,,Branch_Mispredicts,,,,,,,,,,,#Mispred_Clears_Fraction * Bad_Speculation,BR_MISP_RETIRED.ALL_BRANCHES_PS,Slots,"This metric represents slots fraction the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path, or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",> 0.05 & P
+BAD,,Machine_Clears,,,,,,,,,,,Bad_Speculation - Branch_Mispredicts,MACHINE_CLEARS.COUNT,Slots,"This metric represents slots fraction the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear, or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example, this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",> 0.05 & P
+BE,Backend_Bound,,,,,,,,,,,,1 - ( Frontend_Bound + Bad_Speculation + Retiring ),,Slots,"This category represents slots fraction where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units, and once completed these uops get retired according to program order. For example, stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",> 0.2
+BE/Mem,,Memory_Bound,,,,,,,,,,,#Memory_Bound_Fraction * Backend_Bound,,Slots,"This metric represents slots fraction the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates slots fraction where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation, in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",> 0.2 & P
+BE/Mem,,,L1_Bound,,,,( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CLKS,,,,( #STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_PENDING ) / CLKS,,N/A,SKL ? MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS : MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS,Clocks,"This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However, in certain cases like loads blocked on older stores, a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls, while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",(> 0.07 & P) | DTLB_Load
+BE/Mem,,,,DTLB_Load,( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_ACTIVE ) / CLKS,,( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION:c1 ) / CLKS,,,,,,( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION ) / CLKS,SKL ? MEM_INST_RETIRED.STLB_MISS_LOADS_PS : MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS,Clocks,This metric represents cycles fraction where the TLB was missed by load instructions. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric estimates the performance penalty paid by demand loads when missing the first-level data TLB (DTLB). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.,> 0.1 & P
+BE/Mem,,,L2_Bound,,,,( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CLKS,,,,( CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING ) / CLKS,,N/A,SKL ? MEM_LOAD_RETIRED.L2_HIT_PS : MEM_LOAD_UOPS_RETIRED.L2_HIT_PS,Clocks,This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.,> 0.03 & P
+BE/Mem,,,L3_Bound,,( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CLKS,,#Mem_L3_Hit_Fraction * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS,,,,,,#Mem_L3_Hit_Fraction * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS,SKL ? MEM_LOAD_RETIRED.L3_HIT_PS : IVB/IVT/SNB/JKT ? MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS : MEM_LOAD_UOPS_RETIRED.L3_HIT_PS,Clocks,This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.,> 0.1 & P
+BE/Mem,,,MEM_Bound,,CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS,,(1 - #Mem_L3_Hit_Fraction) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS,,,,,,(1 - #Mem_L3_Hit_Fraction) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS,SKL ? MEM_LOAD_RETIRED.L3_MISS_PS : IVB/IVT/JKT ? MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS : SNB ? MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS : MEM_LOAD_UOPS_RETIRED.L3_MISS_PS,Clocks,This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.,> 0.1 & P
+BE/Mem,,,,MEM_Bandwidth,#ORO_L3M_Demand_DRD_C6 / CLKS,,,,,,,,#ORO_Demand_DRD_C6 / CLKS,,Clocks,This metric estimates cycles fraction where the performance was likely hurt due to approaching bandwidth limits of external main (DRAM).  This metric does not aggregate requests from other threads/cores/sockets (see Uncore counters for that).,> 0.1 & P
+BE/Mem,,,,MEM_Latency,( #ORO_L3M_Demand_DRD_C1 - #ORO_L3M_Demand_DRD_C6 ) / CLKS,,,,,,,,( #ORO_Demand_DRD_C1 - #ORO_Demand_DRD_C6 ) / CLKS,,Clocks,This metric estimates cycles fraction where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other threads/cores/sockets (see Uncore counters for that).,> 0.1 & P
+BE/Mem,,,Stores_Bound,,EXE_ACTIVITY.BOUND_ON_STORES / CLKS,,( RESOURCE_STALLS.SB -  CYCLE_ACTIVITY.STALLS_MEM_ANY ) / CLKS,,,,,,( RESOURCE_STALLS.SB -  #STALLS_MEM_ANY ) / CLKS,SKL ? MEM_INST_RETIRED.ALL_STORES_PS : MEM_UOPS_RETIRED.ALL_STORES_PS,Clocks,This metric estimates how often CPU was stalled  due to store memory accesses. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should any of these cases be a bottleneck.,> 0.2 & P
+BE/Core,,Core_Bound,,,,,,,,,,,Backend_Bound - Memory_Bound,,Slots,"This metric represents slots fraction where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources, or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource, certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",> 0.2 & P
+BE/Core,,,Divider,,ARITH.DIVIDER_ACTIVE / CLKS,,ARITH.FPU_DIV_ACTIVE / CORE_CLKS,,10 * ARITH.DIVIDER_UOPS / CORE_CLKS,,,,ARITH.FPU_DIV_ACTIVE / CORE_CLKS,SKL ? ARITH.DIVIDER_ACTIVE : HSW/HSX ? ARITH.DIVIDER_UOPS : ARITH.FPU_DIV_ACTIVE,CoreClocks,"This metric represents cycles fraction where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition, subtraction, or multiplication.",> 0.2 & P
+BE/Core,,,Ports_Utilization,,( #Backend_Bound_Cycles - CYCLE_ACTIVITY.STALLS_MEM_ANY - EXE_ACTIVITY.BOUND_ON_STORES ) / CLKS,,( #Backend_Bound_Cycles - RESOURCE_STALLS.SB -  CYCLE_ACTIVITY.STALLS_MEM_ANY ) / CLKS,,,,,,( #Backend_Bound_Cycles - RESOURCE_STALLS.SB -  #STALLS_MEM_ANY ) / CLKS,,Clocks,"This metric estimates cycles fraction the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example, when there are too many multiply operations.",> 0.2 & P
+RET,Retiring,,,,,,,,,,,,UOPS_RETIRED.RETIRE_SLOTS / SLOTS,,Slots,"This category represents slots fraction utilized by useful work i.e. allocated uops that eventually get retired. Ideally, all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved.  Maximizing Retiring typically increases the Instruction-Per-Cycle metric.
+Note that a high Retiring value does not necessary mean there is no room for more performance.  For example, Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. ",(> 0.7 | Microcode_Sequencer)
+RET,,Base,,,,,,,,,,,Retiring - Microcode_Sequencer,INST_RETIRED.PREC_DIST,Slots,"This metric represents slots fraction where the CPU was retiring regular uops (ones not originated from the microcode-sequencer). This correlates with total number of instructions used by the program. A uops-per-instruction ratio of 1 should be expected. While this is the most desirable of the top 4 categories, high values does not necessarily mean there no room for performance optimizations.",> 0.6 & P
+RET,,,FP_Arith,,,,FP_Scalar + FP_Vector,,N/A,,,,FP_Scalar + FP_Vector,,Uops,This metric represents overall arithmetic floating-point (FP) uops fraction the CPU has executed (retired),> 0.2 & P
+RET,,,,FP_Scalar,,,( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) / UOPS_RETIRED.RETIRE_SLOTS,,N/A,,( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) / UOPS_EXECUTED.THREAD,,( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) / UOPS_DISPATCHED.THREAD,,Uops,This metric represents arithmetic floating-point (FP) scalar uops fraction the CPU has executed (retired).,> 0.1 & P
+RET,,,,FP_Vector,,,( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / UOPS_RETIRED.RETIRE_SLOTS,,N/A,,( FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) / UOPS_EXECUTED.THREAD,,( FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) / UOPS_DISPATCHED.THREAD,,Uops,This metric represents arithmetic floating-point (FP) vector uops fraction the CPU has executed (retired) aggregated across all vector widths.,> 0.2 & P
+RET,,,Other,,,,1 - FP_Arith,,N/A,,,,1 - FP_Arith,,Uops,"This metric represents non-floating-point (FP) uop fraction the CPU has executed. If you application has no FP operations and performs with decent IPC (Instructions Per Cycle), this node will likely be biggest fraction.",> 0.3 & P
+RET,,Microcode_Sequencer,,,,,,,,,,,#Retire_Uop_Fraction * IDQ.MS_UOPS / SLOTS,IDQ.MS_UOPS,Slots,"This metric represents slots fraction the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings, or CPUID), or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",> 0.05; $issueMS
+Info,IPC,,,,,,,,,,,,INST_RETIRED.ANY / CLKS,,Metric/5,Instructions Per Cycle (per logical thread),
+SW_Info,CPI,,,,,,,,,,,,1/IPC,,Metric,Cycles Per Instruction (threaded),
+Info,CoreIPC,,,,,,,,,,,,INST_RETIRED.ANY / CORE_CLKS,,CoreMetric/5,Instructions Per Cycle (per physical core),
+Info,UPI,,,,,,,,,,,,UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY,,Metric/2,Uops Per Instruction,
+Info,IFetch_Line_Utilization,,,,"min( 1 , UOPS_ISSUED.ANY / (UPI * 64 * ( ICACHE_64B.IFTAG_HIT + ICACHE_64B.IFTAG_MISS ) / 4.1) )",,,,,,,,"min( 1 , UOPS_ISSUED.ANY / ( UPI * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4) )",,Metric/1,Rough Estimation of fraction of fetched lines bytes consumed by program instructions,< 0.5
+Info,DSB_Coverage,,,,,,,,,,,,( IDQ.DSB_UOPS + LSD.UOPS ) / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ),,Metric/1,Fraction of Uops delivered by the DSB (decoded instructions cache),
+Info,ILP,,,,,,UOPS_EXECUTED.THREAD / #Execute_Cycles,,( UOPS_EXECUTED.CORE / 2 / #Execute_Cycles ) if #SMT_on else UOPS_EXECUTED.CORE / #Execute_Cycles,,UOPS_EXECUTED.THREAD / #Execute_Cycles,,UOPS_DISPATCHED.THREAD / #Execute_Cycles,,Metric/10,Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed),
+SW_Info,GFLOPs,,,,,,#FLOP_Count / #OneBillion / #DurationTimeInSeconds#,,N/A ,,,,#FLOP_Count / #OneBillion / #DurationTimeInSeconds#,,Metric/100,Giga Floating Point Operations Per Second,
+SW_Info,CPU_Utilization,,,,,,,,,,,,CPU_CLK_UNHALTED.REF_TSC / TSC,,Metric/100,Average CPU Utilization,
+SW_Info,Turbo_Utilization,,,,,,,,,,,,CLKS / CPU_CLK_UNHALTED.REF_TSC,,CoreMetric/10,Average Frequency Utilization relative nominal frequency,
+SW_Info,SMT_2T_Utilization,,,,,,,,,,,,1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0,,Metric/1,Fraction of cycles where both hardware threads were active,
+SW_Info,Kernel_Utilization,,,,,,,,,,,,CPU_CLK_UNHALTED.REF_TSC:sup / CPU_CLK_UNHALTED.REF_TSC,,Metric/1,Fraction of cycles spent in Kernel mode,< 0.1
+SW_Info,MEM_BW_GBs,,,,,,,,,,,64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / #OneMillion / #DurationTimeInSeconds# / 1000,64 * ( UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL ) / #OneMillion / #DurationTimeInSeconds# / 1000,,Metric/100,Average external Memory Bandwidth Use for reads and writes [GB / sec],
+SW_Info,MUX,,,,,,,,,,,,CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD,,Clocks,PerfMon Event Multiplexing accuracy indicator,
+Info,CLKS,,,,,,,,,,,,CPU_CLK_UNHALTED.THREAD,,Count,Per-thread actual clocks when the thread is active,
+Info,CORE_CLKS,,,,,,,,,,,,( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CLKS,,Count,Core actual clocks when any thread is active on the physical core,
+SW_Info,Time,,,,,,,,,,,,#DurationTimeInSeconds#,,Count,Run duration time in seconds,< 1
+Aux,#FLOP_Count,,,,,,( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2* FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4*( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8* FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ),,N/A,,,,( 1*( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2* FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4*( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8* SIMD_FP_256.PACKED_SINGLE ),,Count,Floating Point computational (arithmetic) Operations Count,
+Aux,#Recovery_Cycles,,,,,,,,,,,,( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES,,Count,,
+Aux,#Execute_Cycles,,,,( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1,,( UOPS_EXECUTED.CORE:c1 / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC,,( UOPS_EXECUTED.CORE:c1 / 2) if #SMT_on else UOPS_EXECUTED.CORE:c1,,( UOPS_EXECUTED.CORE:c1 / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC,,( UOPS_DISPATCHED.CORE:c1 / 2) if #SMT_on else UOPS_DISPATCHED.CORE:c1,,Count,,
+Aux,#ITLB_Miss_Cycles,,,,N/A,,( #Mem_STLB_Hit_Cost * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION:c1 ),,,,,,( #Mem_STLB_Hit_Cost * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION ),,Count,,
+Aux,#Frontend_Latency_Cycles,,,,,,N/A,,,,,,"min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE )",,Count,,
+Aux,#STALLS_MEM_ANY,,,,,,N/A,,,,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING )",,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_L1D_PENDING )",,Count,,
+Aux,#STALLS_TOTAL,,,,,,N/A,,,,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE )",,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_DISPATCH )",,Count,,
+Aux,#ORO_Demand_DRD_C1,,,,,,,,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD )",,Count,,
+Aux,#ORO_Demand_DRD_C6,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6 )",,,,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c6 )",,Count,,
+Aux,#ORO_L3M_Demand_DRD_C1,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD )",,,,,,,,N/A,,Count,,
+Aux,#ORO_L3M_Demand_DRD_C6,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6 )",,,,,,,,N/A,,Count,,
+Aux,#Few_Uops_Executed_Threshold,,,,EXE_ACTIVITY.2_PORTS_UTIL if ( IPC > 1.25 ) else 0,,UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( IPC > 1.25 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC,,UOPS_EXECUTED.CORE:c3 if ( IPC > 1.25 ) else UOPS_EXECUTED.CORE:c2,,UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( IPC > 1.25 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC,,UOPS_DISPATCHED.THREAD:c3 if ( IPC > 1.25 ) else UOPS_DISPATCHED.THREAD:c2,,Count,,
+Aux,#Backend_Bound_Cycles,,,,( EXE_ACTIVITY.EXE_BOUND_0_PORTS + EXE_ACTIVITY.1_PORTS_UTIL + #Few_Uops_Executed_Threshold ) + ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) ,,( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - #Few_Uops_Executed_Threshold - RS_EVENTS.EMPTY_CYCLES + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + (UOPS_EXECUTED.CORE:c1 - #Few_Uops_Executed_Threshold)/2 - RS_EVENTS.EMPTY_CYCLES + RESOURCE_STALLS.SB ) if #SMT_on else ( #STALLS_TOTAL + UOPS_EXECUTED.CORE:c1 - #Few_Uops_Executed_Threshold - RS_EVENTS.EMPTY_CYCLES + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - #Few_Uops_Executed_Threshold - RS_EVENTS.EMPTY_CYCLES + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + UOPS_DISPATCHED.THREAD:c1 - #Few_Uops_Executed_Threshold - RS_EVENTS.EMPTY_CYCLES + RESOURCE_STALLS.SB ),,Count,,
+Aux,#Memory_Bound_Fraction,,,,( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / #Backend_Bound_Cycles,,( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / #Backend_Bound_Cycles,,,,,,( #STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / #Backend_Bound_Cycles,,Fraction,,
+Aux,#Mem_L3_Hit_Fraction,,,,N/A,,,,MEM_LOAD_UOPS_RETIRED.L3_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.L3_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.L3_MISS_PS ),,MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS ),MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS ),MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS ),,Fraction,,
+Aux,#Mispred_Clears_Fraction,,,,,,,,,,,,BR_MISP_RETIRED.ALL_BRANCHES_PS / ( BR_MISP_RETIRED.ALL_BRANCHES_PS + MACHINE_CLEARS.COUNT ),,Fraction,,
+Aux,#Avg_RS_Empty_Period_Clears,,,,N/A,,,,( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFDATA_STALL  - #ITLB_Miss_Cycles ) / RS_EVENTS.EMPTY_END,,( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFETCH_STALL ) / RS_EVENTS.EMPTY_END,,( RS_EVENTS.EMPTY_CYCLES - #ITLB_Miss_Cycles ) / RS_EVENTS.EMPTY_END,,Metric,,
+Aux,#Retire_Uop_Fraction,,,,,,,,,,,,UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY,,Fraction,,
+Aux,SLOTS,,,,,,,,,,,,#Pipeline_Width*CORE_CLKS,,Count,Total issue-pipeline slots,
+Aux,#Pipeline_Width,,,,,,,,,,,,4,,Constant,,
+Aux,#Mem_L3_Weight,,,,N/A,,,,,,,,7,,Constant,,
+Aux,#Mem_STLB_Hit_Cost,,,,,,,,,,,,7,,Constant,,
+Aux,#MS_Switches_Cost,,,,,,,,2,,,,3,,Constant,,
+Aux,#OneMillion,,,,,,,,,,,,1000000,,Constant,,
+Aux,#OneBillion,,,,,,,,,,,,1000000000,,Constant,,
diff --git a/x86data/perfmon_data/TMAM_Metrics.xlsx b/x86data/perfmon_data/TMAM_Metrics.xlsx
new file mode 100644
index 0000000..5ebf428
--- /dev/null
+++ b/x86data/perfmon_data/TMAM_Metrics.xlsx
diff --git a/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_core_V1.json b/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_core_V1.json
new file mode 100644
index 0000000..6fd6dbb
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_core_V1.json
@@ -0,0 +1,12514 @@
+[

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.CYCLES_DIV_BUSY",

+    "BriefDescription": "Cycles the divider is busy",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.DIV",

+    "BriefDescription": "Divide Operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x2",

+    "EventName": "ARITH.MUL",

+    "BriefDescription": "Multiply operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x2",

+    "EventName": "BACLEAR.BAD_TARGET",

+    "BriefDescription": "BACLEAR asserted with bad target address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1",

+    "EventName": "BACLEAR.CLEAR",

+    "BriefDescription": "BACLEAR asserted, regardless of cause ",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA7",

+    "UMask": "0x1",

+    "EventName": "BACLEAR_FORCE_IQ",

+    "BriefDescription": "Instruction queue forced BACLEAR",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x1",

+    "EventName": "BPU_CLEARS.EARLY",

+    "BriefDescription": "Early Branch Prediciton Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x2",

+    "EventName": "BPU_CLEARS.LATE",

+    "BriefDescription": "Late Branch Prediction Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE5",

+    "UMask": "0x1",

+    "EventName": "BPU_MISSED_CALL_RET",

+    "BriefDescription": "Branch prediction unit missed call or return",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE0",

+    "UMask": "0x1",

+    "EventName": "BR_INST_DECODED",

+    "BriefDescription": "Branch instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7F",

+    "EventName": "BR_INST_EXEC.ANY",

+    "BriefDescription": "Branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x1",

+    "EventName": "BR_INST_EXEC.COND",

+    "BriefDescription": "Conditional branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x2",

+    "EventName": "BR_INST_EXEC.DIRECT",

+    "BriefDescription": "Unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x10",

+    "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Unconditional call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x20",

+    "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x4",

+    "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x30",

+    "EventName": "BR_INST_EXEC.NEAR_CALLS",

+    "BriefDescription": "Call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7",

+    "EventName": "BR_INST_EXEC.NON_CALLS",

+    "BriefDescription": "All non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x8",

+    "EventName": "BR_INST_EXEC.RETURN_NEAR",

+    "BriefDescription": "Indirect return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x40",

+    "EventName": "BR_INST_EXEC.TAKEN",

+    "BriefDescription": "Taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x1",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Retired conditional branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Retired near call instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",

+    "BriefDescription": "Retired near call instructions Ring 3 only(Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7F",

+    "EventName": "BR_MISP_EXEC.ANY",

+    "BriefDescription": "Mispredicted branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x1",

+    "EventName": "BR_MISP_EXEC.COND",

+    "BriefDescription": "Mispredicted conditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_EXEC.DIRECT",

+    "BriefDescription": "Mispredicted unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x10",

+    "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Mispredicted indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x30",

+    "EventName": "BR_MISP_EXEC.NEAR_CALLS",

+    "BriefDescription": "Mispredicted call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7",

+    "EventName": "BR_MISP_EXEC.NON_CALLS",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x8",

+    "EventName": "BR_MISP_EXEC.RETURN_NEAR",

+    "BriefDescription": "Mispredicted return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x40",

+    "EventName": "BR_MISP_EXEC.TAKEN",

+    "BriefDescription": "Mispredicted taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x1",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_RETIRED.NEAR_CALL",

+    "BriefDescription": "Mispredicted near retired calls (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x2",

+    "EventName": "CACHE_LOCK_CYCLES.L1D",

+    "BriefDescription": "Cycles L1D locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x1",

+    "EventName": "CACHE_LOCK_CYCLES.L1D_L2",

+    "BriefDescription": "Cycles L1D and L2 locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.REF",

+    "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x1",

+    "EventName": "CPU_CLK_UNHALTED.REF_P",

+    "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 2",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",

+    "BriefDescription": "Total CPU cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "2",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x1",

+    "EventName": "DTLB_LOAD_MISSES.ANY",

+    "BriefDescription": "DTLB load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x80",

+    "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",

+    "BriefDescription": "DTLB load miss large page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.PDE_MISS",

+    "BriefDescription": "DTLB load miss caused by low part of address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x2",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB load miss page walks complete",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x4",

+    "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",

+    "BriefDescription": "DTLB load miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x1",

+    "EventName": "DTLB_MISSES.ANY",

+    "BriefDescription": "DTLB misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x80",

+    "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",

+    "BriefDescription": "DTLB miss large page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x20",

+    "EventName": "DTLB_MISSES.PDE_MISS",

+    "BriefDescription": "DTLB misses casued by low part of address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB first level misses but second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x2",

+    "EventName": "DTLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x4",

+    "EventName": "DTLB_MISSES.WALK_CYCLES",

+    "BriefDescription": "DTLB miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4F",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Extended Page Table walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD5",

+    "UMask": "0x1",

+    "EventName": "ES_REG_RENAMES",

+    "BriefDescription": "ES segment renames",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x1",

+    "EventName": "FP_ASSIST.ALL",

+    "BriefDescription": "X87 Floating point assists (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x4",

+    "EventName": "FP_ASSIST.INPUT",

+    "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x2",

+    "EventName": "FP_ASSIST.OUTPUT",

+    "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x2",

+    "EventName": "FP_COMP_OPS_EXE.MMX",

+    "BriefDescription": "MMX Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",

+    "BriefDescription": "SSE* FP double precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x4",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP",

+    "BriefDescription": "SSE and SSE2 FP Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",

+    "BriefDescription": "SSE FP packed Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",

+    "BriefDescription": "SSE FP scalar Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",

+    "BriefDescription": "SSE* FP single precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x8",

+    "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",

+    "BriefDescription": "SSE2 integer Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x1",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Computational floating-point operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x3",

+    "EventName": "FP_MMX_TRANS.ANY",

+    "BriefDescription": "All Floating Point to and from MMX transitions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x1",

+    "EventName": "FP_MMX_TRANS.TO_FP",

+    "BriefDescription": "Transitions from MMX to Floating Point instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x2",

+    "EventName": "FP_MMX_TRANS.TO_MMX",

+    "BriefDescription": "Transitions from Floating Point to MMX instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0xF",

+    "EventName": "ILD_STALL.ANY",

+    "BriefDescription": "Any Instruction Length Decoder stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x4",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Instruction Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x1",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Length Change Prefix stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x2",

+    "EventName": "ILD_STALL.MRU",

+    "BriefDescription": "Stall cycles due to BPU MRU bypass",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x8",

+    "EventName": "ILD_STALL.REGEN",

+    "BriefDescription": "Regen stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x18",

+    "UMask": "0x1",

+    "EventName": "INST_DECODED.DEC0",

+    "BriefDescription": "Instructions that must be decoded by decoder 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x1E",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITE_CYCLES",

+    "BriefDescription": "Cycles instructions are written to the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x17",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITES",

+    "BriefDescription": "Instructions written to instruction queue.",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired (fixed counter)",

+    "Counter": "Fixed counter 1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x4",

+    "EventName": "INST_RETIRED.MMX",

+    "BriefDescription": "Retired MMX instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x2",

+    "EventName": "INST_RETIRED.X87",

+    "BriefDescription": "Retired floating-point operations (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6C",

+    "UMask": "0x1",

+    "EventName": "IO_TRANSACTIONS",

+    "BriefDescription": "I/O transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x1",

+    "EventName": "ITLB_FLUSH",

+    "BriefDescription": "ITLB flushes",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISS_RETIRED",

+    "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x1",

+    "EventName": "ITLB_MISSES.ANY",

+    "BriefDescription": "ITLB miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x80",

+    "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",

+    "BriefDescription": "ITLB miss large page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x2",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "ITLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x4",

+    "EventName": "ITLB_MISSES.WALK_CYCLES",

+    "BriefDescription": "ITLB miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x4",

+    "EventName": "L1D.M_EVICT",

+    "BriefDescription": "L1D cache lines replaced in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x2",

+    "EventName": "L1D.M_REPL",

+    "BriefDescription": "L1D cache lines allocated in the M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x8",

+    "EventName": "L1D.M_SNOOP_EVICT",

+    "BriefDescription": "L1D snoop eviction of cache lines in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x1",

+    "EventName": "L1D.REPL",

+    "BriefDescription": "L1 data cache lines allocated",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x52",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",

+    "BriefDescription": "L1D prefetch load lock accepted in fill buffer",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x2",

+    "EventName": "L1D_PREFETCH.MISS",

+    "BriefDescription": "L1D hardware prefetch misses",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x1",

+    "EventName": "L1D_PREFETCH.REQUESTS",

+    "BriefDescription": "L1D hardware prefetch requests",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x4",

+    "EventName": "L1D_PREFETCH.TRIGGERS",

+    "BriefDescription": "L1D hardware prefetch requests triggered",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x4",

+    "EventName": "L1D_WB_L2.E_STATE",

+    "BriefDescription": "L1 writebacks to L2 in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x1",

+    "EventName": "L1D_WB_L2.I_STATE",

+    "BriefDescription": "L1 writebacks to L2 in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x8",

+    "EventName": "L1D_WB_L2.M_STATE",

+    "BriefDescription": "L1 writebacks to L2 in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0xF",

+    "EventName": "L1D_WB_L2.MESI",

+    "BriefDescription": "All L1 writebacks to L2",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x2",

+    "EventName": "L1D_WB_L2.S_STATE",

+    "BriefDescription": "L1 writebacks to L2 in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x4",

+    "EventName": "L1I.CYCLES_STALLED",

+    "BriefDescription": "L1I instruction fetch stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x1",

+    "EventName": "L1I.HITS",

+    "BriefDescription": "L1I instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x2",

+    "EventName": "L1I.MISSES",

+    "BriefDescription": "L1I instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x3",

+    "EventName": "L1I.READS",

+    "BriefDescription": "L1I Instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xFF",

+    "EventName": "L2_DATA_RQSTS.ANY",

+    "BriefDescription": "All L2 data requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x4",

+    "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",

+    "BriefDescription": "L2 data demand loads in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x1",

+    "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",

+    "BriefDescription": "L2 data demand loads in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x8",

+    "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",

+    "BriefDescription": "L2 data demand loads in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF",

+    "EventName": "L2_DATA_RQSTS.DEMAND.MESI",

+    "BriefDescription": "L2 data demand requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x2",

+    "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",

+    "BriefDescription": "L2 data demand loads in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x40",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",

+    "BriefDescription": "L2 data prefetches in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x10",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",

+    "BriefDescription": "L2 data prefetches in the I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x80",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",

+    "BriefDescription": "L2 data prefetches in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF0",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",

+    "BriefDescription": "All L2 data prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x20",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",

+    "BriefDescription": "L2 data prefetches in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x7",

+    "EventName": "L2_LINES_IN.ANY",

+    "BriefDescription": "L2 lines alloacated",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_IN.E_STATE",

+    "BriefDescription": "L2 lines allocated in the E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_IN.S_STATE",

+    "BriefDescription": "L2 lines allocated in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0xF",

+    "EventName": "L2_LINES_OUT.ANY",

+    "BriefDescription": "L2 lines evicted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x1",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "L2 lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",

+    "BriefDescription": "L2 lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x8",

+    "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.IFETCH_HIT",

+    "BriefDescription": "L2 instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.IFETCH_MISS",

+    "BriefDescription": "L2 instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.IFETCHES",

+    "BriefDescription": "L2 instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x1",

+    "EventName": "L2_RQSTS.LD_HIT",

+    "BriefDescription": "L2 load hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x2",

+    "EventName": "L2_RQSTS.LD_MISS",

+    "BriefDescription": "L2 load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3",

+    "EventName": "L2_RQSTS.LOADS",

+    "BriefDescription": "L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xAA",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All L2 misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PREFETCH_HIT",

+    "BriefDescription": "L2 prefetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PREFETCH_MISS",

+    "BriefDescription": "L2 prefetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.PREFETCHES",

+    "BriefDescription": "All L2 prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x4",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "L2 RFO hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x8",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "L2 RFO misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC",

+    "EventName": "L2_RQSTS.RFOS",

+    "BriefDescription": "L2 RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANSACTIONS.ANY",

+    "BriefDescription": "All L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANSACTIONS.FILL",

+    "BriefDescription": "L2 fill transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x4",

+    "EventName": "L2_TRANSACTIONS.IFETCH",

+    "BriefDescription": "L2 instruction fetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANSACTIONS.L1D_WB",

+    "BriefDescription": "L1D writeback to L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x1",

+    "EventName": "L2_TRANSACTIONS.LOAD",

+    "BriefDescription": "L2 Load transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x8",

+    "EventName": "L2_TRANSACTIONS.PREFETCH",

+    "BriefDescription": "L2 prefetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x2",

+    "EventName": "L2_TRANSACTIONS.RFO",

+    "BriefDescription": "L2 RFO transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANSACTIONS.WB",

+    "BriefDescription": "L2 writeback to LLC transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x40",

+    "EventName": "L2_WRITE.LOCK.E_STATE",

+    "BriefDescription": "L2 demand lock RFOs in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE0",

+    "EventName": "L2_WRITE.LOCK.HIT",

+    "BriefDescription": "All demand L2 lock RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x10",

+    "EventName": "L2_WRITE.LOCK.I_STATE",

+    "BriefDescription": "L2 demand lock RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x80",

+    "EventName": "L2_WRITE.LOCK.M_STATE",

+    "BriefDescription": "L2 demand lock RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF0",

+    "EventName": "L2_WRITE.LOCK.MESI",

+    "BriefDescription": "All demand L2 lock RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x20",

+    "EventName": "L2_WRITE.LOCK.S_STATE",

+    "BriefDescription": "L2 demand lock RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE",

+    "EventName": "L2_WRITE.RFO.HIT",

+    "BriefDescription": "All L2 demand store RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x1",

+    "EventName": "L2_WRITE.RFO.I_STATE",

+    "BriefDescription": "L2 demand store RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x8",

+    "EventName": "L2_WRITE.RFO.M_STATE",

+    "BriefDescription": "L2 demand store RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF",

+    "EventName": "L2_WRITE.RFO.MESI",

+    "BriefDescription": "All L2 demand store RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x2",

+    "EventName": "L2_WRITE.RFO.S_STATE",

+    "BriefDescription": "L2 demand store RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x82",

+    "UMask": "0x1",

+    "EventName": "LARGE_ITLB.HIT",

+    "BriefDescription": "Large ITLB hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3",

+    "UMask": "0x2",

+    "EventName": "LOAD_BLOCK.OVERLAP_STORE",

+    "BriefDescription": "Loads that partially overlap an earlier store",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x7",

+    "EventName": "LOAD_DISPATCH.ANY",

+    "BriefDescription": "All loads dispatched",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x4",

+    "EventName": "LOAD_DISPATCH.MOB",

+    "BriefDescription": "Loads dispatched from the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x1",

+    "EventName": "LOAD_DISPATCH.RS",

+    "BriefDescription": "Loads dispatched that bypass the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x2",

+    "EventName": "LOAD_DISPATCH.RS_DELAYED",

+    "BriefDescription": "Loads dispatched from stage 305",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x1",

+    "EventName": "LOAD_HIT_PRE",

+    "BriefDescription": "Load operations conflicting with software prefetches",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Longest latency cache miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Longest latency cache reference",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.ACTIVE",

+    "BriefDescription": "Cycles when uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.INACTIVE",

+    "BriefDescription": "Cycles no uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x20",

+    "UMask": "0x1",

+    "EventName": "LSD_OVERFLOW",

+    "BriefDescription": "Loops that can't stream from the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x1",

+    "EventName": "MACHINE_CLEARS.CYCLES",

+    "BriefDescription": "Cycles machine clear asserted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x2",

+    "EventName": "MACHINE_CLEARS.MEM_ORDER",

+    "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x4",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-Modifying Code detected",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.DECODED",

+    "BriefDescription": "Instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.FUSIONS_DECODED",

+    "BriefDescription": "Macro-fused instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x1",

+    "EventName": "MEM_INST_RETIRED.LOADS",

+    "BriefDescription": "Instructions retired which contains a load (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x2",

+    "EventName": "MEM_INST_RETIRED.STORES",

+    "BriefDescription": "Instructions retired which contains a store (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x80",

+    "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x1",

+    "EventName": "MEM_LOAD_RETIRED.L1D_HIT",

+    "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x2",

+    "EventName": "MEM_LOAD_RETIRED.L2_HIT",

+    "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_RETIRED.LLC_MISS",

+    "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x4",

+    "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",

+    "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x8",

+    "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",

+    "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC",

+    "UMask": "0x1",

+    "EventName": "MEM_STORE_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5",

+    "UMask": "0x2",

+    "EventName": "MISALIGN_MEM_REF.STORE",

+    "BriefDescription": "Misaligned store references",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x80",

+    "EventName": "OFFCORE_REQUESTS.ANY",

+    "BriefDescription": "All offcore requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS.ANY.READ",

+    "BriefDescription": "Offcore read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x10",

+    "EventName": "OFFCORE_REQUESTS.ANY.RFO",

+    "BriefDescription": "Offcore RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",

+    "BriefDescription": "Offcore demand code read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",

+    "BriefDescription": "Offcore demand data read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",

+    "BriefDescription": "Offcore demand RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x40",

+    "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",

+    "BriefDescription": "Offcore L1 data cache writebacks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",

+    "BriefDescription": "Outstanding offcore reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore reads busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",

+    "BriefDescription": "Outstanding offcore demand code reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand code read busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",

+    "BriefDescription": "Outstanding offcore demand data reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand data read busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",

+    "BriefDescription": "Outstanding offcore demand RFOs",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand RFOs busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_SQ_FULL",

+    "BriefDescription": "Offcore requests blocked due to Super Queue full",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x7",

+    "UMask": "0x1",

+    "EventName": "PARTIAL_ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies due to partial address aliasing",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0xF",

+    "EventName": "RAT_STALLS.ANY",

+    "BriefDescription": "All RAT stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x1",

+    "EventName": "RAT_STALLS.FLAGS",

+    "BriefDescription": "Flag stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x2",

+    "EventName": "RAT_STALLS.REGISTERS",

+    "BriefDescription": "Partial register stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x4",

+    "EventName": "RAT_STALLS.ROB_READ_PORT",

+    "BriefDescription": "ROB read port stalls cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x8",

+    "EventName": "RAT_STALLS.SCOREBOARD",

+    "BriefDescription": "Scoreboard stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x1",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x20",

+    "EventName": "RESOURCE_STALLS.FPCW",

+    "BriefDescription": "FPU control word write stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x2",

+    "EventName": "RESOURCE_STALLS.LOAD",

+    "BriefDescription": "Load buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x40",

+    "EventName": "RESOURCE_STALLS.MXCSR",

+    "BriefDescription": "MXCSR rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x80",

+    "EventName": "RESOURCE_STALLS.OTHER",

+    "BriefDescription": "Other Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB_FULL",

+    "BriefDescription": "ROB full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x4",

+    "EventName": "RESOURCE_STALLS.RS_FULL",

+    "BriefDescription": "Reservation Station full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x8",

+    "EventName": "RESOURCE_STALLS.STORE",

+    "BriefDescription": "Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4",

+    "UMask": "0x7",

+    "EventName": "SB_DRAIN.ANY",

+    "BriefDescription": "All Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD4",

+    "UMask": "0x1",

+    "EventName": "SEG_RENAME_STALLS",

+    "BriefDescription": "Segment rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_128.PACK",

+    "BriefDescription": "128 bit SIMD integer pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_128.PACKED_ARITH",

+    "BriefDescription": "128 bit SIMD integer arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_128.PACKED_LOGICAL",

+    "BriefDescription": "128 bit SIMD integer logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_128.PACKED_MPY",

+    "BriefDescription": "128 bit SIMD integer multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_128.PACKED_SHIFT",

+    "BriefDescription": "128 bit SIMD integer shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_128.SHUFFLE_MOVE",

+    "BriefDescription": "128 bit SIMD integer shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_128.UNPACK",

+    "BriefDescription": "128 bit SIMD integer unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_64.PACK",

+    "BriefDescription": "SIMD integer 64 bit pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_64.PACKED_ARITH",

+    "BriefDescription": "SIMD integer 64 bit arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_64.PACKED_LOGICAL",

+    "BriefDescription": "SIMD integer 64 bit logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_64.PACKED_MPY",

+    "BriefDescription": "SIMD integer 64 bit packed multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_64.PACKED_SHIFT",

+    "BriefDescription": "SIMD integer 64 bit shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_64.SHUFFLE_MOVE",

+    "BriefDescription": "SIMD integer 64 bit shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_64.UNPACK",

+    "BriefDescription": "SIMD integer 64 bit unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x1",

+    "EventName": "SNOOP_RESPONSE.HIT",

+    "BriefDescription": "Thread responded HIT to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x2",

+    "EventName": "SNOOP_RESPONSE.HITE",

+    "BriefDescription": "Thread responded HITE to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x4",

+    "EventName": "SNOOP_RESPONSE.HITM",

+    "BriefDescription": "Thread responded HITM to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS.CODE",

+    "BriefDescription": "Snoop code requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS.DATA",

+    "BriefDescription": "Snoop data requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS.INVALIDATE",

+    "BriefDescription": "Snoop invalidate requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",

+    "BriefDescription": "Outstanding snoop code requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop code requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",

+    "BriefDescription": "Outstanding snoop data requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop data requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",

+    "BriefDescription": "Outstanding snoop invalidate requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop invalidate requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF6",

+    "UMask": "0x1",

+    "EventName": "SQ_FULL_STALL_CYCLES",

+    "BriefDescription": "Super Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x4",

+    "EventName": "SQ_MISC.LRU_HINTS",

+    "BriefDescription": "Super Queue LRU hints sent to LLC",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x10",

+    "EventName": "SQ_MISC.SPLIT_LOCK",

+    "BriefDescription": "Super Queue lock splits across a cache line",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x4",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",

+    "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x1",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",

+    "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x8",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",

+    "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x2",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",

+    "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x10",

+    "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",

+    "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x4",

+    "EventName": "STORE_BLOCKS.AT_RET",

+    "BriefDescription": "Loads delayed with at-Retirement block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x8",

+    "EventName": "STORE_BLOCKS.L1D_BLOCK",

+    "BriefDescription": "Cacheable loads delayed with L1D block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x19",

+    "UMask": "0x1",

+    "EventName": "TWO_UOP_INSTS_DECODED",

+    "BriefDescription": "Two Uop instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xDB",

+    "UMask": "0x1",

+    "EventName": "UOP_UNFUSION",

+    "BriefDescription": "Uop unfusions due to FP exceptions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x4",

+    "EventName": "UOPS_DECODED.ESP_FOLDING",

+    "BriefDescription": "Stack pointer instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x8",

+    "EventName": "UOPS_DECODED.ESP_SYNC",

+    "BriefDescription": "Stack pointer sync operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x2",

+    "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",

+    "BriefDescription": "Uops decoded by Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x1",

+    "EventName": "UOPS_DECODED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops are decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",

+    "BriefDescription": "Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",

+    "BriefDescription": "Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1",

+    "EventName": "UOPS_EXECUTED.PORT0",

+    "BriefDescription": "Uops executed on port 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015",

+    "BriefDescription": "Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x2",

+    "EventName": "UOPS_EXECUTED.PORT1",

+    "BriefDescription": "Uops executed on port 1",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x4",

+    "EventName": "UOPS_EXECUTED.PORT2_CORE",

+    "BriefDescription": "Uops executed on port 2 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED.PORT234_CORE",

+    "BriefDescription": "Uops issued on ports 2, 3 or 4",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x8",

+    "EventName": "UOPS_EXECUTED.PORT3_CORE",

+    "BriefDescription": "Uops executed on port 3 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED.PORT4_CORE",

+    "BriefDescription": "Uops executed on port 4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED.PORT5",

+    "BriefDescription": "Uops executed on port 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued on any thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",

+    "BriefDescription": "Cycles Uops were issued on either thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x2",

+    "EventName": "UOPS_ISSUED.FUSED",

+    "BriefDescription": "Fused Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops are being retired",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ANY",

+    "BriefDescription": "Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x4",

+    "EventName": "UOPS_RETIRED.MACRO_FUSED",

+    "BriefDescription": "Macro-fused Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x2",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles Uops are not retiring (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",

+    "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",

+    "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "100",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x400",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",

+    "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "1000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",

+    "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",

+    "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",

+    "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x800",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",

+    "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "500",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",

+    "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",

+    "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "3",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",

+    "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",

+    "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x1000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",

+    "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "200",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",

+    "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",

+    "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",

+    "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x2000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x111",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x211",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x411",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x144",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x244",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x444",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x50ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7fff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x30ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf8ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xffff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x80ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x10ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x40ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x20ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x122",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x222",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x422",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x108",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x208",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x408",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x177",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x277",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x477",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x133",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x233",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x433",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x103",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x203",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x403",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x101",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x201",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x401",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x104",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x204",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x404",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x102",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x202",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x402",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x180",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x280",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x480",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f50",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff50",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x150",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x250",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x450",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x750",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x110",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x210",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x410",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x140",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x240",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x440",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x120",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x220",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x420",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7f70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xf870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xff70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x170",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x270",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x470",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x111",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x211",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x411",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x144",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x244",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x444",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x50ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7fff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x30ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf8ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xffff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x80ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x10ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x40ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x20ff",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x122",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x222",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x422",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x108",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x208",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x408",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x177",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x277",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x477",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x133",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x233",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x433",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x103",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x203",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x403",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x101",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x201",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x401",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x104",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x204",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x404",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x102",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x202",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x402",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x180",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x280",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x480",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f50",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff50",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x150",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x250",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x450",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x750",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x110",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x210",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x410",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x140",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x240",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x440",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x120",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x220",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x420",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7f70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x3070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xf870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xff70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x170",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x270",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x470",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_core_V1.tsv b/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_core_V1.tsv
new file mode 100644
index 0000000..07c1882
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_core_V1.tsv
@@ -0,0 +1,309 @@
+# Performance Monitoring Events for Intel Xeon Processor 3600, 5600 series Based on the Westmere-EP Microarchitecture - V1
+# 12/13/2013 10:58:33 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0x14	0x1	ARITH.CYCLES_DIV_BUSY	Cycles the divider is busy	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x14	0x1	ARITH.DIV	Divide Operations executed	0,1,2,3	2000000	0	0	1	1	0	1	0	
+0x14	0x2	ARITH.MUL	Multiply operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x2	BACLEAR.BAD_TARGET	BACLEAR asserted with bad target address	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x1	BACLEAR.CLEAR	BACLEAR asserted, regardless of cause 	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA7	0x1	BACLEAR_FORCE_IQ	Instruction queue forced BACLEAR	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x1	BPU_CLEARS.EARLY	Early Branch Prediciton Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x2	BPU_CLEARS.LATE	Late Branch Prediction Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE5	0x1	BPU_MISSED_CALL_RET	Branch prediction unit missed call or return	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE0	0x1	BR_INST_DECODED	Branch instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x88	0x7F	BR_INST_EXEC.ANY	Branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x1	BR_INST_EXEC.COND	Conditional branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x2	BR_INST_EXEC.DIRECT	Unconditional branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x10	BR_INST_EXEC.DIRECT_NEAR_CALL	Unconditional call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x20	BR_INST_EXEC.INDIRECT_NEAR_CALL	Indirect call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x4	BR_INST_EXEC.INDIRECT_NON_CALL	Indirect non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x30	BR_INST_EXEC.NEAR_CALLS	Call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x7	BR_INST_EXEC.NON_CALLS	All non call branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x8	BR_INST_EXEC.RETURN_NEAR	Indirect return branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x40	BR_INST_EXEC.TAKEN	Taken branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x1	BR_INST_RETIRED.CONDITIONAL	Retired conditional branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL	Retired near call instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL_R3	Retired near call instructions Ring 3 only(Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x89	0x7F	BR_MISP_EXEC.ANY	Mispredicted branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x1	BR_MISP_EXEC.COND	Mispredicted conditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x2	BR_MISP_EXEC.DIRECT	Mispredicted unconditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x10	BR_MISP_EXEC.DIRECT_NEAR_CALL	Mispredicted non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x20	BR_MISP_EXEC.INDIRECT_NEAR_CALL	Mispredicted indirect call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x4	BR_MISP_EXEC.INDIRECT_NON_CALL	Mispredicted indirect non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x30	BR_MISP_EXEC.NEAR_CALLS	Mispredicted call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x7	BR_MISP_EXEC.NON_CALLS	Mispredicted non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x8	BR_MISP_EXEC.RETURN_NEAR	Mispredicted return branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x40	BR_MISP_EXEC.TAKEN	Mispredicted taken branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC5	0x4	BR_MISP_RETIRED.ALL_BRANCHES	Mispredicted retired branch instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC5	0x1	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional retired branches (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC5	0x2	BR_MISP_RETIRED.NEAR_CALL	Mispredicted near retired calls (Precise Event)	0,1,2,3	2000	0	0	0	0	0	0	1	
+0x63	0x2	CACHE_LOCK_CYCLES.L1D	Cycles L1D locked	0,1	2000000	0	0	0	0	0	0	0	
+0x63	0x1	CACHE_LOCK_CYCLES.L1D_L2	Cycles L1D and L2 locked	0,1	2000000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.REF	Reference cycles when thread is not halted (fixed counter)	Fixed counter 3	2000000	0	0	0	0	0	0	0	
+0x3C	0x1	CPU_CLK_UNHALTED.REF_P	Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.THREAD	Cycles when thread is not halted (fixed counter)	Fixed counter 2	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.THREAD_P	Cycles when thread is not halted (programmable counter)	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.TOTAL_CYCLES	Total CPU cycles	0,1,2,3	2000000	0	0	2	1	0	0	0	
+0x8	0x1	DTLB_LOAD_MISSES.ANY	DTLB load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x80	DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED	DTLB load miss large page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x20	DTLB_LOAD_MISSES.PDE_MISS	DTLB load miss caused by low part of address	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x10	DTLB_LOAD_MISSES.STLB_HIT	DTLB second level hit	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x8	0x2	DTLB_LOAD_MISSES.WALK_COMPLETED	DTLB load miss page walks complete	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x4	DTLB_LOAD_MISSES.WALK_CYCLES	DTLB load miss page walk cycles	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x1	DTLB_MISSES.ANY	DTLB misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x80	DTLB_MISSES.LARGE_WALK_COMPLETED	DTLB miss large page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x20	DTLB_MISSES.PDE_MISS	DTLB misses casued by low part of address	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x10	DTLB_MISSES.STLB_HIT	DTLB first level misses but second level hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x2	DTLB_MISSES.WALK_COMPLETED	DTLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x4	DTLB_MISSES.WALK_CYCLES	DTLB miss page walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4F	0x10	EPT.WALK_CYCLES	Extended Page Table walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD5	0x1	ES_REG_RENAMES	ES segment renames	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF7	0x1	FP_ASSIST.ALL	X87 Floating point assists (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x4	FP_ASSIST.INPUT	X87 Floating poiint assists for invalid input value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x2	FP_ASSIST.OUTPUT	X87 Floating point assists for invalid output value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x10	0x2	FP_COMP_OPS_EXE.MMX	MMX Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x80	FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION	SSE* FP double precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x4	FP_COMP_OPS_EXE.SSE_FP	SSE and SSE2 FP Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x10	FP_COMP_OPS_EXE.SSE_FP_PACKED	SSE FP packed Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x20	FP_COMP_OPS_EXE.SSE_FP_SCALAR	SSE FP scalar Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x40	FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION	SSE* FP single precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x8	FP_COMP_OPS_EXE.SSE2_INTEGER	SSE2 integer Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x1	FP_COMP_OPS_EXE.X87	Computational floating-point operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x3	FP_MMX_TRANS.ANY	All Floating Point to and from MMX transitions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x1	FP_MMX_TRANS.TO_FP	Transitions from MMX to Floating Point instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x2	FP_MMX_TRANS.TO_MMX	Transitions from Floating Point to MMX instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0xF	ILD_STALL.ANY	Any Instruction Length Decoder stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x4	ILD_STALL.IQ_FULL	Instruction Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x1	ILD_STALL.LCP	Length Change Prefix stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x2	ILD_STALL.MRU	Stall cycles due to BPU MRU bypass	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x8	ILD_STALL.REGEN	Regen stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x18	0x1	INST_DECODED.DEC0	Instructions that must be decoded by decoder 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x1E	0x1	INST_QUEUE_WRITE_CYCLES	Cycles instructions are written to the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x17	0x1	INST_QUEUE_WRITES	Instructions written to instruction queue.	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x0	0x0	INST_RETIRED.ANY	Instructions retired (fixed counter)	Fixed counter 1	2000000	0	0	0	0	0	0	0	
+0xC0	0x1	INST_RETIRED.ANY_P	Instructions retired (Programmable counter and Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x4	INST_RETIRED.MMX	Retired MMX instructions (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x1	INST_RETIRED.TOTAL_CYCLES	Total cycles (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC0	0x2	INST_RETIRED.X87	Retired floating-point operations (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0x6C	0x1	IO_TRANSACTIONS	I/O transactions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xAE	0x1	ITLB_FLUSH	ITLB flushes	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC8	0x20	ITLB_MISS_RETIRED	Retired instructions that missed the ITLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x85	0x1	ITLB_MISSES.ANY	ITLB miss	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x80	ITLB_MISSES.LARGE_WALK_COMPLETED	ITLB miss large page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x2	ITLB_MISSES.WALK_COMPLETED	ITLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x4	ITLB_MISSES.WALK_CYCLES	ITLB miss page walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x51	0x4	L1D.M_EVICT	L1D cache lines replaced in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x2	L1D.M_REPL	L1D cache lines allocated in the M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x8	L1D.M_SNOOP_EVICT	L1D snoop eviction of cache lines in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x1	L1D.REPL	L1 data cache lines allocated	0,1	2000000	0	0	0	0	0	0	0	
+0x52	0x1	L1D_CACHE_PREFETCH_LOCK_FB_HIT	L1D prefetch load lock accepted in fill buffer	0,1	2000000	0	0	0	0	0	0	0	
+0x4E	0x2	L1D_PREFETCH.MISS	L1D hardware prefetch misses	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x1	L1D_PREFETCH.REQUESTS	L1D hardware prefetch requests	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x4	L1D_PREFETCH.TRIGGERS	L1D hardware prefetch requests triggered	0,1	200000	0	0	0	0	0	0	0	
+0x28	0x4	L1D_WB_L2.E_STATE	L1 writebacks to L2 in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x1	L1D_WB_L2.I_STATE	L1 writebacks to L2 in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x8	L1D_WB_L2.M_STATE	L1 writebacks to L2 in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0xF	L1D_WB_L2.MESI	All L1 writebacks to L2	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x2	L1D_WB_L2.S_STATE	L1 writebacks to L2 in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x80	0x4	L1I.CYCLES_STALLED	L1I instruction fetch stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x1	L1I.HITS	L1I instruction fetch hits	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x2	L1I.MISSES	L1I instruction fetch misses	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x3	L1I.READS	L1I Instruction fetches	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x26	0xFF	L2_DATA_RQSTS.ANY	All L2 data requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x4	L2_DATA_RQSTS.DEMAND.E_STATE	L2 data demand loads in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x1	L2_DATA_RQSTS.DEMAND.I_STATE	L2 data demand loads in I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x8	L2_DATA_RQSTS.DEMAND.M_STATE	L2 data demand loads in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF	L2_DATA_RQSTS.DEMAND.MESI	L2 data demand requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x2	L2_DATA_RQSTS.DEMAND.S_STATE	L2 data demand loads in S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x40	L2_DATA_RQSTS.PREFETCH.E_STATE	L2 data prefetches in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x10	L2_DATA_RQSTS.PREFETCH.I_STATE	L2 data prefetches in the I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x80	L2_DATA_RQSTS.PREFETCH.M_STATE	L2 data prefetches in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF0	L2_DATA_RQSTS.PREFETCH.MESI	All L2 data prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x20	L2_DATA_RQSTS.PREFETCH.S_STATE	L2 data prefetches in the S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF1	0x7	L2_LINES_IN.ANY	L2 lines alloacated	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x4	L2_LINES_IN.E_STATE	L2 lines allocated in the E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x2	L2_LINES_IN.S_STATE	L2 lines allocated in the S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0xF	L2_LINES_OUT.ANY	L2 lines evicted	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x1	L2_LINES_OUT.DEMAND_CLEAN	L2 lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x2	L2_LINES_OUT.DEMAND_DIRTY	L2 modified lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x4	L2_LINES_OUT.PREFETCH_CLEAN	L2 lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x8	L2_LINES_OUT.PREFETCH_DIRTY	L2 modified lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x24	0x10	L2_RQSTS.IFETCH_HIT	L2 instruction fetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x20	L2_RQSTS.IFETCH_MISS	L2 instruction fetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x30	L2_RQSTS.IFETCHES	L2 instruction fetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x1	L2_RQSTS.LD_HIT	L2 load hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x2	L2_RQSTS.LD_MISS	L2 load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x3	L2_RQSTS.LOADS	L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xAA	L2_RQSTS.MISS	All L2 misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x40	L2_RQSTS.PREFETCH_HIT	L2 prefetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x80	L2_RQSTS.PREFETCH_MISS	L2 prefetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC0	L2_RQSTS.PREFETCHES	All L2 prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x4	L2_RQSTS.RFO_HIT	L2 RFO hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x8	L2_RQSTS.RFO_MISS	L2 RFO misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC	L2_RQSTS.RFOS	L2 RFO requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x80	L2_TRANSACTIONS.ANY	All L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x20	L2_TRANSACTIONS.FILL	L2 fill transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x4	L2_TRANSACTIONS.IFETCH	L2 instruction fetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x10	L2_TRANSACTIONS.L1D_WB	L1D writeback to L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x1	L2_TRANSACTIONS.LOAD	L2 Load transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x8	L2_TRANSACTIONS.PREFETCH	L2 prefetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x2	L2_TRANSACTIONS.RFO	L2 RFO transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x40	L2_TRANSACTIONS.WB	L2 writeback to LLC transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x27	0x40	L2_WRITE.LOCK.E_STATE	L2 demand lock RFOs in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE0	L2_WRITE.LOCK.HIT	All demand L2 lock RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x10	L2_WRITE.LOCK.I_STATE	L2 demand lock RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x80	L2_WRITE.LOCK.M_STATE	L2 demand lock RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF0	L2_WRITE.LOCK.MESI	All demand L2 lock RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x20	L2_WRITE.LOCK.S_STATE	L2 demand lock RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE	L2_WRITE.RFO.HIT	All L2 demand store RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x1	L2_WRITE.RFO.I_STATE	L2 demand store RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x8	L2_WRITE.RFO.M_STATE	L2 demand store RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF	L2_WRITE.RFO.MESI	All L2 demand store RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x2	L2_WRITE.RFO.S_STATE	L2 demand store RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x82	0x1	LARGE_ITLB.HIT	Large ITLB hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x3	0x2	LOAD_BLOCK.OVERLAP_STORE	Loads that partially overlap an earlier store	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x13	0x7	LOAD_DISPATCH.ANY	All loads dispatched	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x4	LOAD_DISPATCH.MOB	Loads dispatched from the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x1	LOAD_DISPATCH.RS	Loads dispatched that bypass the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x2	LOAD_DISPATCH.RS_DELAYED	Loads dispatched from stage 305	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4C	0x1	LOAD_HIT_PRE	Load operations conflicting with software prefetches	0,1	200000	0	0	0	0	0	0	0	
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Longest latency cache miss	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Longest latency cache reference	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xA8	0x1	LSD.ACTIVE	Cycles when uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xA8	0x1	LSD.INACTIVE	Cycles no uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0x20	0x1	LSD_OVERFLOW	Loops that can't stream from the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC3	0x1	MACHINE_CLEARS.CYCLES	Cycles machine clear asserted	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x2	MACHINE_CLEARS.MEM_ORDER	Execution pipeline restart due to Memory ordering conflicts	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x4	MACHINE_CLEARS.SMC	Self-Modifying Code detected	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xD0	0x1	MACRO_INSTS.DECODED	Instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA6	0x1	MACRO_INSTS.FUSIONS_DECODED	Macro-fused instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB	0x1	MEM_INST_RETIRED.LOADS	Instructions retired which contains a load (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xB	0x2	MEM_INST_RETIRED.STORES	Instructions retired which contains a store (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x80	MEM_LOAD_RETIRED.DTLB_MISS	Retired loads that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x40	MEM_LOAD_RETIRED.HIT_LFB	Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x1	MEM_LOAD_RETIRED.L1D_HIT	Retired loads that hit the L1 data cache (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x2	MEM_LOAD_RETIRED.L2_HIT	Retired loads that hit the L2 cache (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x10	MEM_LOAD_RETIRED.LLC_MISS	Retired loads that miss the LLC cache (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xCB	0x4	MEM_LOAD_RETIRED.LLC_UNSHARED_HIT	Retired loads that hit valid versions in the LLC cache (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xCB	0x8	MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM	Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xC	0x1	MEM_STORE_RETIRED.DTLB_MISS	Retired stores that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x5	0x2	MISALIGN_MEM_REF.STORE	Misaligned store references	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xB0	0x80	OFFCORE_REQUESTS.ANY	All offcore requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x8	OFFCORE_REQUESTS.ANY.READ	Offcore read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x10	OFFCORE_REQUESTS.ANY.RFO	Offcore RFO requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x2	OFFCORE_REQUESTS.DEMAND.READ_CODE	Offcore demand code read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x1	OFFCORE_REQUESTS.DEMAND.READ_DATA	Offcore demand data read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x4	OFFCORE_REQUESTS.DEMAND.RFO	Offcore demand RFO requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x40	OFFCORE_REQUESTS.L1D_WRITEBACK	Offcore L1 data cache writebacks	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x60	0x8	OFFCORE_REQUESTS_OUTSTANDING.ANY.READ	Outstanding offcore reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x8	OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY	Cycles offcore reads busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x2	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE	Outstanding offcore demand code reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x2	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY	Cycles offcore demand code read busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x1	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA	Outstanding offcore demand data reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x1	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY	Cycles offcore demand data read busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x4	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO	Outstanding offcore demand RFOs	0	2000000	0	0	0	0	0	0	0	
+0x60	0x4	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY	Cycles offcore demand RFOs busy	0	2000000	0	0	1	0	0	0	0	
+0xB2	0x1	OFFCORE_REQUESTS_SQ_FULL	Offcore requests blocked due to Super Queue full	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x7	0x1	PARTIAL_ADDRESS_ALIAS	False dependencies due to partial address aliasing	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD2	0xF	RAT_STALLS.ANY	All RAT stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x1	RAT_STALLS.FLAGS	Flag stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x2	RAT_STALLS.REGISTERS	Partial register stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x4	RAT_STALLS.ROB_READ_PORT	ROB read port stalls cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x8	RAT_STALLS.SCOREBOARD	Scoreboard stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x1	RESOURCE_STALLS.ANY	Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x20	RESOURCE_STALLS.FPCW	FPU control word write stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x2	RESOURCE_STALLS.LOAD	Load buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x40	RESOURCE_STALLS.MXCSR	MXCSR rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x80	RESOURCE_STALLS.OTHER	Other Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x10	RESOURCE_STALLS.ROB_FULL	ROB full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x4	RESOURCE_STALLS.RS_FULL	Reservation Station full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x8	RESOURCE_STALLS.STORE	Store buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4	0x7	SB_DRAIN.ANY	All Store buffer stall cycles	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD4	0x1	SEG_RENAME_STALLS	Segment rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x12	0x4	SIMD_INT_128.PACK	128 bit SIMD integer pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x20	SIMD_INT_128.PACKED_ARITH	128 bit SIMD integer arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x10	SIMD_INT_128.PACKED_LOGICAL	128 bit SIMD integer logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x1	SIMD_INT_128.PACKED_MPY	128 bit SIMD integer multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x2	SIMD_INT_128.PACKED_SHIFT	128 bit SIMD integer shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x40	SIMD_INT_128.SHUFFLE_MOVE	128 bit SIMD integer shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x8	SIMD_INT_128.UNPACK	128 bit SIMD integer unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x4	SIMD_INT_64.PACK	SIMD integer 64 bit pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x20	SIMD_INT_64.PACKED_ARITH	SIMD integer 64 bit arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x10	SIMD_INT_64.PACKED_LOGICAL	SIMD integer 64 bit logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x1	SIMD_INT_64.PACKED_MPY	SIMD integer 64 bit packed multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x2	SIMD_INT_64.PACKED_SHIFT	SIMD integer 64 bit shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x40	SIMD_INT_64.SHUFFLE_MOVE	SIMD integer 64 bit shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x8	SIMD_INT_64.UNPACK	SIMD integer 64 bit unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xB8	0x1	SNOOP_RESPONSE.HIT	Thread responded HIT to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x2	SNOOP_RESPONSE.HITE	Thread responded HITE to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x4	SNOOP_RESPONSE.HITM	Thread responded HITM to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x4	SNOOPQ_REQUESTS.CODE	Snoop code requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x1	SNOOPQ_REQUESTS.DATA	Snoop data requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x2	SNOOPQ_REQUESTS.INVALIDATE	Snoop invalidate requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB3	0x4	SNOOPQ_REQUESTS_OUTSTANDING.CODE	Outstanding snoop code requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x4	SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY	Cycles snoop code requests queued	0	2000000	0	0	1	0	0	0	0	
+0xB3	0x1	SNOOPQ_REQUESTS_OUTSTANDING.DATA	Outstanding snoop data requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x1	SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY	Cycles snoop data requests queued	0	2000000	0	0	1	0	0	0	0	
+0xB3	0x2	SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE	Outstanding snoop invalidate requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x2	SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY	Cycles snoop invalidate requests queued	0	2000000	0	0	1	0	0	0	0	
+0xF6	0x1	SQ_FULL_STALL_CYCLES	Super Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF4	0x4	SQ_MISC.LRU_HINTS	Super Queue LRU hints sent to LLC	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF4	0x10	SQ_MISC.SPLIT_LOCK	Super Queue lock splits across a cache line	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC7	0x4	SSEX_UOPS_RETIRED.PACKED_DOUBLE	SIMD Packed-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x1	SSEX_UOPS_RETIRED.PACKED_SINGLE	SIMD Packed-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x8	SSEX_UOPS_RETIRED.SCALAR_DOUBLE	SIMD Scalar-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x2	SSEX_UOPS_RETIRED.SCALAR_SINGLE	SIMD Scalar-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x10	SSEX_UOPS_RETIRED.VECTOR_INTEGER	SIMD Vector Integer Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x6	0x4	STORE_BLOCKS.AT_RET	Loads delayed with at-Retirement block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x6	0x8	STORE_BLOCKS.L1D_BLOCK	Cacheable loads delayed with L1D block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x19	0x1	TWO_UOP_INSTS_DECODED	Two Uop instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xDB	0x1	UOP_UNFUSION	Uop unfusions due to FP exceptions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x4	UOPS_DECODED.ESP_FOLDING	Stack pointer instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x8	UOPS_DECODED.ESP_SYNC	Stack pointer sync operations	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x2	UOPS_DECODED.MS_CYCLES_ACTIVE	Uops decoded by Microcode Sequencer	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xD1	0x1	UOPS_DECODED.STALL_CYCLES	Cycles no Uops are decoded	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES	Cycles Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5	Cycles Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_COUNT	Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	1	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5	Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	1	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_CYCLES	Cycles no Uops issued on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5	Cycles no Uops issued on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1	UOPS_EXECUTED.PORT0	Uops executed on port 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015	Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015_STALL_CYCLES	Cycles no Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x2	UOPS_EXECUTED.PORT1	Uops executed on port 1	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x4	UOPS_EXECUTED.PORT2_CORE	Uops executed on port 2 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x80	UOPS_EXECUTED.PORT234_CORE	Uops issued on ports 2, 3 or 4	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x8	UOPS_EXECUTED.PORT3_CORE	Uops executed on port 3 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x10	UOPS_EXECUTED.PORT4_CORE	Uops executed on port 4 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x20	UOPS_EXECUTED.PORT5	Uops executed on port 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.ANY	Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles no Uops were issued on any thread	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xE	0x1	UOPS_ISSUED.CYCLES_ALL_THREADS	Cycles Uops were issued on either thread	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xE	0x2	UOPS_ISSUED.FUSED	Fused Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.STALL_CYCLES	Cycles no Uops were issued	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xC2	0x1	UOPS_RETIRED.ACTIVE_CYCLES	Cycles Uops are being retired	0,1,2,3	2000000	0	0	1	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.ANY	Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x4	UOPS_RETIRED.MACRO_FUSED	Macro-fused Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x2	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.STALL_CYCLES	Cycles Uops are not retiring (Precise Event)	0,1,2,3	2000000	0	0	1	1	0	0	1	
+0xC2	0x1	UOPS_RETIRED.TOTAL_CYCLES	Total cycles using precise uop retired event (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC5	0x4	BR_MISP_RETIRED.ALL_BRANCHES	Mispredicted retired branch instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0	Memory instructions retired above 0 clocks (Precise Event)	3	2000000	0x3F6	0x0	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024	Memory instructions retired above 1024 clocks (Precise Event)	3	100	0x3F6	0x400	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128	Memory instructions retired above 128 clocks (Precise Event)	3	1000	0x3F6	0x80	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16	Memory instructions retired above 16 clocks (Precise Event)	3	10000	0x3F6	0x10	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384	Memory instructions retired above 16384 clocks (Precise Event)	3	5	0x3F6	0x4000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048	Memory instructions retired above 2048 clocks (Precise Event)	3	50	0x3F6	0x800	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256	Memory instructions retired above 256 clocks (Precise Event)	3	500	0x3F6	0x100	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32	Memory instructions retired above 32 clocks (Precise Event)	3	5000	0x3F6	0x20	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768	Memory instructions retired above 32768 clocks (Precise Event)	3	3	0x3F6	0x8000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4	Memory instructions retired above 4 clocks (Precise Event)	3	50000	0x3F6	0x4	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096	Memory instructions retired above 4096 clocks (Precise Event)	3	20	0x3F6	0x1000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512	Memory instructions retired above 512 clocks (Precise Event)	3	200	0x3F6	0x200	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64	Memory instructions retired above 64 clocks (Precise Event)	3	2000	0x3F6	0x40	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8	Memory instructions retired above 8 clocks (Precise Event)	3	20000	0x3F6	0x8	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192	Memory instructions retired above 8192 clocks (Precise Event)	3	10	0x3F6	0x2000	0	0	0	0	2	
diff --git a/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_offcore_V1.tsv b/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_offcore_V1.tsv
new file mode 100644
index 0000000..92794bf
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EP-DP/WestmereEP-DP_offcore_V1.tsv
@@ -0,0 +1,479 @@
+# Performance Monitoring Events for Intel Xeon Processor 3600, 5600 series Based on the Westmere-EP Microarchitecture - V1
+# 12/13/2013 10:58:33 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM_0	REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS_0	REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION_0	REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO_0	REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE_0	REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x111	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x211	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x411	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_0	REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM_0	REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM_0	REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM_0	REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM_0	REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS_0	REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION_0	REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO_0	REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE_0	REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x144	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x244	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x444	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_0	REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM_0	REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM_0	REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM_0	REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x50ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM_0	REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7fff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x30ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS_0	REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf8ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION_0	REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xffff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO_0	REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x80ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE_0	REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x1ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x2ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x4ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_0	REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x7ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x10ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM_0	REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x40ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM_0	REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x8ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM_0	REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x20ff	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM_0	REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS_0	REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION_0	REQUEST = ANY RFO and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO_0	REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE_0	REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x122	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x222	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x422	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_0	REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM_0	REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM_0	REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM_0	REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM_0	REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS_0	REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ANY_LOCATION_0	REQUEST = CORE_WB and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO_0	REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE_0	REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x108	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x208	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x408	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_0	REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM_0	REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM_0	REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_DRAM_0	REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM_0	REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS_0	REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION_0	REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO_0	REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE_0	REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x177	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x277	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x477	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_0	REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM_0	REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM_0	REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM_0	REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM_0	REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS_0	REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION_0	REQUEST = DATA_IN and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO_0	REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE_0	REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x133	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x233	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x433	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_0	REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM_0	REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM_0	REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM_0	REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM_0	REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS_0	REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION_0	REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO_0	REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE_0	REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x103	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x203	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x403	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_0	REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM_0	REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM_0	REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM_0	REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM_0	REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS_0	REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION_0	REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO_0	REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE_0	REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x101	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x201	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x401	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_0	REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM_0	REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM_0	REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM_0	REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM_0	REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS_0	REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION_0	REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO_0	REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE_0	REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x104	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x204	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x404	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_0	REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM_0	REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM_0	REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM_0	REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM_0	REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS_0	REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION_0	REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO_0	REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE_0	REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x102	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x202	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x402	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_0	REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM_0	REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM_0	REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM_0	REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM_0	REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS_0	REQUEST = OTHER and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ANY_LOCATION_0	REQUEST = OTHER and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO_0	REQUEST = OTHER and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE_0	REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x180	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x280	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x480	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_0	REQUEST = OTHER and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM_0	REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM_0	REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_DRAM_0	REQUEST = OTHER and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM_0	REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f50	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS_0	REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf850	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION_0	REQUEST = PF_DATA and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff50	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO_0	REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE_0	REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x150	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x250	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x450	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_0	REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x750	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM_0	REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM_0	REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x850	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM_0	REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM_0	REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS_0	REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION_0	REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO_0	REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE_0	REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x110	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x210	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x410	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_0	REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM_0	REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM_0	REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM_0	REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM_0	REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS_0	REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION_0	REQUEST = PF_RFO and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO_0	REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE_0	REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x140	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x240	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x440	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_0	REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM_0	REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM_0	REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM_0	REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM_0	REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS_0	REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION_0	REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO_0	REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE_0	REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x120	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x220	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x420	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_0	REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM_0	REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM_0	REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM_0	REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x5070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM_0	REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM	2	100000	0x1A6	0x7f70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD_0	REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	2	100000	0x1A6	0x3070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS_0	REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS	2	100000	0x1A6	0xf870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION_0	REQUEST = PREFETCH and RESPONSE = ANY_LOCATION	2	100000	0x1A6	0xff70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO_0	REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO	2	100000	0x1A6	0x8070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE_0	REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	2	100000	0x1A6	0x170	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT_0	REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	2	100000	0x1A6	0x270	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM_0	REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	2	100000	0x1A6	0x470	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_0	REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE	2	100000	0x1A6	0x770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_0	REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	2	100000	0x1A6	0x1070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM_0	REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM	2	100000	0x1A6	0x4070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM_0	REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM	2	100000	0x1A6	0x870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM_0	REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM	2	100000	0x1A6	0x2070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM_1	REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f11	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS_1	REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf811	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION_1	REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff11	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO_1	REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE_1	REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x111	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x211	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x411	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_1	REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x711	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM_1	REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM_1	REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x811	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM_1	REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM_1	REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f44	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS_1	REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf844	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION_1	REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff44	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO_1	REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE_1	REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x144	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x244	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x444	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_1	REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x744	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM_1	REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM_1	REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x844	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM_1	REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x50ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM_1	REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7fff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x30ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS_1	REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf8ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION_1	REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xffff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO_1	REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x80ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE_1	REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x1ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x2ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x4ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_1	REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x7ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x10ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM_1	REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x40ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM_1	REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x8ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM_1	REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x20ff	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM_1	REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f22	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS_1	REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf822	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION_1	REQUEST = ANY RFO and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff22	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO_1	REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE_1	REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x122	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x222	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x422	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_1	REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x722	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM_1	REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM_1	REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x822	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM_1	REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM_1	REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f08	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS_1	REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf808	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ANY_LOCATION_1	REQUEST = CORE_WB and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff08	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO_1	REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE_1	REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x108	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x208	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x408	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_1	REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x708	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM_1	REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM_1	REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x808	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_DRAM_1	REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM_1	REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f77	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS_1	REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf877	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION_1	REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff77	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO_1	REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE_1	REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x177	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x277	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x477	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_1	REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x777	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM_1	REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM_1	REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x877	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM_1	REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM_1	REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f33	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS_1	REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf833	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION_1	REQUEST = DATA_IN and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff33	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO_1	REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE_1	REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x133	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x233	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x433	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_1	REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x733	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM_1	REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM_1	REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x833	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM_1	REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM_1	REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f03	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS_1	REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf803	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION_1	REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff03	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO_1	REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE_1	REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x103	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x203	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x403	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_1	REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x703	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM_1	REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM_1	REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x803	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM_1	REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM_1	REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f01	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS_1	REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf801	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION_1	REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff01	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO_1	REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE_1	REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x101	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x201	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x401	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_1	REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x701	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM_1	REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM_1	REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x801	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM_1	REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM_1	REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f04	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS_1	REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf804	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION_1	REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff04	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO_1	REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE_1	REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x104	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x204	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x404	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_1	REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x704	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM_1	REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM_1	REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x804	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM_1	REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM_1	REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f02	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS_1	REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf802	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION_1	REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff02	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO_1	REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE_1	REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x102	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x202	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x402	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_1	REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x702	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM_1	REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM_1	REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x802	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM_1	REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM_1	REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f80	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS_1	REQUEST = OTHER and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf880	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ANY_LOCATION_1	REQUEST = OTHER and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff80	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO_1	REQUEST = OTHER and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE_1	REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x180	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x280	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x480	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_1	REQUEST = OTHER and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x780	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM_1	REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM_1	REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x880	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_DRAM_1	REQUEST = OTHER and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM_1	REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f50	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS_1	REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf850	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION_1	REQUEST = PF_DATA and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff50	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO_1	REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE_1	REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x150	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x250	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x450	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_1	REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x750	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM_1	REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM_1	REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x850	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM_1	REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM_1	REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f10	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS_1	REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf810	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION_1	REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff10	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO_1	REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE_1	REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x110	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x210	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x410	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_1	REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x710	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM_1	REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM_1	REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x810	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM_1	REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM_1	REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f40	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS_1	REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf840	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION_1	REQUEST = PF_RFO and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff40	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO_1	REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE_1	REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x140	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x240	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x440	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_1	REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x740	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM_1	REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM_1	REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x840	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM_1	REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM_1	REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f20	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS_1	REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf820	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION_1	REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff20	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO_1	REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE_1	REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x120	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x220	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x420	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_1	REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x720	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM_1	REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM_1	REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x820	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM_1	REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x5070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM_1	REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM	1	100000	0x1A7	0x7f70	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD_1	REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD	1	100000	0x1A7	0x3070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS_1	REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS	1	100000	0x1A7	0xf870	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION_1	REQUEST = PREFETCH and RESPONSE = ANY_LOCATION	1	100000	0x1A7	0xff70	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO_1	REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO	1	100000	0x1A7	0x8070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE_1	REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE	1	100000	0x1A7	0x170	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT_1	REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT	1	100000	0x1A7	0x270	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM_1	REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM	1	100000	0x1A7	0x470	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_1	REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE	1	100000	0x1A7	0x770	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT_1	REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT	1	100000	0x1A7	0x1070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM_1	REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM	1	100000	0x1A7	0x4070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM_1	REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM	1	100000	0x1A7	0x870	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM_1	REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM	1	100000	0x1A7	0x2070	0	0	0	0	0	
diff --git a/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_core_V1.json b/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_core_V1.json
new file mode 100644
index 0000000..f5b9bf2
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_core_V1.json
@@ -0,0 +1,13570 @@
+[

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.CYCLES_DIV_BUSY",

+    "BriefDescription": "Cycles the divider is busy",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.DIV",

+    "BriefDescription": "Divide Operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x2",

+    "EventName": "ARITH.MUL",

+    "BriefDescription": "Multiply operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x2",

+    "EventName": "BACLEAR.BAD_TARGET",

+    "BriefDescription": "BACLEAR asserted with bad target address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1",

+    "EventName": "BACLEAR.CLEAR",

+    "BriefDescription": "BACLEAR asserted, regardless of cause ",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA7",

+    "UMask": "0x1",

+    "EventName": "BACLEAR_FORCE_IQ",

+    "BriefDescription": "Instruction queue forced BACLEAR",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x1",

+    "EventName": "BPU_CLEARS.EARLY",

+    "BriefDescription": "Early Branch Prediciton Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x2",

+    "EventName": "BPU_CLEARS.LATE",

+    "BriefDescription": "Late Branch Prediction Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE5",

+    "UMask": "0x1",

+    "EventName": "BPU_MISSED_CALL_RET",

+    "BriefDescription": "Branch prediction unit missed call or return",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE0",

+    "UMask": "0x1",

+    "EventName": "BR_INST_DECODED",

+    "BriefDescription": "Branch instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7F",

+    "EventName": "BR_INST_EXEC.ANY",

+    "BriefDescription": "Branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x1",

+    "EventName": "BR_INST_EXEC.COND",

+    "BriefDescription": "Conditional branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x2",

+    "EventName": "BR_INST_EXEC.DIRECT",

+    "BriefDescription": "Unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x10",

+    "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Unconditional call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x20",

+    "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x4",

+    "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x30",

+    "EventName": "BR_INST_EXEC.NEAR_CALLS",

+    "BriefDescription": "Call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7",

+    "EventName": "BR_INST_EXEC.NON_CALLS",

+    "BriefDescription": "All non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x8",

+    "EventName": "BR_INST_EXEC.RETURN_NEAR",

+    "BriefDescription": "Indirect return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x40",

+    "EventName": "BR_INST_EXEC.TAKEN",

+    "BriefDescription": "Taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x1",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Retired conditional branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Retired near call instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",

+    "BriefDescription": "Retired near call instructions Ring 3 only(Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7F",

+    "EventName": "BR_MISP_EXEC.ANY",

+    "BriefDescription": "Mispredicted branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x1",

+    "EventName": "BR_MISP_EXEC.COND",

+    "BriefDescription": "Mispredicted conditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_EXEC.DIRECT",

+    "BriefDescription": "Mispredicted unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x10",

+    "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Mispredicted indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x30",

+    "EventName": "BR_MISP_EXEC.NEAR_CALLS",

+    "BriefDescription": "Mispredicted call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7",

+    "EventName": "BR_MISP_EXEC.NON_CALLS",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x8",

+    "EventName": "BR_MISP_EXEC.RETURN_NEAR",

+    "BriefDescription": "Mispredicted return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x40",

+    "EventName": "BR_MISP_EXEC.TAKEN",

+    "BriefDescription": "Mispredicted taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x1",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_RETIRED.NEAR_CALL",

+    "BriefDescription": "Mispredicted near retired calls (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x2",

+    "EventName": "CACHE_LOCK_CYCLES.L1D",

+    "BriefDescription": "Cycles L1D locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x1",

+    "EventName": "CACHE_LOCK_CYCLES.L1D_L2",

+    "BriefDescription": "Cycles L1D and L2 locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.REF",

+    "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x1",

+    "EventName": "CPU_CLK_UNHALTED.REF_P",

+    "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 2",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",

+    "BriefDescription": "Total CPU cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "2",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x1",

+    "EventName": "DTLB_LOAD_MISSES.ANY",

+    "BriefDescription": "DTLB load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.PDE_MISS",

+    "BriefDescription": "DTLB load miss caused by low part of address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x2",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB load miss page walks complete",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x4",

+    "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",

+    "BriefDescription": "DTLB load miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x1",

+    "EventName": "DTLB_MISSES.ANY",

+    "BriefDescription": "DTLB misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x80",

+    "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",

+    "BriefDescription": "DTLB miss large page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB first level misses but second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x2",

+    "EventName": "DTLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x4",

+    "EventName": "DTLB_MISSES.WALK_CYCLES",

+    "BriefDescription": "DTLB miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4F",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Extended Page Table walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD5",

+    "UMask": "0x1",

+    "EventName": "ES_REG_RENAMES",

+    "BriefDescription": "ES segment renames",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x1",

+    "EventName": "FP_ASSIST.ALL",

+    "BriefDescription": "X87 Floating point assists (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x4",

+    "EventName": "FP_ASSIST.INPUT",

+    "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x2",

+    "EventName": "FP_ASSIST.OUTPUT",

+    "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x2",

+    "EventName": "FP_COMP_OPS_EXE.MMX",

+    "BriefDescription": "MMX Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",

+    "BriefDescription": "SSE* FP double precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x4",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP",

+    "BriefDescription": "SSE and SSE2 FP Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",

+    "BriefDescription": "SSE FP packed Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",

+    "BriefDescription": "SSE FP scalar Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",

+    "BriefDescription": "SSE* FP single precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x8",

+    "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",

+    "BriefDescription": "SSE2 integer Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x1",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Computational floating-point operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x3",

+    "EventName": "FP_MMX_TRANS.ANY",

+    "BriefDescription": "All Floating Point to and from MMX transitions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x1",

+    "EventName": "FP_MMX_TRANS.TO_FP",

+    "BriefDescription": "Transitions from MMX to Floating Point instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x2",

+    "EventName": "FP_MMX_TRANS.TO_MMX",

+    "BriefDescription": "Transitions from Floating Point to MMX instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0xF",

+    "EventName": "ILD_STALL.ANY",

+    "BriefDescription": "Any Instruction Length Decoder stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x4",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Instruction Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x1",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Length Change Prefix stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x2",

+    "EventName": "ILD_STALL.MRU",

+    "BriefDescription": "Stall cycles due to BPU MRU bypass",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x8",

+    "EventName": "ILD_STALL.REGEN",

+    "BriefDescription": "Regen stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x18",

+    "UMask": "0x1",

+    "EventName": "INST_DECODED.DEC0",

+    "BriefDescription": "Instructions that must be decoded by decoder 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x1E",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITE_CYCLES",

+    "BriefDescription": "Cycles instructions are written to the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x17",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITES",

+    "BriefDescription": "Instructions written to instruction queue.",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired (fixed counter)",

+    "Counter": "Fixed counter 1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x4",

+    "EventName": "INST_RETIRED.MMX",

+    "BriefDescription": "Retired MMX instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x2",

+    "EventName": "INST_RETIRED.X87",

+    "BriefDescription": "Retired floating-point operations (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6C",

+    "UMask": "0x1",

+    "EventName": "IO_TRANSACTIONS",

+    "BriefDescription": "I/O transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x1",

+    "EventName": "ITLB_FLUSH",

+    "BriefDescription": "ITLB flushes",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISS_RETIRED",

+    "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x1",

+    "EventName": "ITLB_MISSES.ANY",

+    "BriefDescription": "ITLB miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x2",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "ITLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x4",

+    "EventName": "ITLB_MISSES.WALK_CYCLES",

+    "BriefDescription": "ITLB miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x4",

+    "EventName": "L1D.M_EVICT",

+    "BriefDescription": "L1D cache lines replaced in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x2",

+    "EventName": "L1D.M_REPL",

+    "BriefDescription": "L1D cache lines allocated in the M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x8",

+    "EventName": "L1D.M_SNOOP_EVICT",

+    "BriefDescription": "L1D snoop eviction of cache lines in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x1",

+    "EventName": "L1D.REPL",

+    "BriefDescription": "L1 data cache lines allocated",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x52",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",

+    "BriefDescription": "L1D prefetch load lock accepted in fill buffer",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x2",

+    "EventName": "L1D_PREFETCH.MISS",

+    "BriefDescription": "L1D hardware prefetch misses",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x1",

+    "EventName": "L1D_PREFETCH.REQUESTS",

+    "BriefDescription": "L1D hardware prefetch requests",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x4",

+    "EventName": "L1D_PREFETCH.TRIGGERS",

+    "BriefDescription": "L1D hardware prefetch requests triggered",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x4",

+    "EventName": "L1D_WB_L2.E_STATE",

+    "BriefDescription": "L1 writebacks to L2 in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x1",

+    "EventName": "L1D_WB_L2.I_STATE",

+    "BriefDescription": "L1 writebacks to L2 in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x8",

+    "EventName": "L1D_WB_L2.M_STATE",

+    "BriefDescription": "L1 writebacks to L2 in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0xF",

+    "EventName": "L1D_WB_L2.MESI",

+    "BriefDescription": "All L1 writebacks to L2",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x2",

+    "EventName": "L1D_WB_L2.S_STATE",

+    "BriefDescription": "L1 writebacks to L2 in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x4",

+    "EventName": "L1I.CYCLES_STALLED",

+    "BriefDescription": "L1I instruction fetch stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x1",

+    "EventName": "L1I.HITS",

+    "BriefDescription": "L1I instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x2",

+    "EventName": "L1I.MISSES",

+    "BriefDescription": "L1I instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x3",

+    "EventName": "L1I.READS",

+    "BriefDescription": "L1I Instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xFF",

+    "EventName": "L2_DATA_RQSTS.ANY",

+    "BriefDescription": "All L2 data requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x4",

+    "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",

+    "BriefDescription": "L2 data demand loads in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x1",

+    "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",

+    "BriefDescription": "L2 data demand loads in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x8",

+    "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",

+    "BriefDescription": "L2 data demand loads in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF",

+    "EventName": "L2_DATA_RQSTS.DEMAND.MESI",

+    "BriefDescription": "L2 data demand requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x2",

+    "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",

+    "BriefDescription": "L2 data demand loads in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x40",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",

+    "BriefDescription": "L2 data prefetches in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x10",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",

+    "BriefDescription": "L2 data prefetches in the I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x80",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",

+    "BriefDescription": "L2 data prefetches in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF0",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",

+    "BriefDescription": "All L2 data prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x20",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",

+    "BriefDescription": "L2 data prefetches in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x7",

+    "EventName": "L2_LINES_IN.ANY",

+    "BriefDescription": "L2 lines alloacated",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_IN.E_STATE",

+    "BriefDescription": "L2 lines allocated in the E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_IN.S_STATE",

+    "BriefDescription": "L2 lines allocated in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0xF",

+    "EventName": "L2_LINES_OUT.ANY",

+    "BriefDescription": "L2 lines evicted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x1",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "L2 lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",

+    "BriefDescription": "L2 lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x8",

+    "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.IFETCH_HIT",

+    "BriefDescription": "L2 instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.IFETCH_MISS",

+    "BriefDescription": "L2 instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.IFETCHES",

+    "BriefDescription": "L2 instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x1",

+    "EventName": "L2_RQSTS.LD_HIT",

+    "BriefDescription": "L2 load hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x2",

+    "EventName": "L2_RQSTS.LD_MISS",

+    "BriefDescription": "L2 load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3",

+    "EventName": "L2_RQSTS.LOADS",

+    "BriefDescription": "L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xAA",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All L2 misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PREFETCH_HIT",

+    "BriefDescription": "L2 prefetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PREFETCH_MISS",

+    "BriefDescription": "L2 prefetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.PREFETCHES",

+    "BriefDescription": "All L2 prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x4",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "L2 RFO hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x8",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "L2 RFO misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC",

+    "EventName": "L2_RQSTS.RFOS",

+    "BriefDescription": "L2 RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANSACTIONS.ANY",

+    "BriefDescription": "All L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANSACTIONS.FILL",

+    "BriefDescription": "L2 fill transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x4",

+    "EventName": "L2_TRANSACTIONS.IFETCH",

+    "BriefDescription": "L2 instruction fetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANSACTIONS.L1D_WB",

+    "BriefDescription": "L1D writeback to L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x1",

+    "EventName": "L2_TRANSACTIONS.LOAD",

+    "BriefDescription": "L2 Load transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x8",

+    "EventName": "L2_TRANSACTIONS.PREFETCH",

+    "BriefDescription": "L2 prefetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x2",

+    "EventName": "L2_TRANSACTIONS.RFO",

+    "BriefDescription": "L2 RFO transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANSACTIONS.WB",

+    "BriefDescription": "L2 writeback to LLC transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x40",

+    "EventName": "L2_WRITE.LOCK.E_STATE",

+    "BriefDescription": "L2 demand lock RFOs in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE0",

+    "EventName": "L2_WRITE.LOCK.HIT",

+    "BriefDescription": "All demand L2 lock RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x10",

+    "EventName": "L2_WRITE.LOCK.I_STATE",

+    "BriefDescription": "L2 demand lock RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x80",

+    "EventName": "L2_WRITE.LOCK.M_STATE",

+    "BriefDescription": "L2 demand lock RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF0",

+    "EventName": "L2_WRITE.LOCK.MESI",

+    "BriefDescription": "All demand L2 lock RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x20",

+    "EventName": "L2_WRITE.LOCK.S_STATE",

+    "BriefDescription": "L2 demand lock RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE",

+    "EventName": "L2_WRITE.RFO.HIT",

+    "BriefDescription": "All L2 demand store RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x1",

+    "EventName": "L2_WRITE.RFO.I_STATE",

+    "BriefDescription": "L2 demand store RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x8",

+    "EventName": "L2_WRITE.RFO.M_STATE",

+    "BriefDescription": "L2 demand store RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF",

+    "EventName": "L2_WRITE.RFO.MESI",

+    "BriefDescription": "All L2 demand store RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x2",

+    "EventName": "L2_WRITE.RFO.S_STATE",

+    "BriefDescription": "L2 demand store RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x82",

+    "UMask": "0x1",

+    "EventName": "LARGE_ITLB.HIT",

+    "BriefDescription": "Large ITLB hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3",

+    "UMask": "0x2",

+    "EventName": "LOAD_BLOCK.OVERLAP_STORE",

+    "BriefDescription": "Loads that partially overlap an earlier store",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x7",

+    "EventName": "LOAD_DISPATCH.ANY",

+    "BriefDescription": "All loads dispatched",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x4",

+    "EventName": "LOAD_DISPATCH.MOB",

+    "BriefDescription": "Loads dispatched from the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x1",

+    "EventName": "LOAD_DISPATCH.RS",

+    "BriefDescription": "Loads dispatched that bypass the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x2",

+    "EventName": "LOAD_DISPATCH.RS_DELAYED",

+    "BriefDescription": "Loads dispatched from stage 305",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x1",

+    "EventName": "LOAD_HIT_PRE",

+    "BriefDescription": "Load operations conflicting with software prefetches",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Longest latency cache miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Longest latency cache reference",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.ACTIVE",

+    "BriefDescription": "Cycles when uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.INACTIVE",

+    "BriefDescription": "Cycles no uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x20",

+    "UMask": "0x1",

+    "EventName": "LSD_OVERFLOW",

+    "BriefDescription": "Loops that can't stream from the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x1",

+    "EventName": "MACHINE_CLEARS.CYCLES",

+    "BriefDescription": "Cycles machine clear asserted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x2",

+    "EventName": "MACHINE_CLEARS.MEM_ORDER",

+    "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x4",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-Modifying Code detected",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.DECODED",

+    "BriefDescription": "Instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.FUSIONS_DECODED",

+    "BriefDescription": "Macro-fused instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x1",

+    "EventName": "MEM_INST_RETIRED.LOADS",

+    "BriefDescription": "Instructions retired which contains a load (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x2",

+    "EventName": "MEM_INST_RETIRED.STORES",

+    "BriefDescription": "Instructions retired which contains a store (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x80",

+    "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x1",

+    "EventName": "MEM_LOAD_RETIRED.L1D_HIT",

+    "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x2",

+    "EventName": "MEM_LOAD_RETIRED.L2_HIT",

+    "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_RETIRED.LLC_MISS",

+    "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x4",

+    "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",

+    "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x8",

+    "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",

+    "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC",

+    "UMask": "0x1",

+    "EventName": "MEM_STORE_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x10",

+    "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",

+    "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x2",

+    "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",

+    "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x8",

+    "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",

+    "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x20",

+    "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",

+    "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x80",

+    "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",

+    "BriefDescription": "Load instructions retired IO (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "4000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x80",

+    "EventName": "OFFCORE_REQUESTS.ANY",

+    "BriefDescription": "All offcore requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS.ANY.READ",

+    "BriefDescription": "Offcore read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x10",

+    "EventName": "OFFCORE_REQUESTS.ANY.RFO",

+    "BriefDescription": "Offcore RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",

+    "BriefDescription": "Offcore demand code read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",

+    "BriefDescription": "Offcore demand data read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",

+    "BriefDescription": "Offcore demand RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x40",

+    "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",

+    "BriefDescription": "Offcore L1 data cache writebacks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x20",

+    "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM",

+    "BriefDescription": "Offcore uncached memory accesses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",

+    "BriefDescription": "Outstanding offcore reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore reads busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",

+    "BriefDescription": "Outstanding offcore demand code reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand code read busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",

+    "BriefDescription": "Outstanding offcore demand data reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand data read busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",

+    "BriefDescription": "Outstanding offcore demand RFOs",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand RFOs busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_SQ_FULL",

+    "BriefDescription": "Offcore requests blocked due to Super Queue full",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x7",

+    "UMask": "0x1",

+    "EventName": "PARTIAL_ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies due to partial address aliasing",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0xF",

+    "EventName": "RAT_STALLS.ANY",

+    "BriefDescription": "All RAT stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x1",

+    "EventName": "RAT_STALLS.FLAGS",

+    "BriefDescription": "Flag stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x2",

+    "EventName": "RAT_STALLS.REGISTERS",

+    "BriefDescription": "Partial register stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x4",

+    "EventName": "RAT_STALLS.ROB_READ_PORT",

+    "BriefDescription": "ROB read port stalls cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x8",

+    "EventName": "RAT_STALLS.SCOREBOARD",

+    "BriefDescription": "Scoreboard stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x1",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x20",

+    "EventName": "RESOURCE_STALLS.FPCW",

+    "BriefDescription": "FPU control word write stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x2",

+    "EventName": "RESOURCE_STALLS.LOAD",

+    "BriefDescription": "Load buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x40",

+    "EventName": "RESOURCE_STALLS.MXCSR",

+    "BriefDescription": "MXCSR rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x80",

+    "EventName": "RESOURCE_STALLS.OTHER",

+    "BriefDescription": "Other Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB_FULL",

+    "BriefDescription": "ROB full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x4",

+    "EventName": "RESOURCE_STALLS.RS_FULL",

+    "BriefDescription": "Reservation Station full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x8",

+    "EventName": "RESOURCE_STALLS.STORE",

+    "BriefDescription": "Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4",

+    "UMask": "0x7",

+    "EventName": "SB_DRAIN.ANY",

+    "BriefDescription": "All Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD4",

+    "UMask": "0x1",

+    "EventName": "SEG_RENAME_STALLS",

+    "BriefDescription": "Segment rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_128.PACK",

+    "BriefDescription": "128 bit SIMD integer pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_128.PACKED_ARITH",

+    "BriefDescription": "128 bit SIMD integer arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_128.PACKED_LOGICAL",

+    "BriefDescription": "128 bit SIMD integer logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_128.PACKED_MPY",

+    "BriefDescription": "128 bit SIMD integer multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_128.PACKED_SHIFT",

+    "BriefDescription": "128 bit SIMD integer shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_128.SHUFFLE_MOVE",

+    "BriefDescription": "128 bit SIMD integer shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_128.UNPACK",

+    "BriefDescription": "128 bit SIMD integer unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_64.PACK",

+    "BriefDescription": "SIMD integer 64 bit pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_64.PACKED_ARITH",

+    "BriefDescription": "SIMD integer 64 bit arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_64.PACKED_LOGICAL",

+    "BriefDescription": "SIMD integer 64 bit logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_64.PACKED_MPY",

+    "BriefDescription": "SIMD integer 64 bit packed multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_64.PACKED_SHIFT",

+    "BriefDescription": "SIMD integer 64 bit shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_64.SHUFFLE_MOVE",

+    "BriefDescription": "SIMD integer 64 bit shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_64.UNPACK",

+    "BriefDescription": "SIMD integer 64 bit unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x1",

+    "EventName": "SNOOP_RESPONSE.HIT",

+    "BriefDescription": "Thread responded HIT to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x2",

+    "EventName": "SNOOP_RESPONSE.HITE",

+    "BriefDescription": "Thread responded HITE to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x4",

+    "EventName": "SNOOP_RESPONSE.HITM",

+    "BriefDescription": "Thread responded HITM to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS.CODE",

+    "BriefDescription": "Snoop code requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS.DATA",

+    "BriefDescription": "Snoop data requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS.INVALIDATE",

+    "BriefDescription": "Snoop invalidate requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",

+    "BriefDescription": "Outstanding snoop code requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop code requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",

+    "BriefDescription": "Outstanding snoop data requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop data requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",

+    "BriefDescription": "Outstanding snoop invalidate requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop invalidate requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF6",

+    "UMask": "0x1",

+    "EventName": "SQ_FULL_STALL_CYCLES",

+    "BriefDescription": "Super Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x4",

+    "EventName": "SQ_MISC.LRU_HINTS",

+    "BriefDescription": "Super Queue LRU hints sent to LLC",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x10",

+    "EventName": "SQ_MISC.SPLIT_LOCK",

+    "BriefDescription": "Super Queue lock splits across a cache line",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x4",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",

+    "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x1",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",

+    "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x8",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",

+    "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x2",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",

+    "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x10",

+    "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",

+    "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x4",

+    "EventName": "STORE_BLOCKS.AT_RET",

+    "BriefDescription": "Loads delayed with at-Retirement block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x8",

+    "EventName": "STORE_BLOCKS.L1D_BLOCK",

+    "BriefDescription": "Cacheable loads delayed with L1D block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x19",

+    "UMask": "0x1",

+    "EventName": "TWO_UOP_INSTS_DECODED",

+    "BriefDescription": "Two Uop instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xDB",

+    "UMask": "0x1",

+    "EventName": "UOP_UNFUSION",

+    "BriefDescription": "Uop unfusions due to FP exceptions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x4",

+    "EventName": "UOPS_DECODED.ESP_FOLDING",

+    "BriefDescription": "Stack pointer instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x8",

+    "EventName": "UOPS_DECODED.ESP_SYNC",

+    "BriefDescription": "Stack pointer sync operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x2",

+    "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",

+    "BriefDescription": "Uops decoded by Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x1",

+    "EventName": "UOPS_DECODED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops are decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",

+    "BriefDescription": "Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",

+    "BriefDescription": "Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1",

+    "EventName": "UOPS_EXECUTED.PORT0",

+    "BriefDescription": "Uops executed on port 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015",

+    "BriefDescription": "Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x2",

+    "EventName": "UOPS_EXECUTED.PORT1",

+    "BriefDescription": "Uops executed on port 1",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x4",

+    "EventName": "UOPS_EXECUTED.PORT2_CORE",

+    "BriefDescription": "Uops executed on port 2 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED.PORT234_CORE",

+    "BriefDescription": "Uops issued on ports 2, 3 or 4",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x8",

+    "EventName": "UOPS_EXECUTED.PORT3_CORE",

+    "BriefDescription": "Uops executed on port 3 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED.PORT4_CORE",

+    "BriefDescription": "Uops executed on port 4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED.PORT5",

+    "BriefDescription": "Uops executed on port 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued on any thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",

+    "BriefDescription": "Cycles Uops were issued on either thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x2",

+    "EventName": "UOPS_ISSUED.FUSED",

+    "BriefDescription": "Fused Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops are being retired",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ANY",

+    "BriefDescription": "Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x4",

+    "EventName": "UOPS_RETIRED.MACRO_FUSED",

+    "BriefDescription": "Macro-fused Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x2",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles Uops are not retiring (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",

+    "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",

+    "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "100",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x400",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",

+    "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "1000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",

+    "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",

+    "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",

+    "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x800",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",

+    "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "500",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",

+    "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",

+    "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "3",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",

+    "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",

+    "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x1000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",

+    "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "200",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",

+    "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",

+    "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",

+    "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x2000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_0",

+    "BriefDescription": "Offcore data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION_0",

+    "BriefDescription": "All offcore data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x111",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x211",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x411",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_0",

+    "BriefDescription": "Offcore code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION_0",

+    "BriefDescription": "All offcore code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x144",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x244",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x444",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7FFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_0",

+    "BriefDescription": "Offcore requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x60FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION_0",

+    "BriefDescription": "All offcore requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFFFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x80FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x27FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x20FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x18FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x58FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x10FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x40FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_0",

+    "BriefDescription": "Offcore RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION_0",

+    "BriefDescription": "All offcore RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x122",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x222",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x422",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore writebacks to any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_0",

+    "BriefDescription": "Offcore writebacks to any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore writebacks that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION_0",

+    "BriefDescription": "All offcore writebacks",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x108",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x408",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore writebacks to the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore writebacks to the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore writebacks to the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore writebacks to a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore writebacks that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore writebacks that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore writebacks to a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore code or data read requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION_0",

+    "BriefDescription": "All offcore code or data read requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x177",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x277",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x477",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore request = all data, response = any cache_dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_0",

+    "BriefDescription": "Offcore request = all data, response = any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore request = all data, response = any LLC miss",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION_0",

+    "BriefDescription": "Offcore request = all data, response = any location",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x133",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x233",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x433",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore request = all data, response = local cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore request = all data, response = local cache or dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore request = all data, response = remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore request = all data, response = remote cache or dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_0",

+    "BriefDescription": "Offcore demand data requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore demand data requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION_0",

+    "BriefDescription": "All offcore demand data requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x103",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x203",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x403",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore demand data requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore demand data requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_0",

+    "BriefDescription": "Offcore demand data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore demand data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION_0",

+    "BriefDescription": "All offcore demand data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x101",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x201",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x401",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore demand data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore demand data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_0",

+    "BriefDescription": "Offcore demand code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore demand code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION_0",

+    "BriefDescription": "All offcore demand code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x104",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x204",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x404",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore demand code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore demand code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore demand RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION_0",

+    "BriefDescription": "All offcore demand RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x102",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x202",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x402",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_0",

+    "BriefDescription": "Offcore other requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore other requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION_0",

+    "BriefDescription": "All offcore other requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x180",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x280",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x480",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore other requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore other requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore other requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore other requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F50",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore prefetch data requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION_0",

+    "BriefDescription": "All offcore prefetch data requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF50",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x150",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x250",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x450",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x750",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2750",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore prefetch data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION_0",

+    "BriefDescription": "All offcore prefetch data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x110",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x210",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x410",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore prefetch code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION_0",

+    "BriefDescription": "All offcore prefetch code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x140",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x240",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x440",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION_0",

+    "BriefDescription": "All offcore prefetch RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x120",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x220",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x420",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS_0",

+    "BriefDescription": "Offcore prefetch requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION_0",

+    "BriefDescription": "All offcore prefetch requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x170",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x270",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x470",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x5870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT_0",

+    "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM_0",

+    "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM_0",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_1",

+    "BriefDescription": "Offcore data reads satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore data reads that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION_1",

+    "BriefDescription": "All offcore data reads",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x111",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x211",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x411",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore data reads satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore data reads satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore data reads that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore data reads that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore data reads satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_1",

+    "BriefDescription": "Offcore code reads satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore code reads that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION_1",

+    "BriefDescription": "All offcore code reads",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x144",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x244",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x444",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore code reads satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore code reads satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore code reads that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore code reads that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore code reads satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore requests satisfied by any cache or DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7FFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_1",

+    "BriefDescription": "Offcore requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x60FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION_1",

+    "BriefDescription": "All offcore requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFFFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x80FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x27FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore requests satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x20FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x18FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x58FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x10FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x40FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_1",

+    "BriefDescription": "Offcore RFO requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore RFO requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION_1",

+    "BriefDescription": "All offcore RFO requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x122",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x222",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x422",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore RFO requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore RFO requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore writebacks to any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_1",

+    "BriefDescription": "Offcore writebacks to any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore writebacks that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION_1",

+    "BriefDescription": "All offcore writebacks",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x108",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x408",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore writebacks to the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore writebacks to the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore writebacks to the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore writebacks to a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore writebacks that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore writebacks that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore writebacks to a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore code or data read requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION_1",

+    "BriefDescription": "All offcore code or data read requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x177",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x277",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x477",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore request = all data, response = any cache_dram",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_1",

+    "BriefDescription": "Offcore request = all data, response = any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore request = all data, response = any LLC miss",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION_1",

+    "BriefDescription": "Offcore request = all data, response = any location",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x133",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x233",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x433",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore request = all data, response = local cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore request = all data, response = local cache or dram",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore request = all data, response = remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore request = all data, response = remote cache or dram",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_1",

+    "BriefDescription": "Offcore demand data requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore demand data requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION_1",

+    "BriefDescription": "All offcore demand data requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x103",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x203",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x403",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore demand data requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore demand data requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_1",

+    "BriefDescription": "Offcore demand data reads satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore demand data reads that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION_1",

+    "BriefDescription": "All offcore demand data reads",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x101",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x201",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x401",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore demand data reads that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore demand data reads that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_1",

+    "BriefDescription": "Offcore demand code reads satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore demand code reads that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION_1",

+    "BriefDescription": "All offcore demand code reads",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x104",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x204",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x404",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore demand code reads that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore demand code reads that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore demand RFO requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION_1",

+    "BriefDescription": "All offcore demand RFO requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x102",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x202",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x402",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_1",

+    "BriefDescription": "Offcore other requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore other requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION_1",

+    "BriefDescription": "All offcore other requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x180",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x280",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x480",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore other requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore other requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore other requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore other requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F50",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore prefetch data requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION_1",

+    "BriefDescription": "All offcore prefetch data requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF50",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x150",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x250",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x450",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x750",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2750",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x850",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4050",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore prefetch data reads that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION_1",

+    "BriefDescription": "All offcore prefetch data reads",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x110",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x210",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x410",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore prefetch code reads that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION_1",

+    "BriefDescription": "All offcore prefetch code reads",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x140",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x240",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x440",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION_1",

+    "BriefDescription": "All offcore prefetch RFO requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x120",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x220",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x420",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x7F70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x6070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS_1",

+    "BriefDescription": "Offcore prefetch requests that missed the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xF870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION_1",

+    "BriefDescription": "All offcore prefetch requests",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0xFF70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x8070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x170",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x270",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x470",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x2070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x5870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT_1",

+    "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x1070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM_1",

+    "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xBB",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM_1",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",

+    "Counter": "1",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A7",

+    "MSRValue": "0x4070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_core_V1.tsv b/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_core_V1.tsv
new file mode 100644
index 0000000..13dfa27
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_core_V1.tsv
@@ -0,0 +1,311 @@
+# Performance Monitoring Events for Intel Xeon Processor 3600, 5600 series Based on the Westmere-EP Microarchitecture - V1
+# 12/13/2013 10:59:56 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0x14	0x1	ARITH.CYCLES_DIV_BUSY	Cycles the divider is busy	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x14	0x1	ARITH.DIV	Divide Operations executed	0,1,2,3	2000000	0	0	1	1	0	1	0	
+0x14	0x2	ARITH.MUL	Multiply operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x2	BACLEAR.BAD_TARGET	BACLEAR asserted with bad target address	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x1	BACLEAR.CLEAR	BACLEAR asserted, regardless of cause 	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA7	0x1	BACLEAR_FORCE_IQ	Instruction queue forced BACLEAR	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x1	BPU_CLEARS.EARLY	Early Branch Prediciton Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x2	BPU_CLEARS.LATE	Late Branch Prediction Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE5	0x1	BPU_MISSED_CALL_RET	Branch prediction unit missed call or return	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE0	0x1	BR_INST_DECODED	Branch instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x88	0x7F	BR_INST_EXEC.ANY	Branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x1	BR_INST_EXEC.COND	Conditional branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x2	BR_INST_EXEC.DIRECT	Unconditional branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x10	BR_INST_EXEC.DIRECT_NEAR_CALL	Unconditional call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x20	BR_INST_EXEC.INDIRECT_NEAR_CALL	Indirect call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x4	BR_INST_EXEC.INDIRECT_NON_CALL	Indirect non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x30	BR_INST_EXEC.NEAR_CALLS	Call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x7	BR_INST_EXEC.NON_CALLS	All non call branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x8	BR_INST_EXEC.RETURN_NEAR	Indirect return branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x40	BR_INST_EXEC.TAKEN	Taken branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x1	BR_INST_RETIRED.CONDITIONAL	Retired conditional branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL	Retired near call instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL_R3	Retired near call instructions Ring 3 only(Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x89	0x7F	BR_MISP_EXEC.ANY	Mispredicted branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x1	BR_MISP_EXEC.COND	Mispredicted conditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x2	BR_MISP_EXEC.DIRECT	Mispredicted unconditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x10	BR_MISP_EXEC.DIRECT_NEAR_CALL	Mispredicted non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x20	BR_MISP_EXEC.INDIRECT_NEAR_CALL	Mispredicted indirect call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x4	BR_MISP_EXEC.INDIRECT_NON_CALL	Mispredicted indirect non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x30	BR_MISP_EXEC.NEAR_CALLS	Mispredicted call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x7	BR_MISP_EXEC.NON_CALLS	Mispredicted non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x8	BR_MISP_EXEC.RETURN_NEAR	Mispredicted return branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x40	BR_MISP_EXEC.TAKEN	Mispredicted taken branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC5	0x4	BR_MISP_RETIRED.ALL_BRANCHES	Mispredicted retired branch instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC5	0x1	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional retired branches (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC5	0x2	BR_MISP_RETIRED.NEAR_CALL	Mispredicted near retired calls (Precise Event)	0,1,2,3	2000	0	0	0	0	0	0	1	
+0x63	0x2	CACHE_LOCK_CYCLES.L1D	Cycles L1D locked	0,1	2000000	0	0	0	0	0	0	0	
+0x63	0x1	CACHE_LOCK_CYCLES.L1D_L2	Cycles L1D and L2 locked	0,1	2000000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.REF	Reference cycles when thread is not halted (fixed counter)	Fixed counter 3	2000000	0	0	0	0	0	0	0	
+0x3C	0x1	CPU_CLK_UNHALTED.REF_P	Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.THREAD	Cycles when thread is not halted (fixed counter)	Fixed counter 2	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.THREAD_P	Cycles when thread is not halted (programmable counter)	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.TOTAL_CYCLES	Total CPU cycles	0,1,2,3	2000000	0	0	2	1	0	0	0	
+0x8	0x1	DTLB_LOAD_MISSES.ANY	DTLB load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x20	DTLB_LOAD_MISSES.PDE_MISS	DTLB load miss caused by low part of address	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x10	DTLB_LOAD_MISSES.STLB_HIT	DTLB second level hit	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x8	0x2	DTLB_LOAD_MISSES.WALK_COMPLETED	DTLB load miss page walks complete	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x4	DTLB_LOAD_MISSES.WALK_CYCLES	DTLB load miss page walk cycles	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x1	DTLB_MISSES.ANY	DTLB misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x80	DTLB_MISSES.LARGE_WALK_COMPLETED	DTLB miss large page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x10	DTLB_MISSES.STLB_HIT	DTLB first level misses but second level hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x2	DTLB_MISSES.WALK_COMPLETED	DTLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x4	DTLB_MISSES.WALK_CYCLES	DTLB miss page walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4F	0x10	EPT.WALK_CYCLES	Extended Page Table walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD5	0x1	ES_REG_RENAMES	ES segment renames	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF7	0x1	FP_ASSIST.ALL	X87 Floating point assists (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x4	FP_ASSIST.INPUT	X87 Floating poiint assists for invalid input value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x2	FP_ASSIST.OUTPUT	X87 Floating point assists for invalid output value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x10	0x2	FP_COMP_OPS_EXE.MMX	MMX Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x80	FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION	SSE* FP double precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x4	FP_COMP_OPS_EXE.SSE_FP	SSE and SSE2 FP Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x10	FP_COMP_OPS_EXE.SSE_FP_PACKED	SSE FP packed Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x20	FP_COMP_OPS_EXE.SSE_FP_SCALAR	SSE FP scalar Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x40	FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION	SSE* FP single precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x8	FP_COMP_OPS_EXE.SSE2_INTEGER	SSE2 integer Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x1	FP_COMP_OPS_EXE.X87	Computational floating-point operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x3	FP_MMX_TRANS.ANY	All Floating Point to and from MMX transitions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x1	FP_MMX_TRANS.TO_FP	Transitions from MMX to Floating Point instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x2	FP_MMX_TRANS.TO_MMX	Transitions from Floating Point to MMX instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0xF	ILD_STALL.ANY	Any Instruction Length Decoder stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x4	ILD_STALL.IQ_FULL	Instruction Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x1	ILD_STALL.LCP	Length Change Prefix stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x2	ILD_STALL.MRU	Stall cycles due to BPU MRU bypass	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x8	ILD_STALL.REGEN	Regen stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x18	0x1	INST_DECODED.DEC0	Instructions that must be decoded by decoder 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x1E	0x1	INST_QUEUE_WRITE_CYCLES	Cycles instructions are written to the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x17	0x1	INST_QUEUE_WRITES	Instructions written to instruction queue.	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x0	0x0	INST_RETIRED.ANY	Instructions retired (fixed counter)	Fixed counter 1	2000000	0	0	0	0	0	0	0	
+0xC0	0x1	INST_RETIRED.ANY_P	Instructions retired (Programmable counter and Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x4	INST_RETIRED.MMX	Retired MMX instructions (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x1	INST_RETIRED.TOTAL_CYCLES	Total cycles (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC0	0x2	INST_RETIRED.X87	Retired floating-point operations (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0x6C	0x1	IO_TRANSACTIONS	I/O transactions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xAE	0x1	ITLB_FLUSH	ITLB flushes	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC8	0x20	ITLB_MISS_RETIRED	Retired instructions that missed the ITLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x85	0x1	ITLB_MISSES.ANY	ITLB miss	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x2	ITLB_MISSES.WALK_COMPLETED	ITLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x4	ITLB_MISSES.WALK_CYCLES	ITLB miss page walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x51	0x4	L1D.M_EVICT	L1D cache lines replaced in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x2	L1D.M_REPL	L1D cache lines allocated in the M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x8	L1D.M_SNOOP_EVICT	L1D snoop eviction of cache lines in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x1	L1D.REPL	L1 data cache lines allocated	0,1	2000000	0	0	0	0	0	0	0	
+0x52	0x1	L1D_CACHE_PREFETCH_LOCK_FB_HIT	L1D prefetch load lock accepted in fill buffer	0,1	2000000	0	0	0	0	0	0	0	
+0x4E	0x2	L1D_PREFETCH.MISS	L1D hardware prefetch misses	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x1	L1D_PREFETCH.REQUESTS	L1D hardware prefetch requests	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x4	L1D_PREFETCH.TRIGGERS	L1D hardware prefetch requests triggered	0,1	200000	0	0	0	0	0	0	0	
+0x28	0x4	L1D_WB_L2.E_STATE	L1 writebacks to L2 in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x1	L1D_WB_L2.I_STATE	L1 writebacks to L2 in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x8	L1D_WB_L2.M_STATE	L1 writebacks to L2 in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0xF	L1D_WB_L2.MESI	All L1 writebacks to L2	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x2	L1D_WB_L2.S_STATE	L1 writebacks to L2 in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x80	0x4	L1I.CYCLES_STALLED	L1I instruction fetch stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x1	L1I.HITS	L1I instruction fetch hits	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x2	L1I.MISSES	L1I instruction fetch misses	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x3	L1I.READS	L1I Instruction fetches	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x26	0xFF	L2_DATA_RQSTS.ANY	All L2 data requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x4	L2_DATA_RQSTS.DEMAND.E_STATE	L2 data demand loads in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x1	L2_DATA_RQSTS.DEMAND.I_STATE	L2 data demand loads in I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x8	L2_DATA_RQSTS.DEMAND.M_STATE	L2 data demand loads in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF	L2_DATA_RQSTS.DEMAND.MESI	L2 data demand requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x2	L2_DATA_RQSTS.DEMAND.S_STATE	L2 data demand loads in S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x40	L2_DATA_RQSTS.PREFETCH.E_STATE	L2 data prefetches in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x10	L2_DATA_RQSTS.PREFETCH.I_STATE	L2 data prefetches in the I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x80	L2_DATA_RQSTS.PREFETCH.M_STATE	L2 data prefetches in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF0	L2_DATA_RQSTS.PREFETCH.MESI	All L2 data prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x20	L2_DATA_RQSTS.PREFETCH.S_STATE	L2 data prefetches in the S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF1	0x7	L2_LINES_IN.ANY	L2 lines alloacated	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x4	L2_LINES_IN.E_STATE	L2 lines allocated in the E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x2	L2_LINES_IN.S_STATE	L2 lines allocated in the S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0xF	L2_LINES_OUT.ANY	L2 lines evicted	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x1	L2_LINES_OUT.DEMAND_CLEAN	L2 lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x2	L2_LINES_OUT.DEMAND_DIRTY	L2 modified lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x4	L2_LINES_OUT.PREFETCH_CLEAN	L2 lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x8	L2_LINES_OUT.PREFETCH_DIRTY	L2 modified lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x24	0x10	L2_RQSTS.IFETCH_HIT	L2 instruction fetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x20	L2_RQSTS.IFETCH_MISS	L2 instruction fetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x30	L2_RQSTS.IFETCHES	L2 instruction fetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x1	L2_RQSTS.LD_HIT	L2 load hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x2	L2_RQSTS.LD_MISS	L2 load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x3	L2_RQSTS.LOADS	L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xAA	L2_RQSTS.MISS	All L2 misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x40	L2_RQSTS.PREFETCH_HIT	L2 prefetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x80	L2_RQSTS.PREFETCH_MISS	L2 prefetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC0	L2_RQSTS.PREFETCHES	All L2 prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x4	L2_RQSTS.RFO_HIT	L2 RFO hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x8	L2_RQSTS.RFO_MISS	L2 RFO misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC	L2_RQSTS.RFOS	L2 RFO requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x80	L2_TRANSACTIONS.ANY	All L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x20	L2_TRANSACTIONS.FILL	L2 fill transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x4	L2_TRANSACTIONS.IFETCH	L2 instruction fetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x10	L2_TRANSACTIONS.L1D_WB	L1D writeback to L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x1	L2_TRANSACTIONS.LOAD	L2 Load transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x8	L2_TRANSACTIONS.PREFETCH	L2 prefetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x2	L2_TRANSACTIONS.RFO	L2 RFO transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x40	L2_TRANSACTIONS.WB	L2 writeback to LLC transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x27	0x40	L2_WRITE.LOCK.E_STATE	L2 demand lock RFOs in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE0	L2_WRITE.LOCK.HIT	All demand L2 lock RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x10	L2_WRITE.LOCK.I_STATE	L2 demand lock RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x80	L2_WRITE.LOCK.M_STATE	L2 demand lock RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF0	L2_WRITE.LOCK.MESI	All demand L2 lock RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x20	L2_WRITE.LOCK.S_STATE	L2 demand lock RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE	L2_WRITE.RFO.HIT	All L2 demand store RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x1	L2_WRITE.RFO.I_STATE	L2 demand store RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x8	L2_WRITE.RFO.M_STATE	L2 demand store RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF	L2_WRITE.RFO.MESI	All L2 demand store RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x2	L2_WRITE.RFO.S_STATE	L2 demand store RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x82	0x1	LARGE_ITLB.HIT	Large ITLB hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x3	0x2	LOAD_BLOCK.OVERLAP_STORE	Loads that partially overlap an earlier store	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x13	0x7	LOAD_DISPATCH.ANY	All loads dispatched	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x4	LOAD_DISPATCH.MOB	Loads dispatched from the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x1	LOAD_DISPATCH.RS	Loads dispatched that bypass the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x2	LOAD_DISPATCH.RS_DELAYED	Loads dispatched from stage 305	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4C	0x1	LOAD_HIT_PRE	Load operations conflicting with software prefetches	0,1	200000	0	0	0	0	0	0	0	
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Longest latency cache miss	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Longest latency cache reference	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xA8	0x1	LSD.ACTIVE	Cycles when uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xA8	0x1	LSD.INACTIVE	Cycles no uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0x20	0x1	LSD_OVERFLOW	Loops that can't stream from the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC3	0x1	MACHINE_CLEARS.CYCLES	Cycles machine clear asserted	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x2	MACHINE_CLEARS.MEM_ORDER	Execution pipeline restart due to Memory ordering conflicts	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x4	MACHINE_CLEARS.SMC	Self-Modifying Code detected	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xD0	0x1	MACRO_INSTS.DECODED	Instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA6	0x1	MACRO_INSTS.FUSIONS_DECODED	Macro-fused instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB	0x1	MEM_INST_RETIRED.LOADS	Instructions retired which contains a load (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xB	0x2	MEM_INST_RETIRED.STORES	Instructions retired which contains a store (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x80	MEM_LOAD_RETIRED.DTLB_MISS	Retired loads that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x40	MEM_LOAD_RETIRED.HIT_LFB	Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x1	MEM_LOAD_RETIRED.L1D_HIT	Retired loads that hit the L1 data cache (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x2	MEM_LOAD_RETIRED.L2_HIT	Retired loads that hit the L2 cache (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x10	MEM_LOAD_RETIRED.LLC_MISS	Retired loads that miss the LLC cache (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xCB	0x4	MEM_LOAD_RETIRED.LLC_UNSHARED_HIT	Retired loads that hit valid versions in the LLC cache (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xCB	0x8	MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM	Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xC	0x1	MEM_STORE_RETIRED.DTLB_MISS	Retired stores that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xF	0x10	MEM_UNCORE_RETIRED.LOCAL_DRAM	Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xF	0x2	MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM	Load instructions retired that HIT modified data in sibling core (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xF	0x8	MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT	Load instructions retired remote cache HIT data source (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF	0x20	MEM_UNCORE_RETIRED.REMOTE_DRAM	Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xF	0x80	MEM_UNCORE_RETIRED.UNCACHEABLE	Load instructions retired IO (Precise Event)	0,1,2,3	4000	0	0	0	0	0	0	1	
+0xB0	0x80	OFFCORE_REQUESTS.ANY	All offcore requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x8	OFFCORE_REQUESTS.ANY.READ	Offcore read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x10	OFFCORE_REQUESTS.ANY.RFO	Offcore RFO requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x2	OFFCORE_REQUESTS.DEMAND.READ_CODE	Offcore demand code read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x1	OFFCORE_REQUESTS.DEMAND.READ_DATA	Offcore demand data read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x4	OFFCORE_REQUESTS.DEMAND.RFO	Offcore demand RFO requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x40	OFFCORE_REQUESTS.L1D_WRITEBACK	Offcore L1 data cache writebacks	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x20	OFFCORE_REQUESTS.UNCACHED_MEM	Offcore uncached memory accesses	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x60	0x8	OFFCORE_REQUESTS_OUTSTANDING.ANY.READ	Outstanding offcore reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x8	OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY	Cycles offcore reads busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x2	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE	Outstanding offcore demand code reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x2	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY	Cycles offcore demand code read busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x1	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA	Outstanding offcore demand data reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x1	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY	Cycles offcore demand data read busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x4	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO	Outstanding offcore demand RFOs	0	2000000	0	0	0	0	0	0	0	
+0x60	0x4	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY	Cycles offcore demand RFOs busy	0	2000000	0	0	1	0	0	0	0	
+0xB2	0x1	OFFCORE_REQUESTS_SQ_FULL	Offcore requests blocked due to Super Queue full	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x7	0x1	PARTIAL_ADDRESS_ALIAS	False dependencies due to partial address aliasing	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD2	0xF	RAT_STALLS.ANY	All RAT stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x1	RAT_STALLS.FLAGS	Flag stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x2	RAT_STALLS.REGISTERS	Partial register stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x4	RAT_STALLS.ROB_READ_PORT	ROB read port stalls cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x8	RAT_STALLS.SCOREBOARD	Scoreboard stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x1	RESOURCE_STALLS.ANY	Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x20	RESOURCE_STALLS.FPCW	FPU control word write stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x2	RESOURCE_STALLS.LOAD	Load buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x40	RESOURCE_STALLS.MXCSR	MXCSR rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x80	RESOURCE_STALLS.OTHER	Other Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x10	RESOURCE_STALLS.ROB_FULL	ROB full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x4	RESOURCE_STALLS.RS_FULL	Reservation Station full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x8	RESOURCE_STALLS.STORE	Store buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4	0x7	SB_DRAIN.ANY	All Store buffer stall cycles	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD4	0x1	SEG_RENAME_STALLS	Segment rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x12	0x4	SIMD_INT_128.PACK	128 bit SIMD integer pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x20	SIMD_INT_128.PACKED_ARITH	128 bit SIMD integer arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x10	SIMD_INT_128.PACKED_LOGICAL	128 bit SIMD integer logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x1	SIMD_INT_128.PACKED_MPY	128 bit SIMD integer multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x2	SIMD_INT_128.PACKED_SHIFT	128 bit SIMD integer shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x40	SIMD_INT_128.SHUFFLE_MOVE	128 bit SIMD integer shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x8	SIMD_INT_128.UNPACK	128 bit SIMD integer unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x4	SIMD_INT_64.PACK	SIMD integer 64 bit pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x20	SIMD_INT_64.PACKED_ARITH	SIMD integer 64 bit arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x10	SIMD_INT_64.PACKED_LOGICAL	SIMD integer 64 bit logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x1	SIMD_INT_64.PACKED_MPY	SIMD integer 64 bit packed multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x2	SIMD_INT_64.PACKED_SHIFT	SIMD integer 64 bit shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x40	SIMD_INT_64.SHUFFLE_MOVE	SIMD integer 64 bit shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x8	SIMD_INT_64.UNPACK	SIMD integer 64 bit unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xB8	0x1	SNOOP_RESPONSE.HIT	Thread responded HIT to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x2	SNOOP_RESPONSE.HITE	Thread responded HITE to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x4	SNOOP_RESPONSE.HITM	Thread responded HITM to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x4	SNOOPQ_REQUESTS.CODE	Snoop code requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x1	SNOOPQ_REQUESTS.DATA	Snoop data requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x2	SNOOPQ_REQUESTS.INVALIDATE	Snoop invalidate requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB3	0x4	SNOOPQ_REQUESTS_OUTSTANDING.CODE	Outstanding snoop code requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x4	SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY	Cycles snoop code requests queued	0	2000000	0	0	1	0	0	0	0	
+0xB3	0x1	SNOOPQ_REQUESTS_OUTSTANDING.DATA	Outstanding snoop data requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x1	SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY	Cycles snoop data requests queued	0	2000000	0	0	1	0	0	0	0	
+0xB3	0x2	SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE	Outstanding snoop invalidate requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x2	SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY	Cycles snoop invalidate requests queued	0	2000000	0	0	1	0	0	0	0	
+0xF6	0x1	SQ_FULL_STALL_CYCLES	Super Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF4	0x4	SQ_MISC.LRU_HINTS	Super Queue LRU hints sent to LLC	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF4	0x10	SQ_MISC.SPLIT_LOCK	Super Queue lock splits across a cache line	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC7	0x4	SSEX_UOPS_RETIRED.PACKED_DOUBLE	SIMD Packed-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x1	SSEX_UOPS_RETIRED.PACKED_SINGLE	SIMD Packed-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x8	SSEX_UOPS_RETIRED.SCALAR_DOUBLE	SIMD Scalar-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x2	SSEX_UOPS_RETIRED.SCALAR_SINGLE	SIMD Scalar-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x10	SSEX_UOPS_RETIRED.VECTOR_INTEGER	SIMD Vector Integer Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x6	0x4	STORE_BLOCKS.AT_RET	Loads delayed with at-Retirement block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x6	0x8	STORE_BLOCKS.L1D_BLOCK	Cacheable loads delayed with L1D block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x19	0x1	TWO_UOP_INSTS_DECODED	Two Uop instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xDB	0x1	UOP_UNFUSION	Uop unfusions due to FP exceptions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x4	UOPS_DECODED.ESP_FOLDING	Stack pointer instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x8	UOPS_DECODED.ESP_SYNC	Stack pointer sync operations	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x2	UOPS_DECODED.MS_CYCLES_ACTIVE	Uops decoded by Microcode Sequencer	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xD1	0x1	UOPS_DECODED.STALL_CYCLES	Cycles no Uops are decoded	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES	Cycles Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5	Cycles Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_COUNT	Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	1	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5	Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	1	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_CYCLES	Cycles no Uops issued on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5	Cycles no Uops issued on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1	UOPS_EXECUTED.PORT0	Uops executed on port 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015	Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015_STALL_CYCLES	Cycles no Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x2	UOPS_EXECUTED.PORT1	Uops executed on port 1	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x4	UOPS_EXECUTED.PORT2_CORE	Uops executed on port 2 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x80	UOPS_EXECUTED.PORT234_CORE	Uops issued on ports 2, 3 or 4	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x8	UOPS_EXECUTED.PORT3_CORE	Uops executed on port 3 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x10	UOPS_EXECUTED.PORT4_CORE	Uops executed on port 4 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x20	UOPS_EXECUTED.PORT5	Uops executed on port 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.ANY	Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles no Uops were issued on any thread	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xE	0x1	UOPS_ISSUED.CYCLES_ALL_THREADS	Cycles Uops were issued on either thread	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xE	0x2	UOPS_ISSUED.FUSED	Fused Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.STALL_CYCLES	Cycles no Uops were issued	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xC2	0x1	UOPS_RETIRED.ACTIVE_CYCLES	Cycles Uops are being retired	0,1,2,3	2000000	0	0	1	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.ANY	Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x4	UOPS_RETIRED.MACRO_FUSED	Macro-fused Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x2	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.STALL_CYCLES	Cycles Uops are not retiring (Precise Event)	0,1,2,3	2000000	0	0	1	1	0	0	1	
+0xC2	0x1	UOPS_RETIRED.TOTAL_CYCLES	Total cycles using precise uop retired event (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC5	0x4	BR_MISP_RETIRED.ALL_BRANCHES	Mispredicted retired branch instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0	Memory instructions retired above 0 clocks (Precise Event)	3	2000000	0x3F6	0x0	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024	Memory instructions retired above 1024 clocks (Precise Event)	3	100	0x3F6	0x400	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128	Memory instructions retired above 128 clocks (Precise Event)	3	1000	0x3F6	0x80	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16	Memory instructions retired above 16 clocks (Precise Event)	3	10000	0x3F6	0x10	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384	Memory instructions retired above 16384 clocks (Precise Event)	3	5	0x3F6	0x4000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048	Memory instructions retired above 2048 clocks (Precise Event)	3	50	0x3F6	0x800	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256	Memory instructions retired above 256 clocks (Precise Event)	3	500	0x3F6	0x100	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32	Memory instructions retired above 32 clocks (Precise Event)	3	5000	0x3F6	0x20	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768	Memory instructions retired above 32768 clocks (Precise Event)	3	3	0x3F6	0x8000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4	Memory instructions retired above 4 clocks (Precise Event)	3	50000	0x3F6	0x4	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096	Memory instructions retired above 4096 clocks (Precise Event)	3	20	0x3F6	0x1000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512	Memory instructions retired above 512 clocks (Precise Event)	3	200	0x3F6	0x200	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64	Memory instructions retired above 64 clocks (Precise Event)	3	2000	0x3F6	0x40	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8	Memory instructions retired above 8 clocks (Precise Event)	3	20000	0x3F6	0x8	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192	Memory instructions retired above 8192 clocks (Precise Event)	3	10	0x3F6	0x2000	0	0	0	0	2	
diff --git a/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_offcore_V1.tsv b/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_offcore_V1.tsv
new file mode 100644
index 0000000..6db467e
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EP-SP/WestmereEP-SP_offcore_V1.tsv
@@ -0,0 +1,543 @@
+# Performance Monitoring Events for Intel Xeon Processor 3600, 5600 series Based on the Westmere-EP Microarchitecture - V1
+# 12/13/2013 10:59:56 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM_0	Offcore data reads satisfied by any cache or DRAM	2	100000	0x1A6	0x7F11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_0	Offcore data reads satisfied by any DRAM	2	100000	0x1A6	0x6011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS_0	Offcore data reads that missed the LLC	2	100000	0x1A6	0xF811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION_0	All offcore data reads	2	100000	0x1A6	0xFF11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO_0	Offcore data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE_0	Offcore data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x111	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT_0	Offcore data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x211	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM_0	Offcore data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x411	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_0	Offcore data reads satisfied by the LLC	2	100000	0x1A6	0x711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM_0	Offcore data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_0	Offcore data reads satisfied by the local DRAM	2	100000	0x1A6	0x2011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_0	Offcore data reads satisfied by a remote cache	2	100000	0x1A6	0x1811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM_0	Offcore data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT_0	Offcore data reads that HIT in a remote cache	2	100000	0x1A6	0x1011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM_0	Offcore data reads that HITM in a remote cache	2	100000	0x1A6	0x811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM_0	Offcore data reads satisfied by a remote DRAM	2	100000	0x1A6	0x4011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM_0	Offcore code reads satisfied by any cache or DRAM	2	100000	0x1A6	0x7F44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_0	Offcore code reads satisfied by any DRAM	2	100000	0x1A6	0x6044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS_0	Offcore code reads that missed the LLC	2	100000	0x1A6	0xF844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION_0	All offcore code reads	2	100000	0x1A6	0xFF44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO_0	Offcore code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE_0	Offcore code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x144	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT_0	Offcore code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x244	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM_0	Offcore code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x444	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_0	Offcore code reads satisfied by the LLC	2	100000	0x1A6	0x744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM_0	Offcore code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_0	Offcore code reads satisfied by the local DRAM	2	100000	0x1A6	0x2044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_0	Offcore code reads satisfied by a remote cache	2	100000	0x1A6	0x1844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM_0	Offcore code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT_0	Offcore code reads that HIT in a remote cache	2	100000	0x1A6	0x1044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM_0	Offcore code reads that HITM in a remote cache	2	100000	0x1A6	0x844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM_0	Offcore code reads satisfied by a remote DRAM	2	100000	0x1A6	0x4044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM_0	Offcore requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7FFF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_0	Offcore requests satisfied by any DRAM	2	100000	0x1A6	0x60FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS_0	Offcore requests that missed the LLC	2	100000	0x1A6	0xF8FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION_0	All offcore requests	2	100000	0x1A6	0xFFFF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO_0	Offcore requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x80FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE_0	Offcore requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x1FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT_0	Offcore requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x2FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM_0	Offcore requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x4FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_0	Offcore requests satisfied by the LLC	2	100000	0x1A6	0x7FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM_0	Offcore requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x27FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_0	Offcore requests satisfied by the local DRAM	2	100000	0x1A6	0x20FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_0	Offcore requests satisfied by a remote cache	2	100000	0x1A6	0x18FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM_0	Offcore requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x58FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT_0	Offcore requests that HIT in a remote cache	2	100000	0x1A6	0x10FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM_0	Offcore requests that HITM in a remote cache	2	100000	0x1A6	0x8FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM_0	Offcore requests satisfied by a remote DRAM	2	100000	0x1A6	0x40FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM_0	Offcore RFO requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_0	Offcore RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS_0	Offcore RFO requests that missed the LLC	2	100000	0x1A6	0xF822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION_0	All offcore RFO requests	2	100000	0x1A6	0xFF22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO_0	Offcore RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE_0	Offcore RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x122	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT_0	Offcore RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x222	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM_0	Offcore RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x422	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_0	Offcore RFO requests satisfied by the LLC	2	100000	0x1A6	0x722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM_0	Offcore RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_0	Offcore RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x2022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_0	Offcore RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM_0	Offcore RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT_0	Offcore RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM_0	Offcore RFO requests that HITM in a remote cache	2	100000	0x1A6	0x822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM_0	Offcore RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x4022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM_0	Offcore writebacks to any cache or DRAM.	2	100000	0x1A6	0x7F08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ANY_DRAM_0	Offcore writebacks to any DRAM	2	100000	0x1A6	0x6008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS_0	Offcore writebacks that missed the LLC	2	100000	0x1A6	0xF808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.ANY_LOCATION_0	All offcore writebacks	2	100000	0x1A6	0xFF08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO_0	Offcore writebacks to the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE_0	Offcore writebacks to the LLC and not found in a sibling core	2	100000	0x1A6	0x108	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM_0	Offcore writebacks to the LLC  and HITM in a sibling core	2	100000	0x1A6	0x408	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_0	Offcore writebacks to the LLC	2	100000	0x1A6	0x708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM_0	Offcore writebacks to the LLC or local DRAM	2	100000	0x1A6	0x2708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_0	Offcore writebacks to the local DRAM	2	100000	0x1A6	0x2008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_0	Offcore writebacks to a remote cache	2	100000	0x1A6	0x1808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM_0	Offcore writebacks to a remote cache or remote DRAM	2	100000	0x1A6	0x5808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT_0	Offcore writebacks that HIT in a remote cache	2	100000	0x1A6	0x1008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM_0	Offcore writebacks that HITM in a remote cache	2	100000	0x1A6	0x808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_DRAM_0	Offcore writebacks to a remote DRAM	2	100000	0x1A6	0x4008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM_0	Offcore code or data read requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_0	Offcore code or data read requests satisfied by any DRAM	2	100000	0x1A6	0x6077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS_0	Offcore code or data read requests that missed the LLC	2	100000	0x1A6	0xF877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION_0	All offcore code or data read requests	2	100000	0x1A6	0xFF77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO_0	Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE_0	Offcore code or data read requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x177	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT_0	Offcore code or data read requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x277	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM_0	Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x477	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_0	Offcore code or data read requests satisfied by the LLC	2	100000	0x1A6	0x777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM_0	Offcore code or data read requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_0	Offcore code or data read requests satisfied by the local DRAM	2	100000	0x1A6	0x2077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_0	Offcore code or data read requests satisfied by a remote cache	2	100000	0x1A6	0x1877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM_0	Offcore code or data read requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT_0	Offcore code or data read requests that HIT in a remote cache	2	100000	0x1A6	0x1077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM_0	Offcore code or data read requests that HITM in a remote cache	2	100000	0x1A6	0x877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM_0	Offcore code or data read requests satisfied by a remote DRAM	2	100000	0x1A6	0x4077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM_0	Offcore request = all data, response = any cache_dram	2	100000	0x1A6	0x7F33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_0	Offcore request = all data, response = any DRAM	2	100000	0x1A6	0x6033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS_0	Offcore request = all data, response = any LLC miss	2	100000	0x1A6	0xF833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION_0	Offcore request = all data, response = any location	2	100000	0x1A6	0xFF33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO_0	Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE_0	Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x133	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT_0	Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x233	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM_0	Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x433	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_0	Offcore request = all data, response = local cache	2	100000	0x1A6	0x733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM_0	Offcore request = all data, response = local cache or dram	2	100000	0x1A6	0x2733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_0	Offcore data reads, RFO's and prefetches statisfied by the local DRAM.	2	100000	0x1A6	0x2033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_0	Offcore request = all data, response = remote cache	2	100000	0x1A6	0x1833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM_0	Offcore request = all data, response = remote cache or dram	2	100000	0x1A6	0x5833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT_0	Offcore data reads, RFO's and prefetches that HIT in a remote cache 	2	100000	0x1A6	0x1033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM_0	Offcore data reads, RFO's and prefetches that HITM in a remote cache	2	100000	0x1A6	0x833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM_0	Offcore data reads, RFO's and prefetches statisfied by the remote DRAM	2	100000	0x1A6	0x4033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM_0	Offcore demand data requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_0	Offcore demand data requests satisfied by any DRAM	2	100000	0x1A6	0x6003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS_0	Offcore demand data requests that missed the LLC	2	100000	0x1A6	0xF803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION_0	All offcore demand data requests	2	100000	0x1A6	0xFF03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO_0	Offcore demand data requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE_0	Offcore demand data requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x103	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT_0	Offcore demand data requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x203	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM_0	Offcore demand data requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x403	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_0	Offcore demand data requests satisfied by the LLC	2	100000	0x1A6	0x703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM_0	Offcore demand data requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_0	Offcore demand data requests satisfied by the local DRAM	2	100000	0x1A6	0x2003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_0	Offcore demand data requests satisfied by a remote cache	2	100000	0x1A6	0x1803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM_0	Offcore demand data requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT_0	Offcore demand data requests that HIT in a remote cache	2	100000	0x1A6	0x1003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM_0	Offcore demand data requests that HITM in a remote cache	2	100000	0x1A6	0x803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM_0	Offcore demand data requests satisfied by a remote DRAM	2	100000	0x1A6	0x4003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM_0	Offcore demand data reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_0	Offcore demand data reads satisfied by any DRAM	2	100000	0x1A6	0x6001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS_0	Offcore demand data reads that missed the LLC	2	100000	0x1A6	0xF801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION_0	All offcore demand data reads	2	100000	0x1A6	0xFF01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO_0	Offcore demand data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE_0	Offcore demand data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x101	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT_0	Offcore demand data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x201	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM_0	Offcore demand data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x401	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_0	Offcore demand data reads satisfied by the LLC	2	100000	0x1A6	0x701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM_0	Offcore demand data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_0	Offcore demand data reads satisfied by the local DRAM	2	100000	0x1A6	0x2001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_0	Offcore demand data reads satisfied by a remote cache	2	100000	0x1A6	0x1801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM_0	Offcore demand data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT_0	Offcore demand data reads that HIT in a remote cache	2	100000	0x1A6	0x1001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM_0	Offcore demand data reads that HITM in a remote cache	2	100000	0x1A6	0x801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM_0	Offcore demand data reads satisfied by a remote DRAM	2	100000	0x1A6	0x4001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM_0	Offcore demand code reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_0	Offcore demand code reads satisfied by any DRAM	2	100000	0x1A6	0x6004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS_0	Offcore demand code reads that missed the LLC	2	100000	0x1A6	0xF804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION_0	All offcore demand code reads	2	100000	0x1A6	0xFF04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO_0	Offcore demand code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE_0	Offcore demand code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x104	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT_0	Offcore demand code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x204	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM_0	Offcore demand code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x404	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_0	Offcore demand code reads satisfied by the LLC	2	100000	0x1A6	0x704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM_0	Offcore demand code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_0	Offcore demand code reads satisfied by the local DRAM	2	100000	0x1A6	0x2004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_0	Offcore demand code reads satisfied by a remote cache	2	100000	0x1A6	0x1804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM_0	Offcore demand code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT_0	Offcore demand code reads that HIT in a remote cache	2	100000	0x1A6	0x1004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM_0	Offcore demand code reads that HITM in a remote cache	2	100000	0x1A6	0x804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM_0	Offcore demand code reads satisfied by a remote DRAM	2	100000	0x1A6	0x4004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM_0	Offcore demand RFO requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_0	Offcore demand RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS_0	Offcore demand RFO requests that missed the LLC	2	100000	0x1A6	0xF802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION_0	All offcore demand RFO requests	2	100000	0x1A6	0xFF02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO_0	Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE_0	Offcore demand RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x102	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT_0	Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x202	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM_0	Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x402	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_0	Offcore demand RFO requests satisfied by the LLC	2	100000	0x1A6	0x702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM_0	Offcore demand RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_0	Offcore demand RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x2002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_0	Offcore demand RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM_0	Offcore demand RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT_0	Offcore demand RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM_0	Offcore demand RFO requests that HITM in a remote cache	2	100000	0x1A6	0x802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM_0	Offcore demand RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x4002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM_0	Offcore other requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ANY_DRAM_0	Offcore other requests satisfied by any DRAM	2	100000	0x1A6	0x6080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS_0	Offcore other requests that missed the LLC	2	100000	0x1A6	0xF880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.ANY_LOCATION_0	All offcore other requests	2	100000	0x1A6	0xFF80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO_0	Offcore other requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE_0	Offcore other requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x180	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT_0	Offcore other requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x280	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM_0	Offcore other requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x480	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_0	Offcore other requests satisfied by the LLC	2	100000	0x1A6	0x780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM_0	Offcore other requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_0	Offcore other requests satisfied by a remote cache	2	100000	0x1A6	0x1880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM_0	Offcore other requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT_0	Offcore other requests that HIT in a remote cache	2	100000	0x1A6	0x1080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM_0	Offcore other requests that HITM in a remote cache	2	100000	0x1A6	0x880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_DRAM_0	Offcore other requests satisfied by a remote DRAM	2	100000	0x1A6	0x4080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM_0	Offcore prefetch data requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F50	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_0	Offcore prefetch data requests satisfied by any DRAM	2	100000	0x1A6	0x6050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS_0	Offcore prefetch data requests that missed the LLC	2	100000	0x1A6	0xF850	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION_0	All offcore prefetch data requests	2	100000	0x1A6	0xFF50	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO_0	Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE_0	Offcore prefetch data requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x150	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT_0	Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x250	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM_0	Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x450	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_0	Offcore prefetch data requests satisfied by the LLC	2	100000	0x1A6	0x750	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM_0	Offcore prefetch data requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2750	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_0	Offcore prefetch data requests satisfied by the local DRAM	2	100000	0x1A6	0x2050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_0	Offcore prefetch data requests satisfied by a remote cache	2	100000	0x1A6	0x1850	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM_0	Offcore prefetch data requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5850	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT_0	Offcore prefetch data requests that HIT in a remote cache	2	100000	0x1A6	0x1050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM_0	Offcore prefetch data requests that HITM in a remote cache	2	100000	0x1A6	0x850	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM_0	Offcore prefetch data requests satisfied by a remote DRAM	2	100000	0x1A6	0x4050	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM_0	Offcore prefetch data reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_0	Offcore prefetch data reads satisfied by any DRAM	2	100000	0x1A6	0x6010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS_0	Offcore prefetch data reads that missed the LLC	2	100000	0x1A6	0xF810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION_0	All offcore prefetch data reads	2	100000	0x1A6	0xFF10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO_0	Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE_0	Offcore prefetch data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x110	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT_0	Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x210	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM_0	Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x410	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_0	Offcore prefetch data reads satisfied by the LLC	2	100000	0x1A6	0x710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM_0	Offcore prefetch data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_0	Offcore prefetch data reads satisfied by the local DRAM	2	100000	0x1A6	0x2010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_0	Offcore prefetch data reads satisfied by a remote cache	2	100000	0x1A6	0x1810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM_0	Offcore prefetch data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT_0	Offcore prefetch data reads that HIT in a remote cache	2	100000	0x1A6	0x1010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM_0	Offcore prefetch data reads that HITM in a remote cache	2	100000	0x1A6	0x810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM_0	Offcore prefetch data reads satisfied by a remote DRAM	2	100000	0x1A6	0x4010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM_0	Offcore prefetch code reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_0	Offcore prefetch code reads satisfied by any DRAM	2	100000	0x1A6	0x6040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS_0	Offcore prefetch code reads that missed the LLC	2	100000	0x1A6	0xF840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION_0	All offcore prefetch code reads	2	100000	0x1A6	0xFF40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO_0	Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE_0	Offcore prefetch code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x140	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT_0	Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x240	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM_0	Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x440	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_0	Offcore prefetch code reads satisfied by the LLC	2	100000	0x1A6	0x740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM_0	Offcore prefetch code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_0	Offcore prefetch code reads satisfied by the local DRAM	2	100000	0x1A6	0x2040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_0	Offcore prefetch code reads satisfied by a remote cache	2	100000	0x1A6	0x1840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM_0	Offcore prefetch code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT_0	Offcore prefetch code reads that HIT in a remote cache	2	100000	0x1A6	0x1040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM_0	Offcore prefetch code reads that HITM in a remote cache	2	100000	0x1A6	0x840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM_0	Offcore prefetch code reads satisfied by a remote DRAM	2	100000	0x1A6	0x4040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM_0	Offcore prefetch RFO requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_0	Offcore prefetch RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS_0	Offcore prefetch RFO requests that missed the LLC	2	100000	0x1A6	0xF820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION_0	All offcore prefetch RFO requests	2	100000	0x1A6	0xFF20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO_0	Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE_0	Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x120	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT_0	Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x220	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM_0	Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x420	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_0	Offcore prefetch RFO requests satisfied by the LLC	2	100000	0x1A6	0x720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM_0	Offcore prefetch RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_0	Offcore prefetch RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x2020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_0	Offcore prefetch RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM_0	Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT_0	Offcore prefetch RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM_0	Offcore prefetch RFO requests that HITM in a remote cache	2	100000	0x1A6	0x820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM_0	Offcore prefetch RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x4020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM_0	Offcore prefetch requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_0	Offcore prefetch requests satisfied by any DRAM	2	100000	0x1A6	0x6070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS_0	Offcore prefetch requests that missed the LLC	2	100000	0x1A6	0xF870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION_0	All offcore prefetch requests	2	100000	0x1A6	0xFF70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO_0	Offcore prefetch requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE_0	Offcore prefetch requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x170	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT_0	Offcore prefetch requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x270	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM_0	Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x470	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_0	Offcore prefetch requests satisfied by the LLC	2	100000	0x1A6	0x770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM_0	Offcore prefetch requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x2770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_0	Offcore prefetch requests satisfied by the local DRAM	2	100000	0x1A6	0x2070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_0	Offcore prefetch requests satisfied by a remote cache	2	100000	0x1A6	0x1870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM_0	Offcore prefetch requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x5870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT_0	Offcore prefetch requests that HIT in a remote cache	2	100000	0x1A6	0x1070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM_0	Offcore prefetch requests that HITM in a remote cache	2	100000	0x1A6	0x870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM_0	Offcore prefetch requests satisfied by a remote DRAM	2	100000	0x1A6	0x4070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM_1	Offcore data reads satisfied by any cache or DRAM	1	100000	0x1A7	0x7F11	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_1	Offcore data reads satisfied by any DRAM	1	100000	0x1A7	0x6011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS_1	Offcore data reads that missed the LLC	1	100000	0x1A7	0xF811	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION_1	All offcore data reads	1	100000	0x1A7	0xFF11	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO_1	Offcore data reads satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE_1	Offcore data reads satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x111	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT_1	Offcore data reads satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x211	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM_1	Offcore data reads satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x411	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_1	Offcore data reads satisfied by the LLC	1	100000	0x1A7	0x711	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM_1	Offcore data reads satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2711	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_1	Offcore data reads satisfied by the local DRAM	1	100000	0x1A7	0x2011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_1	Offcore data reads satisfied by a remote cache	1	100000	0x1A7	0x1811	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM_1	Offcore data reads satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5811	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT_1	Offcore data reads that HIT in a remote cache	1	100000	0x1A7	0x1011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM_1	Offcore data reads that HITM in a remote cache	1	100000	0x1A7	0x811	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM_1	Offcore data reads satisfied by a remote DRAM	1	100000	0x1A7	0x4011	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM_1	Offcore code reads satisfied by any cache or DRAM	1	100000	0x1A7	0x7F44	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_1	Offcore code reads satisfied by any DRAM	1	100000	0x1A7	0x6044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS_1	Offcore code reads that missed the LLC	1	100000	0x1A7	0xF844	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION_1	All offcore code reads	1	100000	0x1A7	0xFF44	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO_1	Offcore code reads satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE_1	Offcore code reads satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x144	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT_1	Offcore code reads satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x244	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM_1	Offcore code reads satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x444	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_1	Offcore code reads satisfied by the LLC	1	100000	0x1A7	0x744	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM_1	Offcore code reads satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2744	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_1	Offcore code reads satisfied by the local DRAM	1	100000	0x1A7	0x2044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_1	Offcore code reads satisfied by a remote cache	1	100000	0x1A7	0x1844	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM_1	Offcore code reads satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5844	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT_1	Offcore code reads that HIT in a remote cache	1	100000	0x1A7	0x1044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM_1	Offcore code reads that HITM in a remote cache	1	100000	0x1A7	0x844	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM_1	Offcore code reads satisfied by a remote DRAM	1	100000	0x1A7	0x4044	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM_1	Offcore requests satisfied by any cache or DRAM	1	100000	0x1A7	0x7FFF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_1	Offcore requests satisfied by any DRAM	1	100000	0x1A7	0x60FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS_1	Offcore requests that missed the LLC	1	100000	0x1A7	0xF8FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION_1	All offcore requests	1	100000	0x1A7	0xFFFF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO_1	Offcore requests satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x80FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE_1	Offcore requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x1FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT_1	Offcore requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x2FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM_1	Offcore requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x4FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_1	Offcore requests satisfied by the LLC	1	100000	0x1A7	0x7FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM_1	Offcore requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x27FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_1	Offcore requests satisfied by the local DRAM	1	100000	0x1A7	0x20FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_1	Offcore requests satisfied by a remote cache	1	100000	0x1A7	0x18FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM_1	Offcore requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x58FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT_1	Offcore requests that HIT in a remote cache	1	100000	0x1A7	0x10FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM_1	Offcore requests that HITM in a remote cache	1	100000	0x1A7	0x8FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM_1	Offcore requests satisfied by a remote DRAM	1	100000	0x1A7	0x40FF	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM_1	Offcore RFO requests satisfied by any cache or DRAM	1	100000	0x1A7	0x7F22	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_1	Offcore RFO requests satisfied by any DRAM	1	100000	0x1A7	0x6022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS_1	Offcore RFO requests that missed the LLC	1	100000	0x1A7	0xF822	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION_1	All offcore RFO requests	1	100000	0x1A7	0xFF22	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO_1	Offcore RFO requests satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE_1	Offcore RFO requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x122	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT_1	Offcore RFO requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x222	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM_1	Offcore RFO requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x422	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_1	Offcore RFO requests satisfied by the LLC	1	100000	0x1A7	0x722	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM_1	Offcore RFO requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2722	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_1	Offcore RFO requests satisfied by the local DRAM	1	100000	0x1A7	0x2022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_1	Offcore RFO requests satisfied by a remote cache	1	100000	0x1A7	0x1822	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM_1	Offcore RFO requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5822	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT_1	Offcore RFO requests that HIT in a remote cache	1	100000	0x1A7	0x1022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM_1	Offcore RFO requests that HITM in a remote cache	1	100000	0x1A7	0x822	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM_1	Offcore RFO requests satisfied by a remote DRAM	1	100000	0x1A7	0x4022	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM_1	Offcore writebacks to any cache or DRAM.	1	100000	0x1A7	0x7F08	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ANY_DRAM_1	Offcore writebacks to any DRAM	1	100000	0x1A7	0x6008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS_1	Offcore writebacks that missed the LLC	1	100000	0x1A7	0xF808	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.ANY_LOCATION_1	All offcore writebacks	1	100000	0x1A7	0xFF08	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO_1	Offcore writebacks to the IO, CSR, MMIO unit.	1	100000	0x1A7	0x8008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE_1	Offcore writebacks to the LLC and not found in a sibling core	1	100000	0x1A7	0x108	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM_1	Offcore writebacks to the LLC  and HITM in a sibling core	1	100000	0x1A7	0x408	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_1	Offcore writebacks to the LLC	1	100000	0x1A7	0x708	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM_1	Offcore writebacks to the LLC or local DRAM	1	100000	0x1A7	0x2708	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_1	Offcore writebacks to the local DRAM	1	100000	0x1A7	0x2008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_1	Offcore writebacks to a remote cache	1	100000	0x1A7	0x1808	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM_1	Offcore writebacks to a remote cache or remote DRAM	1	100000	0x1A7	0x5808	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT_1	Offcore writebacks that HIT in a remote cache	1	100000	0x1A7	0x1008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM_1	Offcore writebacks that HITM in a remote cache	1	100000	0x1A7	0x808	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.COREWB.REMOTE_DRAM_1	Offcore writebacks to a remote DRAM	1	100000	0x1A7	0x4008	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM_1	Offcore code or data read requests satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F77	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_1	Offcore code or data read requests satisfied by any DRAM	1	100000	0x1A7	0x6077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS_1	Offcore code or data read requests that missed the LLC	1	100000	0x1A7	0xF877	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION_1	All offcore code or data read requests	1	100000	0x1A7	0xFF77	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO_1	Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.	1	100000	0x1A7	0x8077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE_1	Offcore code or data read requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x177	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT_1	Offcore code or data read requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x277	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM_1	Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x477	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_1	Offcore code or data read requests satisfied by the LLC	1	100000	0x1A7	0x777	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM_1	Offcore code or data read requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2777	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_1	Offcore code or data read requests satisfied by the local DRAM	1	100000	0x1A7	0x2077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_1	Offcore code or data read requests satisfied by a remote cache	1	100000	0x1A7	0x1877	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM_1	Offcore code or data read requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5877	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT_1	Offcore code or data read requests that HIT in a remote cache	1	100000	0x1A7	0x1077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM_1	Offcore code or data read requests that HITM in a remote cache	1	100000	0x1A7	0x877	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM_1	Offcore code or data read requests satisfied by a remote DRAM	1	100000	0x1A7	0x4077	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM_1	Offcore request = all data, response = any cache_dram	1	100000	0x1A7	0x7F33	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_1	Offcore request = all data, response = any DRAM	1	100000	0x1A7	0x6033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS_1	Offcore request = all data, response = any LLC miss	1	100000	0x1A7	0xF833	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION_1	Offcore request = all data, response = any location	1	100000	0x1A7	0xFF33	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO_1	Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE_1	Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x133	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT_1	Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x233	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM_1	Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x433	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_1	Offcore request = all data, response = local cache	1	100000	0x1A7	0x733	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM_1	Offcore request = all data, response = local cache or dram	1	100000	0x1A7	0x2733	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_1	Offcore data reads, RFO's and prefetches statisfied by the local DRAM.	1	100000	0x1A7	0x2033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_1	Offcore request = all data, response = remote cache	1	100000	0x1A7	0x1833	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM_1	Offcore request = all data, response = remote cache or dram	1	100000	0x1A7	0x5833	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT_1	Offcore data reads, RFO's and prefetches that HIT in a remote cache 	1	100000	0x1A7	0x1033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM_1	Offcore data reads, RFO's and prefetches that HITM in a remote cache	1	100000	0x1A7	0x833	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM_1	Offcore data reads, RFO's and prefetches statisfied by the remote DRAM	1	100000	0x1A7	0x4033	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM_1	Offcore demand data requests satisfied by any cache or DRAM	1	100000	0x1A7	0x7F03	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_1	Offcore demand data requests satisfied by any DRAM	1	100000	0x1A7	0x6003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS_1	Offcore demand data requests that missed the LLC	1	100000	0x1A7	0xF803	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION_1	All offcore demand data requests	1	100000	0x1A7	0xFF03	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO_1	Offcore demand data requests satisfied by the IO, CSR, MMIO unit.	1	100000	0x1A7	0x8003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE_1	Offcore demand data requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x103	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT_1	Offcore demand data requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x203	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM_1	Offcore demand data requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x403	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_1	Offcore demand data requests satisfied by the LLC	1	100000	0x1A7	0x703	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM_1	Offcore demand data requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2703	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_1	Offcore demand data requests satisfied by the local DRAM	1	100000	0x1A7	0x2003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_1	Offcore demand data requests satisfied by a remote cache	1	100000	0x1A7	0x1803	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM_1	Offcore demand data requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5803	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT_1	Offcore demand data requests that HIT in a remote cache	1	100000	0x1A7	0x1003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM_1	Offcore demand data requests that HITM in a remote cache	1	100000	0x1A7	0x803	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM_1	Offcore demand data requests satisfied by a remote DRAM	1	100000	0x1A7	0x4003	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM_1	Offcore demand data reads satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F01	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_1	Offcore demand data reads satisfied by any DRAM	1	100000	0x1A7	0x6001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS_1	Offcore demand data reads that missed the LLC	1	100000	0x1A7	0xF801	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION_1	All offcore demand data reads	1	100000	0x1A7	0xFF01	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO_1	Offcore demand data reads satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE_1	Offcore demand data reads satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x101	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT_1	Offcore demand data reads satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x201	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM_1	Offcore demand data reads satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x401	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_1	Offcore demand data reads satisfied by the LLC	1	100000	0x1A7	0x701	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM_1	Offcore demand data reads satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2701	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_1	Offcore demand data reads satisfied by the local DRAM	1	100000	0x1A7	0x2001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_1	Offcore demand data reads satisfied by a remote cache	1	100000	0x1A7	0x1801	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM_1	Offcore demand data reads satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5801	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT_1	Offcore demand data reads that HIT in a remote cache	1	100000	0x1A7	0x1001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM_1	Offcore demand data reads that HITM in a remote cache	1	100000	0x1A7	0x801	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM_1	Offcore demand data reads satisfied by a remote DRAM	1	100000	0x1A7	0x4001	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM_1	Offcore demand code reads satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F04	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_1	Offcore demand code reads satisfied by any DRAM	1	100000	0x1A7	0x6004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS_1	Offcore demand code reads that missed the LLC	1	100000	0x1A7	0xF804	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION_1	All offcore demand code reads	1	100000	0x1A7	0xFF04	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO_1	Offcore demand code reads satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE_1	Offcore demand code reads satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x104	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT_1	Offcore demand code reads satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x204	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM_1	Offcore demand code reads satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x404	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_1	Offcore demand code reads satisfied by the LLC	1	100000	0x1A7	0x704	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM_1	Offcore demand code reads satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2704	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_1	Offcore demand code reads satisfied by the local DRAM	1	100000	0x1A7	0x2004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_1	Offcore demand code reads satisfied by a remote cache	1	100000	0x1A7	0x1804	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM_1	Offcore demand code reads satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5804	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT_1	Offcore demand code reads that HIT in a remote cache	1	100000	0x1A7	0x1004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM_1	Offcore demand code reads that HITM in a remote cache	1	100000	0x1A7	0x804	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM_1	Offcore demand code reads satisfied by a remote DRAM	1	100000	0x1A7	0x4004	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM_1	Offcore demand RFO requests satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F02	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_1	Offcore demand RFO requests satisfied by any DRAM	1	100000	0x1A7	0x6002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS_1	Offcore demand RFO requests that missed the LLC	1	100000	0x1A7	0xF802	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION_1	All offcore demand RFO requests	1	100000	0x1A7	0xFF02	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO_1	Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE_1	Offcore demand RFO requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x102	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT_1	Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x202	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM_1	Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x402	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_1	Offcore demand RFO requests satisfied by the LLC	1	100000	0x1A7	0x702	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM_1	Offcore demand RFO requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2702	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_1	Offcore demand RFO requests satisfied by the local DRAM	1	100000	0x1A7	0x2002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_1	Offcore demand RFO requests satisfied by a remote cache	1	100000	0x1A7	0x1802	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM_1	Offcore demand RFO requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5802	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT_1	Offcore demand RFO requests that HIT in a remote cache	1	100000	0x1A7	0x1002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM_1	Offcore demand RFO requests that HITM in a remote cache	1	100000	0x1A7	0x802	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM_1	Offcore demand RFO requests satisfied by a remote DRAM	1	100000	0x1A7	0x4002	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM_1	Offcore other requests satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F80	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ANY_DRAM_1	Offcore other requests satisfied by any DRAM	1	100000	0x1A7	0x6080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS_1	Offcore other requests that missed the LLC	1	100000	0x1A7	0xF880	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.ANY_LOCATION_1	All offcore other requests	1	100000	0x1A7	0xFF80	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO_1	Offcore other requests satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE_1	Offcore other requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x180	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT_1	Offcore other requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x280	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM_1	Offcore other requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x480	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_1	Offcore other requests satisfied by the LLC	1	100000	0x1A7	0x780	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM_1	Offcore other requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2780	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_1	Offcore other requests satisfied by a remote cache	1	100000	0x1A7	0x1880	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM_1	Offcore other requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5880	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT_1	Offcore other requests that HIT in a remote cache	1	100000	0x1A7	0x1080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM_1	Offcore other requests that HITM in a remote cache	1	100000	0x1A7	0x880	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.OTHER.REMOTE_DRAM_1	Offcore other requests satisfied by a remote DRAM	1	100000	0x1A7	0x4080	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM_1	Offcore prefetch data requests satisfied by any cache or DRAM	1	100000	0x1A7	0x7F50	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_1	Offcore prefetch data requests satisfied by any DRAM	1	100000	0x1A7	0x6050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS_1	Offcore prefetch data requests that missed the LLC	1	100000	0x1A7	0xF850	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION_1	All offcore prefetch data requests	1	100000	0x1A7	0xFF50	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO_1	Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.	1	100000	0x1A7	0x8050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE_1	Offcore prefetch data requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x150	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT_1	Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x250	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM_1	Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x450	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_1	Offcore prefetch data requests satisfied by the LLC	1	100000	0x1A7	0x750	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM_1	Offcore prefetch data requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2750	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_1	Offcore prefetch data requests satisfied by the local DRAM	1	100000	0x1A7	0x2050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_1	Offcore prefetch data requests satisfied by a remote cache	1	100000	0x1A7	0x1850	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM_1	Offcore prefetch data requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5850	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT_1	Offcore prefetch data requests that HIT in a remote cache	1	100000	0x1A7	0x1050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM_1	Offcore prefetch data requests that HITM in a remote cache	1	100000	0x1A7	0x850	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM_1	Offcore prefetch data requests satisfied by a remote DRAM	1	100000	0x1A7	0x4050	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM_1	Offcore prefetch data reads satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F10	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_1	Offcore prefetch data reads satisfied by any DRAM	1	100000	0x1A7	0x6010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS_1	Offcore prefetch data reads that missed the LLC	1	100000	0x1A7	0xF810	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION_1	All offcore prefetch data reads	1	100000	0x1A7	0xFF10	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO_1	Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE_1	Offcore prefetch data reads satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x110	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT_1	Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x210	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM_1	Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x410	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_1	Offcore prefetch data reads satisfied by the LLC	1	100000	0x1A7	0x710	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM_1	Offcore prefetch data reads satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2710	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_1	Offcore prefetch data reads satisfied by the local DRAM	1	100000	0x1A7	0x2010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_1	Offcore prefetch data reads satisfied by a remote cache	1	100000	0x1A7	0x1810	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM_1	Offcore prefetch data reads satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5810	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT_1	Offcore prefetch data reads that HIT in a remote cache	1	100000	0x1A7	0x1010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM_1	Offcore prefetch data reads that HITM in a remote cache	1	100000	0x1A7	0x810	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM_1	Offcore prefetch data reads satisfied by a remote DRAM	1	100000	0x1A7	0x4010	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM_1	Offcore prefetch code reads satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F40	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_1	Offcore prefetch code reads satisfied by any DRAM	1	100000	0x1A7	0x6040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS_1	Offcore prefetch code reads that missed the LLC	1	100000	0x1A7	0xF840	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION_1	All offcore prefetch code reads	1	100000	0x1A7	0xFF40	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO_1	Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE_1	Offcore prefetch code reads satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x140	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT_1	Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x240	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM_1	Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x440	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_1	Offcore prefetch code reads satisfied by the LLC	1	100000	0x1A7	0x740	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM_1	Offcore prefetch code reads satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2740	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_1	Offcore prefetch code reads satisfied by the local DRAM	1	100000	0x1A7	0x2040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_1	Offcore prefetch code reads satisfied by a remote cache	1	100000	0x1A7	0x1840	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM_1	Offcore prefetch code reads satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5840	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT_1	Offcore prefetch code reads that HIT in a remote cache	1	100000	0x1A7	0x1040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM_1	Offcore prefetch code reads that HITM in a remote cache	1	100000	0x1A7	0x840	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM_1	Offcore prefetch code reads satisfied by a remote DRAM	1	100000	0x1A7	0x4040	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM_1	Offcore prefetch RFO requests satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F20	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_1	Offcore prefetch RFO requests satisfied by any DRAM	1	100000	0x1A7	0x6020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS_1	Offcore prefetch RFO requests that missed the LLC	1	100000	0x1A7	0xF820	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION_1	All offcore prefetch RFO requests	1	100000	0x1A7	0xFF20	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO_1	Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE_1	Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x120	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT_1	Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x220	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM_1	Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x420	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_1	Offcore prefetch RFO requests satisfied by the LLC	1	100000	0x1A7	0x720	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM_1	Offcore prefetch RFO requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2720	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_1	Offcore prefetch RFO requests satisfied by the local DRAM	1	100000	0x1A7	0x2020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_1	Offcore prefetch RFO requests satisfied by a remote cache	1	100000	0x1A7	0x1820	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM_1	Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5820	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT_1	Offcore prefetch RFO requests that HIT in a remote cache	1	100000	0x1A7	0x1020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM_1	Offcore prefetch RFO requests that HITM in a remote cache	1	100000	0x1A7	0x820	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM_1	Offcore prefetch RFO requests satisfied by a remote DRAM	1	100000	0x1A7	0x4020	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM_1	Offcore prefetch requests satisfied by any cache or DRAM.	1	100000	0x1A7	0x7F70	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_1	Offcore prefetch requests satisfied by any DRAM	1	100000	0x1A7	0x6070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS_1	Offcore prefetch requests that missed the LLC	1	100000	0x1A7	0xF870	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION_1	All offcore prefetch requests	1	100000	0x1A7	0xFF70	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO_1	Offcore prefetch requests satisfied by the IO, CSR, MMIO unit	1	100000	0x1A7	0x8070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE_1	Offcore prefetch requests satisfied by the LLC and not found in a sibling core	1	100000	0x1A7	0x170	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT_1	Offcore prefetch requests satisfied by the LLC and HIT in a sibling core	1	100000	0x1A7	0x270	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM_1	Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core	1	100000	0x1A7	0x470	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_1	Offcore prefetch requests satisfied by the LLC	1	100000	0x1A7	0x770	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM_1	Offcore prefetch requests satisfied by the LLC or local DRAM	1	100000	0x1A7	0x2770	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_1	Offcore prefetch requests satisfied by the local DRAM	1	100000	0x1A7	0x2070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_1	Offcore prefetch requests satisfied by a remote cache	1	100000	0x1A7	0x1870	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM_1	Offcore prefetch requests satisfied by a remote cache or remote DRAM	1	100000	0x1A7	0x5870	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT_1	Offcore prefetch requests that HIT in a remote cache	1	100000	0x1A7	0x1070	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM_1	Offcore prefetch requests that HITM in a remote cache	1	100000	0x1A7	0x870	0	0	0	0	0	
+0xBB	0x1	OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM_1	Offcore prefetch requests satisfied by a remote DRAM	1	100000	0x1A7	0x4070	0	0	0	0	0	
diff --git a/x86data/perfmon_data/WSM-EX/WestmereEX_core_V1.json b/x86data/perfmon_data/WSM-EX/WestmereEX_core_V1.json
new file mode 100644
index 0000000..112cd27
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EX/WestmereEX_core_V1.json
@@ -0,0 +1,9314 @@
+[

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.CYCLES_DIV_BUSY",

+    "BriefDescription": "Cycles the divider is busy",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x1",

+    "EventName": "ARITH.DIV",

+    "BriefDescription": "Divide Operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x14",

+    "UMask": "0x2",

+    "EventName": "ARITH.MUL",

+    "BriefDescription": "Multiply operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x2",

+    "EventName": "BACLEAR.BAD_TARGET",

+    "BriefDescription": "BACLEAR asserted with bad target address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE6",

+    "UMask": "0x1",

+    "EventName": "BACLEAR.CLEAR",

+    "BriefDescription": "BACLEAR asserted, regardless of cause ",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA7",

+    "UMask": "0x1",

+    "EventName": "BACLEAR_FORCE_IQ",

+    "BriefDescription": "Instruction queue forced BACLEAR",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x1",

+    "EventName": "BPU_CLEARS.EARLY",

+    "BriefDescription": "Early Branch Prediciton Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE8",

+    "UMask": "0x2",

+    "EventName": "BPU_CLEARS.LATE",

+    "BriefDescription": "Late Branch Prediction Unit clears",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE5",

+    "UMask": "0x1",

+    "EventName": "BPU_MISSED_CALL_RET",

+    "BriefDescription": "Branch prediction unit missed call or return",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE0",

+    "UMask": "0x1",

+    "EventName": "BR_INST_DECODED",

+    "BriefDescription": "Branch instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7F",

+    "EventName": "BR_INST_EXEC.ANY",

+    "BriefDescription": "Branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x1",

+    "EventName": "BR_INST_EXEC.COND",

+    "BriefDescription": "Conditional branch instructions executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x2",

+    "EventName": "BR_INST_EXEC.DIRECT",

+    "BriefDescription": "Unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x10",

+    "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Unconditional call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x20",

+    "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x4",

+    "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x30",

+    "EventName": "BR_INST_EXEC.NEAR_CALLS",

+    "BriefDescription": "Call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x7",

+    "EventName": "BR_INST_EXEC.NON_CALLS",

+    "BriefDescription": "All non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x8",

+    "EventName": "BR_INST_EXEC.RETURN_NEAR",

+    "BriefDescription": "Indirect return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x88",

+    "UMask": "0x40",

+    "EventName": "BR_INST_EXEC.TAKEN",

+    "BriefDescription": "Taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x1",

+    "EventName": "BR_INST_RETIRED.CONDITIONAL",

+    "BriefDescription": "Retired conditional branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL",

+    "BriefDescription": "Retired near call instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x2",

+    "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",

+    "BriefDescription": "Retired near call instructions Ring 3 only(Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7F",

+    "EventName": "BR_MISP_EXEC.ANY",

+    "BriefDescription": "Mispredicted branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x1",

+    "EventName": "BR_MISP_EXEC.COND",

+    "BriefDescription": "Mispredicted conditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_EXEC.DIRECT",

+    "BriefDescription": "Mispredicted unconditional branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x10",

+    "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x20",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",

+    "BriefDescription": "Mispredicted indirect call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",

+    "BriefDescription": "Mispredicted indirect non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x30",

+    "EventName": "BR_MISP_EXEC.NEAR_CALLS",

+    "BriefDescription": "Mispredicted call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x7",

+    "EventName": "BR_MISP_EXEC.NON_CALLS",

+    "BriefDescription": "Mispredicted non call branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x8",

+    "EventName": "BR_MISP_EXEC.RETURN_NEAR",

+    "BriefDescription": "Mispredicted return branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x89",

+    "UMask": "0x40",

+    "EventName": "BR_MISP_EXEC.TAKEN",

+    "BriefDescription": "Mispredicted taken branches executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x1",

+    "EventName": "BR_MISP_RETIRED.CONDITIONAL",

+    "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x2",

+    "EventName": "BR_MISP_RETIRED.NEAR_CALL",

+    "BriefDescription": "Mispredicted near retired calls (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x2",

+    "EventName": "CACHE_LOCK_CYCLES.L1D",

+    "BriefDescription": "Cycles L1D locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x63",

+    "UMask": "0x1",

+    "EventName": "CACHE_LOCK_CYCLES.L1D_L2",

+    "BriefDescription": "Cycles L1D and L2 locked",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.REF",

+    "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x1",

+    "EventName": "CPU_CLK_UNHALTED.REF_P",

+    "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD",

+    "BriefDescription": "Cycles when thread is not halted (fixed counter)",

+    "Counter": "Fixed counter 2",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Cycles when thread is not halted (programmable counter)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",

+    "BriefDescription": "Total CPU cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "2",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x1",

+    "EventName": "DTLB_LOAD_MISSES.ANY",

+    "BriefDescription": "DTLB load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x80",

+    "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",

+    "BriefDescription": "DTLB load miss large page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x20",

+    "EventName": "DTLB_LOAD_MISSES.PDE_MISS",

+    "BriefDescription": "DTLB load miss caused by low part of address",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x10",

+    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x2",

+    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB load miss page walks complete",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x8",

+    "UMask": "0x4",

+    "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",

+    "BriefDescription": "DTLB load miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x1",

+    "EventName": "DTLB_MISSES.ANY",

+    "BriefDescription": "DTLB misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x80",

+    "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",

+    "BriefDescription": "DTLB miss large page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x20",

+    "EventName": "DTLB_MISSES.PDE_MISS",

+    "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x10",

+    "EventName": "DTLB_MISSES.STLB_HIT",

+    "BriefDescription": "DTLB first level misses but second level hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x2",

+    "EventName": "DTLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "DTLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x49",

+    "UMask": "0x4",

+    "EventName": "DTLB_MISSES.WALK_CYCLES",

+    "BriefDescription": "DTLB miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4F",

+    "UMask": "0x10",

+    "EventName": "EPT.WALK_CYCLES",

+    "BriefDescription": "Extended Page Table walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD5",

+    "UMask": "0x1",

+    "EventName": "ES_REG_RENAMES",

+    "BriefDescription": "ES segment renames",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x1",

+    "EventName": "FP_ASSIST.ALL",

+    "BriefDescription": "X87 Floating point assists (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x4",

+    "EventName": "FP_ASSIST.INPUT",

+    "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF7",

+    "UMask": "0x2",

+    "EventName": "FP_ASSIST.OUTPUT",

+    "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x2",

+    "EventName": "FP_COMP_OPS_EXE.MMX",

+    "BriefDescription": "MMX Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x80",

+    "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",

+    "BriefDescription": "SSE* FP double precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x4",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP",

+    "BriefDescription": "SSE and SSE2 FP Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x10",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",

+    "BriefDescription": "SSE FP packed Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x20",

+    "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",

+    "BriefDescription": "SSE FP scalar Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x40",

+    "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",

+    "BriefDescription": "SSE* FP single precision Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x8",

+    "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",

+    "BriefDescription": "SSE2 integer Uops",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x10",

+    "UMask": "0x1",

+    "EventName": "FP_COMP_OPS_EXE.X87",

+    "BriefDescription": "Computational floating-point operations executed",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x3",

+    "EventName": "FP_MMX_TRANS.ANY",

+    "BriefDescription": "All Floating Point to and from MMX transitions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x1",

+    "EventName": "FP_MMX_TRANS.TO_FP",

+    "BriefDescription": "Transitions from MMX to Floating Point instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCC",

+    "UMask": "0x2",

+    "EventName": "FP_MMX_TRANS.TO_MMX",

+    "BriefDescription": "Transitions from Floating Point to MMX instructions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0xF",

+    "EventName": "ILD_STALL.ANY",

+    "BriefDescription": "Any Instruction Length Decoder stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x4",

+    "EventName": "ILD_STALL.IQ_FULL",

+    "BriefDescription": "Instruction Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x1",

+    "EventName": "ILD_STALL.LCP",

+    "BriefDescription": "Length Change Prefix stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x2",

+    "EventName": "ILD_STALL.MRU",

+    "BriefDescription": "Stall cycles due to BPU MRU bypass",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x87",

+    "UMask": "0x8",

+    "EventName": "ILD_STALL.REGEN",

+    "BriefDescription": "Regen stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x18",

+    "UMask": "0x1",

+    "EventName": "INST_DECODED.DEC0",

+    "BriefDescription": "Instructions that must be decoded by decoder 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x1E",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITE_CYCLES",

+    "BriefDescription": "Cycles instructions are written to the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x17",

+    "UMask": "0x1",

+    "EventName": "INST_QUEUE_WRITES",

+    "BriefDescription": "Instructions written to instruction queue.",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x0",

+    "UMask": "0x0",

+    "EventName": "INST_RETIRED.ANY",

+    "BriefDescription": "Instructions retired (fixed counter)",

+    "Counter": "Fixed counter 1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.ANY_P",

+    "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x4",

+    "EventName": "INST_RETIRED.MMX",

+    "BriefDescription": "Retired MMX instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x1",

+    "EventName": "INST_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC0",

+    "UMask": "0x2",

+    "EventName": "INST_RETIRED.X87",

+    "BriefDescription": "Retired floating-point operations (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6C",

+    "UMask": "0x1",

+    "EventName": "IO_TRANSACTIONS",

+    "BriefDescription": "I/O transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xAE",

+    "UMask": "0x1",

+    "EventName": "ITLB_FLUSH",

+    "BriefDescription": "ITLB flushes",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC8",

+    "UMask": "0x20",

+    "EventName": "ITLB_MISS_RETIRED",

+    "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x1",

+    "EventName": "ITLB_MISSES.ANY",

+    "BriefDescription": "ITLB miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x80",

+    "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",

+    "BriefDescription": "ITLB miss large page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x2",

+    "EventName": "ITLB_MISSES.WALK_COMPLETED",

+    "BriefDescription": "ITLB miss page walks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x85",

+    "UMask": "0x4",

+    "EventName": "ITLB_MISSES.WALK_CYCLES",

+    "BriefDescription": "ITLB miss page walk cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x4",

+    "EventName": "L1D.M_EVICT",

+    "BriefDescription": "L1D cache lines replaced in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x2",

+    "EventName": "L1D.M_REPL",

+    "BriefDescription": "L1D cache lines allocated in the M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x8",

+    "EventName": "L1D.M_SNOOP_EVICT",

+    "BriefDescription": "L1D snoop eviction of cache lines in M state",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x51",

+    "UMask": "0x1",

+    "EventName": "L1D.REPL",

+    "BriefDescription": "L1 data cache lines allocated",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x52",

+    "UMask": "0x1",

+    "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",

+    "BriefDescription": "L1D prefetch load lock accepted in fill buffer",

+    "Counter": "0,1",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x2",

+    "EventName": "L1D_PREFETCH.MISS",

+    "BriefDescription": "L1D hardware prefetch misses",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x1",

+    "EventName": "L1D_PREFETCH.REQUESTS",

+    "BriefDescription": "L1D hardware prefetch requests",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4E",

+    "UMask": "0x4",

+    "EventName": "L1D_PREFETCH.TRIGGERS",

+    "BriefDescription": "L1D hardware prefetch requests triggered",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x4",

+    "EventName": "L1D_WB_L2.E_STATE",

+    "BriefDescription": "L1 writebacks to L2 in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x1",

+    "EventName": "L1D_WB_L2.I_STATE",

+    "BriefDescription": "L1 writebacks to L2 in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x8",

+    "EventName": "L1D_WB_L2.M_STATE",

+    "BriefDescription": "L1 writebacks to L2 in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0xF",

+    "EventName": "L1D_WB_L2.MESI",

+    "BriefDescription": "All L1 writebacks to L2",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x28",

+    "UMask": "0x2",

+    "EventName": "L1D_WB_L2.S_STATE",

+    "BriefDescription": "L1 writebacks to L2 in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x4",

+    "EventName": "L1I.CYCLES_STALLED",

+    "BriefDescription": "L1I instruction fetch stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x1",

+    "EventName": "L1I.HITS",

+    "BriefDescription": "L1I instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x2",

+    "EventName": "L1I.MISSES",

+    "BriefDescription": "L1I instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x80",

+    "UMask": "0x3",

+    "EventName": "L1I.READS",

+    "BriefDescription": "L1I Instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xFF",

+    "EventName": "L2_DATA_RQSTS.ANY",

+    "BriefDescription": "All L2 data requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x4",

+    "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",

+    "BriefDescription": "L2 data demand loads in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x1",

+    "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",

+    "BriefDescription": "L2 data demand loads in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x8",

+    "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",

+    "BriefDescription": "L2 data demand loads in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF",

+    "EventName": "L2_DATA_RQSTS.DEMAND.MESI",

+    "BriefDescription": "L2 data demand requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x2",

+    "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",

+    "BriefDescription": "L2 data demand loads in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x40",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",

+    "BriefDescription": "L2 data prefetches in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x10",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",

+    "BriefDescription": "L2 data prefetches in the I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x80",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",

+    "BriefDescription": "L2 data prefetches in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0xF0",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",

+    "BriefDescription": "All L2 data prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x26",

+    "UMask": "0x20",

+    "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",

+    "BriefDescription": "L2 data prefetches in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x7",

+    "EventName": "L2_LINES_IN.ANY",

+    "BriefDescription": "L2 lines alloacated",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_IN.E_STATE",

+    "BriefDescription": "L2 lines allocated in the E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF1",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_IN.S_STATE",

+    "BriefDescription": "L2 lines allocated in the S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0xF",

+    "EventName": "L2_LINES_OUT.ANY",

+    "BriefDescription": "L2 lines evicted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x1",

+    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",

+    "BriefDescription": "L2 lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x2",

+    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a demand request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x4",

+    "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",

+    "BriefDescription": "L2 lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF2",

+    "UMask": "0x8",

+    "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",

+    "BriefDescription": "L2 modified lines evicted by a prefetch request",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x10",

+    "EventName": "L2_RQSTS.IFETCH_HIT",

+    "BriefDescription": "L2 instruction fetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x20",

+    "EventName": "L2_RQSTS.IFETCH_MISS",

+    "BriefDescription": "L2 instruction fetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x30",

+    "EventName": "L2_RQSTS.IFETCHES",

+    "BriefDescription": "L2 instruction fetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x1",

+    "EventName": "L2_RQSTS.LD_HIT",

+    "BriefDescription": "L2 load hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x2",

+    "EventName": "L2_RQSTS.LD_MISS",

+    "BriefDescription": "L2 load misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x3",

+    "EventName": "L2_RQSTS.LOADS",

+    "BriefDescription": "L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xAA",

+    "EventName": "L2_RQSTS.MISS",

+    "BriefDescription": "All L2 misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x40",

+    "EventName": "L2_RQSTS.PREFETCH_HIT",

+    "BriefDescription": "L2 prefetch hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x80",

+    "EventName": "L2_RQSTS.PREFETCH_MISS",

+    "BriefDescription": "L2 prefetch misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC0",

+    "EventName": "L2_RQSTS.PREFETCHES",

+    "BriefDescription": "All L2 prefetches",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xFF",

+    "EventName": "L2_RQSTS.REFERENCES",

+    "BriefDescription": "All L2 requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x4",

+    "EventName": "L2_RQSTS.RFO_HIT",

+    "BriefDescription": "L2 RFO hits",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0x8",

+    "EventName": "L2_RQSTS.RFO_MISS",

+    "BriefDescription": "L2 RFO misses",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x24",

+    "UMask": "0xC",

+    "EventName": "L2_RQSTS.RFOS",

+    "BriefDescription": "L2 RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x80",

+    "EventName": "L2_TRANSACTIONS.ANY",

+    "BriefDescription": "All L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x20",

+    "EventName": "L2_TRANSACTIONS.FILL",

+    "BriefDescription": "L2 fill transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x4",

+    "EventName": "L2_TRANSACTIONS.IFETCH",

+    "BriefDescription": "L2 instruction fetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x10",

+    "EventName": "L2_TRANSACTIONS.L1D_WB",

+    "BriefDescription": "L1D writeback to L2 transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x1",

+    "EventName": "L2_TRANSACTIONS.LOAD",

+    "BriefDescription": "L2 Load transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x8",

+    "EventName": "L2_TRANSACTIONS.PREFETCH",

+    "BriefDescription": "L2 prefetch transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x2",

+    "EventName": "L2_TRANSACTIONS.RFO",

+    "BriefDescription": "L2 RFO transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF0",

+    "UMask": "0x40",

+    "EventName": "L2_TRANSACTIONS.WB",

+    "BriefDescription": "L2 writeback to LLC transactions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x40",

+    "EventName": "L2_WRITE.LOCK.E_STATE",

+    "BriefDescription": "L2 demand lock RFOs in E state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE0",

+    "EventName": "L2_WRITE.LOCK.HIT",

+    "BriefDescription": "All demand L2 lock RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x10",

+    "EventName": "L2_WRITE.LOCK.I_STATE",

+    "BriefDescription": "L2 demand lock RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x80",

+    "EventName": "L2_WRITE.LOCK.M_STATE",

+    "BriefDescription": "L2 demand lock RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF0",

+    "EventName": "L2_WRITE.LOCK.MESI",

+    "BriefDescription": "All demand L2 lock RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x20",

+    "EventName": "L2_WRITE.LOCK.S_STATE",

+    "BriefDescription": "L2 demand lock RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xE",

+    "EventName": "L2_WRITE.RFO.HIT",

+    "BriefDescription": "All L2 demand store RFOs that hit the cache",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x1",

+    "EventName": "L2_WRITE.RFO.I_STATE",

+    "BriefDescription": "L2 demand store RFOs in I state (misses)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x8",

+    "EventName": "L2_WRITE.RFO.M_STATE",

+    "BriefDescription": "L2 demand store RFOs in M state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0xF",

+    "EventName": "L2_WRITE.RFO.MESI",

+    "BriefDescription": "All L2 demand store RFOs",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x27",

+    "UMask": "0x2",

+    "EventName": "L2_WRITE.RFO.S_STATE",

+    "BriefDescription": "L2 demand store RFOs in S state",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x82",

+    "UMask": "0x1",

+    "EventName": "LARGE_ITLB.HIT",

+    "BriefDescription": "Large ITLB hit",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3",

+    "UMask": "0x2",

+    "EventName": "LOAD_BLOCK.OVERLAP_STORE",

+    "BriefDescription": "Loads that partially overlap an earlier store",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x7",

+    "EventName": "LOAD_DISPATCH.ANY",

+    "BriefDescription": "All loads dispatched",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x4",

+    "EventName": "LOAD_DISPATCH.MOB",

+    "BriefDescription": "Loads dispatched from the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x1",

+    "EventName": "LOAD_DISPATCH.RS",

+    "BriefDescription": "Loads dispatched that bypass the MOB",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x13",

+    "UMask": "0x2",

+    "EventName": "LOAD_DISPATCH.RS_DELAYED",

+    "BriefDescription": "Loads dispatched from stage 305",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4C",

+    "UMask": "0x1",

+    "EventName": "LOAD_HIT_PRE",

+    "BriefDescription": "Load operations conflicting with software prefetches",

+    "Counter": "0,1",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x41",

+    "EventName": "LONGEST_LAT_CACHE.MISS",

+    "BriefDescription": "Longest latency cache miss",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x2E",

+    "UMask": "0x4F",

+    "EventName": "LONGEST_LAT_CACHE.REFERENCE",

+    "BriefDescription": "Longest latency cache reference",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.ACTIVE",

+    "BriefDescription": "Cycles when uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA8",

+    "UMask": "0x1",

+    "EventName": "LSD.INACTIVE",

+    "BriefDescription": "Cycles no uops were delivered by the LSD",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x20",

+    "UMask": "0x1",

+    "EventName": "LSD_OVERFLOW",

+    "BriefDescription": "Loops that can't stream from the instruction queue",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x1",

+    "EventName": "MACHINE_CLEARS.CYCLES",

+    "BriefDescription": "Cycles machine clear asserted",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x2",

+    "EventName": "MACHINE_CLEARS.MEM_ORDER",

+    "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC3",

+    "UMask": "0x4",

+    "EventName": "MACHINE_CLEARS.SMC",

+    "BriefDescription": "Self-Modifying Code detected",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD0",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.DECODED",

+    "BriefDescription": "Instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA6",

+    "UMask": "0x1",

+    "EventName": "MACRO_INSTS.FUSIONS_DECODED",

+    "BriefDescription": "Macro-fused instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x1",

+    "EventName": "MEM_INST_RETIRED.LOADS",

+    "BriefDescription": "Instructions retired which contains a load (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x2",

+    "EventName": "MEM_INST_RETIRED.STORES",

+    "BriefDescription": "Instructions retired which contains a store (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x80",

+    "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x40",

+    "EventName": "MEM_LOAD_RETIRED.HIT_LFB",

+    "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x1",

+    "EventName": "MEM_LOAD_RETIRED.L1D_HIT",

+    "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x2",

+    "EventName": "MEM_LOAD_RETIRED.L2_HIT",

+    "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x10",

+    "EventName": "MEM_LOAD_RETIRED.LLC_MISS",

+    "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x4",

+    "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",

+    "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xCB",

+    "UMask": "0x8",

+    "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",

+    "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC",

+    "UMask": "0x1",

+    "EventName": "MEM_STORE_RETIRED.DTLB_MISS",

+    "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x2",

+    "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM",

+    "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x8",

+    "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",

+    "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x20",

+    "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",

+    "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x80",

+    "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",

+    "BriefDescription": "Load instructions retired IO (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "4000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF",

+    "UMask": "0x4",

+    "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM",

+    "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "40000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x5",

+    "UMask": "0x2",

+    "EventName": "MISALIGN_MEM_REF.STORE",

+    "BriefDescription": "Misaligned store references",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x80",

+    "EventName": "OFFCORE_REQUESTS.ANY",

+    "BriefDescription": "All offcore requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS.ANY.READ",

+    "BriefDescription": "Offcore read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x10",

+    "EventName": "OFFCORE_REQUESTS.ANY.RFO",

+    "BriefDescription": "Offcore RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",

+    "BriefDescription": "Offcore demand code read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",

+    "BriefDescription": "Offcore demand data read requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",

+    "BriefDescription": "Offcore demand RFO requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB0",

+    "UMask": "0x40",

+    "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",

+    "BriefDescription": "Offcore L1 data cache writebacks",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",

+    "BriefDescription": "Outstanding offcore reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x8",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore reads busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",

+    "BriefDescription": "Outstanding offcore demand code reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x2",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand code read busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",

+    "BriefDescription": "Outstanding offcore demand data reads",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand data read busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",

+    "BriefDescription": "Outstanding offcore demand RFOs",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x60",

+    "UMask": "0x4",

+    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",

+    "BriefDescription": "Cycles offcore demand RFOs busy",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB2",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_REQUESTS_SQ_FULL",

+    "BriefDescription": "Offcore requests blocked due to Super Queue full",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x7",

+    "UMask": "0x1",

+    "EventName": "PARTIAL_ADDRESS_ALIAS",

+    "BriefDescription": "False dependencies due to partial address aliasing",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0xF",

+    "EventName": "RAT_STALLS.ANY",

+    "BriefDescription": "All RAT stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x1",

+    "EventName": "RAT_STALLS.FLAGS",

+    "BriefDescription": "Flag stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x2",

+    "EventName": "RAT_STALLS.REGISTERS",

+    "BriefDescription": "Partial register stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x4",

+    "EventName": "RAT_STALLS.ROB_READ_PORT",

+    "BriefDescription": "ROB read port stalls cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD2",

+    "UMask": "0x8",

+    "EventName": "RAT_STALLS.SCOREBOARD",

+    "BriefDescription": "Scoreboard stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x1",

+    "EventName": "RESOURCE_STALLS.ANY",

+    "BriefDescription": "Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x20",

+    "EventName": "RESOURCE_STALLS.FPCW",

+    "BriefDescription": "FPU control word write stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x2",

+    "EventName": "RESOURCE_STALLS.LOAD",

+    "BriefDescription": "Load buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x40",

+    "EventName": "RESOURCE_STALLS.MXCSR",

+    "BriefDescription": "MXCSR rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x80",

+    "EventName": "RESOURCE_STALLS.OTHER",

+    "BriefDescription": "Other Resource related stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x10",

+    "EventName": "RESOURCE_STALLS.ROB_FULL",

+    "BriefDescription": "ROB full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x4",

+    "EventName": "RESOURCE_STALLS.RS_FULL",

+    "BriefDescription": "Reservation Station full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xA2",

+    "UMask": "0x8",

+    "EventName": "RESOURCE_STALLS.STORE",

+    "BriefDescription": "Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x4",

+    "UMask": "0x7",

+    "EventName": "SB_DRAIN.ANY",

+    "BriefDescription": "All Store buffer stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD4",

+    "UMask": "0x1",

+    "EventName": "SEG_RENAME_STALLS",

+    "BriefDescription": "Segment rename stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_128.PACK",

+    "BriefDescription": "128 bit SIMD integer pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_128.PACKED_ARITH",

+    "BriefDescription": "128 bit SIMD integer arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_128.PACKED_LOGICAL",

+    "BriefDescription": "128 bit SIMD integer logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_128.PACKED_MPY",

+    "BriefDescription": "128 bit SIMD integer multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_128.PACKED_SHIFT",

+    "BriefDescription": "128 bit SIMD integer shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_128.SHUFFLE_MOVE",

+    "BriefDescription": "128 bit SIMD integer shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x12",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_128.UNPACK",

+    "BriefDescription": "128 bit SIMD integer unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x4",

+    "EventName": "SIMD_INT_64.PACK",

+    "BriefDescription": "SIMD integer 64 bit pack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x20",

+    "EventName": "SIMD_INT_64.PACKED_ARITH",

+    "BriefDescription": "SIMD integer 64 bit arithmetic operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x10",

+    "EventName": "SIMD_INT_64.PACKED_LOGICAL",

+    "BriefDescription": "SIMD integer 64 bit logical operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x1",

+    "EventName": "SIMD_INT_64.PACKED_MPY",

+    "BriefDescription": "SIMD integer 64 bit packed multiply operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x2",

+    "EventName": "SIMD_INT_64.PACKED_SHIFT",

+    "BriefDescription": "SIMD integer 64 bit shift operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x40",

+    "EventName": "SIMD_INT_64.SHUFFLE_MOVE",

+    "BriefDescription": "SIMD integer 64 bit shuffle/move operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xFD",

+    "UMask": "0x8",

+    "EventName": "SIMD_INT_64.UNPACK",

+    "BriefDescription": "SIMD integer 64 bit unpack operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x1",

+    "EventName": "SNOOP_RESPONSE.HIT",

+    "BriefDescription": "Thread responded HIT to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x2",

+    "EventName": "SNOOP_RESPONSE.HITE",

+    "BriefDescription": "Thread responded HITE to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB8",

+    "UMask": "0x4",

+    "EventName": "SNOOP_RESPONSE.HITM",

+    "BriefDescription": "Thread responded HITM to snoop",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS.CODE",

+    "BriefDescription": "Snoop code requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS.DATA",

+    "BriefDescription": "Snoop data requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB4",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS.INVALIDATE",

+    "BriefDescription": "Snoop invalidate requests",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",

+    "BriefDescription": "Outstanding snoop code requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x4",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop code requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",

+    "BriefDescription": "Outstanding snoop data requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x1",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop data requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",

+    "BriefDescription": "Outstanding snoop invalidate requests",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB3",

+    "UMask": "0x2",

+    "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",

+    "BriefDescription": "Cycles snoop invalidate requests queued",

+    "Counter": "0",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF6",

+    "UMask": "0x1",

+    "EventName": "SQ_FULL_STALL_CYCLES",

+    "BriefDescription": "Super Queue full stall cycles",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x4",

+    "EventName": "SQ_MISC.LRU_HINTS",

+    "BriefDescription": "Super Queue LRU hints sent to LLC",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xF4",

+    "UMask": "0x10",

+    "EventName": "SQ_MISC.SPLIT_LOCK",

+    "BriefDescription": "Super Queue lock splits across a cache line",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x4",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",

+    "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x1",

+    "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",

+    "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x8",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",

+    "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x2",

+    "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",

+    "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC7",

+    "UMask": "0x10",

+    "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",

+    "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x4",

+    "EventName": "STORE_BLOCKS.AT_RET",

+    "BriefDescription": "Loads delayed with at-Retirement block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x6",

+    "UMask": "0x8",

+    "EventName": "STORE_BLOCKS.L1D_BLOCK",

+    "BriefDescription": "Cacheable loads delayed with L1D block code",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x3C",

+    "UMask": "0x0",

+    "EventName": "CPU_CLK_UNHALTED.THREAD_P",

+    "BriefDescription": "Cycles thread is active",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0x19",

+    "UMask": "0x1",

+    "EventName": "TWO_UOP_INSTS_DECODED",

+    "BriefDescription": "Two Uop instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xDB",

+    "UMask": "0x1",

+    "EventName": "UOP_UNFUSION",

+    "BriefDescription": "Uop unfusions due to FP exceptions",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x4",

+    "EventName": "UOPS_DECODED.ESP_FOLDING",

+    "BriefDescription": "Stack pointer instructions decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x8",

+    "EventName": "UOPS_DECODED.ESP_SYNC",

+    "BriefDescription": "Stack pointer sync operations",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x2",

+    "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",

+    "BriefDescription": "Uops decoded by Microcode Sequencer",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xD1",

+    "UMask": "0x1",

+    "EventName": "UOPS_DECODED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops are decoded",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",

+    "BriefDescription": "Uops executed on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",

+    "BriefDescription": "Uops executed on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "1",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x3F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on any port (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1F",

+    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",

+    "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x1",

+    "EventName": "UOPS_EXECUTED.PORT0",

+    "BriefDescription": "Uops executed on port 0",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015",

+    "BriefDescription": "Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x40",

+    "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x2",

+    "EventName": "UOPS_EXECUTED.PORT1",

+    "BriefDescription": "Uops executed on port 1",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x4",

+    "EventName": "UOPS_EXECUTED.PORT2_CORE",

+    "BriefDescription": "Uops executed on port 2 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x80",

+    "EventName": "UOPS_EXECUTED.PORT234_CORE",

+    "BriefDescription": "Uops issued on ports 2, 3 or 4",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x8",

+    "EventName": "UOPS_EXECUTED.PORT3_CORE",

+    "BriefDescription": "Uops executed on port 3 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x10",

+    "EventName": "UOPS_EXECUTED.PORT4_CORE",

+    "BriefDescription": "Uops executed on port 4 (core count)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB1",

+    "UMask": "0x20",

+    "EventName": "UOPS_EXECUTED.PORT5",

+    "BriefDescription": "Uops executed on port 5",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.ANY",

+    "BriefDescription": "Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued on any thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",

+    "BriefDescription": "Cycles Uops were issued on either thread",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "1",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x2",

+    "EventName": "UOPS_ISSUED.FUSED",

+    "BriefDescription": "Fused Uops issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xE",

+    "UMask": "0x1",

+    "EventName": "UOPS_ISSUED.STALL_CYCLES",

+    "BriefDescription": "Cycles no Uops were issued",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",

+    "BriefDescription": "Cycles Uops are being retired",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.ANY",

+    "BriefDescription": "Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x4",

+    "EventName": "UOPS_RETIRED.MACRO_FUSED",

+    "BriefDescription": "Macro-fused Uops retired (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x2",

+    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",

+    "BriefDescription": "Retirement slots used (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.STALL_CYCLES",

+    "BriefDescription": "Cycles Uops are not retiring (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "1",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC2",

+    "UMask": "0x1",

+    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",

+    "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "16",

+    "Invert": "1",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC4",

+    "UMask": "0x4",

+    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "200000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xC5",

+    "UMask": "0x4",

+    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",

+    "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",

+    "Counter": "0,1,2,3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0",

+    "MSRValue": "0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "1",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",

+    "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x0",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",

+    "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "100",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x400",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",

+    "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "1000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",

+    "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",

+    "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",

+    "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x800",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",

+    "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "500",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x100",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",

+    "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "5000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",

+    "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "3",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",

+    "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "50000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x4",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",

+    "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x1000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",

+    "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "200",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x200",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",

+    "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "2000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",

+    "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "20000",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x8",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  },

+  {

+    "EventCode": "0xB",

+    "UMask": "0x10",

+    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",

+    "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",

+    "Counter": "3",

+    "SampleAfterValue": "10",

+    "MSRIndex": "0x3F6",

+    "MSRValue": "0x2000",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "2",

+    "Offcore": "0"

+  }
,

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF11",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x111",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x211",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x411",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4711",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x811",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2011",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF44",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x144",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x244",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x444",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4744",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x844",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2044",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7FFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM",

+    "BriefDescription": "Offcore requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x60FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS",

+    "BriefDescription": "Offcore requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION",

+    "BriefDescription": "All offcore requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFFFF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO",

+    "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x80FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE",

+    "BriefDescription": "Offcore requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x47FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM",

+    "BriefDescription": "Offcore requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x40FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE",

+    "BriefDescription": "Offcore requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x18FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x38FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x10FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM",

+    "BriefDescription": "Offcore requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x20FF",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF22",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x122",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x222",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x422",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4722",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x822",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2022",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_DRAM",

+    "BriefDescription": "Offcore writebacks to any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS",

+    "BriefDescription": "Offcore writebacks that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION",

+    "BriefDescription": "All offcore writebacks",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF08",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO",

+    "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x108",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x408",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE",

+    "BriefDescription": "Offcore writebacks to the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4708",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM",

+    "BriefDescription": "Offcore writebacks to the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE",

+    "BriefDescription": "Offcore writebacks to a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore writebacks that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore writebacks that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x808",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM",

+    "BriefDescription": "Offcore writebacks to a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2008",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore code or data read requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore code or data read requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF77",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x177",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x277",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x477",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4777",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x877",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2077",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = any cache_dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM",

+    "BriefDescription": "Offcore request = all data, response = any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS",

+    "BriefDescription": "Offcore request = all data, response = any LLC miss",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION",

+    "BriefDescription": "Offcore request = all data, response = any location",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF33",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x133",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x233",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x433",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE",

+    "BriefDescription": "Offcore request = all data, response = local cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = local cache or dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4733",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE",

+    "BriefDescription": "Offcore request = all data, response = remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore request = all data, response = remote cache or dram",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x833",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM",

+    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2033",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand data requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore demand data requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF03",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x103",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x203",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x403",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4703",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand data requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand data requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x803",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2003",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION",

+    "BriefDescription": "All offcore demand data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF01",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x101",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x201",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x401",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4701",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x801",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2001",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore demand code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF04",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x104",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x204",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x404",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4704",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x804",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2004",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore demand RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore demand RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF02",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x102",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x202",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x402",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4702",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x802",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2002",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS",

+    "BriefDescription": "Offcore other requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION",

+    "BriefDescription": "All offcore other requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF80",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO",

+    "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x180",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x280",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x480",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE",

+    "BriefDescription": "Offcore other requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4780",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore other requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore other requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x880",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM",

+    "BriefDescription": "Offcore other requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2080",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F30",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch data requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch data requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF30",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x130",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x230",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x430",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x730",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4730",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x830",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2030",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch data reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch data reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF10",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x110",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x210",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x410",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4710",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x810",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2010",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch code reads that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch code reads",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF40",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x140",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x240",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x440",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4740",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x840",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2040",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch RFO requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF20",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x120",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x220",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x420",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4720",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x820",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2020",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x7F70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x6070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS",

+    "BriefDescription": "Offcore prefetch requests that missed the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xF870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION",

+    "BriefDescription": "All offcore prefetch requests",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0xFF70",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO",

+    "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x8070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x170",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x270",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x470",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4770",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x4070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x3870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT",

+    "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x1070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM",

+    "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x870",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  },

+  {

+    "EventCode": "0xB7",

+    "UMask": "0x1",

+    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM",

+    "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",

+    "Counter": "2",

+    "SampleAfterValue": "100000",

+    "MSRIndex": "0x1A6",

+    "MSRValue": "0x2070",

+    "CounterMask": "0",

+    "Invert": "0",

+    "AnyThread": "0",

+    "EdgeDetect": "0",

+    "PEBS": "0",

+    "Offcore": "1"

+  }

+]
\ No newline at end of file
diff --git a/x86data/perfmon_data/WSM-EX/WestmereEX_core_V1.tsv b/x86data/perfmon_data/WSM-EX/WestmereEX_core_V1.tsv
new file mode 100644
index 0000000..4ed03e4
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EX/WestmereEX_core_V1.tsv
@@ -0,0 +1,315 @@
+# Performance Monitoring Events for Intel Xeon Processor E7 Family Based on the Westmere-EX Microarchitecture - V1
+# 12/13/2013 11:00:48 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0x14	0x1	ARITH.CYCLES_DIV_BUSY	Cycles the divider is busy	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x14	0x1	ARITH.DIV	Divide Operations executed	0,1,2,3	2000000	0	0	1	1	0	1	0	
+0x14	0x2	ARITH.MUL	Multiply operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x2	BACLEAR.BAD_TARGET	BACLEAR asserted with bad target address	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE6	0x1	BACLEAR.CLEAR	BACLEAR asserted, regardless of cause 	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA7	0x1	BACLEAR_FORCE_IQ	Instruction queue forced BACLEAR	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x1	BPU_CLEARS.EARLY	Early Branch Prediciton Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE8	0x2	BPU_CLEARS.LATE	Late Branch Prediction Unit clears	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE5	0x1	BPU_MISSED_CALL_RET	Branch prediction unit missed call or return	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE0	0x1	BR_INST_DECODED	Branch instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x88	0x7F	BR_INST_EXEC.ANY	Branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x1	BR_INST_EXEC.COND	Conditional branch instructions executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x2	BR_INST_EXEC.DIRECT	Unconditional branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x10	BR_INST_EXEC.DIRECT_NEAR_CALL	Unconditional call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x20	BR_INST_EXEC.INDIRECT_NEAR_CALL	Indirect call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x4	BR_INST_EXEC.INDIRECT_NON_CALL	Indirect non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x30	BR_INST_EXEC.NEAR_CALLS	Call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x7	BR_INST_EXEC.NON_CALLS	All non call branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x88	0x8	BR_INST_EXEC.RETURN_NEAR	Indirect return branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x88	0x40	BR_INST_EXEC.TAKEN	Taken branches executed	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x1	BR_INST_RETIRED.CONDITIONAL	Retired conditional branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL	Retired near call instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC4	0x2	BR_INST_RETIRED.NEAR_CALL_R3	Retired near call instructions Ring 3 only(Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x89	0x7F	BR_MISP_EXEC.ANY	Mispredicted branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x1	BR_MISP_EXEC.COND	Mispredicted conditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x2	BR_MISP_EXEC.DIRECT	Mispredicted unconditional branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x10	BR_MISP_EXEC.DIRECT_NEAR_CALL	Mispredicted non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x20	BR_MISP_EXEC.INDIRECT_NEAR_CALL	Mispredicted indirect call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x4	BR_MISP_EXEC.INDIRECT_NON_CALL	Mispredicted indirect non call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x30	BR_MISP_EXEC.NEAR_CALLS	Mispredicted call branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x7	BR_MISP_EXEC.NON_CALLS	Mispredicted non call branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0x89	0x8	BR_MISP_EXEC.RETURN_NEAR	Mispredicted return branches executed	0,1,2,3	2000	0	0	0	0	0	0	0	
+0x89	0x40	BR_MISP_EXEC.TAKEN	Mispredicted taken branches executed	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC5	0x4	BR_MISP_RETIRED.ALL_BRANCHES	Mispredicted retired branch instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC5	0x1	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional retired branches (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xC5	0x2	BR_MISP_RETIRED.NEAR_CALL	Mispredicted near retired calls (Precise Event)	0,1,2,3	2000	0	0	0	0	0	0	1	
+0x63	0x2	CACHE_LOCK_CYCLES.L1D	Cycles L1D locked	0,1	2000000	0	0	0	0	0	0	0	
+0x63	0x1	CACHE_LOCK_CYCLES.L1D_L2	Cycles L1D and L2 locked	0,1	2000000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.REF	Reference cycles when thread is not halted (fixed counter)	Fixed counter 3	2000000	0	0	0	0	0	0	0	
+0x3C	0x1	CPU_CLK_UNHALTED.REF_P	Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x0	0x0	CPU_CLK_UNHALTED.THREAD	Cycles when thread is not halted (fixed counter)	Fixed counter 2	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.THREAD_P	Cycles when thread is not halted (programmable counter)	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.TOTAL_CYCLES	Total CPU cycles	0,1,2,3	2000000	0	0	2	1	0	0	0	
+0x8	0x1	DTLB_LOAD_MISSES.ANY	DTLB load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x80	DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED	DTLB load miss large page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x20	DTLB_LOAD_MISSES.PDE_MISS	DTLB load miss caused by low part of address	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x10	DTLB_LOAD_MISSES.STLB_HIT	DTLB second level hit	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x8	0x2	DTLB_LOAD_MISSES.WALK_COMPLETED	DTLB load miss page walks complete	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x8	0x4	DTLB_LOAD_MISSES.WALK_CYCLES	DTLB load miss page walk cycles	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x1	DTLB_MISSES.ANY	DTLB misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x80	DTLB_MISSES.LARGE_WALK_COMPLETED	DTLB miss large page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x20	DTLB_MISSES.PDE_MISS	DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x10	DTLB_MISSES.STLB_HIT	DTLB first level misses but second level hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x2	DTLB_MISSES.WALK_COMPLETED	DTLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x49	0x4	DTLB_MISSES.WALK_CYCLES	DTLB miss page walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4F	0x10	EPT.WALK_CYCLES	Extended Page Table walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD5	0x1	ES_REG_RENAMES	ES segment renames	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF7	0x1	FP_ASSIST.ALL	X87 Floating point assists (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x4	FP_ASSIST.INPUT	X87 Floating poiint assists for invalid input value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF7	0x2	FP_ASSIST.OUTPUT	X87 Floating point assists for invalid output value (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0x10	0x2	FP_COMP_OPS_EXE.MMX	MMX Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x80	FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION	SSE* FP double precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x4	FP_COMP_OPS_EXE.SSE_FP	SSE and SSE2 FP Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x10	FP_COMP_OPS_EXE.SSE_FP_PACKED	SSE FP packed Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x20	FP_COMP_OPS_EXE.SSE_FP_SCALAR	SSE FP scalar Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x40	FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION	SSE* FP single precision Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x8	FP_COMP_OPS_EXE.SSE2_INTEGER	SSE2 integer Uops	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x10	0x1	FP_COMP_OPS_EXE.X87	Computational floating-point operations executed	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x3	FP_MMX_TRANS.ANY	All Floating Point to and from MMX transitions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x1	FP_MMX_TRANS.TO_FP	Transitions from MMX to Floating Point instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xCC	0x2	FP_MMX_TRANS.TO_MMX	Transitions from Floating Point to MMX instructions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0xF	ILD_STALL.ANY	Any Instruction Length Decoder stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x4	ILD_STALL.IQ_FULL	Instruction Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x1	ILD_STALL.LCP	Length Change Prefix stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x2	ILD_STALL.MRU	Stall cycles due to BPU MRU bypass	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x87	0x8	ILD_STALL.REGEN	Regen stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x18	0x1	INST_DECODED.DEC0	Instructions that must be decoded by decoder 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x1E	0x1	INST_QUEUE_WRITE_CYCLES	Cycles instructions are written to the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x17	0x1	INST_QUEUE_WRITES	Instructions written to instruction queue.	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x0	0x0	INST_RETIRED.ANY	Instructions retired (fixed counter)	Fixed counter 1	2000000	0	0	0	0	0	0	0	
+0xC0	0x1	INST_RETIRED.ANY_P	Instructions retired (Programmable counter and Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x4	INST_RETIRED.MMX	Retired MMX instructions (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC0	0x1	INST_RETIRED.TOTAL_CYCLES	Total cycles (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC0	0x2	INST_RETIRED.X87	Retired floating-point operations (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0x6C	0x1	IO_TRANSACTIONS	I/O transactions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xAE	0x1	ITLB_FLUSH	ITLB flushes	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC8	0x20	ITLB_MISS_RETIRED	Retired instructions that missed the ITLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x85	0x1	ITLB_MISSES.ANY	ITLB miss	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x80	ITLB_MISSES.LARGE_WALK_COMPLETED	ITLB miss large page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x2	ITLB_MISSES.WALK_COMPLETED	ITLB miss page walks	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x85	0x4	ITLB_MISSES.WALK_CYCLES	ITLB miss page walk cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x51	0x4	L1D.M_EVICT	L1D cache lines replaced in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x2	L1D.M_REPL	L1D cache lines allocated in the M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x8	L1D.M_SNOOP_EVICT	L1D snoop eviction of cache lines in M state	0,1	2000000	0	0	0	0	0	0	0	
+0x51	0x1	L1D.REPL	L1 data cache lines allocated	0,1	2000000	0	0	0	0	0	0	0	
+0x52	0x1	L1D_CACHE_PREFETCH_LOCK_FB_HIT	L1D prefetch load lock accepted in fill buffer	0,1	2000000	0	0	0	0	0	0	0	
+0x4E	0x2	L1D_PREFETCH.MISS	L1D hardware prefetch misses	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x1	L1D_PREFETCH.REQUESTS	L1D hardware prefetch requests	0,1	200000	0	0	0	0	0	0	0	
+0x4E	0x4	L1D_PREFETCH.TRIGGERS	L1D hardware prefetch requests triggered	0,1	200000	0	0	0	0	0	0	0	
+0x28	0x4	L1D_WB_L2.E_STATE	L1 writebacks to L2 in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x1	L1D_WB_L2.I_STATE	L1 writebacks to L2 in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x8	L1D_WB_L2.M_STATE	L1 writebacks to L2 in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0xF	L1D_WB_L2.MESI	All L1 writebacks to L2	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x28	0x2	L1D_WB_L2.S_STATE	L1 writebacks to L2 in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x80	0x4	L1I.CYCLES_STALLED	L1I instruction fetch stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x1	L1I.HITS	L1I instruction fetch hits	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x2	L1I.MISSES	L1I instruction fetch misses	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x80	0x3	L1I.READS	L1I Instruction fetches	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x26	0xFF	L2_DATA_RQSTS.ANY	All L2 data requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x4	L2_DATA_RQSTS.DEMAND.E_STATE	L2 data demand loads in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x1	L2_DATA_RQSTS.DEMAND.I_STATE	L2 data demand loads in I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x8	L2_DATA_RQSTS.DEMAND.M_STATE	L2 data demand loads in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF	L2_DATA_RQSTS.DEMAND.MESI	L2 data demand requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x2	L2_DATA_RQSTS.DEMAND.S_STATE	L2 data demand loads in S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x40	L2_DATA_RQSTS.PREFETCH.E_STATE	L2 data prefetches in E state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x10	L2_DATA_RQSTS.PREFETCH.I_STATE	L2 data prefetches in the I state (misses)	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x80	L2_DATA_RQSTS.PREFETCH.M_STATE	L2 data prefetches in M state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0xF0	L2_DATA_RQSTS.PREFETCH.MESI	All L2 data prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x26	0x20	L2_DATA_RQSTS.PREFETCH.S_STATE	L2 data prefetches in the S state	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF1	0x7	L2_LINES_IN.ANY	L2 lines alloacated	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x4	L2_LINES_IN.E_STATE	L2 lines allocated in the E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF1	0x2	L2_LINES_IN.S_STATE	L2 lines allocated in the S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0xF	L2_LINES_OUT.ANY	L2 lines evicted	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x1	L2_LINES_OUT.DEMAND_CLEAN	L2 lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x2	L2_LINES_OUT.DEMAND_DIRTY	L2 modified lines evicted by a demand request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x4	L2_LINES_OUT.PREFETCH_CLEAN	L2 lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xF2	0x8	L2_LINES_OUT.PREFETCH_DIRTY	L2 modified lines evicted by a prefetch request	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x24	0x10	L2_RQSTS.IFETCH_HIT	L2 instruction fetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x20	L2_RQSTS.IFETCH_MISS	L2 instruction fetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x30	L2_RQSTS.IFETCHES	L2 instruction fetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x1	L2_RQSTS.LD_HIT	L2 load hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x2	L2_RQSTS.LD_MISS	L2 load misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x3	L2_RQSTS.LOADS	L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xAA	L2_RQSTS.MISS	All L2 misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x40	L2_RQSTS.PREFETCH_HIT	L2 prefetch hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x80	L2_RQSTS.PREFETCH_MISS	L2 prefetch misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC0	L2_RQSTS.PREFETCHES	All L2 prefetches	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xFF	L2_RQSTS.REFERENCES	All L2 requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x4	L2_RQSTS.RFO_HIT	L2 RFO hits	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0x8	L2_RQSTS.RFO_MISS	L2 RFO misses	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x24	0xC	L2_RQSTS.RFOS	L2 RFO requests	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x80	L2_TRANSACTIONS.ANY	All L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x20	L2_TRANSACTIONS.FILL	L2 fill transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x4	L2_TRANSACTIONS.IFETCH	L2 instruction fetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x10	L2_TRANSACTIONS.L1D_WB	L1D writeback to L2 transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x1	L2_TRANSACTIONS.LOAD	L2 Load transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x8	L2_TRANSACTIONS.PREFETCH	L2 prefetch transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x2	L2_TRANSACTIONS.RFO	L2 RFO transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xF0	0x40	L2_TRANSACTIONS.WB	L2 writeback to LLC transactions	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x27	0x40	L2_WRITE.LOCK.E_STATE	L2 demand lock RFOs in E state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE0	L2_WRITE.LOCK.HIT	All demand L2 lock RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x10	L2_WRITE.LOCK.I_STATE	L2 demand lock RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x80	L2_WRITE.LOCK.M_STATE	L2 demand lock RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF0	L2_WRITE.LOCK.MESI	All demand L2 lock RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x20	L2_WRITE.LOCK.S_STATE	L2 demand lock RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xE	L2_WRITE.RFO.HIT	All L2 demand store RFOs that hit the cache	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x1	L2_WRITE.RFO.I_STATE	L2 demand store RFOs in I state (misses)	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x8	L2_WRITE.RFO.M_STATE	L2 demand store RFOs in M state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0xF	L2_WRITE.RFO.MESI	All L2 demand store RFOs	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x27	0x2	L2_WRITE.RFO.S_STATE	L2 demand store RFOs in S state	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x82	0x1	LARGE_ITLB.HIT	Large ITLB hit	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x3	0x2	LOAD_BLOCK.OVERLAP_STORE	Loads that partially overlap an earlier store	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x13	0x7	LOAD_DISPATCH.ANY	All loads dispatched	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x4	LOAD_DISPATCH.MOB	Loads dispatched from the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x1	LOAD_DISPATCH.RS	Loads dispatched that bypass the MOB	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x13	0x2	LOAD_DISPATCH.RS_DELAYED	Loads dispatched from stage 305	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4C	0x1	LOAD_HIT_PRE	Load operations conflicting with software prefetches	0,1	200000	0	0	0	0	0	0	0	
+0x2E	0x41	LONGEST_LAT_CACHE.MISS	Longest latency cache miss	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Longest latency cache reference	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xA8	0x1	LSD.ACTIVE	Cycles when uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xA8	0x1	LSD.INACTIVE	Cycles no uops were delivered by the LSD	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0x20	0x1	LSD_OVERFLOW	Loops that can't stream from the instruction queue	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC3	0x1	MACHINE_CLEARS.CYCLES	Cycles machine clear asserted	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x2	MACHINE_CLEARS.MEM_ORDER	Execution pipeline restart due to Memory ordering conflicts	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xC3	0x4	MACHINE_CLEARS.SMC	Self-Modifying Code detected	0,1,2,3	20000	0	0	0	0	0	0	0	
+0xD0	0x1	MACRO_INSTS.DECODED	Instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA6	0x1	MACRO_INSTS.FUSIONS_DECODED	Macro-fused instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB	0x1	MEM_INST_RETIRED.LOADS	Instructions retired which contains a load (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xB	0x2	MEM_INST_RETIRED.STORES	Instructions retired which contains a store (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x80	MEM_LOAD_RETIRED.DTLB_MISS	Retired loads that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x40	MEM_LOAD_RETIRED.HIT_LFB	Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x1	MEM_LOAD_RETIRED.L1D_HIT	Retired loads that hit the L1 data cache (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xCB	0x2	MEM_LOAD_RETIRED.L2_HIT	Retired loads that hit the L2 cache (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xCB	0x10	MEM_LOAD_RETIRED.LLC_MISS	Retired loads that miss the LLC cache (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xCB	0x4	MEM_LOAD_RETIRED.LLC_UNSHARED_HIT	Retired loads that hit valid versions in the LLC cache (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xCB	0x8	MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM	Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xC	0x1	MEM_STORE_RETIRED.DTLB_MISS	Retired stores that miss the DTLB (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xF	0x2	MEM_UNCORE_RETIRED.LOCAL_HITM	Load instructions retired that HIT modified data in sibling core (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0xF	0x8	MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT	Load instructions retired local dram and remote cache HIT data sources (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xF	0x20	MEM_UNCORE_RETIRED.REMOTE_DRAM	Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)	0,1,2,3	10000	0	0	0	0	0	0	1	
+0xF	0x80	MEM_UNCORE_RETIRED.UNCACHEABLE	Load instructions retired IO (Precise Event)	0,1,2,3	4000	0	0	0	0	0	0	1	
+0xF	0x4	MEM_UNCORE_RETIRED.REMOTE_HITM	Retired loads that hit remote socket in modified state (Precise Event)	0,1,2,3	40000	0	0	0	0	0	0	1	
+0x5	0x2	MISALIGN_MEM_REF.STORE	Misaligned store references	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xB0	0x80	OFFCORE_REQUESTS.ANY	All offcore requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x8	OFFCORE_REQUESTS.ANY.READ	Offcore read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x10	OFFCORE_REQUESTS.ANY.RFO	Offcore RFO requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x2	OFFCORE_REQUESTS.DEMAND.READ_CODE	Offcore demand code read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x1	OFFCORE_REQUESTS.DEMAND.READ_DATA	Offcore demand data read requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x4	OFFCORE_REQUESTS.DEMAND.RFO	Offcore demand RFO requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB0	0x40	OFFCORE_REQUESTS.L1D_WRITEBACK	Offcore L1 data cache writebacks	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x60	0x8	OFFCORE_REQUESTS_OUTSTANDING.ANY.READ	Outstanding offcore reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x8	OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY	Cycles offcore reads busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x2	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE	Outstanding offcore demand code reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x2	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY	Cycles offcore demand code read busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x1	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA	Outstanding offcore demand data reads	0	2000000	0	0	0	0	0	0	0	
+0x60	0x1	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY	Cycles offcore demand data read busy	0	2000000	0	0	1	0	0	0	0	
+0x60	0x4	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO	Outstanding offcore demand RFOs	0	2000000	0	0	0	0	0	0	0	
+0x60	0x4	OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY	Cycles offcore demand RFOs busy	0	2000000	0	0	1	0	0	0	0	
+0xB2	0x1	OFFCORE_REQUESTS_SQ_FULL	Offcore requests blocked due to Super Queue full	0,1,2,3	100000	0	0	0	0	0	0	0	
+0x7	0x1	PARTIAL_ADDRESS_ALIAS	False dependencies due to partial address aliasing	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD2	0xF	RAT_STALLS.ANY	All RAT stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x1	RAT_STALLS.FLAGS	Flag stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x2	RAT_STALLS.REGISTERS	Partial register stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x4	RAT_STALLS.ROB_READ_PORT	ROB read port stalls cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD2	0x8	RAT_STALLS.SCOREBOARD	Scoreboard stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x1	RESOURCE_STALLS.ANY	Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x20	RESOURCE_STALLS.FPCW	FPU control word write stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x2	RESOURCE_STALLS.LOAD	Load buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x40	RESOURCE_STALLS.MXCSR	MXCSR rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x80	RESOURCE_STALLS.OTHER	Other Resource related stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x10	RESOURCE_STALLS.ROB_FULL	ROB full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x4	RESOURCE_STALLS.RS_FULL	Reservation Station full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xA2	0x8	RESOURCE_STALLS.STORE	Store buffer stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x4	0x7	SB_DRAIN.ANY	All Store buffer stall cycles	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xD4	0x1	SEG_RENAME_STALLS	Segment rename stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x12	0x4	SIMD_INT_128.PACK	128 bit SIMD integer pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x20	SIMD_INT_128.PACKED_ARITH	128 bit SIMD integer arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x10	SIMD_INT_128.PACKED_LOGICAL	128 bit SIMD integer logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x1	SIMD_INT_128.PACKED_MPY	128 bit SIMD integer multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x2	SIMD_INT_128.PACKED_SHIFT	128 bit SIMD integer shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x40	SIMD_INT_128.SHUFFLE_MOVE	128 bit SIMD integer shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x12	0x8	SIMD_INT_128.UNPACK	128 bit SIMD integer unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x4	SIMD_INT_64.PACK	SIMD integer 64 bit pack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x20	SIMD_INT_64.PACKED_ARITH	SIMD integer 64 bit arithmetic operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x10	SIMD_INT_64.PACKED_LOGICAL	SIMD integer 64 bit logical operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x1	SIMD_INT_64.PACKED_MPY	SIMD integer 64 bit packed multiply operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x2	SIMD_INT_64.PACKED_SHIFT	SIMD integer 64 bit shift operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x40	SIMD_INT_64.SHUFFLE_MOVE	SIMD integer 64 bit shuffle/move operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xFD	0x8	SIMD_INT_64.UNPACK	SIMD integer 64 bit unpack operations	0,1,2,3	200000	0	0	0	0	0	0	0	
+0xB8	0x1	SNOOP_RESPONSE.HIT	Thread responded HIT to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x2	SNOOP_RESPONSE.HITE	Thread responded HITE to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB8	0x4	SNOOP_RESPONSE.HITM	Thread responded HITM to snoop	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x4	SNOOPQ_REQUESTS.CODE	Snoop code requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x1	SNOOPQ_REQUESTS.DATA	Snoop data requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB4	0x2	SNOOPQ_REQUESTS.INVALIDATE	Snoop invalidate requests	0,1,2,3	100000	0	0	0	0	0	0	0	
+0xB3	0x4	SNOOPQ_REQUESTS_OUTSTANDING.CODE	Outstanding snoop code requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x4	SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY	Cycles snoop code requests queued	0	2000000	0	0	1	0	0	0	0	
+0xB3	0x1	SNOOPQ_REQUESTS_OUTSTANDING.DATA	Outstanding snoop data requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x1	SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY	Cycles snoop data requests queued	0	2000000	0	0	1	0	0	0	0	
+0xB3	0x2	SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE	Outstanding snoop invalidate requests	0	2000000	0	0	0	0	0	0	0	
+0xB3	0x2	SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY	Cycles snoop invalidate requests queued	0	2000000	0	0	1	0	0	0	0	
+0xF6	0x1	SQ_FULL_STALL_CYCLES	Super Queue full stall cycles	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF4	0x4	SQ_MISC.LRU_HINTS	Super Queue LRU hints sent to LLC	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xF4	0x10	SQ_MISC.SPLIT_LOCK	Super Queue lock splits across a cache line	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xC7	0x4	SSEX_UOPS_RETIRED.PACKED_DOUBLE	SIMD Packed-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x1	SSEX_UOPS_RETIRED.PACKED_SINGLE	SIMD Packed-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x8	SSEX_UOPS_RETIRED.SCALAR_DOUBLE	SIMD Scalar-Double Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x2	SSEX_UOPS_RETIRED.SCALAR_SINGLE	SIMD Scalar-Single Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC7	0x10	SSEX_UOPS_RETIRED.VECTOR_INTEGER	SIMD Vector Integer Uops retired (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0x6	0x4	STORE_BLOCKS.AT_RET	Loads delayed with at-Retirement block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x6	0x8	STORE_BLOCKS.L1D_BLOCK	Cacheable loads delayed with L1D block code	0,1,2,3	200000	0	0	0	0	0	0	0	
+0x3C	0x0	CPU_CLK_UNHALTED.THREAD_P	Cycles thread is active	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0x19	0x1	TWO_UOP_INSTS_DECODED	Two Uop instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xDB	0x1	UOP_UNFUSION	Uop unfusions due to FP exceptions	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x4	UOPS_DECODED.ESP_FOLDING	Stack pointer instructions decoded	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x8	UOPS_DECODED.ESP_SYNC	Stack pointer sync operations	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xD1	0x2	UOPS_DECODED.MS_CYCLES_ACTIVE	Uops decoded by Microcode Sequencer	0,1,2,3	2000000	0	0	1	0	0	0	0	
+0xD1	0x1	UOPS_DECODED.STALL_CYCLES	Cycles no Uops are decoded	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES	Cycles Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5	Cycles Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_COUNT	Uops executed on any port (core count)	0,1,2,3	2000000	0	0	1	1	0	1	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5	Uops executed on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	0	1	0	
+0xB1	0x3F	UOPS_EXECUTED.CORE_STALL_CYCLES	Cycles no Uops issued on any port (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1F	UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5	Cycles no Uops issued on ports 0-4 (core count)	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xB1	0x1	UOPS_EXECUTED.PORT0	Uops executed on port 0	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015	Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x40	UOPS_EXECUTED.PORT015_STALL_CYCLES	Cycles no Uops issued on ports 0, 1 or 5	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xB1	0x2	UOPS_EXECUTED.PORT1	Uops executed on port 1	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xB1	0x4	UOPS_EXECUTED.PORT2_CORE	Uops executed on port 2 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x80	UOPS_EXECUTED.PORT234_CORE	Uops issued on ports 2, 3 or 4	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x8	UOPS_EXECUTED.PORT3_CORE	Uops executed on port 3 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x10	UOPS_EXECUTED.PORT4_CORE	Uops executed on port 4 (core count)	0,1,2,3	2000000	0	0	0	0	1	0	0	
+0xB1	0x20	UOPS_EXECUTED.PORT5	Uops executed on port 5	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.ANY	Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles no Uops were issued on any thread	0,1,2,3	2000000	0	0	1	1	1	0	0	
+0xE	0x1	UOPS_ISSUED.CYCLES_ALL_THREADS	Cycles Uops were issued on either thread	0,1,2,3	2000000	0	0	1	0	1	0	0	
+0xE	0x2	UOPS_ISSUED.FUSED	Fused Uops issued	0,1,2,3	2000000	0	0	0	0	0	0	0	
+0xE	0x1	UOPS_ISSUED.STALL_CYCLES	Cycles no Uops were issued	0,1,2,3	2000000	0	0	1	1	0	0	0	
+0xC2	0x1	UOPS_RETIRED.ACTIVE_CYCLES	Cycles Uops are being retired	0,1,2,3	2000000	0	0	1	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.ANY	Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x4	UOPS_RETIRED.MACRO_FUSED	Macro-fused Uops retired (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x2	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used (Precise Event)	0,1,2,3	2000000	0	0	0	0	0	0	1	
+0xC2	0x1	UOPS_RETIRED.STALL_CYCLES	Cycles Uops are not retiring (Precise Event)	0,1,2,3	2000000	0	0	1	1	0	0	1	
+0xC2	0x1	UOPS_RETIRED.TOTAL_CYCLES	Total cycles using precise uop retired event (Precise Event)	0,1,2,3	2000000	0	0	16	1	0	0	1	
+0xC4	0x4	BR_INST_RETIRED.ALL_BRANCHES	Retired branch instructions (Precise Event)	0,1,2,3	200000	0	0	0	0	0	0	1	
+0xC5	0x4	BR_MISP_RETIRED.ALL_BRANCHES	Mispredicted retired branch instructions (Precise Event)	0,1,2,3	20000	0	0	0	0	0	0	1	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0	Memory instructions retired above 0 clocks (Precise Event)	3	2000000	0x3F6	0x0	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024	Memory instructions retired above 1024 clocks (Precise Event)	3	100	0x3F6	0x400	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128	Memory instructions retired above 128 clocks (Precise Event)	3	1000	0x3F6	0x80	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16	Memory instructions retired above 16 clocks (Precise Event)	3	10000	0x3F6	0x10	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384	Memory instructions retired above 16384 clocks (Precise Event)	3	5	0x3F6	0x4000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048	Memory instructions retired above 2048 clocks (Precise Event)	3	50	0x3F6	0x800	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256	Memory instructions retired above 256 clocks (Precise Event)	3	500	0x3F6	0x100	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32	Memory instructions retired above 32 clocks (Precise Event)	3	5000	0x3F6	0x20	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768	Memory instructions retired above 32768 clocks (Precise Event)	3	3	0x3F6	0x8000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4	Memory instructions retired above 4 clocks (Precise Event)	3	50000	0x3F6	0x4	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096	Memory instructions retired above 4096 clocks (Precise Event)	3	20	0x3F6	0x1000	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512	Memory instructions retired above 512 clocks (Precise Event)	3	200	0x3F6	0x200	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64	Memory instructions retired above 64 clocks (Precise Event)	3	2000	0x3F6	0x40	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8	Memory instructions retired above 8 clocks (Precise Event)	3	20000	0x3F6	0x8	0	0	0	0	2	
+0xB	0x10	MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192	Memory instructions retired above 8192 clocks (Precise Event)	3	10	0x3F6	0x2000	0	0	0	0	2	
diff --git a/x86data/perfmon_data/WSM-EX/WestmereEX_offcore_V1.tsv b/x86data/perfmon_data/WSM-EX/WestmereEX_offcore_V1.tsv
new file mode 100644
index 0000000..433e9d2
--- /dev/null
+++ b/x86data/perfmon_data/WSM-EX/WestmereEX_offcore_V1.tsv
@@ -0,0 +1,273 @@
+# Performance Monitoring Events for Intel Xeon Processor E7 Family Based on the Westmere-EX Microarchitecture - V1
+# 12/13/2013 11:00:48 AM
+EventCode	UMask	EventName	BriefDescription	Counter	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM	Offcore data reads satisfied by any cache or DRAM	2	100000	0x1A6	0x7F11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM	Offcore data reads satisfied by any DRAM	2	100000	0x1A6	0x6011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS	Offcore data reads that missed the LLC	2	100000	0x1A6	0xF811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION	All offcore data reads	2	100000	0x1A6	0xFF11	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO	Offcore data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE	Offcore data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x111	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x211	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x411	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE	Offcore data reads satisfied by the LLC	2	100000	0x1A6	0x711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM	Offcore data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4711	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM	Offcore data reads satisfied by the local DRAM	2	100000	0x1A6	0x4011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE	Offcore data reads satisfied by a remote cache	2	100000	0x1A6	0x1811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM	Offcore data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT	Offcore data reads that HIT in a remote cache	2	100000	0x1A6	0x1011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM	Offcore data reads that HITM in a remote cache	2	100000	0x1A6	0x811	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM	Offcore data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2011	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM	Offcore code reads satisfied by any cache or DRAM	2	100000	0x1A6	0x7F44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM	Offcore code reads satisfied by any DRAM	2	100000	0x1A6	0x6044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS	Offcore code reads that missed the LLC	2	100000	0x1A6	0xF844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION	All offcore code reads	2	100000	0x1A6	0xFF44	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO	Offcore code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x144	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x244	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x444	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE	Offcore code reads satisfied by the LLC	2	100000	0x1A6	0x744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM	Offcore code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4744	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM	Offcore code reads satisfied by the local DRAM	2	100000	0x1A6	0x4044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE	Offcore code reads satisfied by a remote cache	2	100000	0x1A6	0x1844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM	Offcore code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT	Offcore code reads that HIT in a remote cache	2	100000	0x1A6	0x1044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM	Offcore code reads that HITM in a remote cache	2	100000	0x1A6	0x844	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM	Offcore code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2044	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM	Offcore requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7FFF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM	Offcore requests satisfied by any DRAM	2	100000	0x1A6	0x60FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS	Offcore requests that missed the LLC	2	100000	0x1A6	0xF8FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION	All offcore requests	2	100000	0x1A6	0xFFFF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO	Offcore requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x80FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE	Offcore requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x1FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT	Offcore requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x2FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM	Offcore requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x4FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE	Offcore requests satisfied by the LLC	2	100000	0x1A6	0x7FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM	Offcore requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x47FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM	Offcore requests satisfied by the local DRAM	2	100000	0x1A6	0x40FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE	Offcore requests satisfied by a remote cache	2	100000	0x1A6	0x18FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM	Offcore requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x38FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT	Offcore requests that HIT in a remote cache	2	100000	0x1A6	0x10FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM	Offcore requests that HITM in a remote cache	2	100000	0x1A6	0x8FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM	Offcore requests satisfied by a remote DRAM	2	100000	0x1A6	0x20FF	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM	Offcore RFO requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM	Offcore RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS	Offcore RFO requests that missed the LLC	2	100000	0x1A6	0xF822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION	All offcore RFO requests	2	100000	0x1A6	0xFF22	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO	Offcore RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE	Offcore RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x122	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x222	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x422	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE	Offcore RFO requests satisfied by the LLC	2	100000	0x1A6	0x722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM	Offcore RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4722	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM	Offcore RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE	Offcore RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM	Offcore RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT	Offcore RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM	Offcore RFO requests that HITM in a remote cache	2	100000	0x1A6	0x822	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM	Offcore RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2022	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM	Offcore writebacks to any cache or DRAM.	2	100000	0x1A6	0x7F08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_DRAM	Offcore writebacks to any DRAM	2	100000	0x1A6	0x6008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS	Offcore writebacks that missed the LLC	2	100000	0x1A6	0xF808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION	All offcore writebacks	2	100000	0x1A6	0xFF08	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO	Offcore writebacks to the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE	Offcore writebacks to the LLC and not found in a sibling core	2	100000	0x1A6	0x108	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM	Offcore writebacks to the LLC  and HITM in a sibling core	2	100000	0x1A6	0x408	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE	Offcore writebacks to the LLC	2	100000	0x1A6	0x708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM	Offcore writebacks to the LLC or local DRAM	2	100000	0x1A6	0x4708	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM	Offcore writebacks to the local DRAM	2	100000	0x1A6	0x4008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE	Offcore writebacks to a remote cache	2	100000	0x1A6	0x1808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM	Offcore writebacks to a remote cache or remote DRAM	2	100000	0x1A6	0x3808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT	Offcore writebacks that HIT in a remote cache	2	100000	0x1A6	0x1008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM	Offcore writebacks that HITM in a remote cache	2	100000	0x1A6	0x808	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM	Offcore writebacks to a remote DRAM	2	100000	0x1A6	0x2008	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM	Offcore code or data read requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM	Offcore code or data read requests satisfied by any DRAM	2	100000	0x1A6	0x6077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS	Offcore code or data read requests that missed the LLC	2	100000	0x1A6	0xF877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION	All offcore code or data read requests	2	100000	0x1A6	0xFF77	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO	Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore code or data read requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x177	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore code or data read requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x277	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x477	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE	Offcore code or data read requests satisfied by the LLC	2	100000	0x1A6	0x777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM	Offcore code or data read requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4777	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM	Offcore code or data read requests satisfied by the local DRAM	2	100000	0x1A6	0x4077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE	Offcore code or data read requests satisfied by a remote cache	2	100000	0x1A6	0x1877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM	Offcore code or data read requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT	Offcore code or data read requests that HIT in a remote cache	2	100000	0x1A6	0x1077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM	Offcore code or data read requests that HITM in a remote cache	2	100000	0x1A6	0x877	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM	Offcore code or data read requests satisfied by a remote DRAM	2	100000	0x1A6	0x2077	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM	Offcore request = all data, response = any cache_dram	2	100000	0x1A6	0x7F33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM	Offcore request = all data, response = any DRAM	2	100000	0x1A6	0x6033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS	Offcore request = all data, response = any LLC miss	2	100000	0x1A6	0xF833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION	Offcore request = all data, response = any location	2	100000	0x1A6	0xFF33	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO	Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE	Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x133	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT	Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x233	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM	Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x433	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE	Offcore request = all data, response = local cache	2	100000	0x1A6	0x733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM	Offcore request = all data, response = local cache or dram	2	100000	0x1A6	0x4733	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM	Offcore data reads, RFO's and prefetches statisfied by the local DRAM.	2	100000	0x1A6	0x4033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE	Offcore request = all data, response = remote cache	2	100000	0x1A6	0x1833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM	Offcore request = all data, response = remote cache or dram	2	100000	0x1A6	0x3833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT	Offcore data reads, RFO's and prefetches that HIT in a remote cache 	2	100000	0x1A6	0x1033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM	Offcore data reads, RFO's and prefetches that HITM in a remote cache	2	100000	0x1A6	0x833	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM	Offcore data reads, RFO's and prefetches statisfied by the remote DRAM	2	100000	0x1A6	0x2033	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM	Offcore demand data requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM	Offcore demand data requests satisfied by any DRAM	2	100000	0x1A6	0x6003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS	Offcore demand data requests that missed the LLC	2	100000	0x1A6	0xF803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION	All offcore demand data requests	2	100000	0x1A6	0xFF03	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO	Offcore demand data requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE	Offcore demand data requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x103	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore demand data requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x203	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore demand data requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x403	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE	Offcore demand data requests satisfied by the LLC	2	100000	0x1A6	0x703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM	Offcore demand data requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4703	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM	Offcore demand data requests satisfied by the local DRAM	2	100000	0x1A6	0x4003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE	Offcore demand data requests satisfied by a remote cache	2	100000	0x1A6	0x1803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM	Offcore demand data requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT	Offcore demand data requests that HIT in a remote cache	2	100000	0x1A6	0x1003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM	Offcore demand data requests that HITM in a remote cache	2	100000	0x1A6	0x803	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM	Offcore demand data requests satisfied by a remote DRAM	2	100000	0x1A6	0x2003	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM	Offcore demand data reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM	Offcore demand data reads satisfied by any DRAM	2	100000	0x1A6	0x6001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS	Offcore demand data reads that missed the LLC	2	100000	0x1A6	0xF801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION	All offcore demand data reads	2	100000	0x1A6	0xFF01	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO	Offcore demand data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE	Offcore demand data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x101	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT	Offcore demand data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x201	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM	Offcore demand data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x401	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE	Offcore demand data reads satisfied by the LLC	2	100000	0x1A6	0x701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM	Offcore demand data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4701	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM	Offcore demand data reads satisfied by the local DRAM	2	100000	0x1A6	0x4001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE	Offcore demand data reads satisfied by a remote cache	2	100000	0x1A6	0x1801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM	Offcore demand data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT	Offcore demand data reads that HIT in a remote cache	2	100000	0x1A6	0x1001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM	Offcore demand data reads that HITM in a remote cache	2	100000	0x1A6	0x801	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM	Offcore demand data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2001	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM	Offcore demand code reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM	Offcore demand code reads satisfied by any DRAM	2	100000	0x1A6	0x6004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS	Offcore demand code reads that missed the LLC	2	100000	0x1A6	0xF804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION	All offcore demand code reads	2	100000	0x1A6	0xFF04	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO	Offcore demand code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore demand code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x104	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore demand code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x204	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore demand code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x404	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE	Offcore demand code reads satisfied by the LLC	2	100000	0x1A6	0x704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM	Offcore demand code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4704	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM	Offcore demand code reads satisfied by the local DRAM	2	100000	0x1A6	0x4004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE	Offcore demand code reads satisfied by a remote cache	2	100000	0x1A6	0x1804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM	Offcore demand code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT	Offcore demand code reads that HIT in a remote cache	2	100000	0x1A6	0x1004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM	Offcore demand code reads that HITM in a remote cache	2	100000	0x1A6	0x804	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM	Offcore demand code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2004	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM	Offcore demand RFO requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM	Offcore demand RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS	Offcore demand RFO requests that missed the LLC	2	100000	0x1A6	0xF802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION	All offcore demand RFO requests	2	100000	0x1A6	0xFF02	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO	Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE	Offcore demand RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x102	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x202	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x402	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE	Offcore demand RFO requests satisfied by the LLC	2	100000	0x1A6	0x702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM	Offcore demand RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4702	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM	Offcore demand RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE	Offcore demand RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM	Offcore demand RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT	Offcore demand RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM	Offcore demand RFO requests that HITM in a remote cache	2	100000	0x1A6	0x802	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM	Offcore demand RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2002	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM	Offcore other requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_DRAM	Offcore other requests satisfied by any DRAM	2	100000	0x1A6	0x6080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS	Offcore other requests that missed the LLC	2	100000	0x1A6	0xF880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION	All offcore other requests	2	100000	0x1A6	0xFF80	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO	Offcore other requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE	Offcore other requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x180	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT	Offcore other requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x280	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM	Offcore other requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x480	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE	Offcore other requests satisfied by the LLC	2	100000	0x1A6	0x780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM	Offcore other requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4780	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE	Offcore other requests satisfied by a remote cache	2	100000	0x1A6	0x1880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM	Offcore other requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT	Offcore other requests that HIT in a remote cache	2	100000	0x1A6	0x1080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM	Offcore other requests that HITM in a remote cache	2	100000	0x1A6	0x880	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM	Offcore other requests satisfied by a remote DRAM	2	100000	0x1A6	0x2080	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM	Offcore prefetch data requests satisfied by any cache or DRAM	2	100000	0x1A6	0x7F30	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM	Offcore prefetch data requests satisfied by any DRAM	2	100000	0x1A6	0x6030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS	Offcore prefetch data requests that missed the LLC	2	100000	0x1A6	0xF830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION	All offcore prefetch data requests	2	100000	0x1A6	0xFF30	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO	Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.	2	100000	0x1A6	0x8030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE	Offcore prefetch data requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x130	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x230	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x430	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE	Offcore prefetch data requests satisfied by the LLC	2	100000	0x1A6	0x730	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM	Offcore prefetch data requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4730	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM	Offcore prefetch data requests satisfied by the local DRAM	2	100000	0x1A6	0x4030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE	Offcore prefetch data requests satisfied by a remote cache	2	100000	0x1A6	0x1830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM	Offcore prefetch data requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT	Offcore prefetch data requests that HIT in a remote cache	2	100000	0x1A6	0x1030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM	Offcore prefetch data requests that HITM in a remote cache	2	100000	0x1A6	0x830	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM	Offcore prefetch data requests satisfied by a remote DRAM	2	100000	0x1A6	0x2030	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM	Offcore prefetch data reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM	Offcore prefetch data reads satisfied by any DRAM	2	100000	0x1A6	0x6010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS	Offcore prefetch data reads that missed the LLC	2	100000	0x1A6	0xF810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION	All offcore prefetch data reads	2	100000	0x1A6	0xFF10	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO	Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE	Offcore prefetch data reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x110	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x210	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x410	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE	Offcore prefetch data reads satisfied by the LLC	2	100000	0x1A6	0x710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM	Offcore prefetch data reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4710	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM	Offcore prefetch data reads satisfied by the local DRAM	2	100000	0x1A6	0x4010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE	Offcore prefetch data reads satisfied by a remote cache	2	100000	0x1A6	0x1810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM	Offcore prefetch data reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT	Offcore prefetch data reads that HIT in a remote cache	2	100000	0x1A6	0x1010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM	Offcore prefetch data reads that HITM in a remote cache	2	100000	0x1A6	0x810	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM	Offcore prefetch data reads satisfied by a remote DRAM	2	100000	0x1A6	0x2010	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM	Offcore prefetch code reads satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM	Offcore prefetch code reads satisfied by any DRAM	2	100000	0x1A6	0x6040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS	Offcore prefetch code reads that missed the LLC	2	100000	0x1A6	0xF840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION	All offcore prefetch code reads	2	100000	0x1A6	0xFF40	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO	Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE	Offcore prefetch code reads satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x140	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x240	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x440	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE	Offcore prefetch code reads satisfied by the LLC	2	100000	0x1A6	0x740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM	Offcore prefetch code reads satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4740	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM	Offcore prefetch code reads satisfied by the local DRAM	2	100000	0x1A6	0x4040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE	Offcore prefetch code reads satisfied by a remote cache	2	100000	0x1A6	0x1840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM	Offcore prefetch code reads satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT	Offcore prefetch code reads that HIT in a remote cache	2	100000	0x1A6	0x1040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM	Offcore prefetch code reads that HITM in a remote cache	2	100000	0x1A6	0x840	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM	Offcore prefetch code reads satisfied by a remote DRAM	2	100000	0x1A6	0x2040	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM	Offcore prefetch RFO requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM	Offcore prefetch RFO requests satisfied by any DRAM	2	100000	0x1A6	0x6020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS	Offcore prefetch RFO requests that missed the LLC	2	100000	0x1A6	0xF820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION	All offcore prefetch RFO requests	2	100000	0x1A6	0xFF20	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO	Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE	Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x120	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x220	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x420	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE	Offcore prefetch RFO requests satisfied by the LLC	2	100000	0x1A6	0x720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM	Offcore prefetch RFO requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4720	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM	Offcore prefetch RFO requests satisfied by the local DRAM	2	100000	0x1A6	0x4020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE	Offcore prefetch RFO requests satisfied by a remote cache	2	100000	0x1A6	0x1820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM	Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT	Offcore prefetch RFO requests that HIT in a remote cache	2	100000	0x1A6	0x1020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM	Offcore prefetch RFO requests that HITM in a remote cache	2	100000	0x1A6	0x820	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM	Offcore prefetch RFO requests satisfied by a remote DRAM	2	100000	0x1A6	0x2020	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM	Offcore prefetch requests satisfied by any cache or DRAM.	2	100000	0x1A6	0x7F70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM	Offcore prefetch requests satisfied by any DRAM	2	100000	0x1A6	0x6070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS	Offcore prefetch requests that missed the LLC	2	100000	0x1A6	0xF870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION	All offcore prefetch requests	2	100000	0x1A6	0xFF70	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO	Offcore prefetch requests satisfied by the IO, CSR, MMIO unit	2	100000	0x1A6	0x8070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE	Offcore prefetch requests satisfied by the LLC and not found in a sibling core	2	100000	0x1A6	0x170	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT	Offcore prefetch requests satisfied by the LLC and HIT in a sibling core	2	100000	0x1A6	0x270	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM	Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core	2	100000	0x1A6	0x470	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE	Offcore prefetch requests satisfied by the LLC	2	100000	0x1A6	0x770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM	Offcore prefetch requests satisfied by the LLC or local DRAM	2	100000	0x1A6	0x4770	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM	Offcore prefetch requests satisfied by the local DRAM	2	100000	0x1A6	0x4070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE	Offcore prefetch requests satisfied by a remote cache	2	100000	0x1A6	0x1870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM	Offcore prefetch requests satisfied by a remote cache or remote DRAM	2	100000	0x1A6	0x3870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT	Offcore prefetch requests that HIT in a remote cache	2	100000	0x1A6	0x1070	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM	Offcore prefetch requests that HITM in a remote cache	2	100000	0x1A6	0x870	0	0	0	0	0	
+0xB7	0x1	OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM	Offcore prefetch requests satisfied by a remote DRAM	2	100000	0x1A6	0x2070	0	0	0	0	0	
diff --git a/x86data/perfmon_data/mapfile.csv b/x86data/perfmon_data/mapfile.csv
new file mode 100644
index 0000000..26485ad
--- /dev/null
+++ b/x86data/perfmon_data/mapfile.csv
@@ -0,0 +1,59 @@
+Family-model,Version,Filename,EventType
+GenuineIntel-6-2E,V1,/NHM-EX/NehalemEX_core_V1.json,core
+GenuineIntel-6-1E,V1,/NHM-EP/NehalemEP_core_V1.json,core
+GenuineIntel-6-1F,V1,/NHM-EP/NehalemEP_core_V1.json,core
+GenuineIntel-6-1A,V1,/NHM-EP/NehalemEP_core_V1.json,core
+GenuineIntel-6-2F,V1,/WSM-EX/WestmereEX_core_V1.json,core
+GenuineIntel-6-25,V1,/WSM-EP-SP/WestmereEP-SP_core_V1.json,core
+GenuineIntel-6-2C,V1,/WSM-EP-DP/WestmereEP-DP_core_V1.json,core
+GenuineIntel-6-37,V8,/SLM/Silvermont_core_V10.json,core
+GenuineIntel-6-37,V8,/SLM/Silvermont_matrix_V10.json,offcore
+GenuineIntel-6-4D,V8,/SLM/Silvermont_core_V10.json,core
+GenuineIntel-6-4D,V8,/SLM/Silvermont_matrix_V10.json,offcore
+GenuineIntel-6-4C,V8,/SLM/Silvermont_core_V10.json,core
+GenuineIntel-6-4C,V8,/SLM/Silvermont_matrix_V10.json,offcore
+GenuineIntel-6-1C,V1,/BNL/Bonnell_core_V1.json,core
+GenuineIntel-6-26,V1,/BNL/Bonnell_core_V1.json,core
+GenuineIntel-6-27,V1,/BNL/Bonnell_core_V1.json,core
+GenuineIntel-6-36,V1,/BNL/Bonnell_core_V1.json,core
+GenuineIntel-6-35,V1,/BNL/Bonnell_core_V1.json,core
+GenuineIntel-6-2A,V12,/SNB/SandyBridge_core_V12.json,core
+GenuineIntel-6-2A,V12,/SNB/SandyBridge_matrix_V12.json,offcore
+GenuineIntel-6-2A,V12,/SNB/SandyBridge_uncore_V12.json,uncore
+GenuineIntel-6-2D,V18,/JKT/Jaketown_core_V18.json,core
+GenuineIntel-6-2D,V18,/JKT/Jaketown_matrix_V18.json,offcore
+GenuineIntel-6-2D,V18,/JKT/Jaketown_uncore_V18.json,uncore
+GenuineIntel-6-3A,V15,/IVB/IvyBridge_core_V15.json,core
+GenuineIntel-6-3A,V15,/IVB/IvyBridge_matrix_V15.json,offcore
+GenuineIntel-6-3A,V15,/IVB/IvyBridge_uncore_V15.json,uncore
+GenuineIntel-6-3E,V17,/IVT/IvyTown_core_V17.json,core
+GenuineIntel-6-3E,V17,/IVT/IvyTown_matrix_V17.json,offcore
+GenuineIntel-6-3E,V17,/IVT/IvyTown_uncore_V17.json,uncore
+GenuineIntel-6-3C,V20,/HSW/Haswell_core_V20.json,core
+GenuineIntel-6-45,V20,/HSW/Haswell_core_V20.json,core
+GenuineIntel-6-46,V20,/HSW/Haswell_core_V20.json,core
+GenuineIntel-6-3C,V20,/HSW/Haswell_matrix_V20.json,offcore
+GenuineIntel-6-45,V20,/HSW/Haswell_matrix_V20.json,offcore
+GenuineIntel-6-46,V20,/HSW/Haswell_matrix_V20.json,offcore
+GenuineIntel-6-3C,V20,/HSW/Haswell_uncore_V20.json,uncore
+GenuineIntel-6-45,V20,/HSW/Haswell_uncore_V20.json,uncore
+GenuineIntel-6-46,V20,/HSW/Haswell_uncore_V20.json,uncore
+GenuineIntel-6-3F,V14,/HSX/HaswellX_core_V14.json,core
+GenuineIntel-6-3F,V14,/HSX/HaswellX_matrix_V14.json,offcore
+GenuineIntel-6-3F,V14,/HSX/HaswellX_uncore_V14.json,uncore
+GenuineIntel-6-3D,V11,/BDW/Broadwell_core_V11.json,core
+GenuineIntel-6-3D,V11,/BDW/Broadwell_matrix_V11.json,offcore
+GenuineIntel-6-3D,V11,/BDW/Broadwell_uncore_V11.json,uncore
+GenuineIntel-6-3D,V11,/BDW/Broadwell_FP_ARITH_INST_V11.json,fp_arith_inst
+GenuineIntel-6-47,V11,/BDW/Broadwell_core_V11.json,core
+GenuineIntel-6-47,V11,/BDW/Broadwell_matrix_V11.json,offcore
+GenuineIntel-6-47,V11,/BDW/Broadwell_uncore_V11.json,uncore
+GenuineIntel-6-47,V11,/BDW/Broadwell_FP_ARITH_INST_V11.json,fp_arith_inst
+GenuineIntel-6-56,V1,/BDW-DE/BroadwellDE_core_V1.json,core
+GenuineIntel-6-56,V1,/BDW-DE/BroadwellDE_uncore_V1.json,uncore
+GenuineIntel-6-4E,V11,/SKL/Skylake_core_V13.json,core
+GenuineIntel-6-5E,V11,/SKL/Skylake_core_V13.json,core
+GenuineIntel-6-4E,V11,/SKL/Skylake_matrix_V13.json,offcore
+GenuineIntel-6-5E,V11,/SKL/Skylake_matrix_V13.json,offcore
+GenuineIntel-6-4E,V11,/SKL/Skylake_FP_ARITH_INST_V13.json,fp_arith_inst
+GenuineIntel-6-5E,V11,/SKL/Skylake_FP_ARITH_INST_V13.json,fp_arith_inst
diff --git a/x86data/perfmon_data/readme.txt b/x86data/perfmon_data/readme.txt
new file mode 100644
index 0000000..ffdd889
--- /dev/null
+++ b/x86data/perfmon_data/readme.txt
@@ -0,0 +1,182 @@
+---------------------	
+This package contains performance monitoring event lists for Intel processors, as well as a mapping file	
+to help match event lists to processor Family/Model/Stepping codes. 	
+---------------------	
+	
+The event lists are available in 2 formats:	
+	Tab delimited (.tsv)
+	Json (.json)
+	
+Event lists are created per microarchitecture, and each has a version. Versions are listed in the event list	
+name as well as the header for each file. For some microarchitectures, up to three different event lists will	
+be available. These event lists correspond to the types of events that can be collected: 	
+	
+core - Contains events counted from within a logical processor core.		
+offcore - Contains matrix events counted from the core, but measuring responses that come from offcore.	
+	
+The event list filename indicates which type of list it contains, and follows this format:	
+<microarchitecture-codename>_<core/offcore>_<version>
+
+New version releases will be announced in the mail list perfmon-announce@lists.01.org 	
+	
+Different microarchitectures provide different performance monitoring capabilities, so field names and categories	
+of events may vary.	
+	
+---------------------	
+Event List Field Defitions: 	
+---------------------	
+Below is a list of the fields/headers in the event files and a description of how SW tools should	
+interpret these values. A particular event list from this package may not contain all the fields described	
+below. For more detailed information of the Performance monitoring unit please refer to chapters 18 and 19	
+of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2.	
+	
+http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html	
+	
+	
+----EventCode----	
+This field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs. The set of values for this field	
+is defined architecturally. Each value corresponds to an event logic unit and should be used with a unit 	
+mask value to obtain an architectural performance event.	
+	
+----UMask----	
+This field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs. It further qualifies the event logic 
+unit selected in the event select field to detect a specific micro-architectural condition.
+ 	
+----EventName----	
+It is a string of characters to identify the programming of an event.	
+	
+----BriefDescription----	
+This field contains a description of what is being counted by a particular event.	
+	
+----PublicDescription----	
+In some cases, this field will contain a more detailed description of what is counted by an event.	
+	
+----Counter----	
+This field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX) counters that can be used to count the event.	
+	
+----CounterHTOff----	
+This field lists the counters where this event can be sampled when Intel® Hyper-Threading Technology (Intel® HT Technology) is 	
+disabled. When Intel® HT Technology is disabled, some processor cores gain access to the programmable counters of the second 	
+thread, making a total of eight programmable counters available. The additional counters will be numbered 4,5,6,7. Fixed counter 	
+behavior remains unaffected.
+
+----PEBScounters----	
+This field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event.
+	
+----SampleAfterValue----	
+Sample After Value (SAV) is the value that can be pre-loaded into the counter registers to set the point at which they will overflow. 	
+To make the counter overflow after N occurrences of the event, it should be loaded with (0xFF..FF – N) or –(N-1). On overflow a 	
+hardware interrupt is generated through the Local APIC and additional architectural state can be collected in the interrupt handler. 	
+This is useful in event-based sampling. This field gives a recommended default overflow value, which may be adjusted based on 	
+workload or tool preference. 	
+	
+----MSRIndex----	
+Additional MSRs may be required for programming certain events. This field gives the address of such MSRS. 	
+Potential values are: 	
+0x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Perforamnce Monitoring Facility 	
+0x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events	
+	
+----MSRValue----	
+When an MSRIndex is used (indicated by the MSRIndex column), this field will contain the value that needs to be loaded into the	
+register whose address is given in MSRIndex column. For example, in the case of the load latency events, MSRValue defines the	
+latency threshold value to write into the MSR defined in MSRIndex (0x3F6).	
+	
+----TakenAlone----	
+This field is set for an event which can only be sampled or counted by itself, meaning that when this event is being collected,	
+the remaining programmable counters are not available to count any other events.	
+	
+----CounterMask----	
+This field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR.
+	
+----Invert----	
+This field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR.
+		
+----AnyThread----	
+This field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR. 
+	
+----EdgeDetect----	
+This field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR.
+ 	
+----PEBS----	
+A '0' in this field means that the event cannot be programmed as a PEBS event. A '1' in this field means that the event is a 
+precise event and can be programmed in one of two ways – as a regular event or as a PEBS event. And a '2' in this field means 
+that the event can only be programmed as a PEBS event. 	
+	
+----PRECISE_STORE----	
+A '1' in this field means the event uses the Precise Store feature and Bit 3 and bit 63 in IA32_PEBS_ENABLE MSR must be set 
+to enable IA32_PMC3 as a PEBS counter and enable the precise store facility respectively. Processors based on SandyBridge and 
+IvyBridge micro-architecture offer a precise store capability that provides a means to profile store memory references in 
+the system.	
+	
+----DATA_LA---- 	
+A '1' in this field means that when the event is configured as a PEBS event, the Data Linear Address facility is supported. 
+The Data Linear Address facility is a new feature added to Haswell as a replacement or extension of the precise store facility 
+in SNB.	
+
+----L1_HIT_INDICATION----	
+A '1' in this field means that when the event is configured as a PEBS event, the DCU hit field of the PEBS record is set to 1 
+when the store hits in the L1 cache and 0 when it misses.	
+	
+----Errata----	
+This field lists the known bugs that apply to the events. For the latest, up to date errata refer to	
+	
+Haswell:	
+http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf	
+	
+IvyBridge:	
+https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf	
+	
+SandyBridge:	
+https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-family-mobile-specification-update.pdf	
+
+----offcore----
+This field is specific to the json format. There is only 1 file for core and offcore events in this format. This field is set to 1 for offcore events
+and 0 for core events. 
+	
+---------------------	
+For additional information:	
+---------------------	
+Intel Platform Monitoring Homepage	
+http://software.intel.com/en-us/platform-monitoring/	
+  	
+http://software.intel.com/en-us/articles/performance-monitoring-on-intel-xeon-processor-e5-family	
+ 	
+http://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel
+
+http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf	
+	
+---------------------	
+For questions:	
+---------------------
+email perfmon-discuss@lists.01.org	
+
+---------------------
+Notices:
+---------------------
+INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, 
+TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH 
+PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF 
+INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY 
+PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 
+
+A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in 
+personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY 
+AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST 
+ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT 
+LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR 
+WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. 
+
+Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or 
+characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have 
+no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to 
+change without notice. Do not finalize a design with this information. 
+
+The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from 
+published specifications. Current characterized errata are available on request. 
+
+Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 
+
+Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 
+1-800-548-4725, or go to: http://www.intel.com/design/literature.htm
+
+Copyright © 2014 Intel Corporation. All rights reserved.
\ No newline at end of file