update to Rust 2018 edition

* specify 2018 edition in the manifest
* changes to fix build with 2018 edition

15 files changed, 31 insertions, 28 deletions

diff --git a/Cargo.toml b/Cargo.toml
index 0dcdfbf..047a1e8 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -19,6 +19,7 @@ readme = "README.md"
 keywords = ["ia32", "os", "amd64", "x86", "x86-64"]
 license = "MIT"
 build = "build.rs"
+edition = '2018'
 
 [features]
 #default = ["performance-counter"]
diff --git a/src/bits16/segmentation.rs b/src/bits16/segmentation.rs
index 7626a15..b9ddc56 100644
--- a/src/bits16/segmentation.rs
+++ b/src/bits16/segmentation.rs
@@ -1,4 +1,4 @@
-use segmentation::{
+use crate::segmentation::{
     DescriptorBuilder, DescriptorType, GateDescriptorBuilder, SegmentSelector,
     SystemDescriptorTypes32,
 };
diff --git a/src/bits32/eflags.rs b/src/bits32/eflags.rs
index ca75130..b2c58d8 100644
--- a/src/bits32/eflags.rs
+++ b/src/bits32/eflags.rs
@@ -1,6 +1,8 @@
 //! Processor state stored in the EFLAGS register.
 
-use Ring;
+use bitflags::*;
+
+use crate::Ring;
 
 /// The EFLAGS register.
 bitflags! {
diff --git a/src/bits32/segmentation.rs b/src/bits32/segmentation.rs
index d46070e..b046035 100644
--- a/src/bits32/segmentation.rs
+++ b/src/bits32/segmentation.rs
@@ -1,5 +1,5 @@
 #[allow(unused_imports)]
-use segmentation::SegmentSelector;
+use crate::segmentation::SegmentSelector;
 
 /// Reload code segment register.
 /// Note this is special since we can not directly move
diff --git a/src/bits64/paging.rs b/src/bits64/paging.rs
index 90a8f9c..024f7d5 100644
--- a/src/bits64/paging.rs
+++ b/src/bits64/paging.rs
@@ -1,4 +1,7 @@
 //! Description of the data-structures for IA-32e paging mode.
+
+use bitflags::*;
+
 use core::convert::{From, Into};
 use core::fmt;
 use core::ops;
diff --git a/src/bits64/rflags.rs b/src/bits64/rflags.rs
index 0fac008..fe1d633 100644
--- a/src/bits64/rflags.rs
+++ b/src/bits64/rflags.rs
@@ -4,7 +4,9 @@
 //! The upper 32 bits of RFLAGS register is reserved.
 //! The lower 32 bits of RFLAGS is the same as EFLAGS.
 
-use Ring;
+use bitflags::*;
+
+use crate::Ring;
 
 /// The RFLAGS register.
 /// This is duplicated code from bits32 eflags.rs.
diff --git a/src/bits64/segmentation.rs b/src/bits64/segmentation.rs
index 02a0788..978025f 100644
--- a/src/bits64/segmentation.rs
+++ b/src/bits64/segmentation.rs
@@ -1,6 +1,6 @@
 #[allow(unused_imports)]
-use segmentation::SegmentSelector;
-use segmentation::{
+use crate::segmentation::SegmentSelector;
+use crate::segmentation::{
     BuildDescriptor, Descriptor, DescriptorBuilder, DescriptorType, GateDescriptorBuilder,
     LdtDescriptorBuilder, SystemDescriptorTypes64,
 };
diff --git a/src/controlregs.rs b/src/controlregs.rs
index 1445eab..02855bb 100644
--- a/src/controlregs.rs
+++ b/src/controlregs.rs
@@ -1,7 +1,9 @@
 //! Functions to read and write control registers.
 //! See Intel Vol. 3a Section 2.5, especially Figure 2-7.
 
-use arch::{_xgetbv, _xsetbv};
+use bitflags::*;
+
+use crate::arch::{_xgetbv, _xsetbv};
 
 bitflags! {
     pub struct Cr0: usize {
diff --git a/src/irq.rs b/src/irq.rs
index 727fd7d..12534f1 100644
--- a/src/irq.rs
+++ b/src/irq.rs
@@ -1,6 +1,8 @@
 //! Shared interrupt description and set-up code.
 //! See the `bits*::irq` modules for arch-specific portions.
 
+use bitflags::*;
+
 use core::fmt;
 
 /// x86 Exception description (see also Intel Vol. 3a Chapter 6).
diff --git a/src/lib.rs b/src/lib.rs
index 234de11..97a6922 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -4,21 +4,10 @@
 #![no_std]
 #![cfg_attr(test, allow(unused_features))]
 
-#[macro_use]
-extern crate bitflags;
-extern crate raw_cpuid;
-#[cfg(feature = "performance-counter")]
-#[macro_use]
-extern crate phf;
-
-#[cfg(test)]
-#[macro_use]
-extern crate std;
-
 #[cfg(target_arch = "x86")]
-use core::arch::x86 as arch;
+pub(crate) use core::arch::x86 as arch;
 #[cfg(target_arch = "x86_64")]
-use core::arch::x86_64 as arch;
+pub(crate) use core::arch::x86_64 as arch;
 
 macro_rules! bit {
     ($x:expr) => {
@@ -48,7 +37,7 @@ pub mod current {
     #[cfg(target_arch = "x86")]
     pub use bits32::*;
     #[cfg(target_arch = "x86_64")]
-    pub use bits64::*;
+    pub use crate::bits64::*;
 }
 
 pub mod cpuid {
diff --git a/src/perfcnt/intel/mod.rs b/src/perfcnt/intel/mod.rs
index b1d1f3b..22dbd67 100644
--- a/src/perfcnt/intel/mod.rs
+++ b/src/perfcnt/intel/mod.rs
@@ -7,7 +7,7 @@ pub use self::description::{Counter, EventDescription, MSRIndex, PebsType, Tuple
 
 use core::fmt::{Error, Result, Write};
 use core::str;
-use cpuid;
+use crate::cpuid;
 use phf;
 
 const MODEL_LEN: usize = 30;
diff --git a/src/segmentation.rs b/src/segmentation.rs
index 5342239..51553fd 100644
--- a/src/segmentation.rs
+++ b/src/segmentation.rs
@@ -1,6 +1,8 @@
+use bitflags::*;
+
 use core::fmt;
 
-use Ring;
+use crate::Ring;
 
 /// Specifies which element to load into a segment from
 /// descriptor tables (i.e., is a index to LDT or GDT table
@@ -566,8 +568,8 @@ pub fn cs() -> SegmentSelector {
 
 #[cfg(test)]
 mod test {
-    use segmentation::*;
-    use Ring;
+    use super::*;
+    use crate::Ring;
 
     #[test]
     fn test_x86_64_default_gdt() {
diff --git a/src/task.rs b/src/task.rs
index 20890c9..a7637f2 100644
--- a/src/task.rs
+++ b/src/task.rs
@@ -1,7 +1,7 @@
 //! Helpers to program the task state segment.
 //! See Intel 3a, Chapter 7
 
-pub use segmentation;
+pub use crate::segmentation;
 
 /// Load the task state register.
 pub unsafe fn load_tr(sel: segmentation::SegmentSelector) {
diff --git a/src/time.rs b/src/time.rs
index 7eaf55d..7620a0c 100644
--- a/src/time.rs
+++ b/src/time.rs
@@ -1,6 +1,6 @@
 //! Functions to read time stamp counters on x86.
 
-use arch::{__rdtscp, _rdtsc};
+use crate::arch::{__rdtscp, _rdtsc};
 
 /// Read the time stamp counter.
 ///
diff --git a/src/tlb.rs b/src/tlb.rs
index ec39e3e..5688ddb 100644
--- a/src/tlb.rs
+++ b/src/tlb.rs
@@ -15,6 +15,6 @@ pub unsafe fn flush(addr: usize) {
 /// This function is unsafe as it causes a general protection fault (GP) if the current privilege
 /// level is not 0.
 pub unsafe fn flush_all() {
-    use controlregs::{cr3, cr3_write};
+    use crate::controlregs::{cr3, cr3_write};
     cr3_write(cr3())
 }