diff options
author | 2018-07-14 00:14:36 -0700 | |
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committer | 2018-07-14 00:14:36 -0700 | |
commit | af820214bcfde26051b18bb3fd384819e45ffc13 (patch) | |
tree | ddc54cdf0ea05008bd9add33639b5ca2084d765a | |
parent | e8af882c479eb063ef6f505cef4e9471b43e9c44 (diff) | |
download | rust-x86-af820214bcfde26051b18bb3fd384819e45ffc13.tar.gz rust-x86-af820214bcfde26051b18bb3fd384819e45ffc13.tar.zst rust-x86-af820214bcfde26051b18bb3fd384819e45ffc13.zip |
rustfmt.
Signed-off-by: Gerd Zellweger <mail@gerdzellweger.com>
-rw-r--r-- | build.rs | 147 | ||||
-rw-r--r-- | src/bits16/segmentation.rs | 20 | ||||
-rw-r--r-- | src/bits32/eflags.rs | 10 | ||||
-rw-r--r-- | src/bits32/mod.rs | 4 | ||||
-rw-r--r-- | src/bits32/segmentation.rs | 6 | ||||
-rw-r--r-- | src/bits32/task.rs | 4 | ||||
-rw-r--r-- | src/bits64/mod.rs | 4 | ||||
-rw-r--r-- | src/bits64/paging.rs | 2 | ||||
-rw-r--r-- | src/bits64/rflags.rs | 14 | ||||
-rw-r--r-- | src/bits64/segmentation.rs | 66 | ||||
-rw-r--r-- | src/bits64/sgx.rs | 64 | ||||
-rw-r--r-- | src/bits64/syscall.rs | 96 | ||||
-rw-r--r-- | src/controlregs.rs | 1 | ||||
-rw-r--r-- | src/io.rs | 1 | ||||
-rw-r--r-- | src/msr.rs | 1 | ||||
-rw-r--r-- | src/perfcnt/intel/counters.rs | 3 | ||||
-rw-r--r-- | src/perfcnt/intel/description.rs | 56 | ||||
-rw-r--r-- | src/perfcnt/intel/mod.rs | 13 | ||||
-rw-r--r-- | src/segmentation.rs | 117 | ||||
-rw-r--r-- | src/task.rs | 2 | ||||
-rw-r--r-- | tests/kvm/bin.rs | 2 | ||||
-rw-r--r-- | tests/no_std_build.rs | 8 |
22 files changed, 401 insertions, 240 deletions
@@ -9,22 +9,24 @@ fn main() { #[cfg(feature = "performance-counter")] mod performance_counter { + extern crate csv; extern crate phf_codegen; extern crate serde_json; - extern crate csv; use std::ascii::AsciiExt; + use std::collections::HashMap; use std::env; use std::fs::File; - use std::io::{BufWriter, BufReader, Write}; - use std::path::Path; - use std::collections::HashMap; + use std::io::{BufReader, BufWriter, Write}; use std::mem; + use std::path::Path; use self::serde_json::Value; - include!(concat!(env!("CARGO_MANIFEST_DIR"), - "/src/shared/perfcnt/intel/description.rs")); + include!(concat!( + env!("CARGO_MANIFEST_DIR"), + "/src/shared/perfcnt/intel/description.rs" + )); /// HACK: We need to convert parsed strings to static because we're reusing /// the struct definition which declare strings as static in the generated code. @@ -45,7 +47,8 @@ mod performance_counter { } fn parse_hex_numbers(split_str_parts: Vec<&str>) -> Vec<u64> { - split_str_parts.iter() + split_str_parts + .iter() .map(|x| { assert!(x.starts_with("0x")); match u64::from_str_radix(&x[2..], 16) { @@ -71,7 +74,8 @@ mod performance_counter { } fn parse_counter_values(value_str: &str) -> u64 { - value_str.split(",") + value_str + .split(",") .map(|x| x.trim()) .filter(|x| x.len() > 0) .map(|x| match u64::from_str_radix(&x, 10) { @@ -127,7 +131,6 @@ mod performance_counter { if data.is_array() { let entries = data.as_array().unwrap(); for entry in entries.iter() { - if !entry.is_object() { panic!("Expected JSON object."); } @@ -195,8 +198,8 @@ mod performance_counter { 2 => { assert!(split_parts[0] <= u8::max_value() as u64); assert!(split_parts[1] <= u8::max_value() as u64); - event_code = Tuple::Two(split_parts[0] as u8, - split_parts[1] as u8) + event_code = + Tuple::Two(split_parts[0] as u8, split_parts[1] as u8) } _ => panic!("More than two event codes?"), } @@ -229,7 +232,8 @@ mod performance_counter { "PEBScounters" => pebs_counters = Some(parse_counters(value_str)), "SampleAfterValue" => sample_after_value = parse_number(value_str), "MSRIndex" => { - let split_parts: Vec<u64> = value_str.split(",") + let split_parts: Vec<u64> = value_str + .split(",") .map(|x| x.trim()) .map(|x| parse_number(x)) .collect(); @@ -268,32 +272,34 @@ mod performance_counter { }; } - let ipcd = EventDescription::new(event_code, - umask, - event_name, - brief_description, - public_description, - counter, - counter_ht_off, - pebs_counters, - sample_after_value, - msr_index, - msr_value, - taken_alone, - counter_mask, - invert, - any_thread, - edge_detect, - pebs, - precise_store, - collect_pebs_record, - data_la, - l1_hit_indication, - errata, - offcore, - unit, - filter, - extsel); + let ipcd = EventDescription::new( + event_code, + umask, + event_name, + brief_description, + public_description, + counter, + counter_ht_off, + pebs_counters, + sample_after_value, + msr_index, + msr_value, + taken_alone, + counter_mask, + invert, + any_thread, + edge_detect, + pebs, + precise_store, + collect_pebs_record, + data_la, + l1_hit_indication, + errata, + offcore, + unit, + filter, + extsel, + ); //println!("{:?}", ipcd.event_name); if do_insert == true { @@ -304,11 +310,11 @@ mod performance_counter { panic!("JSON data is not an array."); } - - write!(file, - "pub const {}: phf::Map<&'static str, EventDescription<'static>> = ", - variable) - .unwrap(); + write!( + file, + "pub const {}: phf::Map<&'static str, EventDescription<'static>> = ", + variable + ).unwrap(); builder.build(file).unwrap(); write!(file, ";\n").unwrap(); } @@ -358,14 +364,20 @@ mod performance_counter { // Parse CSV for record in rdr.decode() { - let (family_model, version, file_name, event_type): (String, String, String, String) = - record.unwrap(); + let (family_model, version, file_name, event_type): ( + String, + String, + String, + String, + ) = record.unwrap(); // TODO: Parse offcore counter descriptions. if !data_files.contains_key(&file_name) { let suffix = get_file_suffix(file_name.clone()); if suffix == "core" || suffix == "uncore" { - data_files.insert(file_name.clone(), - (family_model + "-" + suffix, version, event_type)); + data_files.insert( + file_name.clone(), + (family_model + "-" + suffix, version, event_type), + ); } } } @@ -379,15 +391,18 @@ mod performance_counter { let (ref family_model, _, _): (String, String, String) = *data; let path = Path::new(file.as_str()); let (_, ref variable_upper) = make_file_name(&path); - builder.entry(family_model.as_str(), - format!("{}", variable_upper.as_str()).as_str()); + builder.entry( + family_model.as_str(), + format!("{}", variable_upper.as_str()).as_str(), + ); } - write!(&mut filewriter, - "pub static {}: phf::Map<&'static str, phf::Map<&'static str, \ - EventDescription<'static>>> = ", - "COUNTER_MAP") - .unwrap(); + write!( + &mut filewriter, + "pub static {}: phf::Map<&'static str, phf::Map<&'static str, \ + EventDescription<'static>>> = ", + "COUNTER_MAP" + ).unwrap(); builder.build(&mut filewriter).unwrap(); write!(&mut filewriter, ";\n").unwrap(); @@ -395,19 +410,23 @@ mod performance_counter { for (file, data) in &data_files { let suffix = get_file_suffix(file.clone()); if suffix == "core" || suffix == "uncore" { - let (ref family_model, ref version, ref event_type): (String, String, String) = - *data; - println!("Processing {:?} {} {} {}", - file, - family_model, - version, - event_type); + let (ref family_model, ref version, ref event_type): ( + String, + String, + String, + ) = *data; + println!( + "Processing {:?} {} {} {}", + file, family_model, version, event_type + ); let path = Path::new(file.as_str()); let (_, ref variable_upper) = make_file_name(&path); - parse_performance_counters(format!("x86data/perfmon_data{}", file).as_str(), - variable_upper, - &mut filewriter); + parse_performance_counters( + format!("x86data/perfmon_data{}", file).as_str(), + variable_upper, + &mut filewriter, + ); } } } diff --git a/src/bits16/segmentation.rs b/src/bits16/segmentation.rs index 516433d..7626a15 100644 --- a/src/bits16/segmentation.rs +++ b/src/bits16/segmentation.rs @@ -1,7 +1,9 @@ -use segmentation::{SegmentSelector, DescriptorBuilder, GateDescriptorBuilder, DescriptorType, SystemDescriptorTypes32}; +use segmentation::{ + DescriptorBuilder, DescriptorType, GateDescriptorBuilder, SegmentSelector, + SystemDescriptorTypes32, +}; impl GateDescriptorBuilder<u16> for DescriptorBuilder { - fn tss_descriptor(base: u64, limit: u64, available: bool) -> DescriptorBuilder { let typ = match available { true => DescriptorType::System32(SystemDescriptorTypes32::TSSAvailable16), @@ -12,14 +14,20 @@ impl GateDescriptorBuilder<u16> for DescriptorBuilder { } fn call_gate_descriptor(selector: SegmentSelector, offset: u16) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type(DescriptorType::System32(SystemDescriptorTypes32::CallGate16)) + DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type( + DescriptorType::System32(SystemDescriptorTypes32::CallGate16), + ) } fn interrupt_descriptor(selector: SegmentSelector, offset: u16) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type(DescriptorType::System32(SystemDescriptorTypes32::InterruptGate16)) + DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type( + DescriptorType::System32(SystemDescriptorTypes32::InterruptGate16), + ) } fn trap_gate_descriptor(selector: SegmentSelector, offset: u16) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type(DescriptorType::System32(SystemDescriptorTypes32::TrapGate16)) + DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type( + DescriptorType::System32(SystemDescriptorTypes32::TrapGate16), + ) } -}
\ No newline at end of file +} diff --git a/src/bits32/eflags.rs b/src/bits32/eflags.rs index 1b1591c..ca75130 100644 --- a/src/bits32/eflags.rs +++ b/src/bits32/eflags.rs @@ -1,6 +1,6 @@ //! Processor state stored in the EFLAGS register. -use ::Ring; +use Ring; /// The EFLAGS register. bitflags! { @@ -58,18 +58,20 @@ impl EFlags { /// Creates a new Flags with the given I/O privilege level. pub const fn from_priv(iopl: Ring) -> EFlags { - EFlags { bits: (iopl as u32) << 12 } + EFlags { + bits: (iopl as u32) << 12, + } } } -#[cfg(target_arch="x86")] +#[cfg(target_arch = "x86")] pub unsafe fn read() -> EFlags { let r: u32; asm!("pushfl; popl $0" : "=r"(r) :: "memory"); EFlags::from_bits_truncate(r) } -#[cfg(target_arch="x86")] +#[cfg(target_arch = "x86")] pub unsafe fn set(val: EFlags) { asm!("pushl $0; popfl" :: "r"(val.bits()) : "memory" "flags"); } diff --git a/src/bits32/mod.rs b/src/bits32/mod.rs index e79b1e6..917398c 100644 --- a/src/bits32/mod.rs +++ b/src/bits32/mod.rs @@ -5,5 +5,5 @@ pub mod task; #[inline(always)] pub unsafe fn stack_jmp(stack: *mut (), ip: *const ()) -> ! { asm!("mov esp, $0; jmp $1" :: "rg"(stack), "r"(ip) :: "volatile", "intel"); - loop { } -}
\ No newline at end of file + loop {} +} diff --git a/src/bits32/segmentation.rs b/src/bits32/segmentation.rs index 5114394..d46070e 100644 --- a/src/bits32/segmentation.rs +++ b/src/bits32/segmentation.rs @@ -1,15 +1,15 @@ #[allow(unused_imports)] -use segmentation::{SegmentSelector}; +use segmentation::SegmentSelector; /// Reload code segment register. /// Note this is special since we can not directly move /// to %cs. Instead we push the new segment selector /// and return value on the stack and use lretl /// to reload cs and continue at 1:. -#[cfg(target_arch="x86")] +#[cfg(target_arch = "x86")] pub unsafe fn load_cs(sel: SegmentSelector) { asm!("pushl $0; \ pushl $$1f; \ lretl; \ 1:" :: "ri" (sel.bits() as u32) : "memory"); -}
\ No newline at end of file +} diff --git a/src/bits32/task.rs b/src/bits32/task.rs index 17bdcd4..9f0e0e7 100644 --- a/src/bits32/task.rs +++ b/src/bits32/task.rs @@ -45,7 +45,7 @@ pub struct TaskStateSegment { reserved9: u16, pub ldtr: u16, reserved10: u32, - pub iobp_offset: u16 + pub iobp_offset: u16, } impl TaskStateSegment { @@ -87,7 +87,7 @@ impl TaskStateSegment { reserved9: 0, ldtr: 0, reserved10: 0, - iobp_offset: size_of::<TaskStateSegment>() as u16 + iobp_offset: size_of::<TaskStateSegment>() as u16, } } } diff --git a/src/bits64/mod.rs b/src/bits64/mod.rs index 72ea049..a4df759 100644 --- a/src/bits64/mod.rs +++ b/src/bits64/mod.rs @@ -3,9 +3,7 @@ pub mod paging; pub mod rflags; pub mod segmentation; -#[cfg(target_arch="x86-64")] +#[cfg(target_arch = "x86-64")] pub mod sgx; pub mod syscall; pub mod task; - - diff --git a/src/bits64/paging.rs b/src/bits64/paging.rs index 77c6a9f..566eb5f 100644 --- a/src/bits64/paging.rs +++ b/src/bits64/paging.rs @@ -27,7 +27,7 @@ pub type PD = [PDEntry; 512]; pub type PT = [PTEntry; 512]; /// Given virtual address calculate corresponding entry in PML4. -#[cfg(target_arch="x86_64")] +#[cfg(target_arch = "x86_64")] #[inline] pub fn pml4_index(addr: VAddr) -> usize { (addr >> 39) & 0b111111111 diff --git a/src/bits64/rflags.rs b/src/bits64/rflags.rs index e6dae17..1d10219 100644 --- a/src/bits64/rflags.rs +++ b/src/bits64/rflags.rs @@ -1,10 +1,10 @@ //! Processor state stored in the RFLAGS register. //! -//! In 64-bit mode, EFLAGS is extended to 64 bits and called RFLAGS. -//! The upper 32 bits of RFLAGS register is reserved. +//! In 64-bit mode, EFLAGS is extended to 64 bits and called RFLAGS. +//! The upper 32 bits of RFLAGS register is reserved. //! The lower 32 bits of RFLAGS is the same as EFLAGS. -use ::Ring; +use Ring; /// The RFLAGS register. /// This is duplicated code from bits32 eflags.rs. @@ -63,18 +63,20 @@ impl RFlags { /// Creates a new Flags with the given I/O privilege level. pub const fn from_priv(iopl: Ring) -> RFlags { - RFlags { bits: (iopl as u64) << 12 } + RFlags { + bits: (iopl as u64) << 12, + } } } -#[cfg(target_arch="x86-64")] +#[cfg(target_arch = "x86-64")] pub unsafe fn read() -> RFlags { let r: u64; asm!("pushfq; popq $0" : "=r"(r) :: "memory"); RFlags::from_bits_truncate(r) } -#[cfg(target_arch="x86-64")] +#[cfg(target_arch = "x86-64")] pub unsafe fn set(val: RFlags) { asm!("pushq $0; popfq" :: "r"(val.bits()) : "memory" "flags"); } diff --git a/src/bits64/segmentation.rs b/src/bits64/segmentation.rs index bf39a82..11b49e7 100644 --- a/src/bits64/segmentation.rs +++ b/src/bits64/segmentation.rs @@ -1,6 +1,9 @@ #[allow(unused_imports)] -use segmentation::{SegmentSelector}; -use segmentation::{DescriptorBuilder, BuildDescriptor, Descriptor, DescriptorType, GateDescriptorBuilder, LdtDescriptorBuilder, SystemDescriptorTypes64}; +use segmentation::SegmentSelector; +use segmentation::{ + BuildDescriptor, Descriptor, DescriptorBuilder, DescriptorType, GateDescriptorBuilder, + LdtDescriptorBuilder, SystemDescriptorTypes64, +}; /// Entry for IDT, GDT or LDT. /// @@ -11,17 +14,24 @@ use segmentation::{DescriptorBuilder, BuildDescriptor, Descriptor, DescriptorTyp pub struct Descriptor64 { desc32: Descriptor, lower: u32, - upper: u32 + upper: u32, } impl Descriptor64 { - - pub const NULL: Descriptor64 = Descriptor64 { desc32: Descriptor::NULL, lower: 0, upper: 0 }; + pub const NULL: Descriptor64 = Descriptor64 { + desc32: Descriptor::NULL, + lower: 0, + upper: 0, + }; pub(crate) fn apply_builder_settings(&mut self, builder: &DescriptorBuilder) { self.desc32.apply_builder_settings(builder); - builder.base_limit.map(|(base, limit)| self.set_base_limit(base, limit)); - builder.selector_offset.map(|(selector, offset)| self.set_selector_offset(selector, offset)); + builder + .base_limit + .map(|(base, limit)| self.set_base_limit(base, limit)); + builder + .selector_offset + .map(|(selector, offset)| self.set_selector_offset(selector, offset)); } /// Create a new segment, TSS or LDT descriptor @@ -31,7 +41,7 @@ impl Descriptor64 { self.lower = (base >> 32) as u32; } - /// Creates a new descriptor with selector and offset (for IDT Gate descriptors, + /// Creates a new descriptor with selector and offset (for IDT Gate descriptors, /// e.g. Trap, Interrupts and Task gates) pub fn set_selector_offset(&mut self, selector: SegmentSelector, offset: u64) { self.desc32.set_selector_offset(selector, offset as u32); @@ -39,17 +49,15 @@ impl Descriptor64 { } /// Sets the interrupt stack table index. - /// The 3-bit IST index field that provides an offset into the IST section of the TSS. + /// The 3-bit IST index field that provides an offset into the IST section of the TSS. /// Using the IST mechanism, the processor loads the value pointed by an IST pointer into the RSP. pub fn set_ist(&mut self, index: u8) { assert!(index <= 0b111); self.desc32.upper |= index as u32; } - } impl GateDescriptorBuilder<u64> for DescriptorBuilder { - fn tss_descriptor(base: u64, limit: u64, available: bool) -> DescriptorBuilder { let typ = match available { true => DescriptorType::System64(SystemDescriptorTypes64::TssAvailable), @@ -60,21 +68,26 @@ impl GateDescriptorBuilder<u64> for DescriptorBuilder { } fn call_gate_descriptor(selector: SegmentSelector, offset: u64) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset).set_type(DescriptorType::System64(SystemDescriptorTypes64::CallGate)) + DescriptorBuilder::with_selector_offset(selector, offset) + .set_type(DescriptorType::System64(SystemDescriptorTypes64::CallGate)) } fn interrupt_descriptor(selector: SegmentSelector, offset: u64) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset).set_type(DescriptorType::System64(SystemDescriptorTypes64::InterruptGate)) + DescriptorBuilder::with_selector_offset(selector, offset).set_type( + DescriptorType::System64(SystemDescriptorTypes64::InterruptGate), + ) } fn trap_gate_descriptor(selector: SegmentSelector, offset: u64) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset).set_type(DescriptorType::System64(SystemDescriptorTypes64::TrapGate)) + DescriptorBuilder::with_selector_offset(selector, offset) + .set_type(DescriptorType::System64(SystemDescriptorTypes64::TrapGate)) } } impl LdtDescriptorBuilder<u64> for DescriptorBuilder { fn ldt_descriptor(base: u64, limit: u64) -> DescriptorBuilder { - DescriptorBuilder::with_base_limit(base, limit).set_type(DescriptorType::System64(SystemDescriptorTypes64::LDT)) + DescriptorBuilder::with_base_limit(base, limit) + .set_type(DescriptorType::System64(SystemDescriptorTypes64::LDT)) } } @@ -86,14 +99,23 @@ impl BuildDescriptor<Descriptor64> for DescriptorBuilder { let typ = match self.typ { Some(DescriptorType::System64(typ)) => { assert!(!self.l); - if typ == SystemDescriptorTypes64::LDT || typ == SystemDescriptorTypes64::TssAvailable || typ == SystemDescriptorTypes64::TssBusy { + if typ == SystemDescriptorTypes64::LDT + || typ == SystemDescriptorTypes64::TssAvailable + || typ == SystemDescriptorTypes64::TssBusy + { assert!(!self.db); } typ as u8 - }, - Some(DescriptorType::System32(_typ)) => panic!("Can't build a 64-bit version of this type."), - Some(DescriptorType::Data(_typ)) => panic!("Can't build a 64-bit version of this type."), - Some(DescriptorType::Code(_typ)) => panic!("Can't build a 64-bit version of this type."), + } + Some(DescriptorType::System32(_typ)) => { + panic!("Can't build a 64-bit version of this type.") + } + Some(DescriptorType::Data(_typ)) => { + panic!("Can't build a 64-bit version of this type.") + } + Some(DescriptorType::Code(_typ)) => { + panic!("Can't build a 64-bit version of this type.") + } None => unreachable!("Type not set, this is a library bug in x86."), }; @@ -107,11 +129,11 @@ impl BuildDescriptor<Descriptor64> for DescriptorBuilder { /// to %cs. Instead we push the new segment selector /// and return value on the stack and use lretq /// to reload cs and continue at 1:. -#[cfg(target_arch="x86_64")] +#[cfg(target_arch = "x86_64")] pub unsafe fn load_cs(sel: SegmentSelector) { asm!("pushq $0; \ leaq 1f(%rip), %rax; \ pushq %rax; \ lretq; \ 1:" :: "ri" (sel.bits() as usize) : "rax" "memory"); -}
\ No newline at end of file +} diff --git a/src/bits64/sgx.rs b/src/bits64/sgx.rs index c705e47..6c423cc 100644 --- a/src/bits64/sgx.rs +++ b/src/bits64/sgx.rs @@ -5,14 +5,17 @@ /// # Safety /// * Function needs to be executed in ring 0. macro_rules! encls { - ($rax:expr, $rbx:expr) - => ( $crate::bits64::sgx::encls2($rax as u64, $rbx as u64) ); + ($rax:expr, $rbx:expr) => { + $crate::bits64::sgx::encls2($rax as u64, $rbx as u64) + }; - ($rax:expr, $rbx:expr, $rcx:expr) - => ( $crate::bits64::sgx::encls3($rax as u64, $rbx as u64, $rcx as u64) ); + ($rax:expr, $rbx:expr, $rcx:expr) => { + $crate::bits64::sgx::encls3($rax as u64, $rbx as u64, $rcx as u64) + }; - ($rax:expr, $rbx:expr, $rcx:expr, $rdx:expr) - => ( $crate::bits64::sgx::encls4($rax as u64, $rbx as u64, $rcx as u64, $rdx as u64) ); + ($rax:expr, $rbx:expr, $rcx:expr, $rdx:expr) => { + $crate::bits64::sgx::encls4($rax as u64, $rbx as u64, $rcx as u64, $rdx as u64) + }; } /// encls with two arguments -- consider calling the encls! macro instead! @@ -58,10 +61,9 @@ enum EnclsCommand { EPA = 0x0A, EREMOVE = 0x03, ETRACK = 0x0C, - EWB = 0x0B + EWB = 0x0B, } - /// Add a Page to an Uninitialized Enclave. /// /// # Arguments @@ -148,7 +150,12 @@ pub unsafe fn encls_einit(sigstruct: u64, secs: u64, einittoken: u64) -> u32 { /// * Address of the version-array slot /// pub unsafe fn encls_eldb(pageinfo: u64, epc_page: u64, verion_array_slot: u64) -> u32 { - encls!(EnclsCommand::ELDB as u64, pageinfo, epc_page, verion_array_slot).0 + encls!( + EnclsCommand::ELDB as u64, + pageinfo, + epc_page, + verion_array_slot + ).0 } /// Loads, verifies an EPC page and marks the page as unblocked. @@ -159,7 +166,12 @@ pub unsafe fn encls_eldb(pageinfo: u64, epc_page: u64, verion_array_slot: u64) - /// * Address of the version-array slot /// pub unsafe fn encls_eldu(pageinfo: u64, epc_page: u64, verion_array_slot: u64) -> u32 { - encls!(EnclsCommand::ELDU as u64, pageinfo, epc_page, verion_array_slot).0 + encls!( + EnclsCommand::ELDU as u64, + pageinfo, + epc_page, + verion_array_slot + ).0 } /// Restrict the Permissions of an EPC Page. @@ -225,11 +237,13 @@ pub unsafe fn encls_ewb(pageinfo: u64, epc_page: u64, va_slot: u64) -> u32 { /// # Safety /// * Function needs to be executed in ring 3. macro_rules! enclu { - ($rax:expr, $rbx:expr, $rcx:expr) - => ( $crate::bits64::sgx::enclu3($rax as u64, $rbx as u64, $rcx as u64) ); + ($rax:expr, $rbx:expr, $rcx:expr) => { + $crate::bits64::sgx::enclu3($rax as u64, $rbx as u64, $rcx as u64) + }; - ($rax:expr, $rbx:expr, $rcx:expr, $rdx:expr) - => ( $crate::bits64::sgx::enclu4($rax as u64, $rbx as u64, $rcx as u64, $rdx as u64) ); + ($rax:expr, $rbx:expr, $rcx:expr, $rdx:expr) => { + $crate::bits64::sgx::enclu4($rax as u64, $rbx as u64, $rcx as u64, $rdx as u64) + }; } /// enclu with three arguments -- consider calling the enclu! macro instead! @@ -282,8 +296,17 @@ pub unsafe fn enclu_eaccept(secinfo: u64, epc_page: u64) -> u32 { /// /// Returns an error code. /// -pub unsafe fn enclu_eacceptcopy(secinfo: u64, destination_epc_page: u64, source_epc_page: u64) -> u32 { - enclu!(EncluCommand::EACCEPTCOPY as u64, secinfo, destination_epc_page, source_epc_page).0 +pub unsafe fn enclu_eacceptcopy( + secinfo: u64, + destination_epc_page: u64, + source_epc_page: u64, +) -> u32 { + enclu!( + EncluCommand::EACCEPTCOPY as u64, + secinfo, + destination_epc_page, + source_epc_page + ).0 } /// Enters an Enclave. @@ -295,7 +318,7 @@ pub unsafe fn enclu_eacceptcopy(secinfo: u64, destination_epc_page: u64, source_ /// /// Returns content of RBX.CSSA and Address of IP following EENTER. /// -pub unsafe fn enclu_eenter(tcs: u64, aep: u64) -> (u32, u64) { +pub unsafe fn enclu_eenter(tcs: u64, aep: u64) -> (u32, u64) { enclu!(EncluCommand::EENTER as u64, tcs, aep) } @@ -337,7 +360,12 @@ pub unsafe fn enclu_emodepe(secinfo: u64, epc_page: u64) { /// * Address where the REPORT is written to in an OUTPUTDATA /// pub unsafe fn enclu_ereport(targetinfo: u64, reportdata: u64, outputdata: u64) { - enclu!(EncluCommand::EREPORT as u64, targetinfo, reportdata, outputdata); + enclu!( + EncluCommand::EREPORT as u64, + targetinfo, + reportdata, + outputdata + ); } /// Re-Enters an Enclave. diff --git a/src/bits64/syscall.rs b/src/bits64/syscall.rs index c554177..40ef87c 100644 --- a/src/bits64/syscall.rs +++ b/src/bits64/syscall.rs @@ -14,29 +14,76 @@ /// This code is inspired by the syscall.rs (https://github.com/kmcallister/syscall.rs/) project. #[macro_export] macro_rules! syscall { - ($arg0:expr) - => ( $crate::syscall::syscall0($arg0 as u64) ); + ($arg0:expr) => { + $crate::syscall::syscall0($arg0 as u64) + }; - ($arg0:expr, $arg1:expr) - => ( $crate::syscall::syscall1($arg0 as u64, $arg1 as u64) ); + ($arg0:expr, $arg1:expr) => { + $crate::syscall::syscall1($arg0 as u64, $arg1 as u64) + }; - ($arg0:expr, $arg1:expr, $arg2:expr) - => ( $crate::syscall::syscall2($arg0 as u64, $arg1 as u64, $arg2 as u64) ); + ($arg0:expr, $arg1:expr, $arg2:expr) => { + $crate::syscall::syscall2($arg0 as u64, $arg1 as u64, $arg2 as u64) + }; - ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr) - => ( $crate::syscall::syscall3($arg0 as u64, $arg1 as u64, $arg2 as u64, $arg3 as u64) ); + ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr) => { + $crate::syscall::syscall3($arg0 as u64, $arg1 as u64, $arg2 as u64, $arg3 as u64) + }; - ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr) - => ( $crate::syscall::syscall4($arg0 as u64, $arg1 as u64, $arg2 as u64, $arg3 as u64, $arg4 as u64) ); + ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr) => { + $crate::syscall::syscall4( + $arg0 as u64, + $arg1 as u64, + $arg2 as u64, + $arg3 as u64, + $arg4 as u64, + ) + }; - ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr, $arg5:expr) - => ( $crate::syscall::syscall5($arg0 as u64, $arg1 as u64, $arg2 as u64, $arg3 as u64, $arg4 as u64, $arg5 as u64) ); + ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr, $arg5:expr) => { + $crate::syscall::syscall5( + $arg0 as u64, + $arg1 as u64, + $arg2 as u64, + $arg3 as u64, + $arg4 as u64, + $arg5 as u64, + ) + }; - ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr, $arg5:expr, $arg6:expr) - => ( $crate::syscall::syscall6($arg0 as u64, $arg1 as u64, $arg2 as u64, $arg3 as u64, $arg4 as u64, $arg5 as u64, $arg6 as u64) ); + ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr, $arg5:expr, $arg6:expr) => { + $crate::syscall::syscall6( + $arg0 as u64, + $arg1 as u64, + $arg2 as u64, + $arg3 as u64, + $arg4 as u64, + $arg5 as u64, + $arg6 as u64, + ) + }; - ($arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr, $arg5:expr, $arg6:expr, $arg7:expr) - => ( $crate::syscall::syscall7($arg0 as u64, $arg1 as u64, $arg2 as u64, $arg3 as u64, $arg4 as u64, $arg5 as u64, $arg6 as u64, $arg7 as u64) ); + ( + $arg0:expr, + $arg1:expr, + $arg2:expr, + $arg3:expr, + $arg4:expr, + $arg5:expr, + $arg6:expr, + $arg7:expr + ) => { + $crate::syscall::syscall7( + $arg0 as u64, + $arg1 as u64, + $arg2 as u64, + $arg3 as u64, + $arg4 as u64, + $arg5 as u64, + $arg6 as u64, + $arg7 as u64, + ) + }; } #[inline(always)] @@ -97,14 +144,15 @@ pub unsafe fn syscall5(arg0: u64, arg1: u64, arg2: u64, arg3: u64, arg4: u64, ar #[inline(always)] #[allow(unused_mut)] -pub unsafe fn syscall6(arg0: u64, - arg1: u64, - arg2: u64, - arg3: u64, - arg4: u64, - arg5: u64, - arg6: u64) - -> u64 { +pub unsafe fn syscall6( + arg0: u64, + arg1: u64, + arg2: u64, + arg3: u64, + arg4: u64, + arg5: u64, + arg6: u64, +) -> u64 { let mut ret: u64; asm!("syscall" : "={rax}" (ret) : "{rax}" (arg0), "{rdi}" (arg1), "{rsi}" (arg2), "{rdx}" (arg3), diff --git a/src/controlregs.rs b/src/controlregs.rs index 3e611e1..70b1c99 100644 --- a/src/controlregs.rs +++ b/src/controlregs.rs @@ -56,7 +56,6 @@ bitflags! { } } - /// Read cr0 pub unsafe fn cr0() -> Cr0 { let ret: usize; @@ -36,7 +36,6 @@ pub unsafe fn inl(port: u16) -> u32 { ret } - // Write 8-bit array to port pub unsafe fn outsb(port: u16, buf: &[u8]) { asm!("rep outsb (%esi), %dx" @@ -15,7 +15,6 @@ pub unsafe fn rdmsr(msr: u32) -> u64 { ((high as u64) << 32) | (low as u64) } - // What follows is a long list of all MSR register taken from Intel's manual. // Some of the register values appear duplicated as they may be // called differently for different architectures or they just have diff --git a/src/perfcnt/intel/counters.rs b/src/perfcnt/intel/counters.rs index f99a3fb..e8dcaeb 100644 --- a/src/perfcnt/intel/counters.rs +++ b/src/perfcnt/intel/counters.rs @@ -1,8 +1,7 @@ //! Performance counter for all Intel architectures. +use super::description::{Counter, EventDescription, MSRIndex, PebsType, Tuple}; /// The content of this file is automatically generated by `build.rs` /// from the data in `x86data/perfmon_data`. - use phf; -use super::description::{EventDescription, Counter, PebsType, Tuple, MSRIndex}; include!(concat!(env!("OUT_DIR"), "/counters.rs")); diff --git a/src/perfcnt/intel/description.rs b/src/perfcnt/intel/description.rs index 5e1b66f..ec0149f 100644 --- a/src/perfcnt/intel/description.rs +++ b/src/perfcnt/intel/description.rs @@ -218,34 +218,34 @@ pub struct EventDescription<'a> { } impl<'a> EventDescription<'a> { - pub fn new(event_code: Tuple, - umask: Tuple, - event_name: &'a str, - brief_description: &'a str, - public_description: Option<&'a str>, - counter: Counter, - counter_ht_off: Option<Counter>, - pebs_counters: Option<Counter>, - sample_after_value: u64, - msr_index: MSRIndex, - msr_value: u64, - taken_alone: bool, - counter_mask: u8, - invert: bool, - any_thread: bool, - edge_detect: bool, - pebs: PebsType, - precise_store: bool, - collect_pebs_record: Option<u64>, - data_la: bool, - l1_hit_indication: bool, - errata: Option<&'a str>, - offcore: bool, - unit: Option<&'a str>, - filter: Option<&'a str>, - extsel: bool) - -> EventDescription<'a> { - + pub fn new( + event_code: Tuple, + umask: Tuple, + event_name: &'a str, + brief_description: &'a str, + public_description: Option<&'a str>, + counter: Counter, + counter_ht_off: Option<Counter>, + pebs_counters: Option<Counter>, + sample_after_value: u64, + msr_index: MSRIndex, + msr_value: u64, + taken_alone: bool, + counter_mask: u8, + invert: bool, + any_thread: bool, + edge_detect: bool, + pebs: PebsType, + precise_store: bool, + collect_pebs_record: Option<u64>, + data_la: bool, + l1_hit_indication: bool, + errata: Option<&'a str>, + offcore: bool, + unit: Option<&'a str>, + filter: Option<&'a str>, + extsel: bool, + ) -> EventDescription<'a> { EventDescription { event_code: event_code, umask: umask, diff --git a/src/perfcnt/intel/mod.rs b/src/perfcnt/intel/mod.rs index f038055..9a69092 100644 --- a/src/perfcnt/intel/mod.rs +++ b/src/perfcnt/intel/mod.rs @@ -3,12 +3,12 @@ pub mod counters; // The types need to be in a spearate file so we don't get circular // dependencies with build.rs include: mod description; -pub use self::description::{EventDescription, Counter, PebsType, Tuple, MSRIndex}; +pub use self::description::{Counter, EventDescription, MSRIndex, PebsType, Tuple}; +use core::fmt::{Error, Result, Write}; +use core::str; use phf; use shared::cpuid; -use core::fmt::{Write, Result, Error}; -use core::str; const MODEL_LEN: usize = 30; @@ -40,13 +40,14 @@ impl Write for ModelWriter { // Format must be a string literal macro_rules! get_counters { - ($format:expr) => ({ + ($format:expr) => {{ let cpuid = cpuid::CpuId::new(); cpuid.get_vendor_info().map_or(None, |vf| { cpuid.get_feature_info().map_or(None, |fi| { let vendor = vf.as_string(); - let (family, extended_model, model) = (fi.family_id(), fi.extended_model_id(), fi.model_id()); + let (family, extended_model, model) = + (fi.family_id(), fi.extended_model_id(), fi.model_id()); let mut writer: ModelWriter = Default::default(); // Should work as long as it fits in MODEL_LEN bytes: @@ -56,7 +57,7 @@ macro_rules! get_counters { counters::COUNTER_MAP.get(key) }) }) - }); + }}; } /// Return all core performance counters for the running micro-architecture. diff --git a/src/segmentation.rs b/src/segmentation.rs index f91a6ec..ee73b8d 100644 --- a/src/segmentation.rs +++ b/src/segmentation.rs @@ -174,7 +174,7 @@ pub(crate) enum DescriptorType { System64(SystemDescriptorTypes64), System32(SystemDescriptorTypes32), Data(DataSegmentType), - Code(CodeSegmentType) + Code(CodeSegmentType), } /// Trait that defines the architecture specific functions for building various system segment descriptors @@ -186,7 +186,7 @@ pub trait GateDescriptorBuilder<Size> { fn trap_gate_descriptor(selector: SegmentSelector, offset: Size) -> Self; } -/// Trait to implement for building a task-gate (this descriptor is not implemented for 64-bit systems since +/// Trait to implement for building a task-gate (this descriptor is not implemented for 64-bit systems since /// Hardware task switches are not supported in IA-32e mode.). pub trait TaskGateDescriptorBuilder { fn task_gate_descriptor(selector: SegmentSelector) -> Self; @@ -229,22 +229,43 @@ pub struct DescriptorBuilder { /// Determines the scaling of the segment limit field. When the granularity flag is clear, the segment limit is interpreted in byte units; when flag is set, the segment limit is interpreted in 4-KByte units. pub(crate) limit_granularity_4k: bool, /// 64-bit code segment (IA-32e mode only) - pub(crate) l: bool - + pub(crate) l: bool, } impl DescriptorBuilder { - /// Start building a new descriptor with a base and limit. pub(crate) fn with_base_limit(base: u64, limit: u64) -> DescriptorBuilder { - DescriptorBuilder { base_limit: Some((base, limit)), selector_offset: None, typ: None, dpl: None, present: false, avl: false, db: false, limit_granularity_4k: false, l: false } + DescriptorBuilder { + base_limit: Some((base, limit)), + selector_offset: None, + typ: None, + dpl: None, + present: false, + avl: false, + db: false, + limit_granularity_4k: false, + l: false, + } } /// Start building a new descriptor with a segment selector and offset. - pub(crate) fn with_selector_offset(selector: SegmentSelector, offset: u64) -> DescriptorBuilder { - DescriptorBuilder { base_limit: None, selector_offset: Some((selector, offset)), typ: None, dpl: None, present: false, avl: false, db: false, limit_granularity_4k: false, l: false } + pub(crate) fn with_selector_offset( + selector: SegmentSelector, + offset: u64, + ) -> DescriptorBuilder { + DescriptorBuilder { + base_limit: None, + selector_offset: Some((selector, offset)), + typ: None, + dpl: None, + present: false, + avl: false, + db: false, + limit_granularity_4k: false, + l: false, + } } - + pub(crate) fn set_type(mut self, typ: DescriptorType) -> DescriptorBuilder { self.typ = Some(typ); self @@ -281,7 +302,7 @@ impl DescriptorBuilder { } /// Set L bit if this descriptor is a 64-bit code segment. - /// In IA-32e mode, bit 21 of the second doubleword of the segment descriptor indicates whether a code segment + /// In IA-32e mode, bit 21 of the second doubleword of the segment descriptor indicates whether a code segment /// contains native 64-bit code. A value of 1 indicates instructions in this code segment are executed in 64-bit mode. pub fn l(mut self) -> DescriptorBuilder { self.l = true; @@ -290,7 +311,6 @@ impl DescriptorBuilder { } impl GateDescriptorBuilder<u32> for DescriptorBuilder { - fn tss_descriptor(base: u64, limit: u64, available: bool) -> DescriptorBuilder { let typ = match available { true => DescriptorType::System32(SystemDescriptorTypes32::TssAvailable32), @@ -301,37 +321,49 @@ impl GateDescriptorBuilder<u32> for DescriptorBuilder { } fn call_gate_descriptor(selector: SegmentSelector, offset: u32) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type(DescriptorType::System32(SystemDescriptorTypes32::CallGate32)) + DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type( + DescriptorType::System32(SystemDescriptorTypes32::CallGate32), + ) } fn interrupt_descriptor(selector: SegmentSelector, offset: u32) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type(DescriptorType::System32(SystemDescriptorTypes32::InterruptGate32)) + DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type( + DescriptorType::System32(SystemDescriptorTypes32::InterruptGate32), + ) } fn trap_gate_descriptor(selector: SegmentSelector, offset: u32) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type(DescriptorType::System32(SystemDescriptorTypes32::TrapGate32)) + DescriptorBuilder::with_selector_offset(selector, offset.into()).set_type( + DescriptorType::System32(SystemDescriptorTypes32::TrapGate32), + ) } } impl TaskGateDescriptorBuilder for DescriptorBuilder { fn task_gate_descriptor(selector: SegmentSelector) -> DescriptorBuilder { - DescriptorBuilder::with_selector_offset(selector, 0).set_type(DescriptorType::System32(SystemDescriptorTypes32::TaskGate)) + DescriptorBuilder::with_selector_offset(selector, 0) + .set_type(DescriptorType::System32(SystemDescriptorTypes32::TaskGate)) } } impl SegmentDescriptorBuilder<u32> for DescriptorBuilder { fn code_descriptor(base: u32, limit: u32, cst: CodeSegmentType) -> DescriptorBuilder { - DescriptorBuilder::with_base_limit(base.into(), limit.into()).set_type(DescriptorType::Code(cst)).db() + DescriptorBuilder::with_base_limit(base.into(), limit.into()) + .set_type(DescriptorType::Code(cst)) + .db() } fn data_descriptor(base: u32, limit: u32, dst: DataSegmentType) -> DescriptorBuilder { - DescriptorBuilder::with_base_limit(base.into(), limit.into()).set_type(DescriptorType::Data(dst)).db() + DescriptorBuilder::with_base_limit(base.into(), limit.into()) + .set_type(DescriptorType::Data(dst)) + .db() } } impl LdtDescriptorBuilder<u32> for DescriptorBuilder { fn ldt_descriptor(base: u32, limit: u32) -> DescriptorBuilder { - DescriptorBuilder::with_base_limit(base.into(), limit.into()).set_type(DescriptorType::System32(SystemDescriptorTypes32::LDT)) + DescriptorBuilder::with_base_limit(base.into(), limit.into()) + .set_type(DescriptorType::System32(SystemDescriptorTypes32::LDT)) } } @@ -341,18 +373,18 @@ impl BuildDescriptor<Descriptor> for DescriptorBuilder { desc.apply_builder_settings(self); let typ = match self.typ { - Some(DescriptorType::System64(_)) => panic!("You shall not use 64-bit types on 32-bit descriptor."), - Some(DescriptorType::System32(typ)) => { - typ as u8 - }, + Some(DescriptorType::System64(_)) => { + panic!("You shall not use 64-bit types on 32-bit descriptor.") + } + Some(DescriptorType::System32(typ)) => typ as u8, Some(DescriptorType::Data(typ)) => { desc.set_s(); typ as u8 - }, + } Some(DescriptorType::Code(typ)) => { desc.set_s(); typ as u8 - }, + } None => unreachable!("Type not set, this is a library bug in x86."), }; desc.set_type(typ); @@ -361,7 +393,6 @@ impl BuildDescriptor<Descriptor> for DescriptorBuilder { } } - /// Entry for IDT, GDT or LDT. Provides size and location of a segment. /// /// See Intel 3a, Section 3.4.5 "Segment Descriptors", and Section 3.5.2 @@ -373,13 +404,16 @@ pub struct Descriptor { } impl Descriptor { - pub const NULL: Descriptor = Descriptor { lower: 0, upper: 0 }; pub(crate) fn apply_builder_settings(&mut self, builder: &DescriptorBuilder) { builder.dpl.map(|ring| self.set_dpl(ring)); - builder.base_limit.map(|(base, limit)| self.set_base_limit(base as u32, limit as u32)); - builder.selector_offset.map(|(selector, offset)| self.set_selector_offset(selector, offset as u32)); + builder + .base_limit + .map(|(base, limit)| self.set_base_limit(base as u32, limit as u32)); + builder + .selector_offset + .map(|(selector, offset)| self.set_selector_offset(selector, offset as u32)); if builder.present { self.set_p(); @@ -416,7 +450,7 @@ impl Descriptor { self.upper |= limit_last_four_bits << 16; } - /// Creates a new descriptor with selector and offset (for IDT Gate descriptors, + /// Creates a new descriptor with selector and offset (for IDT Gate descriptors, /// e.g. Trap, Interrupts and Task gates) pub fn set_selector_offset(&mut self, selector: SegmentSelector, offset: u32) { // Clear the selector and offset @@ -432,8 +466,8 @@ impl Descriptor { } /// Set the type of the descriptor (bits 8-11). - /// Indicates the segment or gate type and specifies the kinds of access that can be made to the - /// segment and the direction of growth. The interpretation of this field depends on whether the descriptor + /// Indicates the segment or gate type and specifies the kinds of access that can be made to the + /// segment and the direction of growth. The interpretation of this field depends on whether the descriptor /// type flag specifies an application (code or data) descriptor or a system descriptor. pub fn set_type(&mut self, typ: u8) { self.upper &= !(0x0f << 8); // clear @@ -453,44 +487,43 @@ impl Descriptor { } /// Set Present bit. - /// Indicates whether the segment is present in memory (set) or not present (clear). - /// If this flag is clear, the processor generates a segment-not-present exception (#NP) when a segment selector + /// Indicates whether the segment is present in memory (set) or not present (clear). + /// If this flag is clear, the processor generates a segment-not-present exception (#NP) when a segment selector /// that points to the segment descriptor is loaded into a segment register. pub fn set_p(&mut self) { self.upper |= bit!(15); } - + /// Set AVL bit. System software can use this bit to store information. pub fn set_avl(&mut self) { self.upper |= bit!(20); } /// Set L - /// In IA-32e mode, bit 21 of the second doubleword of the segment descriptor indicates whether a - /// code segment contains native 64-bit code. A value of 1 indicates instructions in this code - /// segment are executed in 64-bit mode. A value of 0 indicates the instructions in this code segment + /// In IA-32e mode, bit 21 of the second doubleword of the segment descriptor indicates whether a + /// code segment contains native 64-bit code. A value of 1 indicates instructions in this code + /// segment are executed in 64-bit mode. A value of 0 indicates the instructions in this code segment /// are executed in compatibility mode. If L-bit is set, then D-bit must be cleared. pub fn set_l(&mut self) { self.upper |= bit!(21); } - + /// Set D/B. - /// Performs different functions depending on whether the segment descriptor is an executable code segment, + /// Performs different functions depending on whether the segment descriptor is an executable code segment, /// an expand-down data segment, or a stack segment. pub fn set_db(&mut self) { self.upper |= bit!(22); } /// Set G bit - /// Determines the scaling of the segment limit field. - /// When the granularity flag is clear, the segment limit is interpreted in byte units; + /// Determines the scaling of the segment limit field. + /// When the granularity flag is clear, the segment limit is interpreted in byte units; /// when flag is set, the segment limit is interpreted in 4-KByte units. pub fn set_g(&mut self) { self.upper |= bit!(23); } } - /// Reload stack segment register. pub unsafe fn load_ss(sel: SegmentSelector) { asm!("movw $0, %ss " :: "r" (sel.bits()) : "memory"); diff --git a/src/task.rs b/src/task.rs index b0dd2ff..20890c9 100644 --- a/src/task.rs +++ b/src/task.rs @@ -1,7 +1,7 @@ //! Helpers to program the task state segment. //! See Intel 3a, Chapter 7 -pub use ::segmentation; +pub use segmentation; /// Load the task state register. pub unsafe fn load_tr(sel: segmentation::SegmentSelector) { diff --git a/tests/kvm/bin.rs b/tests/kvm/bin.rs index dd16dfa..ef524c1 100644 --- a/tests/kvm/bin.rs +++ b/tests/kvm/bin.rs @@ -1,8 +1,8 @@ #![feature(proc_macro)] // RUSTFLAGS="-C relocation-model=dynamic-no-pic -C code-model=kernel" RUST_BACKTRACE=1 cargo test --verbose --test kvm -- --nocapture -extern crate x86; extern crate core; +extern crate x86; #[macro_use] extern crate klogger; diff --git a/tests/no_std_build.rs b/tests/no_std_build.rs index bddedc8..b99cd85 100644 --- a/tests/no_std_build.rs +++ b/tests/no_std_build.rs @@ -9,5 +9,9 @@ fn start(_argc: isize, _argv: *const *const u8) -> isize { 0 } -#[lang = "eh_personality"] extern fn eh_personality() {} -#[lang = "panic_fmt"] fn panic_fmt() -> ! { loop {} } +#[lang = "eh_personality"] +extern "C" fn eh_personality() {} +#[lang = "panic_fmt"] +fn panic_fmt() -> ! { + loop {} +} |