diff options
| author |  Gerd Zellweger <mail@gerdzellweger.com>
| 2020-04-26 15:49:14 -0700 |
|---|---|---|
| committer | Gerd Zellweger <mail@gerdzellweger.com>
| 2020-04-26 15:49:14 -0700 |
| commit | dcf97bbb55bfcd39f3b78013c44195712e1d5b76 (patch) | |
| tree | dbb15c907e5194fc129f7c9daf56df1b77e13a63 /src/apic/xapic.rs | |
| parent | 0a677f3e2cfcaaac7faaf5c702d548a0f607bb15 (diff) | |
| download | rust-x86-dcf97bbb55bfcd39f3b78013c44195712e1d5b76.tar.gz rust-x86-dcf97bbb55bfcd39f3b78013c44195712e1d5b76.tar.zst rust-x86-dcf97bbb55bfcd39f3b78013c44195712e1d5b76.zip | |
Specify timer vector through `tsc_enable`.
Diffstat (limited to 'src/apic/xapic.rs')
| -rw-r--r-- | src/apic/xapic.rs | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/apic/xapic.rs b/src/apic/xapic.rs index 3af446f..4b85580 100644 --- a/src/apic/xapic.rs +++ b/src/apic/xapic.rs @@ -270,8 +270,12 @@ impl ApicControl for XAPIC { } /// Enable TSC timer. - fn tsc_enable(&mut self) { + fn tsc_enable(&mut self, vector: u8) { let mut lvt: u32 = self.read(ApicRegister::XAPIC_LVT_TIMER); + lvt &= !0xff; + lvt |= vector as u32; + + lvt.set_bit(16, false); lvt.set_bit(17, false); lvt.set_bit(18, true); self.write(ApicRegister::XAPIC_LVT_TIMER, lvt); |