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authorGravatar Gerd Zellweger <mail@gerdzellweger.com> 2016-07-04 14:08:17 +0200
committerGravatar GitHub <noreply@github.com> 2016-07-04 14:08:17 +0200
commitc12e050a69dd1a9b04f07ab78a166c6371d35a6f (patch)
treefea35bcf5b507efdd4c1c0f5dab146360c70478a /src/bits64/task.rs
parent32257991aaa3700620f1d6c180cfec3e2d65a360 (diff)
parentbd2950de1a48d72cbb718cc9a367142e0eb97b72 (diff)
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Merge pull request #16 from QuiltOS/master
Fix #15: Combine with https://github.com/Tobba/libcpu
Diffstat (limited to 'src/bits64/task.rs')
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diff --git a/src/bits64/task.rs b/src/bits64/task.rs
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+//! Helpers to program the task state segment.
+//! See Intel 3a, Chapter 7, Section 7
+
+use shared::segmentation;
+
+pub type TaskStateDescriptorLow = segmentation::SegmentDescriptor;
+pub type TaskStateDescriptorHigh = u64;
+
+/// In 64-bit mode the TSS holds information that is not
+/// directly related to the task-switch mechanism,
+/// but is used for finding kernel level stack
+/// if interrupts arrive while in kernel mode.
+#[derive(Debug)]
+#[repr(C, packed)]
+pub struct TaskStateSegment {
+ pub reserved: u32,
+ /// The full 64-bit canonical forms of the stack pointers (RSP) for privilege levels 0-2.
+ pub rsp: [u64; 3],
+ pub reserved2: u64,
+ /// The full 64-bit canonical forms of the interrupt stack table (IST) pointers.
+ pub ist: [u64; 7],
+ pub reserved3: u64,
+ pub reserved4: u16,
+ /// The 16-bit offset to the I/O permission bit map from the 64-bit TSS base.
+ pub iomap_base: u16,
+}
+
+impl TaskStateSegment {
+ pub const fn new() -> TaskStateSegment {
+ TaskStateSegment {
+ reserved: 0,
+ rsp: [0; 3],
+ reserved2: 0,
+ ist: [0; 7],
+ reserved3: 0,
+ reserved4: 0,
+ iomap_base: 0,
+ }
+ }
+}