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author | 2021-04-24 00:43:37 -0700 | |
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committer | 2021-04-24 00:43:37 -0700 | |
commit | c4c34367652f206d49cbba8fb502b8c5df4f67a3 (patch) | |
tree | 71dde2730a162f04b82de07a3ea2b89dc7f544dc /src/fence.rs | |
parent | 523296c4ecfad57ef26aabdde1446c788dbc668e (diff) | |
download | rust-x86-c4c34367652f206d49cbba8fb502b8c5df4f67a3.tar.gz rust-x86-c4c34367652f206d49cbba8fb502b8c5df4f67a3.tar.zst rust-x86-c4c34367652f206d49cbba8fb502b8c5df4f67a3.zip |
Add fence instructions.
Diffstat (limited to 'src/fence.rs')
-rw-r--r-- | src/fence.rs | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/fence.rs b/src/fence.rs new file mode 100644 index 0000000..9268d02 --- /dev/null +++ b/src/fence.rs @@ -0,0 +1,28 @@ +//! Intel fence instructions + +/// mfence -- Memory Fence +/// +/// Performs a serializing operation on all load-from-memory and store-to-memory +/// instructions that were issued prior the MFENCE instruction. +pub fn mfence() { + unsafe { llvm_asm!("mfence" ::: "memory") }; +} + +/// sfence -- Store Fence +/// +/// Orders processor execution relative to all memory stores prior to the SFENCE +/// instruction. The processor ensures that every store prior to SFENCE is +/// globally visible before any store after SFENCE becomes globally visible. +pub fn sfence() { + unsafe { llvm_asm!("sfence" ::: "memory") }; +} + +/// lfence -- Load Fence +/// +/// Performs a serializing operation on all load-from-memory instructions that +/// were issued prior the LFENCE instruction. Specifically, LFENCE does not +/// execute until all prior instructions have completed locally, and no later +/// instruction begins execution until LFENCE completes. +pub fn lfence() { + unsafe { llvm_asm!("sfence" ::: "memory") }; +}
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