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authorGravatar Gerd Zellweger <mail@gerdzellweger.com> 2019-05-06 00:00:23 -0700
committerGravatar Gerd Zellweger <mail@gerdzellweger.com> 2019-05-06 00:00:23 -0700
commitd33a20587a1406ece7f71c2cd6e767c4ad2ae39b (patch)
tree3afa828745a5e96874c042978edba37077c37a5c /src/perfcnt/intel/description.rs
parentaf776f308e97e24f4eb3d63272596a505c3debe6 (diff)
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Implement Pointer and Debug for VAddr, PAddr.
Also formatting.
Diffstat (limited to 'src/perfcnt/intel/description.rs')
-rw-r--r--src/perfcnt/intel/description.rs5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/perfcnt/intel/description.rs b/src/perfcnt/intel/description.rs
index d47da75..4e5e8cc 100644
--- a/src/perfcnt/intel/description.rs
+++ b/src/perfcnt/intel/description.rs
@@ -234,11 +234,10 @@ pub struct EventDescription<'a> {
/// Port Mask
pub port_mask: u8,
- /// This field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs.
- /// It further qualifies the event logic unit selected in the event select
+ /// This field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs.
+ /// It further qualifies the event logic unit selected in the event select
/// field to detect a specific micro-architectural condition.
pub umask_ext: u8,
-
}
impl<'a> EventDescription<'a> {