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authorGravatar Dan Cross <cross@gajendra.net> 2021-12-22 17:54:39 +0000
committerGravatar Gerd Zellweger <mail@gerdzellweger.com> 2021-12-26 09:31:14 -0800
commit161ef95308f6faf4b47a1425054e0104a0348cbc (patch)
tree350e14fa801c39b74e905a25ea198440d39e40fc /src
parentb0dcf8dd08b0a817510d2f55e8bc25edcc4f8809 (diff)
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Add explicit `use` statements core::arch::asm.
The new asm!() syntx has been stabilized in nightly Rust, but requires either a `use` statement or explicit package qualification. This PR adds `use` statements in the modules that use the new macro. Fixes #117. Signed-off-by: Dan Cross <cross@gajendra.net>
Diffstat (limited to 'src')
-rw-r--r--src/debugregs.rs2
-rw-r--r--src/irq.rs1
-rw-r--r--src/lib.rs1
-rw-r--r--src/task.rs1
-rw-r--r--src/tlb.rs2
5 files changed, 7 insertions, 0 deletions
diff --git a/src/debugregs.rs b/src/debugregs.rs
index 7255d5b..8319630 100644
--- a/src/debugregs.rs
+++ b/src/debugregs.rs
@@ -17,6 +17,8 @@
use bit_field::BitField;
use bitflags::bitflags;
+use core::arch::asm;
+
/// An array list of all available breakpoint registers.
pub const BREAKPOINT_REGS: [Breakpoint; 4] = [
Breakpoint::Dr0,
diff --git a/src/irq.rs b/src/irq.rs
index c35b056..bd67997 100644
--- a/src/irq.rs
+++ b/src/irq.rs
@@ -3,6 +3,7 @@
use bitflags::*;
+use core::arch::asm;
use core::fmt;
/// x86 Exception description (see also Intel Vol. 3a Chapter 6).
diff --git a/src/lib.rs b/src/lib.rs
index a98bf1e..94775a9 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -6,6 +6,7 @@
#![cfg_attr(all(test, feature = "vmtest"), feature(custom_test_frameworks))]
#![cfg_attr(all(test, feature = "vmtest"), test_runner(x86test::runner::runner))]
+use core::arch::asm;
#[cfg(target_arch = "x86")]
pub(crate) use core::arch::x86 as arch;
#[cfg(target_arch = "x86_64")]
diff --git a/src/task.rs b/src/task.rs
index d819e2d..d572c8d 100644
--- a/src/task.rs
+++ b/src/task.rs
@@ -1,6 +1,7 @@
//! Helpers to program the task state segment.
//! See Intel 3a, Chapter 7
+use core::arch::asm;
pub use crate::segmentation;
/// Returns the current value of the task register.
diff --git a/src/tlb.rs b/src/tlb.rs
index 1c90120..abc8a35 100644
--- a/src/tlb.rs
+++ b/src/tlb.rs
@@ -1,5 +1,7 @@
//! Functions to flush the translation lookaside buffer (TLB).
+use core::arch::asm;
+
/// Invalidate the given address in the TLB using the `invlpg` instruction.
///
/// # Safety