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authorGravatar Colin Finck <mail@colinfinck.de> 2017-11-14 09:19:22 +0100
committerGravatar Colin Finck <mail@colinfinck.de> 2017-11-14 09:19:22 +0100
commit4f1d9fce9ffae8d613e651322532faa989bb3f8e (patch)
tree6e21fca545635e940291f8aec7f09d8c6c3b0677 /src
parenta8371f959c2192c49a448e8592f921c49de2fb6c (diff)
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Make the Xcr0 functions compatible with 32-bit Intel architecture.
Thanks to @stlankes for noticing!
Diffstat (limited to 'src')
-rw-r--r--src/shared/control_regs.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/shared/control_regs.rs b/src/shared/control_regs.rs
index 23fce28..1a1f6a3 100644
--- a/src/shared/control_regs.rs
+++ b/src/shared/control_regs.rs
@@ -43,7 +43,7 @@ bitflags! {
}
bitflags! {
- pub flags Xcr0: usize {
+ pub flags Xcr0: u64 {
const XCR0_PKRU_STATE = 1 << 9,
const XCR0_HI16_ZMM_STATE = 1 << 7,
const XCR0_ZMM_HI256_STATE = 1 << 6,
@@ -106,7 +106,7 @@ pub unsafe fn xcr0() -> Xcr0 {
let high: u32;
let low: u32;
asm!("xgetbv" : "={eax}"(low), "={edx}"(high) : "{ecx}"(0));
- Xcr0::from_bits_truncate((high as usize) << 32 | low as usize)
+ Xcr0::from_bits_truncate((high as u64) << 32 | low as u64)
}
/// Write to Extended Control Register XCR0.