Combine Interface: Control Registers; libpcu: Additional bitflags

5 files changed, 88 insertions, 144 deletions

diff --git a/src/bits64/controlregs.rs b/src/bits64/controlregs.rs
deleted file mode 100644
index c243caf..0000000
--- a/src/bits64/controlregs.rs
+++ /dev/null
@@ -1,43 +0,0 @@
-//! Functions to read and write control registers.
-
-pub unsafe fn cr0() -> u64 {
-    let ret: u64;
-    asm!("mov %cr0, $0" : "=r" (ret));
-    ret
-}
-
-/// Write cr0.
-pub unsafe fn cr0_write(val: u64) {
-    asm!("mov $0, %cr0" :: "r" (val) : "memory");
-}
-
-/// Contains page-fault linear address.
-pub unsafe fn cr2() -> u64 {
-    let ret: u64;
-    asm!("mov %cr2, $0" : "=r" (ret));
-    ret
-}
-
-/// Contains page-table root pointer.
-pub unsafe fn cr3() -> u64 {
-    let ret: u64;
-    asm!("mov %cr3, $0" : "=r" (ret));
-    ret
-}
-
-/// Switch page-table PML4 pointer.
-pub unsafe fn cr3_write(val: u64) {
-    asm!("mov $0, %cr3" :: "r" (val) : "memory");
-}
-
-/// Contains various flags to control operations in protected mode.
-pub unsafe fn cr4() -> u64 {
-    let ret: u64;
-    asm!("mov %cr4, $0" : "=r" (ret));
-    ret
-}
-
-/// Write cr4.
-pub unsafe fn cr4_write(val: u64) {
-    asm!("mov $0, %cr4" :: "r" (val) : "memory");
-}
diff --git a/src/bits64/mod.rs b/src/bits64/mod.rs
index 315af02..3ab65e8 100644
--- a/src/bits64/mod.rs
+++ b/src/bits64/mod.rs
@@ -31,7 +31,6 @@ macro_rules! check_bit_fn {
 }
 
 pub mod io;
-pub mod controlregs;
 pub mod msr;
 pub mod time;
 pub mod irq;
diff --git a/src/bits64/tlb.rs b/src/bits64/tlb.rs
index 6b27e8c..f99604f 100644
--- a/src/bits64/tlb.rs
+++ b/src/bits64/tlb.rs
@@ -15,6 +15,6 @@ pub unsafe fn flush(addr: usize) {
 /// This function is unsafe as it causes a general protection fault (GP) if the current privilege
 /// level is not 0.
 pub unsafe fn flush_all() {
-    use super::controlregs::{cr3, cr3_write};
+    use shared::control_regs::{cr3, cr3_write};
     cr3_write(cr3())
 }
diff --git a/src/shared/control_regs.rs b/src/shared/control_regs.rs
new file mode 100644
index 0000000..4893445
--- /dev/null
+++ b/src/shared/control_regs.rs
@@ -0,0 +1,84 @@
+//! Functions to read and write control registers.
+//! See Intel Vol. 3a Section 2.5, especially Figure 2.6.
+
+bitflags! {
+    pub flags Cr0: usize {
+        const EnablePaging = 1 << 31,
+        const CacheDisable = 1 << 30,
+        const NotWriteThrough = 1 << 29,
+        const AlignmentMask = 1 << 18,
+        const WriteProtect = 1 << 16,
+        const NumericError = 1 << 5,
+        const ExtensionType = 1 << 4,
+        const TaskSwitched = 1 << 3,
+        const EmulateCoprocessor = 1 << 2,
+        const MonitorCoprocessor = 1 << 1,
+        const ProtectedMode = 1 << 0,
+    }
+}
+
+bitflags! {
+    pub flags Cr4: usize {
+        const EnableSmap = 1 << 21,
+        const EnableSmep = 1 << 20,
+        const EnableOsXSave = 1 << 18,
+        const EnablePcid = 1 << 17,
+        const EnableSmx = 1 << 14,
+        const EnableVmx = 1 << 13,
+        const UnmaskedSse = 1 << 10,
+        const EnableSse = 1 << 9,
+        const EnablePpmc = 1 << 8,
+        const EnableGlobalPages = 1 << 7,
+        const EnableMachineCheck = 1 << 6,
+        const EnablePae = 1 << 5,
+        const EnablePse = 1 << 4,
+        const DebuggingExtensions = 1 << 3,
+        const TimeStampDisable = 1 << 2,
+        const VirtualInterrupts = 1 << 1,
+        const EnableVme = 1 << 0,
+    }
+}
+
+
+/// Read cr0
+pub unsafe fn cr0() -> Cr0 {
+    let ret: usize;
+    asm!("mov %cr0, $0" : "=r" (ret));
+    Cr0::from_bits_truncate(ret)
+}
+
+/// Write cr0.
+pub unsafe fn cr0_write(val: Cr0) {
+    asm!("mov $0, %cr0" :: "r" (val.bits) : "memory");
+}
+
+/// Contains page-fault linear address.
+pub unsafe fn cr2() -> usize {
+    let ret: usize;
+    asm!("mov %cr2, $0" : "=r" (ret));
+    ret
+}
+
+/// Contains page-table root pointer.
+pub unsafe fn cr3() -> usize {
+    let ret: usize;
+    asm!("mov %cr3, $0" : "=r" (ret));
+    ret
+}
+
+/// Switch page-table PML4 pointer.
+pub unsafe fn cr3_write(val: usize) {
+    asm!("mov $0, %cr3" :: "r" (val) : "memory");
+}
+
+/// Contains various flags to control operations in protected mode.
+pub unsafe fn cr4() -> Cr4 {
+    let ret: usize;
+    asm!("mov %cr4, $0" : "=r" (ret));
+    Cr4::from_bits_truncate(ret)
+}
+
+/// Write cr4.
+pub unsafe fn cr4_write(val: Cr4) {
+    asm!("mov $0, %cr4" :: "r" (val.bits) : "memory");
+}
diff --git a/src/shared/mod.rs b/src/shared/mod.rs
index 04bc5e0..e9c8084 100644
--- a/src/shared/mod.rs
+++ b/src/shared/mod.rs
@@ -1,14 +1,7 @@
-//! Data structures and functions used by both protected mode and IA-32e.
-
-// In a few rare-cases this module includes mode-specific
-// *implementations*. This is usually because we cannot trust the LLVM inline
-// assembler to infer instruction variants from argument size, and thus we add
-// size-suffixes wherever possible.
-//
-// That said, *interfaces* must always be mode-portable
-
 #![allow(non_upper_case_globals)]
 
+pub mod control_regs;
+
 bitflags! {
     pub flags Flags: usize {
         const CarryFlag = 1 << 0,
@@ -32,44 +25,6 @@ bitflags! {
     }
 }
 
-bitflags! {
-    pub flags Cr0: usize {
-        const ProtectedMode = 1 << 0,
-        const MonitorCoprocessor = 1 << 1,
-        const EmulateCoprocessor = 1 << 2,
-        const TaskSwitched = 1 << 3,
-        const ExtensionType = 1 << 4,
-        const NumericError = 1 << 5,
-        const WriteProtect = 1 << 16,
-        const AlignmentMask = 1 << 18,
-        const NotWriteThrough = 1 << 29,
-        const CacheDisable = 1 << 30,
-        const EnablePaging = 1 << 31
-    }
-}
-
-bitflags! {
-    pub flags Cr4: usize {
-        const EnableVme = 1 << 0,
-        const VirtualInterrupts = 1 << 1,
-        const TimeStampDisable = 1 << 2,
-        const DebuggingExtensions = 1 << 3,
-        const EnablePse = 1 << 4,
-        const EnablePae = 1 << 5,
-        const EnableMachineCheck = 1 << 6,
-        const EnableGlobalPages = 1 << 7,
-        const EnablePpmc = 1 << 8,
-        const EnableSse = 1 << 9,
-        const UnmaskedSse = 1 << 10,
-        const EnableVmx = 1 << 13,
-        const EnableSmx = 1 << 14,
-        const EnablePcid = 1 << 17,
-        const EnableOsXSave = 1 << 18,
-        const EnableSmep = 1 << 20,
-        const EnableSmap = 1 << 21
-    }
-}
-
 bitflags!(
     pub flags Features: u64 {
         const Fpu = 1 << 0,
@@ -184,7 +139,7 @@ impl Exception {
             19 => Exception::Simd,
             20 => Exception::Virtualization,
             30 => Exception::Security,
-            
+
             _ => return None
         })
     }
@@ -285,57 +240,6 @@ pub unsafe fn set_cs(selector: SegmentSelector) {
 }
 
 #[inline(always)]
-pub fn get_cr0() -> Cr0 {
-    unsafe {
-        let r: usize;
-        asm!("mov $0, cr0" : "=r"(r) ::: "intel");
-        Cr0::from_bits_truncate(r)
-    }
-}
-
-#[inline(always)]
-pub fn get_cr2() -> usize {
-    unsafe {
-        let r: usize;
-        asm!("mov $0, cr2" : "=r"(r) ::: "intel");
-        r
-    }
-}
-
-#[inline(always)]
-pub fn get_cr3() -> usize {
-    unsafe {
-        let r: usize;
-        asm!("mov $0, cr3" : "=r"(r) ::: "intel");
-        r
-    }
-}
-
-#[inline(always)]
-pub fn get_cr4() -> Cr4 {
-    unsafe {
-        let r: usize;
-        asm!("mov $0, cr4" : "=r"(r) ::: "intel");
-        Cr4::from_bits_truncate(r)
-    }
-}
-
-#[inline(always)]
-pub unsafe fn set_cr0(flags: Cr0) {
-    asm!("mov cr0, $0" :: "r"(flags.bits()) :: "volatile", "intel");
-}
-
-#[inline(always)]
-pub unsafe fn set_cr3(val: usize) {
-    asm!("mov cr3, $0" :: "r"(val) :: "volatile", "intel");
-}
-
-#[inline(always)]
-pub unsafe fn set_cr4(flags: Cr4) {
-    asm!("mov cr4, $0" :: "r"(flags.bits()) :: "volatile", "intel");
-}
-
-#[inline(always)]
 pub unsafe fn enable_interrupts() {
     asm!("sti" :::: "volatile", "intel");
 }