1 files changed, 65 insertions, 15 deletions

diff --git a/src/apic/x2apic.rs b/src/apic/x2apic.rs
index ceb8aad..fc23152 100644
--- a/src/apic/x2apic.rs
+++ b/src/apic/x2apic.rs
@@ -1,11 +1,11 @@
 //! x2APIC, the most recent APIC on x86 for large servers with more than 255 cores.
 use bit_field::BitField;
 
-use super::{ApicControl, ApicId, Icr};
+use super::*;
 use crate::msr::{
-    rdmsr, wrmsr, IA32_APIC_BASE, IA32_TSC_DEADLINE, IA32_X2APIC_APICID, IA32_X2APIC_ESR,
-    IA32_X2APIC_LVT_LINT0, IA32_X2APIC_LVT_TIMER, IA32_X2APIC_SELF_IPI, IA32_X2APIC_SIVR,
-    IA32_X2APIC_VERSION,
+    rdmsr, wrmsr, IA32_APIC_BASE, IA32_TSC_DEADLINE, IA32_X2APIC_APICID, IA32_X2APIC_EOI,
+    IA32_X2APIC_ESR, IA32_X2APIC_ICR, IA32_X2APIC_LDR, IA32_X2APIC_LVT_LINT0,
+    IA32_X2APIC_LVT_TIMER, IA32_X2APIC_SELF_IPI, IA32_X2APIC_SIVR, IA32_X2APIC_VERSION,
 };
 
 /// Represents an x2APIC driver instance.
@@ -39,8 +39,7 @@ impl X2APIC {
             let svr: u64 = 1 << 8 | 15;
             wrmsr(IA32_X2APIC_SIVR, svr);
 
-            //TODO: let mut lint0 = rdmsr(IA32_X2APIC_LVT_LINT0);
-            // TODO: Fix magic number
+            // TODO: Fix magic number?
             let lint0 = 1 << 16 | (1 << 15) | (0b111 << 8) | 0x20;
             wrmsr(IA32_X2APIC_LVT_LINT0, lint0);
 
@@ -71,11 +70,16 @@ impl ApicControl for X2APIC {
         (self.base & (1 << 8)) > 0
     }
 
-    /// Read local APIC ID.
+    /// Read local x2APIC ID.
     fn id(&self) -> u32 {
         unsafe { rdmsr(IA32_X2APIC_APICID) as u32 }
     }
 
+    /// In x2APIC mode, the 32-bit logical x2APIC ID, can be read from LDR.
+    fn logical_id(&self) -> u32 {
+        unsafe { rdmsr(IA32_X2APIC_LDR) as u32 }
+    }
+
     /// Read APIC version.
     fn version(&self) -> u32 {
         unsafe { rdmsr(IA32_X2APIC_VERSION) as u32 }
@@ -106,26 +110,72 @@ impl ApicControl for X2APIC {
 
     /// End Of Interrupt -- Acknowledge interrupt delivery.
     fn eoi(&mut self) {
-        unreachable!("NYI");
+        unsafe {
+            wrmsr(IA32_X2APIC_EOI, 0);
+        }
     }
 
     /// Send a INIT IPI to a core.
-    unsafe fn ipi_init(&mut self, _core: ApicId) {
-        unreachable!("NYI");
+    unsafe fn ipi_init(&mut self, core: ApicId) {
+        let icr = Icr::for_x2apic(
+            0,
+            core,
+            DestinationShorthand::NoShorthand,
+            DeliveryMode::Init,
+            DestinationMode::Physical,
+            DeliveryStatus::Idle,
+            Level::Assert,
+            TriggerMode::Level,
+        );
+        self.send_ipi(icr);
     }
 
     /// Deassert INIT IPI.
     unsafe fn ipi_init_deassert(&mut self) {
-        unreachable!("NYI");
+        let icr = Icr::for_x2apic(
+            0,
+            ApicId::X2Apic(0),
+            // INIT deassert is always sent to everyone, so we are supposed to specify:
+            DestinationShorthand::AllIncludingSelf,
+            DeliveryMode::Init,
+            DestinationMode::Physical,
+            DeliveryStatus::Idle,
+            Level::Deassert,
+            TriggerMode::Level,
+        );
+        self.send_ipi(icr);
     }
 
     /// Send a STARTUP IPI to a core.
-    unsafe fn ipi_startup(&mut self, _core: ApicId, _start_page: u8) {
-        unreachable!("NYI");
+    unsafe fn ipi_startup(&mut self, core: ApicId, start_page: u8) {
+        let icr = Icr::for_x2apic(
+            start_page,
+            core,
+            DestinationShorthand::NoShorthand,
+            DeliveryMode::StartUp,
+            DestinationMode::Physical,
+            DeliveryStatus::Idle,
+            Level::Assert,
+            TriggerMode::Edge,
+        );
+        self.send_ipi(icr);
     }
 
     /// Send a generic IPI.
-    unsafe fn send_ipi(&mut self, _icr: Icr) {
-        unreachable!("NYI");
+    unsafe fn send_ipi(&mut self, icr: Icr) {
+        wrmsr(IA32_X2APIC_ESR, 0);
+        wrmsr(IA32_X2APIC_ESR, 0);
+
+        wrmsr(IA32_X2APIC_ICR, icr.0);
+
+        loop {
+            let icr = rdmsr(IA32_X2APIC_ICR);
+            if (icr >> 12 & 0x1) == 0 {
+                break;
+            }
+            if rdmsr(IA32_X2APIC_ESR) > 0 {
+                break;
+            }
+        }
     }
 }