diff options
Diffstat (limited to 'x86data/perfmon_data/GLM/Goldmont_matrix_V8.tsv')
| -rw-r--r-- | x86data/perfmon_data/GLM/Goldmont_matrix_V8.tsv | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/x86data/perfmon_data/GLM/Goldmont_matrix_V8.tsv b/x86data/perfmon_data/GLM/Goldmont_matrix_V8.tsv new file mode 100644 index 0000000..72b2e68 --- /dev/null +++ b/x86data/perfmon_data/GLM/Goldmont_matrix_V8.tsv @@ -0,0 +1,32 @@ +# Performance Monitoring Events for Intel Atom Processors Based on the Goldmont Microarchitecture - V8 +# 8/16/2016 1:31:03 PM +# Copyright (c) 2007 - 2016 Intel Corporation. All rights reserved. +MATRIX_REQUEST MATRIX_RESPONSE MATRIX_VALUE MATRIX_REGISTER DESCRIPTION +DEMAND_DATA_RD Null 0x0001 0,1 Counts demand cacheable data reads of full cache lines +DEMAND_RFO Null 0x0002 0,1 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line +DEMAND_CODE_RD Null 0x0004 0,1 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache +COREWB Null 0x0008 0 Counts the number of writeback transactions caused by L1 or L2 cache evictions +PF_L2_DATA_RD Null 0x0010 0,1 Counts data cacheline reads generated by hardware L2 cache prefetcher +PF_L2_RFO Null 0x0020 0,1 Counts reads for ownership (RFO) requests generated by L2 prefetcher +PARTIAL_READS Null 0x0080 0,1 Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types +PARTIAL_WRITES Null 0x0100 0,1 Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory +UC_CODE_RD Null 0x0200 0,1 Counts code reads in uncacheable (UC) memory region +BUS_LOCKS Null 0x0400 0,1 Counts bus lock and split lock requests +FULL_STREAMING_STORES Null 0x0800 0,1 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes +SW_PREFETCH Null 0x1000 0,1 Counts data cache lines requests by software prefetch instructions +PF_L1_DATA_RD Null 0x2000 0,1 Counts data cache line reads generated by hardware L1 data cache prefetcher +PARTIAL_STREAMING_STORES Null 0x4000 0,1 Counts partial cache line data writes to uncacheable write combining (USWC) memory region +STREAMING_STORES Null 0x4800 0,1 Counts any data writes to uncacheable write combining (USWC) memory region +ANY_REQUEST Null 0x8000 0,1 Counts requests to the uncore subsystem +ANY_PF_DATA_RD Null 0x3010 0,1 Counts data reads generated by L1 or L2 prefetchers +ANY_DATA_RD Null 0x3091 0,1 Counts data reads (demand & prefetch) +ANY_RFO Null 0x0022 0,1 Counts reads for ownership (RFO) requests (demand & prefetch) +ANY_READ Null 0x32b7 0,1 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) +Null ANY_RESPONSE 0x000001 0,1 have any transaction responses from the uncore subsystem. +Null L2_HIT 0x000004 0,1 hit the L2 cache. +Null L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED 0x020000 0,1 true miss for the L2 cache with a snoop miss in the other processor module. +Null L2_MISS.HIT_OTHER_CORE_NO_FWD 0x040000 0,1 miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. +Null L2_MISS.HITM_OTHER_CORE 0x100000 0,1 miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. +Null L2_MISS.NON_DRAM 0x200000 0,1 miss the L2 cache and targets non-DRAM system address. +Null L2_MISS.ANY 0x360000 0,1 miss the L2 cache. +Null OUTSTANDING 0x400000 0 outstanding, per cycle, from the time of the L2 miss to when any response is received. |