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# Performance Monitoring Events for Intel(R) Xeon(R) Processor E5 v4 Family Based on the the Broadwell Microarchitecture - V14
# 8/16/2018 4:41:37 AM
# Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved.
BitName BitIndex Type Description MATRIX_REG BitsNotCombinedWith Errata
DEMAND_DATA_RD 0 1 Counts demand data reads 0,1 na
DEMAND_RFO 1 1 Counts all demand data writes (RFOs) 0,1 na
DEMAND_CODE_RD 2 1 Counts all demand code reads 0,1 na
COREWB 3 1 Counts writebacks (modified to exclusive) 0,1 na
PF_L2_DATA_RD 4 1 Counts prefetch (that bring data to L2) data reads 0,1 na
PF_L2_RFO 5 1 Counts all prefetch (that bring data to L2) RFOs 0,1 na
PF_L2_CODE_RD 6 1 Counts all prefetch (that bring data to LLC only) code reads 0,1 na
PF_L3_DATA_RD 7 1 0,1 na
PF_L3_RFO 8 1 0,1 na
PF_L3_CODE_RD 9 1 0,1 na
SPLIT_LOCK_UC_LOCK 10 1 Counts all locks that are either split across cache line boundaries or to uncacheable addresses 0,1 na
STREAMING_STORES 11 1 Counts all non-temporal stores 0,1 na
OTHER 15 1 Counts any other requests 0,1 na
ALL_PF_DATA_RD 4,7 1 Counts all prefetch data reads 0,1 na
ALL_PF_RFO 5,8 1 Counts prefetch RFOs 0,1 na
ALL_PF_CODE_RD 6,9 1 Counts all prefetch code reads 0,1 na
ALL_DATA_RD 0,4,7 1 Counts all demand & prefetch data reads 0,1 na
ALL_RFO 1,5,8 1 Counts all demand & prefetch RFOs 0,1 na
ALL_CODE_RD 2,6,9 1 Counts all demand & prefetch code reads 0,1 na
ALL_READS 0,1,2,4,5,6,7,8,9,10 1 Counts all data/code/rfo reads (demand & prefetch) 0,1 na
ALL_REQUESTS 0,1,2,3,4,5,6,7,8,9,10,11,15 1 Counts all requests 0,1 na
ANY_RESPONSE 16 2 have any response type. 0,1 na
SUPPLIER_NONE 17 3 0,1 na
L3_HIT_M 18 3 0,1 na
L3_HIT_E 19 3 0,1 na
L3_HIT_S 20 3 0,1 na
L3_HIT_F 21 3 0,1 na
L3_HIT 18,19,20,21 3 0,1 na
L3_MISS_LOCAL_DRAM 26 3 0,1 na
L3_MISS_REMOTE_HOP0_DRAM 27 3 0,1 na
L3_MISS_REMOTE_HOP1_DRAM 28 3 0,1 na
L3_MISS_REMOTE_HOP2P_DRAM 29 3 0,1 na
L3_MISS 26,27,28,29 3 0,1 na
SNOOP_NONE 31 4 0,1 na
SNOOP_NOT_NEEDED 32 4 0,1 na
SNOOP_MISS 33 4 0,1 na
SNOOP_HIT_NO_FWD 34 4 0,1 na
SNOOP_HIT_WITH_FWD 35 4 0,1 18,19,20,21 na
SNOOP_HITM 36 4 0,1 na
SNOOP_NON_DRAM 37 4 0,1 na
ANY_SNOOP 31,32,33,34,35,36,37 4 0,1 na
LLC_HIT.ANY_RESPONSE 18,19,20,21,31,32,33,34,35,36,37 2 hit in the L3 0,1 na na
LLC_HIT.NO_SNOOP_NEEDED 18,19,20,21,32 2 hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores 0,1 na na
LLC_HIT.SNOOP_MISS 18,19,20,21,33 2 hit in the L3 and the snoops sent to sibling cores return clean response 0,1 na na
LLC_HIT.HIT_OTHER_CORE_NO_FWD 18,19,20,21,34 2 hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded 0,1 na na
LLC_HIT.HITM_OTHER_CORE 18,19,20,21,36 2 hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded 0,1 na na
LLC_MISS.ANY_RESPONSE 22,23,24,25,26,27,28,29,31,32,33,34,35,36,37 2 miss in the L3 0,1 na na
LLC_MISS.LOCAL_DRAM 26,33,34 2 miss the L3 and the data is returned from local dram 0,1 na na
LLC_MISS.REMOTE_DRAM 22,23,24,25,27,28,29,33,34 2 miss the L3 and the data is returned from remote dram 0,1 na na
LLC_MISS.ANY_DRAM 22,23,24,25,26,27,28,29,33,34 2 miss the L3 and the data is returned from local or remote dram 0,1 na na
LLC_MISS.REMOTE_HITM 22,23,24,25,26,27,28,29,36 2 miss the L3 and the modified data is transferred from remote cache 0,1 na na
LLC_MISS.REMOTE_HIT_FORWARD 22,23,24,25,26,27,28,29,30,35 2 miss the L3 and clean or shared data is transferred from remote cache 0,1 na na
PF_LLC_DATA_RD 7 1 Counts all prefetch (that bring data to LLC only) data reads 0,1 na na
PF_LLC_RFO 8 1 Counts all prefetch (that bring data to LLC only) RFOs 0,1 na na
PF_LLC_CODE_RD 9 1 Counts prefetch (that bring data to LLC only) code reads 0,1 na na
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