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# Performance Monitoring Events for Intel Atom Processors Based on the Bonnel Microarchitecture - V4
# 8/16/2016 11:57:05 AM
# Copyright (c) 2007 - 2016 Intel Corporation. All rights reserved.
EventCode UMask EventName BriefDescription Counter SampleAfterValue MSRIndex MSRValue CounterMask Invert AnyThread EdgeDetect PEBS Errata
0x2 0x83 STORE_FORWARDS.ANY All store forwards 0,1 200000 0 0 0 0 0 0 0 null
0x2 0x81 STORE_FORWARDS.GOOD Good store forwards 0,1 200000 0 0 0 0 0 0 0 null
0x3 0x7F REISSUE.ANY Micro-op reissues for any cause 0,1 200000 0 0 0 0 0 0 0 null
0x3 0xFF REISSUE.ANY.AR Micro-op reissues for any cause (At Retirement) 0,1 200000 0 0 0 0 0 0 0 null
0x5 0xF MISALIGN_MEM_REF.SPLIT Memory references that cross an 8-byte boundary. 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x9 MISALIGN_MEM_REF.LD_SPLIT Load splits 0,1 200000 0 0 0 0 0 0 0 null
0x5 0xA MISALIGN_MEM_REF.ST_SPLIT Store splits 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x8F MISALIGN_MEM_REF.SPLIT.AR Memory references that cross an 8-byte boundary (At Retirement) 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x89 MISALIGN_MEM_REF.LD_SPLIT.AR Load splits (At Retirement) 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x8A MISALIGN_MEM_REF.ST_SPLIT.AR Store splits (Ar Retirement) 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x8C MISALIGN_MEM_REF.RMW_SPLIT ld-op-st splits 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x97 MISALIGN_MEM_REF.BUBBLE Nonzero segbase 1 bubble 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x91 MISALIGN_MEM_REF.LD_BUBBLE Nonzero segbase load 1 bubble 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x92 MISALIGN_MEM_REF.ST_BUBBLE Nonzero segbase store 1 bubble 0,1 200000 0 0 0 0 0 0 0 null
0x5 0x94 MISALIGN_MEM_REF.RMW_BUBBLE Nonzero segbase ld-op-st 1 bubble 0,1 200000 0 0 0 0 0 0 0 null
0x6 0x80 SEGMENT_REG_LOADS.ANY Number of segment register loads. 0,1 200000 0 0 0 0 0 0 0 null
0x7 0x81 PREFETCH.PREFETCHT0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed. 0,1 200000 0 0 0 0 0 0 0 null
0x7 0x82 PREFETCH.PREFETCHT1 Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed. 0,1 200000 0 0 0 0 0 0 0 null
0x7 0x84 PREFETCH.PREFETCHT2 Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed. 0,1 200000 0 0 0 0 0 0 0 null
0x7 0x86 PREFETCH.SW_L2 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed 0,1 200000 0 0 0 0 0 0 0 null
0x7 0x88 PREFETCH.PREFETCHNTA Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed 0,1 200000 0 0 0 0 0 0 0 null
0x7 0x10 PREFETCH.HW_PREFETCH L1 hardware prefetch request 0,1 2000000 0 0 0 0 0 0 0 null
0x7 0xF PREFETCH.SOFTWARE_PREFETCH Any Software prefetch 0,1 200000 0 0 0 0 0 0 0 null
0x7 0x8F PREFETCH.SOFTWARE_PREFETCH.AR Any Software prefetch 0,1 200000 0 0 0 0 0 0 0 null
0x8 0x7 DATA_TLB_MISSES.DTLB_MISS Memory accesses that missed the DTLB. 0,1 200000 0 0 0 0 0 0 0 null
0x8 0x5 DATA_TLB_MISSES.DTLB_MISS_LD DTLB misses due to load operations. 0,1 200000 0 0 0 0 0 0 0 null
0x8 0x9 DATA_TLB_MISSES.L0_DTLB_MISS_LD L0 DTLB misses due to load operations. 0,1 200000 0 0 0 0 0 0 0 null
0x8 0x6 DATA_TLB_MISSES.DTLB_MISS_ST DTLB misses due to store operations. 0,1 200000 0 0 0 0 0 0 0 null
0x8 0xA DATA_TLB_MISSES.L0_DTLB_MISS_ST L0 DTLB misses due to store operations 0,1 200000 0 0 0 0 0 0 0 null
0x9 0x20 DISPATCH_BLOCKED.ANY Memory cluster signals to block micro-op dispatch for any reason 0,1 200000 0 0 0 0 0 0 0 null
0xC 0x3 PAGE_WALKS.WALKS Number of page-walks executed. 0,1 200000 0 0 0 0 0 0 0 null
0xC 0x3 PAGE_WALKS.CYCLES Duration of page-walks in core cycles 0,1 2000000 0 0 0 0 0 0 0 null
0xC 0x1 PAGE_WALKS.D_SIDE_WALKS Number of D-side only page walks 0,1 200000 0 0 0 0 0 0 0 null
0xC 0x1 PAGE_WALKS.D_SIDE_CYCLES Duration of D-side only page walks 0,1 2000000 0 0 0 0 0 0 0 null
0xC 0x2 PAGE_WALKS.I_SIDE_WALKS Number of I-Side page walks 0,1 200000 0 0 0 0 0 0 0 null
0xC 0x2 PAGE_WALKS.I_SIDE_CYCLES Duration of I-Side page walks 0,1 2000000 0 0 0 0 0 0 0 null
0x10 0x1 X87_COMP_OPS_EXE.ANY.S Floating point computational micro-ops executed. 0,1 2000000 0 0 0 0 0 0 0 null
0x10 0x81 X87_COMP_OPS_EXE.ANY.AR Floating point computational micro-ops retired. 0,1 2000000 0 0 0 0 0 0 2 null
0x10 0x2 X87_COMP_OPS_EXE.FXCH.S FXCH uops executed. 0,1 2000000 0 0 0 0 0 0 0 null
0x10 0x82 X87_COMP_OPS_EXE.FXCH.AR FXCH uops retired. 0,1 2000000 0 0 0 0 0 0 2 null
0x11 0x1 FP_ASSIST.S Floating point assists. 0,1 10000 0 0 0 0 0 0 0 null
0x11 0x81 FP_ASSIST.AR Floating point assists for retired operations. 0,1 10000 0 0 0 0 0 0 0 null
0x12 0x1 MUL.S Multiply operations executed. 0,1 2000000 0 0 0 0 0 0 0 null
0x12 0x81 MUL.AR Multiply operations retired 0,1 2000000 0 0 0 0 0 0 0 null
0x13 0x1 DIV.S Divide operations executed. 0,1 2000000 0 0 0 0 0 0 0 null
0x13 0x81 DIV.AR Divide operations retired 0,1 2000000 0 0 0 0 0 0 0 null
0x14 0x1 CYCLES_DIV_BUSY Cycles the divider is busy. 0,1 2000000 0 0 0 0 0 0 0 null
0x21 0x40 L2_ADS.SELF Cycles L2 address bus is in use. 0,1 200000 0 0 0 0 0 0 0 null
0x22 0x40 L2_DBUS_BUSY.SELF Cycles the L2 cache data bus is busy. 0,1 200000 0 0 0 0 0 0 0 null
0x23 0x40 L2_DBUS_BUSY_RD.SELF Cycles the L2 transfers data to the core. 0,1 200000 0 0 0 0 0 0 0 null
0x24 0x70 L2_LINES_IN.SELF.ANY L2 cache misses. 0,1 200000 0 0 0 0 0 0 0 null
0x24 0x40 L2_LINES_IN.SELF.DEMAND L2 cache misses. 0,1 200000 0 0 0 0 0 0 0 null
0x24 0x50 L2_LINES_IN.SELF.PREFETCH L2 cache misses. 0,1 200000 0 0 0 0 0 0 0 null
0x25 0x40 L2_M_LINES_IN.SELF L2 cache line modifications. 0,1 200000 0 0 0 0 0 0 0 null
0x26 0x70 L2_LINES_OUT.SELF.ANY L2 cache lines evicted. 0,1 200000 0 0 0 0 0 0 0 null
0x26 0x40 L2_LINES_OUT.SELF.DEMAND L2 cache lines evicted. 0,1 200000 0 0 0 0 0 0 0 null
0x26 0x50 L2_LINES_OUT.SELF.PREFETCH L2 cache lines evicted. 0,1 200000 0 0 0 0 0 0 0 null
0x27 0x70 L2_M_LINES_OUT.SELF.ANY Modified lines evicted from the L2 cache 0,1 200000 0 0 0 0 0 0 0 null
0x27 0x40 L2_M_LINES_OUT.SELF.DEMAND Modified lines evicted from the L2 cache 0,1 200000 0 0 0 0 0 0 0 null
0x27 0x50 L2_M_LINES_OUT.SELF.PREFETCH Modified lines evicted from the L2 cache 0,1 200000 0 0 0 0 0 0 0 null
0x28 0x44 L2_IFETCH.SELF.E_STATE L2 cacheable instruction fetch requests 0,1 200000 0 0 0 0 0 0 0 null
0x28 0x41 L2_IFETCH.SELF.I_STATE L2 cacheable instruction fetch requests 0,1 200000 0 0 0 0 0 0 0 null
0x28 0x48 L2_IFETCH.SELF.M_STATE L2 cacheable instruction fetch requests 0,1 200000 0 0 0 0 0 0 0 null
0x28 0x42 L2_IFETCH.SELF.S_STATE L2 cacheable instruction fetch requests 0,1 200000 0 0 0 0 0 0 0 null
0x28 0x4F L2_IFETCH.SELF.MESI L2 cacheable instruction fetch requests 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x74 L2_LD.SELF.ANY.E_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x71 L2_LD.SELF.ANY.I_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x78 L2_LD.SELF.ANY.M_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x72 L2_LD.SELF.ANY.S_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x7F L2_LD.SELF.ANY.MESI L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x44 L2_LD.SELF.DEMAND.E_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x41 L2_LD.SELF.DEMAND.I_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x48 L2_LD.SELF.DEMAND.M_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x42 L2_LD.SELF.DEMAND.S_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x4F L2_LD.SELF.DEMAND.MESI L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x54 L2_LD.SELF.PREFETCH.E_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x51 L2_LD.SELF.PREFETCH.I_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x58 L2_LD.SELF.PREFETCH.M_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x52 L2_LD.SELF.PREFETCH.S_STATE L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x29 0x5F L2_LD.SELF.PREFETCH.MESI L2 cache reads 0,1 200000 0 0 0 0 0 0 0 null
0x2A 0x44 L2_ST.SELF.E_STATE L2 store requests 0,1 200000 0 0 0 0 0 0 0 null
0x2A 0x41 L2_ST.SELF.I_STATE L2 store requests 0,1 200000 0 0 0 0 0 0 0 null
0x2A 0x48 L2_ST.SELF.M_STATE L2 store requests 0,1 200000 0 0 0 0 0 0 0 null
0x2A 0x42 L2_ST.SELF.S_STATE L2 store requests 0,1 200000 0 0 0 0 0 0 0 null
0x2A 0x4F L2_ST.SELF.MESI L2 store requests 0,1 200000 0 0 0 0 0 0 0 null
0x2B 0x44 L2_LOCK.SELF.E_STATE L2 locked accesses 0,1 200000 0 0 0 0 0 0 0 null
0x2B 0x41 L2_LOCK.SELF.I_STATE L2 locked accesses 0,1 200000 0 0 0 0 0 0 0 null
0x2B 0x48 L2_LOCK.SELF.M_STATE L2 locked accesses 0,1 200000 0 0 0 0 0 0 0 null
0x2B 0x42 L2_LOCK.SELF.S_STATE L2 locked accesses 0,1 200000 0 0 0 0 0 0 0 null
0x2B 0x4F L2_LOCK.SELF.MESI L2 locked accesses 0,1 200000 0 0 0 0 0 0 0 null
0x2C 0x44 L2_DATA_RQSTS.SELF.E_STATE All data requests from the L1 data cache 0,1 200000 0 0 0 0 0 0 0 null
0x2C 0x41 L2_DATA_RQSTS.SELF.I_STATE All data requests from the L1 data cache 0,1 200000 0 0 0 0 0 0 0 null
0x2C 0x48 L2_DATA_RQSTS.SELF.M_STATE All data requests from the L1 data cache 0,1 200000 0 0 0 0 0 0 0 null
0x2C 0x42 L2_DATA_RQSTS.SELF.S_STATE All data requests from the L1 data cache 0,1 200000 0 0 0 0 0 0 0 null
0x2C 0x4F L2_DATA_RQSTS.SELF.MESI All data requests from the L1 data cache 0,1 200000 0 0 0 0 0 0 0 null
0x2D 0x44 L2_LD_IFETCH.SELF.E_STATE All read requests from L1 instruction and data caches 0,1 200000 0 0 0 0 0 0 0 null
0x2D 0x41 L2_LD_IFETCH.SELF.I_STATE All read requests from L1 instruction and data caches 0,1 200000 0 0 0 0 0 0 0 null
0x2D 0x48 L2_LD_IFETCH.SELF.M_STATE All read requests from L1 instruction and data caches 0,1 200000 0 0 0 0 0 0 0 null
0x2D 0x42 L2_LD_IFETCH.SELF.S_STATE All read requests from L1 instruction and data caches 0,1 200000 0 0 0 0 0 0 0 null
0x2D 0x4F L2_LD_IFETCH.SELF.MESI All read requests from L1 instruction and data caches 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x74 L2_RQSTS.SELF.ANY.E_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x71 L2_RQSTS.SELF.ANY.I_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x78 L2_RQSTS.SELF.ANY.M_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x72 L2_RQSTS.SELF.ANY.S_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x7F L2_RQSTS.SELF.ANY.MESI L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x44 L2_RQSTS.SELF.DEMAND.E_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x48 L2_RQSTS.SELF.DEMAND.M_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x42 L2_RQSTS.SELF.DEMAND.S_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x54 L2_RQSTS.SELF.PREFETCH.E_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x51 L2_RQSTS.SELF.PREFETCH.I_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x58 L2_RQSTS.SELF.PREFETCH.M_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x52 L2_RQSTS.SELF.PREFETCH.S_STATE L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x5F L2_RQSTS.SELF.PREFETCH.MESI L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x41 L2_RQSTS.SELF.DEMAND.I_STATE L2 cache demand requests from this core that missed the L2 0,1 200000 0 0 0 0 0 0 0 null
0x2E 0x4F L2_RQSTS.SELF.DEMAND.MESI L2 cache demand requests from this core 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x74 L2_REJECT_BUSQ.SELF.ANY.E_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x71 L2_REJECT_BUSQ.SELF.ANY.I_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x78 L2_REJECT_BUSQ.SELF.ANY.M_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x72 L2_REJECT_BUSQ.SELF.ANY.S_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x7F L2_REJECT_BUSQ.SELF.ANY.MESI Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x44 L2_REJECT_BUSQ.SELF.DEMAND.E_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x41 L2_REJECT_BUSQ.SELF.DEMAND.I_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x48 L2_REJECT_BUSQ.SELF.DEMAND.M_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x42 L2_REJECT_BUSQ.SELF.DEMAND.S_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x4F L2_REJECT_BUSQ.SELF.DEMAND.MESI Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x54 L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x51 L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x58 L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x52 L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x30 0x5F L2_REJECT_BUSQ.SELF.PREFETCH.MESI Rejected L2 cache requests 0,1 200000 0 0 0 0 0 0 0 null
0x32 0x40 L2_NO_REQ.SELF Cycles no L2 cache requests are pending 0,1 200000 0 0 0 0 0 0 0 null
0x3A 0x0 EIST_TRANS Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions 0,1 200000 0 0 0 0 0 0 0 null
0x3B 0xC0 THERMAL_TRIP Number of thermal trips 0,1 200000 0 0 0 0 0 0 0 null
0x3C 0x0 CPU_CLK_UNHALTED.CORE_P Core cycles when core is not halted 0,1 2000000 0 0 0 0 0 0 0 null
0x3C 0x1 CPU_CLK_UNHALTED.BUS Bus cycles when core is not halted 0,1 200000 0 0 0 0 0 0 0 null
0xA 0x0 CPU_CLK_UNHALTED.CORE Core cycles when core is not halted Fixed counter 2 2000000 0 0 0 0 0 0 0 null
0xA 0x0 CPU_CLK_UNHALTED.REF Reference cycles when core is not halted. Fixed counter 3 2000000 0 0 0 0 0 0 0 null
0x40 0xA1 L1D_CACHE.LD L1 Cacheable Data Reads 0,1 2000000 0 0 0 0 0 0 0 null
0x40 0xA2 L1D_CACHE.ST L1 Cacheable Data Writes 0,1 2000000 0 0 0 0 0 0 0 null
0x40 0x83 L1D_CACHE.ALL_REF L1 Data reads and writes 0,1 2000000 0 0 0 0 0 0 0 null
0x40 0xA3 L1D_CACHE.ALL_CACHE_REF L1 Data Cacheable reads and writes 0,1 2000000 0 0 0 0 0 0 0 null
0x40 0x8 L1D_CACHE.REPL L1 Data line replacements 0,1 200000 0 0 0 0 0 0 0 null
0x40 0x48 L1D_CACHE.REPLM Modified cache lines allocated in the L1 data cache 0,1 200000 0 0 0 0 0 0 0 null
0x40 0x10 L1D_CACHE.EVICT Modified cache lines evicted from the L1 data cache 0,1 200000 0 0 0 0 0 0 0 null
0x60 0xE0 BUS_REQUEST_OUTSTANDING.ALL_AGENTS Outstanding cacheable data read bus requests duration. 0,1 200000 0 0 0 0 0 0 0 null
0x60 0x40 BUS_REQUEST_OUTSTANDING.SELF Outstanding cacheable data read bus requests duration. 0,1 200000 0 0 0 0 0 0 0 null
0x61 0x20 BUS_BNR_DRV.ALL_AGENTS Number of Bus Not Ready signals asserted. 0,1 200000 0 0 0 0 0 0 0 null
0x61 0x0 BUS_BNR_DRV.THIS_AGENT Number of Bus Not Ready signals asserted. 0,1 200000 0 0 0 0 0 0 0 null
0x62 0x20 BUS_DRDY_CLOCKS.ALL_AGENTS Bus cycles when data is sent on the bus. 0,1 200000 0 0 0 0 0 0 0 null
0x62 0x0 BUS_DRDY_CLOCKS.THIS_AGENT Bus cycles when data is sent on the bus. 0,1 200000 0 0 0 0 0 0 0 null
0x63 0xE0 BUS_LOCK_CLOCKS.ALL_AGENTS Bus cycles when a LOCK signal is asserted. 0,1 200000 0 0 0 0 0 0 0 null
0x63 0x40 BUS_LOCK_CLOCKS.SELF Bus cycles when a LOCK signal is asserted. 0,1 200000 0 0 0 0 0 0 0 null
0x64 0x40 BUS_DATA_RCV.SELF Bus cycles while processor receives data. 0,1 200000 0 0 0 0 0 0 0 null
0x65 0xE0 BUS_TRANS_BRD.ALL_AGENTS Burst read bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x65 0x40 BUS_TRANS_BRD.SELF Burst read bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x66 0xE0 BUS_TRANS_RFO.ALL_AGENTS RFO bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x66 0x40 BUS_TRANS_RFO.SELF RFO bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x67 0xE0 BUS_TRANS_WB.ALL_AGENTS Explicit writeback bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x67 0x40 BUS_TRANS_WB.SELF Explicit writeback bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x68 0xE0 BUS_TRANS_IFETCH.ALL_AGENTS Instruction-fetch bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x68 0x40 BUS_TRANS_IFETCH.SELF Instruction-fetch bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x69 0xE0 BUS_TRANS_INVAL.ALL_AGENTS Invalidate bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x69 0x40 BUS_TRANS_INVAL.SELF Invalidate bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6A 0xE0 BUS_TRANS_PWR.ALL_AGENTS Partial write bus transaction. 0,1 200000 0 0 0 0 0 0 0 null
0x6A 0x40 BUS_TRANS_PWR.SELF Partial write bus transaction. 0,1 200000 0 0 0 0 0 0 0 null
0x6B 0xE0 BUS_TRANS_P.ALL_AGENTS Partial bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6B 0x40 BUS_TRANS_P.SELF Partial bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6C 0xE0 BUS_TRANS_IO.ALL_AGENTS IO bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6C 0x40 BUS_TRANS_IO.SELF IO bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6D 0xE0 BUS_TRANS_DEF.ALL_AGENTS Deferred bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6D 0x40 BUS_TRANS_DEF.SELF Deferred bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6E 0xE0 BUS_TRANS_BURST.ALL_AGENTS Burst (full cache-line) bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6E 0x40 BUS_TRANS_BURST.SELF Burst (full cache-line) bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6F 0xE0 BUS_TRANS_MEM.ALL_AGENTS Memory bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x6F 0x40 BUS_TRANS_MEM.SELF Memory bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x70 0xE0 BUS_TRANS_ANY.ALL_AGENTS All bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x70 0x40 BUS_TRANS_ANY.SELF All bus transactions. 0,1 200000 0 0 0 0 0 0 0 null
0x77 0xB EXT_SNOOP.THIS_AGENT.ANY External snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x77 0x1 EXT_SNOOP.THIS_AGENT.CLEAN External snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x77 0x2 EXT_SNOOP.THIS_AGENT.HIT External snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x77 0x8 EXT_SNOOP.THIS_AGENT.HITM External snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x77 0x2B EXT_SNOOP.ALL_AGENTS.ANY External snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x77 0x21 EXT_SNOOP.ALL_AGENTS.CLEAN External snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x77 0x22 EXT_SNOOP.ALL_AGENTS.HIT External snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x77 0x28 EXT_SNOOP.ALL_AGENTS.HITM External snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x7A 0x20 BUS_HIT_DRV.ALL_AGENTS HIT signal asserted. 0,1 200000 0 0 0 0 0 0 0 null
0x7A 0x0 BUS_HIT_DRV.THIS_AGENT HIT signal asserted. 0,1 200000 0 0 0 0 0 0 0 null
0x7B 0x20 BUS_HITM_DRV.ALL_AGENTS HITM signal asserted. 0,1 200000 0 0 0 0 0 0 0 null
0x7B 0x0 BUS_HITM_DRV.THIS_AGENT HITM signal asserted. 0,1 200000 0 0 0 0 0 0 0 null
0x7D 0x40 BUSQ_EMPTY.SELF Bus queue is empty. 0,1 200000 0 0 0 0 0 0 0 null
0x7E 0xE0 SNOOP_STALL_DRV.ALL_AGENTS Bus stalled for snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x7E 0x40 SNOOP_STALL_DRV.SELF Bus stalled for snoops. 0,1 200000 0 0 0 0 0 0 0 null
0x7F 0x40 BUS_IO_WAIT.SELF IO requests waiting in the bus queue. 0,1 200000 0 0 0 0 0 0 0 null
0x80 0x3 ICACHE.ACCESSES Instruction fetches. 0,1 200000 0 0 0 0 0 0 0 null
0x80 0x1 ICACHE.HIT Icache hit 0,1 200000 0 0 0 0 0 0 0 null
0x80 0x2 ICACHE.MISSES Icache miss 0,1 200000 0 0 0 0 0 0 0 null
0x82 0x1 ITLB.HIT ITLB hits. 0,1 200000 0 0 0 0 0 0 0 null
0x82 0x4 ITLB.FLUSH ITLB flushes. 0,1 200000 0 0 0 0 0 0 0 null
0x82 0x2 ITLB.MISSES ITLB misses. 0,1 200000 0 0 0 0 0 0 2 null
0x86 0x1 CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED Cycles during which instruction fetches are stalled. 0,1 2000000 0 0 0 0 0 0 0 null
0x87 0x1 DECODE_STALL.PFB_EMPTY Decode stall due to PFB empty 0,1 2000000 0 0 0 0 0 0 0 null
0x87 0x2 DECODE_STALL.IQ_FULL Decode stall due to IQ full 0,1 2000000 0 0 0 0 0 0 0 null
0x88 0x1 BR_INST_TYPE_RETIRED.COND All macro conditional branch instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0x88 0x2 BR_INST_TYPE_RETIRED.UNCOND All macro unconditional branch instructions, excluding calls and indirects 0,1 2000000 0 0 0 0 0 0 0 null
0x88 0x4 BR_INST_TYPE_RETIRED.IND All indirect branches that are not calls. 0,1 2000000 0 0 0 0 0 0 0 null
0x88 0x8 BR_INST_TYPE_RETIRED.RET All indirect branches that have a return mnemonic 0,1 2000000 0 0 0 0 0 0 0 null
0x88 0x10 BR_INST_TYPE_RETIRED.DIR_CALL All non-indirect calls 0,1 2000000 0 0 0 0 0 0 0 null
0x88 0x20 BR_INST_TYPE_RETIRED.IND_CALL All indirect calls, including both register and memory indirect. 0,1 2000000 0 0 0 0 0 0 0 null
0x88 0x41 BR_INST_TYPE_RETIRED.COND_TAKEN Only taken macro conditional branch instructions 0,1 2000000 0 0 0 0 0 0 0 null
0x89 0x1 BR_MISSP_TYPE_RETIRED.COND Mispredicted cond branch instructions retired 0,1 200000 0 0 0 0 0 0 0 null
0x89 0x2 BR_MISSP_TYPE_RETIRED.IND Mispredicted ind branches that are not calls 0,1 200000 0 0 0 0 0 0 0 null
0x89 0x4 BR_MISSP_TYPE_RETIRED.RETURN Mispredicted return branches 0,1 200000 0 0 0 0 0 0 0 null
0x89 0x8 BR_MISSP_TYPE_RETIRED.IND_CALL Mispredicted indirect calls, including both register and memory indirect. 0,1 200000 0 0 0 0 0 0 0 null
0x89 0x11 BR_MISSP_TYPE_RETIRED.COND_TAKEN Mispredicted and taken cond branch instructions retired 0,1 200000 0 0 0 0 0 0 0 null
0xAA 0x1 MACRO_INSTS.NON_CISC_DECODED Non-CISC nacro instructions decoded 0,1 2000000 0 0 0 0 0 0 0 null
0xAA 0x2 MACRO_INSTS.CISC_DECODED CISC macro instructions decoded 0,1 2000000 0 0 0 0 0 0 0 null
0xAA 0x3 MACRO_INSTS.ALL_DECODED All Instructions decoded 0,1 2000000 0 0 0 0 0 0 0 null
0xB0 0x0 SIMD_UOPS_EXEC.S SIMD micro-ops executed (excluding stores). 0,1 2000000 0 0 0 0 0 0 0 null
0xB0 0x80 SIMD_UOPS_EXEC.AR SIMD micro-ops retired (excluding stores). 0,1 2000000 0 0 0 0 0 0 2 null
0xB1 0x0 SIMD_SAT_UOP_EXEC.S SIMD saturated arithmetic micro-ops executed. 0,1 2000000 0 0 0 0 0 0 0 null
0xB1 0x80 SIMD_SAT_UOP_EXEC.AR SIMD saturated arithmetic micro-ops retired. 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x1 SIMD_UOP_TYPE_EXEC.MUL.S SIMD packed multiply micro-ops executed 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x81 SIMD_UOP_TYPE_EXEC.MUL.AR SIMD packed multiply micro-ops retired 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x2 SIMD_UOP_TYPE_EXEC.SHIFT.S SIMD packed shift micro-ops executed 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x82 SIMD_UOP_TYPE_EXEC.SHIFT.AR SIMD packed shift micro-ops retired 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x4 SIMD_UOP_TYPE_EXEC.PACK.S SIMD packed micro-ops executed 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x84 SIMD_UOP_TYPE_EXEC.PACK.AR SIMD packed micro-ops retired 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x8 SIMD_UOP_TYPE_EXEC.UNPACK.S SIMD unpacked micro-ops executed 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x88 SIMD_UOP_TYPE_EXEC.UNPACK.AR SIMD unpacked micro-ops retired 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x10 SIMD_UOP_TYPE_EXEC.LOGICAL.S SIMD packed logical micro-ops executed 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x90 SIMD_UOP_TYPE_EXEC.LOGICAL.AR SIMD packed logical micro-ops retired 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0x20 SIMD_UOP_TYPE_EXEC.ARITHMETIC.S SIMD packed arithmetic micro-ops executed 0,1 2000000 0 0 0 0 0 0 0 null
0xB3 0xA0 SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR SIMD packed arithmetic micro-ops retired 0,1 2000000 0 0 0 0 0 0 0 null
0xC0 0x0 INST_RETIRED.ANY_P Instructions retired (precise event). 0,1 2000000 0 0 0 0 0 0 2 null
0xA 0x0 INST_RETIRED.ANY Instructions retired. Fixed counter 1 2000000 0 0 0 0 0 0 0 null
0xC2 0x10 UOPS_RETIRED.ANY Micro-ops retired. 0,1 2000000 0 0 0 0 0 0 0 null
0xC2 0x10 UOPS_RETIRED.STALLED_CYCLES Cycles no micro-ops retired. 0,1 2000000 0 0 0 0 0 0 0 null
0xC2 0x10 UOPS_RETIRED.STALLS Periods no micro-ops retired. 0,1 2000000 0 0 0 0 0 0 0 null
0xA9 0x1 UOPS.MS_CYCLES This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. 0,1 2000000 0 0 1 0 0 0 0 null
0xC3 0x1 MACHINE_CLEARS.SMC Self-Modifying Code detected. 0,1 200000 0 0 0 0 0 0 0 null
0xC4 0x0 BR_INST_RETIRED.ANY Retired branch instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xC4 0x1 BR_INST_RETIRED.PRED_NOT_TAKEN Retired branch instructions that were predicted not-taken. 0,1 2000000 0 0 0 0 0 0 0 null
0xC4 0x2 BR_INST_RETIRED.MISPRED_NOT_TAKEN Retired branch instructions that were mispredicted not-taken. 0,1 200000 0 0 0 0 0 0 0 null
0xC4 0x4 BR_INST_RETIRED.PRED_TAKEN Retired branch instructions that were predicted taken. 0,1 2000000 0 0 0 0 0 0 0 null
0xC4 0x8 BR_INST_RETIRED.MISPRED_TAKEN Retired branch instructions that were mispredicted taken. 0,1 200000 0 0 0 0 0 0 0 null
0xC4 0xC BR_INST_RETIRED.TAKEN Retired taken branch instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xC4 0xF BR_INST_RETIRED.ANY1 Retired branch instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xC5 0x0 BR_INST_RETIRED.MISPRED Retired mispredicted branch instructions (precise event). 0,1 200000 0 0 0 0 0 0 1 null
0xC6 0x1 CYCLES_INT_MASKED.CYCLES_INT_MASKED Cycles during which interrupts are disabled. 0,1 2000000 0 0 0 0 0 0 0 null
0xC6 0x2 CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED Cycles during which interrupts are pending and disabled. 0,1 2000000 0 0 0 0 0 0 0 null
0xC7 0x1 SIMD_INST_RETIRED.PACKED_SINGLE Retired Streaming SIMD Extensions (SSE) packed-single instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xC7 0x2 SIMD_INST_RETIRED.SCALAR_SINGLE Retired Streaming SIMD Extensions (SSE) scalar-single instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xC7 0x8 SIMD_INST_RETIRED.SCALAR_DOUBLE Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xC7 0x10 SIMD_INST_RETIRED.VECTOR Retired Streaming SIMD Extensions 2 (SSE2) vector instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xC8 0x0 HW_INT_RCV Hardware interrupts received. 0,1 200000 0 0 0 0 0 0 0 null
0xCA 0x1 SIMD_COMP_INST_RETIRED.PACKED_SINGLE Retired computational Streaming SIMD Extensions (SSE) packed-single instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xCA 0x2 SIMD_COMP_INST_RETIRED.SCALAR_SINGLE Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xCA 0x8 SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions. 0,1 2000000 0 0 0 0 0 0 0 null
0xCB 0x1 MEM_LOAD_RETIRED.L2_HIT Retired loads that hit the L2 cache (precise event). 0,1 200000 0 0 0 0 0 0 0 null
0xCB 0x2 MEM_LOAD_RETIRED.L2_MISS Retired loads that miss the L2 cache 0,1 10000 0 0 0 0 0 0 0 null
0xCB 0x4 MEM_LOAD_RETIRED.DTLB_MISS Retired loads that miss the DTLB (precise event). 0,1 200000 0 0 0 0 0 0 1 null
0xCD 0x0 SIMD_ASSIST SIMD assists invoked. 0,1 100000 0 0 0 0 0 0 0 null
0xCE 0x0 SIMD_INSTR_RETIRED SIMD Instructions retired. 0,1 2000000 0 0 0 0 0 0 0 null
0xCF 0x0 SIMD_SAT_INSTR_RETIRED Saturated arithmetic instructions retired. 0,1 2000000 0 0 0 0 0 0 0 null
0xDC 0x2 RESOURCE_STALLS.DIV_BUSY Cycles issue is stalled due to div busy. 0,1 2000000 0 0 0 0 0 0 0 null
0xE0 0x1 BR_INST_DECODED Branch instructions decoded 0,1 2000000 0 0 0 0 0 0 0 null
0xE4 0x1 BOGUS_BR Bogus branches 0,1 2000000 0 0 0 0 0 0 0 null
0xE6 0x1 BACLEARS.ANY BACLEARS asserted. 0,1 2000000 0 0 0 0 0 0 0 null
0x3 0x1 REISSUE.OVERLAP_STORE Micro-op reissues on a store-load collision 0,1 200000 0 0 0 0 0 0 0 null
0x3 0x81 REISSUE.OVERLAP_STORE.AR Micro-op reissues on a store-load collision (At Retirement) 0,1 200000 0 0 0 0 0 0 0 null
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