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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2022-11-12 11:26:36 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2022-11-12 11:26:36 +0000 |
| commit | 1a215916eeebdf96d4530e0afb1baa91b93eefb7 (patch) | |
| tree | c5d41bf6683fafc942c3c22eedc1829be2362110 | |
| parent | 90c1cb6f10dcf7d8a8b4c994aea0eeefe3578c7d (diff) | |
| parent | 9bff0c8783a1ea6f3ff7aebac1a55fda15968e40 (diff) | |
| download | cortex-m-1a215916eeebdf96d4530e0afb1baa91b93eefb7.tar.gz cortex-m-1a215916eeebdf96d4530e0afb1baa91b93eefb7.tar.zst cortex-m-1a215916eeebdf96d4530e0afb1baa91b93eefb7.zip | |
Merge #422
422: Add ITNS field to NVIC peripheral r=adamgreig a=sphw
This PR adds the ITNS (Interrupt Target Non-secure) field to the NIVC peripheral. This field is required to write a boot loader for TrustZone-M devices, since it allows the user to use interrupts from non-secure states.
I believe I have maintained the correct padding for the next fields, but I have not tested these changes on a non M33 device. So a close review and test would be appreciated.
Co-authored-by: Sascha Wise <me@saschawise.com>
| -rw-r--r-- | src/peripheral/nvic.rs | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index 57fa94b..067c1d9 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -36,7 +36,15 @@ pub struct RegisterBlock { #[cfg(armv6m)] _reserved4: [u32; 16], - _reserved5: [u32; 48], + _reserved5: [u32; 16], + + #[cfg(armv8m)] + /// Interrupt Target Non-secure (only present on Arm v8-M) + pub itns: [RW<u32>; 16], + #[cfg(not(armv8m))] + _reserved6: [u32; 16], + + _reserved7: [u32; 16], /// Interrupt Priority /// @@ -67,7 +75,7 @@ pub struct RegisterBlock { pub ipr: [RW<u32>; 8], #[cfg(not(armv6m))] - _reserved6: [u32; 580], + _reserved8: [u32; 580], /// Software Trigger Interrupt #[cfg(not(armv6m))] |