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| author |  Sascha Wise <me@saschawise.com>
| 2022-03-15 08:50:08 -0700 |
|---|---|---|
| committer | Sascha Wise <me@saschawise.com>
| 2022-07-16 08:41:42 -0700 |
| commit | 9bff0c8783a1ea6f3ff7aebac1a55fda15968e40 (patch) | |
| tree | 2a9f4bb157c2a0bb868359dde99c4721ad618f19 | |
| parent | 05ddb442301e617352aba697a2f9927ffc50411c (diff) | |
| download | cortex-m-9bff0c8783a1ea6f3ff7aebac1a55fda15968e40.tar.gz cortex-m-9bff0c8783a1ea6f3ff7aebac1a55fda15968e40.tar.zst cortex-m-9bff0c8783a1ea6f3ff7aebac1a55fda15968e40.zip | |
fix and cleanup offsets in nvic
| -rw-r--r-- | src/peripheral/nvic.rs | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index bd4a045..067c1d9 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -33,17 +33,18 @@ pub struct RegisterBlock { /// Interrupt Active Bit (not present on Cortex-M0 variants) #[cfg(not(armv6m))] pub iabr: [RO<u32>; 16], - #[cfg(any(armv6m, armv8m))] + #[cfg(armv6m)] _reserved4: [u32; 16], + _reserved5: [u32; 16], + #[cfg(armv8m)] /// Interrupt Target Non-secure (only present on Arm v8-M) pub itns: [RW<u32>; 16], - #[cfg(armv8m)] - _reserved5: [u32; 32], - #[cfg(not(armv8m))] - _reserved5: [u32; 48], + _reserved6: [u32; 16], + + _reserved7: [u32; 16], /// Interrupt Priority /// @@ -74,7 +75,7 @@ pub struct RegisterBlock { pub ipr: [RW<u32>; 8], #[cfg(not(armv6m))] - _reserved6: [u32; 580], + _reserved8: [u32; 580], /// Software Trigger Interrupt #[cfg(not(armv6m))] |