Merge #234

234: Use assembly sequences to enable caches. r=adamgreig a=cbiffle

See #232, which this partially fixes -- there's still the question of
taking an interrupt in the midst of these sequences.

Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>

9 files changed, 53 insertions, 8 deletions

diff --git a/asm-v7.s b/asm-v7.s
index fad6f4c..17d7110 100644
--- a/asm-v7.s
+++ b/asm-v7.s
@@ -1,3 +1,4 @@
+  .syntax unified
   .cfi_sections .debug_frame
 
   .section .text.__basepri_max
@@ -39,3 +40,39 @@ __faultmask:
   bx lr
   .cfi_endproc
   .size __faultmask, . - __faultmask
+
+  .section .text.__enable_icache
+  .global __enable_icache
+  .thumb_func
+  .cfi_startproc
+__enable_icache:
+  ldr r0, =0xE000ED14       @ CCR
+  mrs r2, PRIMASK           @ save critical nesting info
+  cpsid i                   @ mask interrupts
+  ldr r1, [r0]              @ read CCR
+  orr.w r1, r1, #(1 << 17)  @ Set bit 17, IC
+  str r1, [r0]              @ write it back
+  dsb                       @ ensure store completes
+  isb                       @ synchronize pipeline
+  msr PRIMASK, r2           @ unnest critical section
+  bx lr
+  .cfi_endproc
+  .size __enable_icache, . - __enable_icache
+
+  .section .text.__enable_dcache
+  .global __enable_dcache
+  .thumb_func
+  .cfi_startproc
+__enable_dcache:
+  ldr r0, =0xE000ED14       @ CCR
+  mrs r2, PRIMASK           @ save critical nesting info
+  cpsid i                   @ mask interrupts
+  ldr r1, [r0]              @ read CCR
+  orr.w r1, r1, #(1 << 16)  @ Set bit 16, DC
+  str r1, [r0]              @ write it back
+  dsb                       @ ensure store completes
+  isb                       @ synchronize pipeline
+  msr PRIMASK, r2           @ unnest critical section
+  bx lr
+  .cfi_endproc
+  .size __enable_dcache, . - __enable_dcache
diff --git a/bin/thumbv6m-none-eabi.a b/bin/thumbv6m-none-eabi.a
index 43ecf80..cb7a9f9 100644
--- a/bin/thumbv6m-none-eabi.a
+++ b/bin/thumbv6m-none-eabi.a
diff --git a/bin/thumbv7em-none-eabi.a b/bin/thumbv7em-none-eabi.a
index a250694..b518e41 100644
--- a/bin/thumbv7em-none-eabi.a
+++ b/bin/thumbv7em-none-eabi.a
diff --git a/bin/thumbv7em-none-eabihf.a b/bin/thumbv7em-none-eabihf.a
index efff863..84ff03b 100644
--- a/bin/thumbv7em-none-eabihf.a
+++ b/bin/thumbv7em-none-eabihf.a
diff --git a/bin/thumbv7m-none-eabi.a b/bin/thumbv7m-none-eabi.a
index e1a886b..5fca383 100644
--- a/bin/thumbv7m-none-eabi.a
+++ b/bin/thumbv7m-none-eabi.a
diff --git a/bin/thumbv8m.base-none-eabi.a b/bin/thumbv8m.base-none-eabi.a
index c4db7d5..2913d30 100644
--- a/bin/thumbv8m.base-none-eabi.a
+++ b/bin/thumbv8m.base-none-eabi.a
diff --git a/bin/thumbv8m.main-none-eabi.a b/bin/thumbv8m.main-none-eabi.a
index 719d1df..49f4b10 100644
--- a/bin/thumbv8m.main-none-eabi.a
+++ b/bin/thumbv8m.main-none-eabi.a
diff --git a/bin/thumbv8m.main-none-eabihf.a b/bin/thumbv8m.main-none-eabihf.a
index 0b665bc..bb1ce2e 100644
--- a/bin/thumbv8m.main-none-eabihf.a
+++ b/bin/thumbv8m.main-none-eabihf.a
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index 733a3ec..7343b4d 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -331,11 +331,15 @@ impl SCB {
         cbp.iciallu();
 
         // Enable I-cache
-        // NOTE(unsafe): We have synchronised access by &mut self
-        unsafe { self.ccr.modify(|r| r | SCB_CCR_IC_MASK) };
+        extern "C" {
+            // see asm-v7m.s
+            fn __enable_icache();
+        }
 
-        crate::asm::dsb();
-        crate::asm::isb();
+        // NOTE(unsafe): The asm routine manages exclusive access to the SCB
+        // registers and applies the proper barriers; it is technically safe on
+        // its own, and is only `unsafe` here because it's `extern "C"`.
+        unsafe { __enable_icache(); }
     }
 
     /// Disables I-cache if currently enabled.
@@ -400,11 +404,15 @@ impl SCB {
         unsafe { self.invalidate_dcache(cpuid) };
 
         // Now turn on the D-cache
-        // NOTE(unsafe): We have synchronised access by &mut self
-        unsafe { self.ccr.modify(|r| r | SCB_CCR_DC_MASK) };
+        extern "C" {
+            // see asm-v7m.s
+            fn __enable_dcache();
+        }
 
-        crate::asm::dsb();
-        crate::asm::isb();
+        // NOTE(unsafe): The asm routine manages exclusive access to the SCB
+        // registers and applies the proper barriers; it is technically safe on
+        // its own, and is only `unsafe` here because it's `extern "C"`.
+        unsafe { __enable_dcache(); }
     }
 
     /// Disables D-cache if currently enabled.