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| author |  Dario Nieuwenhuis <dirbaio@dirbaio.net>
| 2022-08-22 14:58:34 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <dirbaio@dirbaio.net>
| 2022-08-22 20:25:23 +0200 |
| commit | 777f07a4466786952e59fbb87816650c6d878082 (patch) | |
| tree | c5300fa2b845b78ccb8519a2828204653878f8c3 | |
| parent | 25f1f9577014421d31b729881d6048854ad50071 (diff) | |
| download | cortex-m-777f07a4466786952e59fbb87816650c6d878082.tar.gz cortex-m-777f07a4466786952e59fbb87816650c6d878082.tar.zst cortex-m-777f07a4466786952e59fbb87816650c6d878082.zip | |
Document critical-section-single-core feature.
| -rw-r--r-- | src/lib.rs | 10 |
1 files changed, 10 insertions, 0 deletions
@@ -9,6 +9,16 @@ //! //! # Optional features //! +//! ## `critical-section-single-core` +//! +//! This feature enables a [`critical-section`](https://github.com/rust-embedded/critical-section) +//! implementation suitable for single-core targets, based on disabling interrupts globally. +//! +//! It is **unsound** to enable it on multi-core targets or for code running in unprivileged mode, +//! and may cause functional problems in systems where some interrupts must be not be disabled +//! or critical sections are managed as part of an RTOS. In these cases, you should use +//! a target-specific implementation instead, typically provided by a HAL or RTOS crate. +//! //! ## `cm7-r0p1` //! //! This feature enables workarounds for errata found on Cortex-M7 chips with revision r0p1. Some |