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-rw-r--r--src/lib.rs10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/lib.rs b/src/lib.rs
index a7c2923..7c1599c 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -9,6 +9,16 @@
//!
//! # Optional features
//!
+//! ## `critical-section-single-core`
+//!
+//! This feature enables a [`critical-section`](https://github.com/rust-embedded/critical-section)
+//! implementation suitable for single-core targets, based on disabling interrupts globally.
+//!
+//! It is **unsound** to enable it on multi-core targets or for code running in unprivileged mode,
+//! and may cause functional problems in systems where some interrupts must be not be disabled
+//! or critical sections are managed as part of an RTOS. In these cases, you should use
+//! a target-specific implementation instead, typically provided by a HAL or RTOS crate.
+//!
//! ## `cm7-r0p1`
//!
//! This feature enables workarounds for errata found on Cortex-M7 chips with revision r0p1. Some