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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2020-09-07 17:19:47 +0000 |
|---|---|---|
| committer |  GitHub <noreply@github.com>
| 2020-09-07 17:19:47 +0000 |
| commit | 109a832a4460236cd224d872d07665a745d6435b (patch) | |
| tree | ff21a90065514e97514ec932fb00e93605b552f5 /cortex-m-rt | |
| parent | 43fdaded1a64ee8729eb22529100204e69bc4365 (diff) | |
| parent | 3ee7dd938231e4aca9f9ec829c47cb2827e91701 (diff) | |
| download | cortex-m-109a832a4460236cd224d872d07665a745d6435b.tar.gz cortex-m-109a832a4460236cd224d872d07665a745d6435b.tar.zst cortex-m-109a832a4460236cd224d872d07665a745d6435b.zip | |
Merge #294
294: add CFI and size info r=jonas-schievink a=japaric
like it was done in rust-embedded/cortex-m#216 and rust-embedded/cortex-m#212
Co-authored-by: Jorge Aparicio <jorge.aparicio@ferrous-systems.com>
Diffstat (limited to 'cortex-m-rt')
| -rw-r--r-- | cortex-m-rt/CHANGELOG.md | 2 | ||||
| -rw-r--r-- | cortex-m-rt/asm.s | 11 |
2 files changed, 13 insertions, 0 deletions
diff --git a/cortex-m-rt/CHANGELOG.md b/cortex-m-rt/CHANGELOG.md index e04c9c9..c39a9ae 100644 --- a/cortex-m-rt/CHANGELOG.md +++ b/cortex-m-rt/CHANGELOG.md @@ -12,6 +12,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - Various fixes to the linker script ([#265], [#286]). - Use the correct ABI for the `main` symbol ([#278]). - Add barriers after FPU enabling ([#279]). +- (ARMv6-M) Set LR value to a known value on reset (as the ARM spec requires) +- Added CFI and size info to external assembly subroutines (`HardFaultTrampoline` and `FpuTrampoline`) [#265]: https://github.com/rust-embedded/cortex-m-rt/pull/265 [#278]: https://github.com/rust-embedded/cortex-m-rt/pull/278 diff --git a/cortex-m-rt/asm.s b/cortex-m-rt/asm.s index 37dedbd..58ed274 100644 --- a/cortex-m-rt/asm.s +++ b/cortex-m-rt/asm.s @@ -1,3 +1,5 @@ + .cfi_sections .debug_frame + # LLD requires that the section flags are explicitly set here .section .HardFaultTrampoline, "ax" .global HardFaultTrampoline @@ -5,6 +7,7 @@ # get set and an invalid vector table is generated .type HardFaultTrampoline,%function .thumb_func + .cfi_startproc HardFaultTrampoline: # depending on the stack mode in EXC_RETURN, fetch stack pointer from # PSP or MSP @@ -17,6 +20,8 @@ HardFaultTrampoline: 0: mrs r0, PSP b HardFault + .cfi_endproc + .size HardFaultTrampoline, . - HardFaultTrampoline .section .text.FpuTrampoline, "ax" .global FpuTrampoline @@ -24,6 +29,7 @@ HardFaultTrampoline: # get set and an invalid vector table is generated .type FpuTrampoline,%function .thumb_func + .cfi_startproc # This enables the FPU and jumps to the main function. FpuTrampoline: # Address of SCB.CPACR. @@ -40,6 +46,8 @@ FpuTrampoline: # Hand execution over to `main`. bl main # Note: `main` must not return. `bl` is used only because it has a wider range than `b`. + .cfi_endproc + .size FpuTrampoline, . - FpuTrampoline # ARMv6-M leaves LR in an unknown state on Reset # this trampoline sets LR before it's pushed onto the stack by Reset @@ -49,8 +57,11 @@ FpuTrampoline: # get set and an invalid vector table is generated .type PreResetTrampoline,%function .thumb_func + .cfi_startproc PreResetTrampoline: # set LR to the initial value used by the ARMv7-M (0xFFFF_FFFF) ldr r0,=0xffffffff mov lr,r0 b Reset + .cfi_endproc + .size PreResetTrampoline, . - PreResetTrampoline |