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| author |  Ulf Lilleengen <ulf.lilleengen@gmail.com>
| 2021-02-25 15:25:57 +0100 |
|---|---|---|
| committer | Ulf Lilleengen <ulf.lilleengen@gmail.com>
| 2021-02-25 15:25:57 +0100 |
| commit | 59d30a44e1584b547f2b13e69a916ceb05a6564e (patch) | |
| tree | 484a241625f8e2bad95ef9ec45afb55f2291b3e2 /cortex-m-rt | |
| parent | d802c58d0fafb45538864c8798fcf71e04de0ad3 (diff) | |
| download | cortex-m-59d30a44e1584b547f2b13e69a916ceb05a6564e.tar.gz cortex-m-59d30a44e1584b547f2b13e69a916ceb05a6564e.tar.zst cortex-m-59d30a44e1584b547f2b13e69a916ceb05a6564e.zip | |
Read all bits from ICSR register
The 9th bit is needed to all 480 interrupts on Cortex-M33
Diffstat (limited to 'cortex-m-rt')
| -rw-r--r-- | cortex-m-rt/macros/src/lib.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cortex-m-rt/macros/src/lib.rs b/cortex-m-rt/macros/src/lib.rs index 7877348..817e9a1 100644 --- a/cortex-m-rt/macros/src/lib.rs +++ b/cortex-m-rt/macros/src/lib.rs @@ -227,7 +227,7 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream { const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32; - let irqn = unsafe { core::ptr::read_volatile(SCB_ICSR) as u8 as i16 - 16 }; + let irqn = unsafe { (core::ptr::read_volatile(SCB_ICSR) & 0x1FF) as i16 - 16 }; #ident(irqn) } |