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| author |  Ulf Lilleengen <ulf.lilleengen@gmail.com>
| 2021-02-25 15:04:42 +0100 |
|---|---|---|
| committer | Ulf Lilleengen <ulf.lilleengen@gmail.com>
| 2021-02-25 15:04:42 +0100 |
| commit | d802c58d0fafb45538864c8798fcf71e04de0ad3 (patch) | |
| tree | f5eec5628f5f002c694337238e061edd3db0e541 /cortex-m-rt | |
| parent | 02b308cf74bd288d63dd9b7ccda610283df099d2 (diff) | |
| download | cortex-m-d802c58d0fafb45538864c8798fcf71e04de0ad3.tar.gz cortex-m-d802c58d0fafb45538864c8798fcf71e04de0ad3.tar.zst cortex-m-d802c58d0fafb45538864c8798fcf71e04de0ad3.zip | |
Use volatile read for ICSR register
This prevents the compiler from optimizing the read
Diffstat (limited to 'cortex-m-rt')
| -rw-r--r-- | cortex-m-rt/macros/src/lib.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cortex-m-rt/macros/src/lib.rs b/cortex-m-rt/macros/src/lib.rs index fe0264f..7877348 100644 --- a/cortex-m-rt/macros/src/lib.rs +++ b/cortex-m-rt/macros/src/lib.rs @@ -227,7 +227,7 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream { const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32; - let irqn = unsafe { core::ptr::read(SCB_ICSR) as u8 as i16 - 16 }; + let irqn = unsafe { core::ptr::read_volatile(SCB_ICSR) as u8 as i16 - 16 }; #ident(irqn) } |