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authorGravatar bors[bot] <26634292+bors[bot]@users.noreply.github.com> 2020-07-05 20:55:57 +0000
committerGravatar GitHub <noreply@github.com> 2020-07-05 20:55:57 +0000
commit2ce2384d8dd239301b606921abe3b3f35d5fbb05 (patch)
tree66c82004d10112306a8700aeb2216babffdbde5b /src/peripheral/mod.rs
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Merge #234
234: Use assembly sequences to enable caches. r=adamgreig a=cbiffle See #232, which this partially fixes -- there's still the question of taking an interrupt in the midst of these sequences. Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
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