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| author |  Jorge Aparicio <jorge@japaric.io>
| 2018-05-11 17:04:05 +0200 |
|---|---|---|
| committer | Jorge Aparicio <jorge@japaric.io>
| 2018-05-11 17:09:36 +0200 |
| commit | 93abfac2a7e092d739e3e9b61bcd4f8614541428 (patch) | |
| tree | 716486743e0fb0de56b5a9ed05e2af57e80a627d /src/peripheral/nvic.rs | |
| parent | b098b6af6aa48826aa1471ba3359a42d6d3e059a (diff) | |
| download | cortex-m-93abfac2a7e092d739e3e9b61bcd4f8614541428.tar.gz cortex-m-93abfac2a7e092d739e3e9b61bcd4f8614541428.tar.zst cortex-m-93abfac2a7e092d739e3e9b61bcd4f8614541428.zip | |
stable by default, remove exception module, add SCB.vect_active, ..
tweak Exception enum to match CMSIS names, document the parts of the API that require opting into
`"inline-asm"`.
Diffstat (limited to 'src/peripheral/nvic.rs')
| -rw-r--r-- | src/peripheral/nvic.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index ecfdd7e..7ce31ba 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -2,8 +2,8 @@ use volatile_register::{RO, RW}; -use peripheral::NVIC; use interrupt::Nr; +use peripheral::NVIC; /// Register block #[repr(C)] |