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| author |  bors[bot] <bors[bot]@users.noreply.github.com>
| 2019-03-12 21:37:20 +0000 |
|---|---|---|
| committer | bors[bot] <bors[bot]@users.noreply.github.com>
| 2019-03-12 21:37:20 +0000 |
| commit | 563c27a152a98b6d1092415e6385b970ebd0c367 (patch) | |
| tree | 6cbbd8ecd1c0ee23a758a71d17396f52443d20b4 /src/peripheral/test.rs | |
| parent | 3b574e88fb15d704b9c2dacbf643f7ca0fa706ca (diff) | |
| parent | 771fc84d6ea9d669848baf6acff9e54b36819eb1 (diff) | |
| download | cortex-m-563c27a152a98b6d1092415e6385b970ebd0c367.tar.gz cortex-m-563c27a152a98b6d1092415e6385b970ebd0c367.tar.zst cortex-m-563c27a152a98b6d1092415e6385b970ebd0c367.zip | |
Merge #106
106: Stir register and debugger check r=adamgreig a=thenewwazoo
Adds support for requesting an interrupt via the STIR register and checking whether a debugger is attached.
Co-authored-by: Brandon Matthews <bmatthews@zipcar.com>
Co-authored-by: Brandon Matthews <bmatthews@optimaltour.us>
Diffstat (limited to 'src/peripheral/test.rs')
| -rw-r--r-- | src/peripheral/test.rs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/peripheral/test.rs b/src/peripheral/test.rs index d0d713a..4eb48f5 100644 --- a/src/peripheral/test.rs +++ b/src/peripheral/test.rs @@ -117,6 +117,8 @@ fn nvic() { assert_eq!(address(&nvic.icpr), 0xE000E280); assert_eq!(address(&nvic.iabr), 0xE000E300); assert_eq!(address(&nvic.ipr), 0xE000E400); + #[cfg(not(armv6m))] + assert_eq!(address(&nvic.stir), 0xE000EF00); } #[test] |